1 /***************************************************************************//**
2 * @file em_cmu_fpga.h
3 * @brief Clock management unit (CMU) API for FPGAs
4 * @version 5.3.5
5 *******************************************************************************
6 * # License
7 * <b>Copyright 2018 Silicon Laboratories, Inc. www.silabs.com</b>
8 *******************************************************************************
9 *
10 * Permission is granted to anyone to use this software for any purpose,
11 * including commercial applications, and to alter it and redistribute it
12 * freely, subject to the following restrictions:
13 *
14 * 1. The origin of this software must not be misrepresented; you must not
15 * claim that you wrote the original software.
16 * 2. Altered source versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software.
18 * 3. This notice may not be removed or altered from any source distribution.
19 *
20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
21 * obligation to support this Software. Silicon Labs is providing the
22 * Software "AS IS", with no express or implied warranties of any kind,
23 * including, but not limited to, any implied warranties of merchantability
24 * or fitness for any particular purpose or warranties against infringement
25 * of any proprietary rights of a third party.
26 *
27 * Silicon Labs will not be liable for any consequential, incidental, or
28 * special damages, or any other relief, or for any claim by any third party,
29 * arising from your use of this Software.
30 *
31 ******************************************************************************/
32 #ifndef EM_CMU_FPGA_H
33 #define EM_CMU_FPGA_H
34
35 #include "em_device.h"
36
37 #if defined(CMU_PRESENT) && defined(FPGA)
38
39 #include <stdbool.h>
40 #include "sl_assert.h"
41 #include "em_bus.h"
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /***************************************************************************//**
48 * @addtogroup emlib
49 * @{
50 ******************************************************************************/
51
52 /***************************************************************************//**
53 * @addtogroup CMU
54 * @{
55 ******************************************************************************/
56
57 #define CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX 40000000UL // Lynx value
58 #define VSCALE_EM01_LOW_POWER 1 // Lynx value
59 #define VSCALE_EM01_HIGH_PERFORMANCE 0 // Lynx value
60
61 #if defined(LFRCO_PRECISION_MODE) && LFRCO_PRECISION_MODE
62 #define PLFRCO_PRESENT
63 #endif
64
65 /*******************************************************************************
66 ******************************** ENUMS ************************************
67 ******************************************************************************/
68 /** Clock divisors. These values are valid for prescalers. */
69 #define cmuClkDiv_1 1 /**< Divide clock by 1. */
70 #define cmuClkDiv_2 2 /**< Divide clock by 2. */
71 #define cmuClkDiv_4 4 /**< Divide clock by 4. */
72 #define cmuClkDiv_8 8 /**< Divide clock by 8. */
73 #define cmuClkDiv_16 16 /**< Divide clock by 16. */
74 #define cmuClkDiv_32 32 /**< Divide clock by 32. */
75 #define cmuClkDiv_64 64 /**< Divide clock by 64. */
76 #define cmuClkDiv_128 128 /**< Divide clock by 128. */
77 #define cmuClkDiv_256 256 /**< Divide clock by 256. */
78 #define cmuClkDiv_512 512 /**< Divide clock by 512. */
79 #define cmuClkDiv_1024 1024 /**< Divide clock by 1024. */
80 #define cmuClkDiv_2048 2048 /**< Divide clock by 2048. */
81 #define cmuClkDiv_4096 4096 /**< Divide clock by 4096. */
82 #define cmuClkDiv_8192 8192 /**< Divide clock by 8192. */
83 #define cmuClkDiv_16384 16384 /**< Divide clock by 16384. */
84 #define cmuClkDiv_32768 32768 /**< Divide clock by 32768. */
85
86 /** Clock divider configuration */
87 typedef uint32_t CMU_ClkDiv_TypeDef;
88
89 /** High frequency system RCO bands */
90 typedef enum {
91 cmuHFRCOFreq_1M0Hz = 1000000U, /**< 1MHz RC band */
92 cmuHFRCOFreq_2M0Hz = 2000000U, /**< 2MHz RC band */
93 cmuHFRCOFreq_4M0Hz = 4000000U, /**< 4MHz RC band */
94 cmuHFRCOFreq_7M0Hz = 7000000U, /**< 7MHz RC band */
95 cmuHFRCOFreq_13M0Hz = 13000000U, /**< 13MHz RC band */
96 cmuHFRCOFreq_16M0Hz = 16000000U, /**< 16MHz RC band */
97 cmuHFRCOFreq_19M0Hz = 19000000U, /**< 19MHz RC band */
98 cmuHFRCOFreq_26M0Hz = 26000000U, /**< 26MHz RC band */
99 cmuHFRCOFreq_32M0Hz = 32000000U, /**< 32MHz RC band */
100 cmuHFRCOFreq_38M0Hz = 38000000U, /**< 38MHz RC band */
101 cmuHFRCOFreq_48M0Hz = 48000000U, /**< 48MHz RC band */
102 cmuHFRCOFreq_56M0Hz = 56000000U, /**< 56MHz RC band */
103 cmuHFRCOFreq_64M0Hz = 64000000U, /**< 64MHz RC band */
104 cmuHFRCOFreq_72M0Hz = 72000000U, /**< 72MHz RC band */
105 cmuHFRCOFreq_UserDefined = 0,
106 } CMU_HFRCOFreq_TypeDef;
107 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
108 #define CMU_HFRCO_MAX cmuHFRCOFreq_72M0Hz
109
110 /** HFRCODPLL frequency bands */
111 typedef enum {
112 cmuHFRCODPLLFreq_1M0Hz = 1000000U, /**< 1MHz RC band. */
113 cmuHFRCODPLLFreq_2M0Hz = 2000000U, /**< 2MHz RC band. */
114 cmuHFRCODPLLFreq_4M0Hz = 4000000U, /**< 4MHz RC band. */
115 cmuHFRCODPLLFreq_7M0Hz = 7000000U, /**< 7MHz RC band. */
116 cmuHFRCODPLLFreq_13M0Hz = 13000000U, /**< 13MHz RC band. */
117 cmuHFRCODPLLFreq_16M0Hz = 16000000U, /**< 16MHz RC band. */
118 cmuHFRCODPLLFreq_19M0Hz = 19000000U, /**< 19MHz RC band. */
119 cmuHFRCODPLLFreq_26M0Hz = 26000000U, /**< 26MHz RC band. */
120 cmuHFRCODPLLFreq_32M0Hz = 32000000U, /**< 32MHz RC band. */
121 cmuHFRCODPLLFreq_38M0Hz = 38000000U, /**< 38MHz RC band. */
122 cmuHFRCODPLLFreq_48M0Hz = 48000000U, /**< 48MHz RC band. */
123 cmuHFRCODPLLFreq_56M0Hz = 56000000U, /**< 56MHz RC band. */
124 cmuHFRCODPLLFreq_64M0Hz = 64000000U, /**< 64MHz RC band. */
125 cmuHFRCODPLLFreq_80M0Hz = 80000000U, /**< 80MHz RC band. */
126 cmuHFRCODPLLFreq_UserDefined = 0,
127 } CMU_HFRCODPLLFreq_TypeDef;
128
129 /** HFRCODPLL maximum frequency */
130 #define CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz
131 /** HFRCODPLL minimum frequency */
132 #define CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz
133
134 /** HFRCOEM23 frequency bands */
135 typedef enum {
136 cmuHFRCOEM23Freq_1M0Hz = 1000000U, /**< 1MHz RC band. */
137 cmuHFRCOEM23Freq_2M0Hz = 2000000U, /**< 2MHz RC band. */
138 cmuHFRCOEM23Freq_4M0Hz = 4000000U, /**< 4MHz RC band. */
139 cmuHFRCOEM23Freq_13M0Hz = 13000000U, /**< 13MHz RC band. */
140 cmuHFRCOEM23Freq_16M0Hz = 16000000U, /**< 16MHz RC band. */
141 cmuHFRCOEM23Freq_19M0Hz = 19000000U, /**< 19MHz RC band. */
142 cmuHFRCOEM23Freq_26M0Hz = 26000000U, /**< 26MHz RC band. */
143 cmuHFRCOEM23Freq_32M0Hz = 32000000U, /**< 32MHz RC band. */
144 cmuHFRCOEM23Freq_40M0Hz = 40000000U, /**< 40MHz RC band. */
145 cmuHFRCOEM23Freq_UserDefined = 0,
146 } CMU_HFRCOEM23Freq_TypeDef;
147
148 /** HFRCOEM23 maximum frequency */
149 #define CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz
150 /** HFRCOEM23 minimum frequency */
151 #define CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz
152
153 /** Clock points in CMU. Please refer to CMU overview in reference manual. */
154 typedef enum {
155 /*******************/
156 /* Clock branches */
157 /*******************/
158
159 cmuClock_SYSCLK, /**< System clock. */
160 cmuClock_HCLK, /**< Core and AHB bus interface clock. */
161 cmuClock_EXPCLK, /**< Export clock. */
162 cmuClock_PCLK, /**< Peripheral APB bus interface clock. */
163 cmuClock_LSPCLK, /**< Low speed peripheral APB bus interface clock. */
164 cmuClock_IADCCLK, /**< IADC clock. */
165 cmuClock_EM01GRPACLK, /**< EM01GRPA clock. */
166 #if defined(_CMU_EM01GRPBCLKCTRL_MASK)
167 cmuClock_EM01GRPBCLK, /**< EM01GRPB clock. */
168 #endif
169 cmuClock_EM01GRPCCLK, /**< EM01GRPC clock. */
170 cmuClock_EM23GRPACLK, /**< EM23GRPA clock. */
171 cmuClock_EM4GRPACLK, /**< EM4GRPA clock. */
172 cmuClock_LFRCO, /**< LFRCO clock. */
173 cmuClock_ULFRCO, /**< ULFRCO clock. */
174 cmuClock_LFXO, /**< LFXO clock. */
175 cmuClock_HFRCO0, /**< HFRCO0 clock. */
176 cmuClock_WDOG0CLK, /**< WDOG0 clock. */
177 #if WDOG_COUNT > 1
178 cmuClock_WDOG1CLK, /**< WDOG1 clock. */
179 #endif
180 cmuClock_DPLLREFCLK, /**< DPLL reference clock. */
181 #if defined(_CMU_TRACECLKCTRL_MASK)
182 cmuClock_TRACECLK, /**< Debug trace clock. */
183 #endif
184 cmuClock_RTCCCLK, /**< RTCC clock. */
185 #if defined(LESENSE_PRESENT)
186 cmuClock_LESENSEHFCLK,
187 cmuClock_LESENSELFCLK,
188 #endif
189
190 /*********************/
191 /* Peripheral clocks */
192 /*********************/
193
194 cmuClock_CORE, /**< Cortex-M33 core clock. */
195 cmuClock_SYSTICK, /**< Optional Cortex-M33 SYSTICK clock. */
196 cmuClock_ACMP0, /**< ACMP0 clock. */
197 cmuClock_ACMP1, /**< ACMP1 clock. */
198 cmuClock_BURTC, /**< BURTC clock. */
199 cmuClock_GPCRC, /**< GPCRC clock. */
200 cmuClock_GPIO, /**< GPIO clock. */
201 cmuClock_I2C0, /**< I2C0 clock. */
202 cmuClock_I2C1, /**< I2C1 clock. */
203 cmuClock_SYSCFG, /**< SYSCFG clock. */
204 cmuClock_IADC0, /**< IADC clock. */
205 cmuClock_LDMA, /**< LDMA clock. */
206 cmuClock_LDMAXBAR, /**< LDMAXBAR clock. */
207 cmuClock_LETIMER0, /**< LETIMER clock. */
208 cmuClock_PRS, /**< PRS clock. */
209 cmuClock_RTCC, /**< RTCC clock. */
210 cmuClock_SYSRTC, /**< SYSRTC clock. */
211 cmuClock_TIMER0, /**< TIMER0 clock. */
212 cmuClock_TIMER1, /**< TIMER1 clock. */
213 cmuClock_TIMER2, /**< TIMER2 clock. */
214 cmuClock_TIMER3, /**< TIMER3 clock. */
215 cmuClock_TIMER4, /**< TIMER4 clock. */
216 cmuClock_TIMER5, /**< TIMER5 clock. */
217 cmuClock_TIMER6, /**< TIMER6 clock. */
218 cmuClock_TIMER7, /**< TIMER7 clock. */
219 cmuClock_BURAM,
220 cmuClock_LESENSE,
221 cmuClock_LESENSEHF, /**< LESENSEHF clock. */
222 #if defined(USART0)
223 cmuClock_USART0, /**< USART0 clock. */
224 #endif
225 #if defined(USART1)
226 cmuClock_USART1, /**< USART1 clock. */
227 #endif
228 #if defined(USART2)
229 cmuClock_USART2, /**< USART2 clock. */
230 #endif
231 cmuClock_WDOG0, /**< WDOG0 clock. */
232 #if defined(WDOG1)
233 cmuClock_WDOG1, /**< WDOG1 clock. */
234 #endif
235 cmuClock_PDM, /**< PDM clock. */
236 cmuClock_PDMREF, /**< PDM reference clock. */
237 cmuClock_LFA,
238 cmuClock_LCDpre,
239 cmuClock_LCD,
240 #if defined(EUART0)
241 cmuClock_EUART0, /**< EUART0 clock. */
242 #endif
243 #if defined(EUSART0)
244 cmuClock_EUSART0, /**< EUSART0 clock. */
245 cmuClock_EUSART0CLK,
246 #endif
247 #if defined(EUSART1)
248 cmuClock_EUSART1, /**< EUSART1 clock. */
249 #endif
250 #if defined(EUSART2)
251 cmuClock_EUSART2, /**< EUSART2 clock. */
252 #endif
253 #if defined(EUSART3)
254 cmuClock_EUSART3, /**< EUSART3 clock. */
255 #endif
256 #if defined(EUSART4)
257 cmuClock_EUSART4, /**< EUSART4 clock. */
258 #endif
259 cmuClock_PCNT0,
260 cmuClock_KEYSCAN,
261 cmuClock_HFPER,
262 cmuClock_MSC,
263 cmuClock_DMEM,
264 cmuClock_SEMAILBOX,
265 cmuClock_SMU,
266 cmuClock_VDAC0
267 } CMU_Clock_TypeDef;
268
269 /** OCELOT TEMPORARY DEFINE. */
270 #define cmuClock_CORELE cmuClock_CORE
271
272 /** Oscillator types. */
273 typedef enum {
274 cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
275 #if defined(LFRCO_PRESENT)
276 cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
277 #endif
278 #if defined(PLFRCO_PRESENT)
279 cmuOsc_PLFRCO, /**< Precision Low frequency RC oscillator. */
280 #endif
281 cmuOsc_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
282 cmuOsc_HFXO, /**< High frequency crystal oscillator. */
283 cmuOsc_HFRCO, /**< High frequency RC oscillator. */
284 cmuOsc_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
285 #if defined(HFRCOEM23_PRESENT)
286 cmuOsc_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
287 #endif
288 cmuOsc_ULFRCO, /**< Ultra low frequency RC oscillator. */
289 } CMU_Osc_TypeDef;
290
291 /** Selectable clock sources. */
292 typedef enum {
293 cmuSelect_Error, /**< Usage error. */
294 cmuSelect_Disabled, /**< Clock selector disabled. */
295 cmuSelect_FSRCO, /**< Fast startup fixed frequency RC oscillator. */
296 cmuSelect_HFXO, /**< High frequency crystal oscillator. */
297 cmuSelect_HFRCO, /**< High frequency RC. */
298 cmuSelect_HFRCODPLL, /**< High frequency RC and DPLL oscillator. */
299 #if defined(HFRCOEM23_PRESENT)
300 cmuSelect_HFRCOEM23, /**< High frequency deep sleep RC oscillator. */
301 #endif
302 cmuSelect_CLKIN0, /**< External clock input. */
303 cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
304 #if defined(LFRCO_PRESENT)
305 cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
306 #endif
307 #if defined(PLFRCO_PRESENT)
308 cmuSelect_PLFRCO, /**< Precision Low frequency RC oscillator. */
309 #endif
310 cmuSelect_ULFRCO, /**< Ultra low frequency RC oscillator. */
311 cmuSelect_PCLK, /**< Peripheral APB bus interface clock. */
312 cmuSelect_HCLK, /**< Core and AHB bus interface clock. */
313 cmuSelect_HCLKDIV1024, /**< Prescaled HCLK frequency clock. */
314 cmuSelect_EM01GRPACLK, /**< EM01GRPA clock. */
315 cmuSelect_EM01GRPCCLK, /**< EM01GRPC clock. */
316 cmuSelect_EM23GRPACLK, /**< EM23GRPACLK clock.*/
317 cmuSelect_EXPCLK, /**< Pin export clock. */
318 cmuSelect_PRS /**< PRS input as clock. */
319 } CMU_Select_TypeDef;
320
321 /** DPLL reference clock edge detect selector. */
322 typedef enum {
323 cmuDPLLEdgeSel_Fall = 0, /**< Detect falling edge of reference clock. */
324 cmuDPLLEdgeSel_Rise = 1 /**< Detect rising edge of reference clock. */
325 } CMU_DPLLEdgeSel_TypeDef;
326
327 /** DPLL lock mode selector. */
328 typedef enum {
329 cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL, /**< Frequency lock mode. */
330 cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL /**< Phase lock mode. */
331 } CMU_DPLLLockMode_TypeDef;
332
333 /** LFXO oscillator modes. */
334 typedef enum {
335 cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
336 cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK, /**< External AC coupled sine. */
337 cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK, /**< External digital clock. */
338 } CMU_LfxoOscMode_TypeDef;
339
340 /** LFXO start-up timeout delay. */
341 typedef enum {
342 cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2, /**< 2 cycles start-up delay. */
343 cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256, /**< 256 cycles start-up delay. */
344 cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K, /**< 1K cycles start-up delay. */
345 cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K, /**< 2K cycles start-up delay. */
346 cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K, /**< 4K cycles start-up delay. */
347 cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K, /**< 8K cycles start-up delay. */
348 cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K, /**< 16K cycles start-up delay. */
349 cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K, /**< 32K cycles start-up delay. */
350 } CMU_LfxoStartupDelay_TypeDef;
351
352 //TODO UPDATE with SYXO new IP.
353 #define SYSXO
354 /** HFXO oscillator modes. */
355 typedef enum {
356 #if defined(SYSXO)
357 cmuHfxoOscMode_Crystal,
358 cmuHfxoOscMode_ExternalSine,
359 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
360 cmuHfxoOscMode_ExternalSinePkDet,
361 #endif
362 #else
363 cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL, /**< Crystal oscillator. */
364 cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK, /**< External digital clock. */
365 #if defined(_HFXO_CFG_MODE_EXTCLKPKDET)
366 cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET, /**< External digital clock with peak detector used. */
367 #endif
368 #endif
369 } CMU_HfxoOscMode_TypeDef;
370
371 /** HFXO core bias LSB change timeout. */
372 typedef enum {
373 #if defined(SYSXO)
374 cmuHfxoCbLsbTimeout_8us, /**< 8 us timeout. */
375 cmuHfxoCbLsbTimeout_20us, /**< 20 us timeout. */
376 cmuHfxoCbLsbTimeout_41us, /**< 41 us timeout. */
377 cmuHfxoCbLsbTimeout_62us, /**< 62 us timeout. */
378 cmuHfxoCbLsbTimeout_83us, /**< 83 us timeout. */
379 cmuHfxoCbLsbTimeout_104us, /**< 104 us timeout. */
380 cmuHfxoCbLsbTimeout_125us, /**< 125 us timeout. */
381 cmuHfxoCbLsbTimeout_166us, /**< 166 us timeout. */
382 cmuHfxoCbLsbTimeout_208us, /**< 208 us timeout. */
383 cmuHfxoCbLsbTimeout_250us, /**< 250 us timeout. */
384 cmuHfxoCbLsbTimeout_333us, /**< 333 us timeout. */
385 cmuHfxoCbLsbTimeout_416us, /**< 416 us timeout. */
386 cmuHfxoCbLsbTimeout_833us, /**< 833 us timeout. */
387 cmuHfxoCbLsbTimeout_1250us, /**< 1250 us timeout. */
388 cmuHfxoCbLsbTimeout_2083us, /**< 2083 us timeout. */
389 cmuHfxoCbLsbTimeout_3750us, /**< 3750 us timeout. */
390 #else
391 cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US, /**< 8 us timeout. */
392 cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US, /**< 20 us timeout. */
393 cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US, /**< 41 us timeout. */
394 cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US, /**< 62 us timeout. */
395 cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US, /**< 83 us timeout. */
396 cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US, /**< 104 us timeout. */
397 cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US, /**< 125 us timeout. */
398 cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US, /**< 166 us timeout. */
399 cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US, /**< 208 us timeout. */
400 cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US, /**< 250 us timeout. */
401 cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US, /**< 333 us timeout. */
402 cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US, /**< 416 us timeout. */
403 cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US, /**< 833 us timeout. */
404 cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US, /**< 1250 us timeout. */
405 cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US, /**< 2083 us timeout. */
406 cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US, /**< 3750 us timeout. */
407 #endif
408 } CMU_HfxoCbLsbTimeout_TypeDef;
409
410 /** HFXO steady state timeout. */
411 typedef enum {
412 #if defined(SYSXO)
413 cmuHfxoSteadyStateTimeout_16us, /**< 16 us timeout. */
414 cmuHfxoSteadyStateTimeout_41us, /**< 41 us timeout. */
415 cmuHfxoSteadyStateTimeout_83us, /**< 83 us timeout. */
416 cmuHfxoSteadyStateTimeout_125us, /**< 125 us timeout. */
417 cmuHfxoSteadyStateTimeout_166us, /**< 166 us timeout. */
418 cmuHfxoSteadyStateTimeout_208us, /**< 208 us timeout. */
419 cmuHfxoSteadyStateTimeout_250us, /**< 250 us timeout. */
420 cmuHfxoSteadyStateTimeout_333us, /**< 333 us timeout. */
421 cmuHfxoSteadyStateTimeout_416us, /**< 416 us timeout. */
422 cmuHfxoSteadyStateTimeout_500us, /**< 500 us timeout. */
423 cmuHfxoSteadyStateTimeout_666us, /**< 666 us timeout. */
424 cmuHfxoSteadyStateTimeout_833us, /**< 833 us timeout. */
425 cmuHfxoSteadyStateTimeout_1666us, /**< 1666 us timeout. */
426 cmuHfxoSteadyStateTimeout_2500us, /**< 2500 us timeout. */
427 cmuHfxoSteadyStateTimeout_4166us, /**< 4166 us timeout. */
428 cmuHfxoSteadyStateTimeout_7500us, /**< 7500 us timeout. */
429 #else
430 cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US, /**< 16 us timeout. */
431 cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US, /**< 41 us timeout. */
432 cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US, /**< 83 us timeout. */
433 cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US, /**< 125 us timeout. */
434 cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US, /**< 166 us timeout. */
435 cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US, /**< 208 us timeout. */
436 cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US, /**< 250 us timeout. */
437 cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US, /**< 333 us timeout. */
438 cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US, /**< 416 us timeout. */
439 cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US, /**< 500 us timeout. */
440 cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US, /**< 666 us timeout. */
441 cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US, /**< 833 us timeout. */
442 cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US, /**< 1666 us timeout. */
443 cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US, /**< 2500 us timeout. */
444 cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US, /**< 4166 us timeout. */
445 cmuHfxoSteadyStateTimeout_7500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T7500US, /**< 7500 us timeout. */
446 #endif
447 } CMU_HfxoSteadyStateTimeout_TypeDef;
448
449 /** HFXO core degeneration control. */
450 typedef enum {
451 #if defined(SYSXO)
452 cmuHfxoCoreDegen_None, /**< No core degeneration. */
453 cmuHfxoCoreDegen_33, /**< Core degeneration control 33. */
454 cmuHfxoCoreDegen_50, /**< Core degeneration control 50. */
455 cmuHfxoCoreDegen_100, /**< Core degeneration control 100. */
456 #else
457 cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE, /**< No core degeneration. */
458 cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33, /**< Core degeneration control 33. */
459 cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50, /**< Core degeneration control 50. */
460 cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100, /**< Core degeneration control 100. */
461 #endif
462 } CMU_HfxoCoreDegen_TypeDef;
463
464 /** HFXO XI and XO pin fixed capacitor control. */
465 typedef enum {
466 #if defined(SYSXO)
467 cmuHfxoCtuneFixCap_None, /**< No fixed capacitors. */
468 cmuHfxoCtuneFixCap_Xi, /**< Fixed capacitor on XI pin. */
469 cmuHfxoCtuneFixCap_Xo, /**< Fixed capacitor on XO pin. */
470 cmuHfxoCtuneFixCap_Both, /**< Fixed capacitor on both pins. */
471 #else
472 cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE, /**< No fixed capacitors. */
473 cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI, /**< Fixed capacitor on XI pin. */
474 cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO, /**< Fixed capacitor on XO pin. */
475 cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH, /**< Fixed capacitor on both pins. */
476 #endif
477 } CMU_HfxoCtuneFixCap_TypeDef;
478
479 /*******************************************************************************
480 ******************************* STRUCTS ***********************************
481 ******************************************************************************/
482
483 /** LFXO initialization structure. Init values should be obtained from a
484 configuration tool, app. note or xtal data sheet. */
485 typedef struct {
486 uint8_t gain; /**< Startup gain. */
487 uint8_t capTune; /**< Internal capacitance tuning. */
488 CMU_LfxoStartupDelay_TypeDef timeout; /**< Startup delay. */
489 CMU_LfxoOscMode_TypeDef mode; /**< Oscillator mode. */
490 bool highAmplitudeEn; /**< High amplitude enable. */
491 bool agcEn; /**< AGC enable. */
492 bool failDetEM4WUEn; /**< EM4 wakeup on failure enable. */
493 bool failDetEn; /**< Oscillator failure detection enable. */
494 bool disOnDemand; /**< Disable on-demand requests. */
495 bool forceEn; /**< Force oscillator enable. */
496 bool regLock; /**< Lock register access. */
497 } CMU_LFXOInit_TypeDef;
498
499 /** Default LFXO initialization values for XTAL mode. */
500 #define CMU_LFXOINIT_DEFAULT \
501 { \
502 1, \
503 38, \
504 cmuLfxoStartupDelay_4KCycles, \
505 cmuLfxoOscMode_Crystal, \
506 false, /* highAmplitudeEn */ \
507 true, /* agcEn */ \
508 false, /* failDetEM4WUEn */ \
509 false, /* failDetEn */ \
510 false, /* DisOndemand */ \
511 false, /* ForceEn */ \
512 false /* Lock registers */ \
513 }
514
515 /** HFXO initialization structure. Init values should be obtained from a configuration tool,
516 app note or xtal data sheet */
517
518 typedef struct {
519 CMU_HfxoCbLsbTimeout_TypeDef timeoutCbLsb; /**< Core bias change timeout. */
520 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteadyFirstLock; /**< Steady state timeout duration for first lock. */
521 CMU_HfxoSteadyStateTimeout_TypeDef timeoutSteady; /**< Steady state timeout duration. */
522 uint8_t ctuneXoStartup; /**< XO pin startup tuning capacitance. */
523 uint8_t ctuneXiStartup; /**< XI pin startup tuning capacitance. */
524 uint8_t coreBiasStartup; /**< Core bias startup current. */
525 uint8_t imCoreBiasStartup; /**< Core bias intermediate startup current. */
526 CMU_HfxoCoreDegen_TypeDef coreDegenAna; /**< Core degeneration control. */
527 CMU_HfxoCtuneFixCap_TypeDef ctuneFixAna; /**< Fixed tuning capacitance on XI/XO. */
528 uint8_t ctuneXoAna; /**< Tuning capacitance on XO. */
529 uint8_t ctuneXiAna; /**< Tuning capacitance on XI. */
530 uint8_t coreBiasAna; /**< Core bias current. */
531 bool enXiDcBiasAna; /**< Enable XI internal DC bias. */
532 CMU_HfxoOscMode_TypeDef mode; /**< Oscillator mode. */
533 bool forceXo2GndAna; /**< Force XO pin to ground. */
534 bool forceXi2GndAna; /**< Force XI pin to ground. */
535 bool disOnDemand; /**< Disable on-demand requests. */
536 bool forceEn; /**< Force oscillator enable. */
537 bool regLock; /**< Lock register access. */
538 } CMU_HFXOInit_TypeDef;
539
540 /** Default HFXO initialization values for XTAL mode. */
541 #define CMU_HFXOINIT_DEFAULT \
542 { \
543 cmuHfxoCbLsbTimeout_416us, \
544 cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
545 cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
546 0U, /* ctuneXoStartup */ \
547 0U, /* ctuneXiStartup */ \
548 32U, /* coreBiasStartup */ \
549 32U, /* imCoreBiasStartup */ \
550 cmuHfxoCoreDegen_None, \
551 cmuHfxoCtuneFixCap_Both, \
552 0U, /* _HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, ctuneXoAna*/ \
553 0U,/* _HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, ctuneXiAna*/ \
554 60U, /* coreBiasAna */ \
555 false, /* enXiDcBiasAna */ \
556 cmuHfxoOscMode_Crystal, \
557 false, /* forceXo2GndAna */ \
558 false, /* forceXi2GndAna */ \
559 false, /* DisOndemand */ \
560 false, /* ForceEn */ \
561 false /* Lock registers */ \
562 }
563
564 /** Default HFXO initialization values for external sine mode. */
565 #define CMU_HFXOINIT_EXTERNAL_SINE \
566 { \
567 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
568 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
569 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
570 0U, /* ctuneXoStartup */ \
571 0U, /* ctuneXiStartup */ \
572 0U, /* coreBiasStartup */ \
573 0U, /* imCoreBiasStartup */ \
574 cmuHfxoCoreDegen_None, \
575 cmuHfxoCtuneFixCap_None, \
576 0U, /* ctuneXoAna */ \
577 0U, /* ctuneXiAna */ \
578 0U, /* coreBiasAna */ \
579 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
580 cmuHfxoOscMode_ExternalSine, \
581 false, /* forceXo2GndAna */ \
582 false, /* forceXi2GndAna */ \
583 false, /* DisOndemand */ \
584 false, /* ForceEn */ \
585 false /* Lock registers */ \
586 }
587
588 /** Default HFXO initialization values for external sine mode with peak detector. */
589 #define CMU_HFXOINIT_EXTERNAL_SINEPKDET \
590 { \
591 (CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
592 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
593 (CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
594 0U, /* ctuneXoStartup */ \
595 0U, /* ctuneXiStartup */ \
596 0U, /* coreBiasStartup */ \
597 0U, /* imCoreBiasStartup */ \
598 cmuHfxoCoreDegen_None, \
599 cmuHfxoCtuneFixCap_None, \
600 0U, /* ctuneXoAna */ \
601 0U, /* ctuneXiAna */ \
602 0U, /* coreBiasAna */ \
603 false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
604 cmuHfxoOscMode_ExternalSinePkDet, \
605 false, /* forceXo2GndAna */ \
606 false, /* forceXi2GndAna */ \
607 false, /* DisOndemand */ \
608 false, /* ForceEn */ \
609 false /* Lock registers */ \
610 }
611
612 #define CMU_HFXOINIT_EXTERNAL_CLOCK CMU_HFXOINIT_DEFAULT
613
614 /*******************************************************************************
615 ***************************** PROTOTYPES **********************************
616 ******************************************************************************/
617 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
618 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
619 CMU_Osc_TypeDef upSel);
620 uint32_t CMU_CalibrateCountGet(void);
621 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
622 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
623 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
624 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
625 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
626 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
627 void CMU_FreezeEnable(bool enable);
628 CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet(void);
629 void CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq);
630 CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet(void);
631 void CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq);
632 uint32_t CMU_HFRCOStartupDelayGet(void);
633 void CMU_HFRCOStartupDelaySet(uint32_t delay);
634 void CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit);
635 void CMU_HFXOCTuneDeltaSet(int32_t delta);
636 int32_t CMU_HFXOCTuneDeltaGet(void);
637 uint32_t CMU_LCDClkFDIVGet(void);
638 void CMU_LCDClkFDIVSet(uint32_t div);
639 void CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit);
640
641 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
642 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
643 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
644 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
645 void CMU_UpdateWaitStates(uint32_t freq, int vscale);
646 void CMU_LFXOPrecisionSet(uint16_t precision);
647 bool CMU_PCNTClockExternalGet(unsigned int instance);
648 void CMU_PCNTClockExternalSet(unsigned int instance, bool external);
649
CMU_CalibrateCont(bool enable)650 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
651 {
652 (void) enable;
653 }
654
CMU_CalibrateStart(void)655 __STATIC_INLINE void CMU_CalibrateStart(void)
656 {
657 }
658
CMU_CalibrateStop(void)659 __STATIC_INLINE void CMU_CalibrateStop(void)
660 {
661 }
662
CMU_DivToLog2(CMU_ClkDiv_TypeDef div)663 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
664 {
665 uint32_t log2;
666
667 /* Fixed 2^n prescalers take argument of 32768 or less. */
668 EFM_ASSERT((div > 0U) && (div <= 32768U));
669
670 /* Count leading zeroes and "reverse" result */
671 log2 = (31U - __CLZ(div));
672
673 return log2;
674 }
675
CMU_IntClear(uint32_t flags)676 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
677 {
678 (void) flags;
679 }
680
CMU_IntDisable(uint32_t flags)681 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
682 {
683 (void) flags;
684 }
685
CMU_IntEnable(uint32_t flags)686 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
687 {
688 (void) flags;
689 }
690
CMU_IntGet(void)691 __STATIC_INLINE uint32_t CMU_IntGet(void)
692 {
693 return 0;
694 }
695
CMU_IntGetEnabled(void)696 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
697 {
698 return 0;
699 }
700
CMU_IntSet(uint32_t flags)701 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
702 {
703 (void) flags;
704 }
CMU_Lock(void)705 __STATIC_INLINE void CMU_Lock(void)
706 {
707 }
CMU_Unlock(void)708 __STATIC_INLINE void CMU_Unlock(void)
709 {
710 }
711
712 #if !defined(_SILICON_LABS_32B_SERIES_0)
713 /***************************************************************************//**
714 * @brief
715 * Convert prescaler dividend to a logarithmic value. It only works for even
716 * numbers equal to 2^n.
717 *
718 * @param[in] presc
719 * An unscaled dividend (dividend = presc + 1).
720 *
721 * @return
722 * Logarithm of 2, as used by fixed 2^n prescalers.
723 ******************************************************************************/
CMU_PrescToLog2(uint32_t presc)724 __STATIC_INLINE uint32_t CMU_PrescToLog2(uint32_t presc)
725 {
726 uint32_t log2;
727
728 /* Integer prescalers take argument less than 32768. */
729 EFM_ASSERT(presc < 32768U);
730
731 /* Count leading zeroes and "reverse" result. */
732 log2 = 31UL - __CLZ(presc + (uint32_t) 1);
733
734 /* Check that prescaler is a 2^n number. */
735 EFM_ASSERT(presc == (SL_Log2ToDiv(log2) - 1U));
736
737 return log2;
738 }
739 #endif // !defined(_SILICON_LABS_32B_SERIES_0)
740
741 /** @} (end addtogroup CMU) */
742 /** @} (end addtogroup emlib) */
743
744 #ifdef __cplusplus
745 }
746 #endif
747
748 #endif /* #if defined(CMU_PRESENT) && defined(LYNX_FPGA) */
749 #endif /* EM_CMU_FPGA_H */
750
