1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 #include <stdint.h> 14 15 /* ---------------------------- Register Layout ------------------------------ */ 16 17 /* The TWAI peripheral's registers are 8bits, however the ESP32 can only access 18 * peripheral registers every 32bits. Therefore each TWAI register is mapped to 19 * the least significant byte of every 32bits. 20 */ 21 22 typedef volatile struct twai_dev_s { 23 //Configuration and Control Registers 24 union { 25 struct { 26 uint32_t rm: 1; /* MOD.0 Reset Mode */ 27 uint32_t lom: 1; /* MOD.1 Listen Only Mode */ 28 uint32_t stm: 1; /* MOD.2 Self Test Mode */ 29 uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */ 30 uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */ 31 }; 32 uint32_t val; 33 } mode_reg; /* Address 0x0000 */ 34 union { 35 struct { 36 uint32_t tr: 1; /* CMR.0 Transmission Request */ 37 uint32_t at: 1; /* CMR.1 Abort Transmission */ 38 uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */ 39 uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */ 40 uint32_t srr: 1; /* CMR.4 Self Reception Request */ 41 uint32_t reserved5: 27; /* Internal Reserved */ 42 }; 43 uint32_t val; 44 } command_reg; /* Address 0x0004 */ 45 union { 46 struct { 47 uint32_t rbs: 1; /* SR.0 Receive Buffer Status */ 48 uint32_t dos: 1; /* SR.1 Data Overrun Status */ 49 uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */ 50 uint32_t tcs: 1; /* SR.3 Transmission Complete Status */ 51 uint32_t rs: 1; /* SR.4 Receive Status */ 52 uint32_t ts: 1; /* SR.5 Transmit Status */ 53 uint32_t es: 1; /* SR.6 Error Status */ 54 uint32_t bs: 1; /* SR.7 Bus Status */ 55 uint32_t reserved8: 24; /* Internal Reserved */ 56 }; 57 uint32_t val; 58 } status_reg; /* Address 0x0008 */ 59 union { 60 struct { 61 uint32_t ri: 1; /* IR.0 Receive Interrupt */ 62 uint32_t ti: 1; /* IR.1 Transmit Interrupt */ 63 uint32_t ei: 1; /* IR.2 Error Interrupt */ 64 uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */ 65 uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */ 66 uint32_t epi: 1; /* IR.5 Error Passive Interrupt */ 67 uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */ 68 uint32_t bei: 1; /* IR.7 Bus Error Interrupt */ 69 uint32_t reserved8: 24; /* Internal Reserved */ 70 }; 71 uint32_t val; 72 } interrupt_reg; /* Address 0x000C */ 73 union { 74 struct { 75 uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */ 76 uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */ 77 uint32_t eie: 1; /* IER.2 Error Interrupt Enable */ 78 uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */ 79 uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */ 80 uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */ 81 uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */ 82 uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */ 83 uint32_t reserved8: 24; /* Internal Reserved */ 84 }; 85 uint32_t val; 86 } interrupt_enable_reg; /* Address 0x0010 */ 87 uint32_t reserved_14; 88 union { 89 struct { 90 uint32_t brp: 6; /* BTR0[5:0] Baud Rate Prescaler */ 91 uint32_t sjw: 2; /* BTR0[7:6] Synchronization Jump Width*/ 92 uint32_t reserved8: 24; /* Internal Reserved */ 93 }; 94 uint32_t val; 95 } bus_timing_0_reg; /* Address 0x0018 */ 96 union { 97 struct { 98 uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */ 99 uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */ 100 uint32_t sam: 1; /* BTR1.7 Sampling*/ 101 uint32_t reserved8: 24; /* Internal Reserved */ 102 }; 103 uint32_t val; 104 } bus_timing_1_reg; /* Address 0x001C */ 105 uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */ 106 uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */ 107 uint32_t reserved_28; /* Address 0x0028 */ 108 109 //Capture and Counter Registers 110 union { 111 struct { 112 uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */ 113 uint32_t reserved5: 27; /* Internal Reserved */ 114 }; 115 uint32_t val; 116 } arbitration_lost_captue_reg; /* Address 0x002C */ 117 union { 118 struct { 119 uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */ 120 uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */ 121 uint32_t errc: 2; /* ECC[7:6] Error Code */ 122 uint32_t reserved8: 24; /* Internal Reserved */ 123 }; 124 uint32_t val; 125 } error_code_capture_reg; /* Address 0x0030 */ 126 union { 127 struct { 128 uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */ 129 uint32_t reserved8: 24; /* Internal Reserved */ 130 }; 131 uint32_t val; 132 } error_warning_limit_reg; /* Address 0x0034 */ 133 union { 134 struct { 135 uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */ 136 uint32_t reserved8: 24; /* Internal Reserved */ 137 }; 138 uint32_t val; 139 } rx_error_counter_reg; /* Address 0x0038 */ 140 union { 141 struct { 142 uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */ 143 uint32_t reserved8: 24; /* Internal Reserved */ 144 }; 145 uint32_t val; 146 } tx_error_counter_reg; /* Address 0x003C */ 147 148 //Shared Registers (TX Buff/RX Buff/Acc Filter) 149 union { 150 struct { 151 union { 152 struct { 153 uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */ 154 uint32_t reserved8: 24; /* Internal Reserved */ 155 }; 156 uint32_t val; 157 } acr[4]; 158 union { 159 struct { 160 uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */ 161 uint32_t reserved8: 24; /* Internal Reserved */ 162 }; 163 uint32_t val; 164 } amr[4]; 165 uint32_t reserved_60; 166 uint32_t reserved_64; 167 uint32_t reserved_68; 168 uint32_t reserved_6c; 169 uint32_t reserved_70; 170 } acceptance_filter; 171 union { 172 struct { 173 uint32_t byte: 8; /* TX/RX Byte X [7:0] */ 174 uint32_t reserved24: 24; /* Internal Reserved */ 175 }; 176 uint32_t val; 177 } tx_rx_buffer[13]; 178 }; /* Address 0x0040 - 0x0070 */ 179 180 //Misc Registers 181 union { 182 struct { 183 uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */ 184 uint32_t reserved7: 25; /* Internal Reserved */ 185 }; 186 uint32_t val; 187 } rx_message_counter_reg; /* Address 0x0074 */ 188 uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */ 189 union { 190 struct { 191 uint32_t cd: 3; /* CDR[2:0] CLKOUT frequency selector based of fOSC */ 192 uint32_t co: 1; /* CDR.3 CLKOUT enable/disable */ 193 uint32_t reserved4: 3; /* Internal Reserved. RXINTEN and CBP not supported */ 194 uint32_t cm: 1; /* CDR.7 Register Layout. Basic:0 Extended:1 */ 195 uint32_t reserved6: 24; /* Internal Reserved */ 196 }; 197 uint32_t val; 198 } clock_divider_reg; /* Address 0x007C */ 199 } twai_dev_t; 200 201 #ifndef __cplusplus 202 _Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes"); 203 #endif 204 205 extern twai_dev_t TWAI; 206 207 #ifdef __cplusplus 208 } 209 #endif 210
