1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020, 2022~2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_ADC_H__
10 #define FSL_ADC_H__
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup lpc_adc
16 * @{
17 */
18
19 /*! @file */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24
25 /*! @name Driver version */
26 /*! @{ */
27 /*! @brief ADC driver version 2.5.3. */
28 #define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 5,3))
29 /*! @} */
30
31 /*!
32 * @brief Flags
33 */
34
35 enum _adc_status_flags
36 {
37 kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */
38 kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */
39 kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */
40 kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */
41 kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */
42 kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */
43 kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */
44 kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */
45 kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */
46 kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */
47 kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
48 kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
49 kADC_OverrunFlagForChn0 =
50 1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
51 kADC_OverrunFlagForChn1 =
52 1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
53 kADC_OverrunFlagForChn2 =
54 1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
55 kADC_OverrunFlagForChn3 =
56 1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
57 kADC_OverrunFlagForChn4 =
58 1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
59 kADC_OverrunFlagForChn5 =
60 1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
61 kADC_OverrunFlagForChn6 =
62 1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
63 kADC_OverrunFlagForChn7 =
64 1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
65 kADC_OverrunFlagForChn8 =
66 1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
67 kADC_OverrunFlagForChn9 =
68 1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
69 kADC_OverrunFlagForChn10 =
70 1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
71 kADC_OverrunFlagForChn11 =
72 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
73 kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
74 kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
75 kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */
76 kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */
77 kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
78 kADC_OverrunInterruptFlag = (int)(1U << 31U), /*!< Overrun interrupt flag. */
79 };
80
81 /*!
82 * @brief Interrupts
83 * @note Not all the interrupt options are listed here
84 */
85 enum _adc_interrupt_enable
86 {
87 kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
88 conversion in sequence A, or entire sequence. */
89 #if !(defined(FSL_FEATURE_ADC_HAS_SINGLE_SEQ) && FSL_FEATURE_ADC_HAS_SINGLE_SEQ)
90 kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
91 conversion in sequence B, or entire sequence. */
92 #endif /* FSL_FEATURE_ADC_HAS_SINGLE_SEQ */
93 kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
94 the channel data registers will cause an overrun
95 interrupt/DMA trigger. */
96 };
97
98 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) && FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE)
99 /*!
100 * @brief Define selection of clock mode.
101 */
102 typedef enum _adc_clock_mode
103 {
104 kADC_ClockSynchronousMode =
105 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
106 kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
107 } adc_clock_mode_t;
108 #endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
109
110 #if defined(FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) && (FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT)
111 /*!
112 * @brief Define selection of resolution.
113 */
114 typedef enum _adc_resolution
115 {
116 kADC_Resolution6bit = 3U,
117 /*!< 6-bit resolution. */ /* This is a HW issue that the ADC resolution enum configure not align with HW implement,
118 ES2 chip already fixed the issue, Currently, update ADC enum define as a workaround */
119 kADC_Resolution8bit = 2U, /*!< 8-bit resolution. */
120 kADC_Resolution10bit = 1U, /*!< 10-bit resolution. */
121 kADC_Resolution12bit = 0U, /*!< 12-bit resolution. */
122 } adc_resolution_t;
123 #elif defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) && FSL_FEATURE_ADC_HAS_CTRL_RESOL
124 /*!
125 * @brief Define selection of resolution.
126 */
127 typedef enum _adc_resolution
128 {
129 kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */
130 kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */
131 kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
132 kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
133 } adc_resolution_t;
134 #endif
135
136 #if (defined(FSL_FEATURE_ADC_HAS_TRIM_REG) && FSL_FEATURE_ADC_HAS_TRIM_REG)
137 /*!
138 * @brief Definfe range of the analog supply voltage VDDA.
139 */
140 typedef enum _adc_voltage_range
141 {
142 kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */
143 kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */
144 } adc_vdda_range_t;
145 #endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */
146
147 /*!
148 * @brief Define selection of polarity of selected input trigger for conversion sequence.
149 */
150 typedef enum _adc_trigger_polarity
151 {
152 kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
153 kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
154 } adc_trigger_polarity_t;
155
156 /*!
157 * @brief Define selection of conversion sequence's priority.
158 */
159 typedef enum _adc_priority
160 {
161 kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */
162 kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */
163 } adc_priority_t;
164
165 /*!
166 * @brief Define selection of conversion sequence's interrupt.
167 */
168 typedef enum _adc_seq_interrupt_mode
169 {
170 kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
171 individual ADC conversion inside this conversion sequence. */
172 kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of
173 this sequence conversions completes. */
174 } adc_seq_interrupt_mode_t;
175
176 /*!
177 * @brief Define status of threshold compare result.
178 */
179 typedef enum _adc_threshold_compare_status
180 {
181 kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */
182 kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
183 kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
184 } adc_threshold_compare_status_t;
185
186 /*!
187 * @brief Define status of threshold crossing detection result.
188 */
189 typedef enum _adc_threshold_crossing_status
190 {
191 /* The conversion on this channel had the same relationship (above or below) to the threshold value established by
192 * the designated LOW threshold value as did the previous conversion on this channel. */
193 kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
194
195 /* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
196 * channel was above the threshold value established by the designated LOW threshold value and the current sample is
197 * below that threshold. */
198 kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
199
200 /* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
201 * channel was below the threshold value established by the designated LOW threshold value and the current sample is
202 * above that threshold. */
203 kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
204 } adc_threshold_crossing_status_t;
205
206 /*!
207 * @brief Define interrupt mode for threshold compare event.
208 */
209 typedef enum _adc_threshold_interrupt_mode
210 {
211 kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */
212 kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */
213 kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
214 } adc_threshold_interrupt_mode_t;
215
216 /*!
217 * @brief Define the info result mode of different resolution.
218 */
219 typedef enum _adc_inforesultshift
220 {
221 kADC_Resolution12bitInfoResultShift = 0U, /*!< Info result shift of Resolution12bit. */
222 kADC_Resolution10bitInfoResultShift = 2U, /*!< Info result shift of Resolution10bit. */
223 kADC_Resolution8bitInfoResultShift = 4U, /*!< Info result shift of Resolution8bit. */
224 kADC_Resolution6bitInfoResultShift = 6U, /*!< Info result shift of Resolution6bit. */
225 } adc_inforesult_t;
226
227 /*!
228 * @brief Define common modes for Temerature sensor.
229 */
230 typedef enum _adc_tempsensor_common_mode
231 {
232 kADC_HighNegativeOffsetAdded = 0x0U, /*!< Temperature sensor common mode: high negative offset added. */
233 kADC_IntermediateNegativeOffsetAdded =
234 0x4U, /*!< Temperature sensor common mode: intermediate negative offset added. */
235 kADC_NoOffsetAdded = 0x8U, /*!< Temperature sensor common mode: no offset added. */
236 kADC_LowPositiveOffsetAdded = 0xcU, /*!< Temperature sensor common mode: low positive offset added. */
237 } adc_tempsensor_common_mode_t;
238
239 /*!
240 * @brief Define source impedance modes for GPADC control.
241 */
242 typedef enum _adc_second_control
243 {
244 kADC_Impedance621Ohm = 0x1U << 9U, /*!< Extand ADC sampling time according to source impedance 1: 0.621 kOhm. */
245 kADC_Impedance55kOhm =
246 0x14U << 9U, /*!< Extand ADC sampling time according to source impedance 20 (default): 55 kOhm. */
247 kADC_Impedance87kOhm = 0x1fU << 9U, /*!< Extand ADC sampling time according to source impedance 31: 87 kOhm. */
248
249 kADC_NormalFunctionalMode = 0x0U << 14U, /*!< TEST mode: Normal functional mode. */
250 kADC_MultiplexeTestMode = 0x1U << 14U, /*!< TEST mode: Multiplexer test mode. */
251 kADC_ADCInUnityGainMode = 0x2U << 14U, /*!< TEST mode: ADC in unity gain mode. */
252 } adc_second_control_t;
253
254 /*!
255 * @brief Define structure for configuring the block.
256 */
257 typedef struct _adc_config
258 {
259 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) && FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE)
260 adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */
261 #endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */
262 uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
263 field. The divider would be plused by 1 based on the value in this field. The
264 available range is in 8 bits. */
265 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) && FSL_FEATURE_ADC_HAS_CTRL_RESOL)
266 adc_resolution_t resolution; /*!< Select the conversion bits. */
267 #endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */
268 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) && FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL)
269 bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
270 powered-up. Re-calibration may be warranted periodically - especially if
271 operating conditions have changed. To enable this option would avoid the need to
272 calibrate if offset error is not a concern in the application. */
273 #endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */
274 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) && FSL_FEATURE_ADC_HAS_CTRL_TSAMP)
275 uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
276 to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
277 #endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */
278 #if (defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) && FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE)
279 bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are
280 requested.
281 If enable low-power mode, The ADC is automatically powered-down when no conversions are
282 taking place. */
283 #endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */
284 #if (defined(FSL_FEATURE_ADC_HAS_TRIM_REG) && FSL_FEATURE_ADC_HAS_TRIM_REG)
285 adc_vdda_range_t
286 voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA.
287 Failure to set the area correctly causes the ADC to return incorrect conversion results. */
288 #endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */
289 } adc_config_t;
290
291 /*!
292 * @brief Define structure for configuring conversion sequence.
293 */
294 typedef struct _adc_conv_seq_config
295 {
296 uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
297 sequence is launched. The masked channels would be involved in current conversion
298 sequence, beginning with the lowest-order. The available range is in 12-bit. */
299 uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
300 conversion sequence to be initiated. The available range is 6-bit.*/
301 adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to launch conversion sequence. */
302 bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
303 flip-flop stages and therefore shorten the time between the trigger input signal and the
304 start of a conversion. */
305 bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
306 channel in the sequence instead of the default response of launching an entire sequence
307 of conversions. */
308 adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
309 #if (defined(FSL_FEATURE_ADC_HAS_SEQ_CTRL_TSAMP) && FSL_FEATURE_ADC_HAS_SEQ_CTRL_TSAMP)
310 uint8_t seqSampleTimeNumber; /*!< Conversion sequence sampling time.*/
311 #endif /* FSL_FEATURE_ADC_HAS_SEQ_CTRL_TSAMP */
312 } adc_conv_seq_config_t;
313
314 /*!
315 * @brief Define structure of keeping conversion result information.
316 */
317 typedef struct _adc_result_info
318 {
319 uint32_t result; /*!< Keep the conversion data value. */
320 adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */
321 adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
322 uint32_t channelNumber; /*!< Keep the channel number for this conversion. */
323 bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
324 /* The data available flag would be returned by the reading result API. */
325 } adc_result_info_t;
326
327 #if defined(__cplusplus)
328 extern "C" {
329 #endif
330
331 /*******************************************************************************
332 * API
333 ******************************************************************************/
334
335 /*!
336 * @name Initialization and Deinitialization
337 * @{
338 */
339
340 /*!
341 * @brief Initialize the ADC module.
342 *
343 * @param base ADC peripheral base address.
344 * @param config Pointer to configuration structure, see to #adc_config_t.
345 */
346 void ADC_Init(ADC_Type *base, const adc_config_t *config);
347
348 /*!
349 * @brief Deinitialize the ADC module.
350 *
351 * @param base ADC peripheral base address.
352 */
353 void ADC_Deinit(ADC_Type *base);
354
355 /*!
356 * @brief Gets an available pre-defined settings for initial configuration.
357 *
358 * This function initializes the initial configuration structure with an available settings. The default values are:
359 * @code
360 * config->clockMode = kADC_ClockSynchronousMode;
361 * config->clockDividerNumber = 0U;
362 * config->resolution = kADC_Resolution12bit;
363 * config->enableBypassCalibration = false;
364 * config->sampleTimeNumber = 0U;
365 * @endcode
366 * @param config Pointer to configuration structure.
367 */
368 void ADC_GetDefaultConfig(adc_config_t *config);
369
370 #if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC)
371 #if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG
372 /*!
373 * @brief Do the hardware self-calibration.
374 * @deprecated Do not use this function. It has been superceded by @ref ADC_DoOffsetCalibration.
375 *
376 * To calibrate the ADC, set the ADC clock to 500 kHz. In order to achieve the specified ADC accuracy, the A/D
377 * converter must be recalibrated, at a minimum, following every chip reset before initiating normal ADC operation.
378 *
379 * @param base ADC peripheral base address.
380 * @retval true Calibration succeed.
381 * @retval false Calibration failed.
382 */
383 bool ADC_DoSelfCalibration(ADC_Type *base);
384
385 /*!
386 * @brief Do the hardware offset-calibration.
387 *
388 * To calibrate the ADC, set the ADC clock to no more then 30 MHz. In order to achieve the specified ADC accuracy, the
389 * A/D converter must be recalibrated, at a minimum, following every chip reset before initiating normal ADC operation.
390 *
391 * @param base ADC peripheral base address.
392 * @param frequency The clock frequency that ADC operates at.
393 * @retval true Calibration succeed.
394 * @retval false Calibration failed.
395 */
396 bool ADC_DoOffsetCalibration(ADC_Type *base, uint32_t frequency);
397 #else
398 /*!
399 * @brief Do the hardware self-calibration.
400 *
401 * To calibrate the ADC, set the ADC clock to 500 kHz. In order to achieve the specified ADC accuracy, the A/D
402 * converter must be recalibrated, at a minimum, following every chip reset before initiating normal ADC operation.
403 *
404 * @param base ADC peripheral base address.
405 * @param frequency The clock frequency that ADC operates at.
406 * @retval true Calibration succeed.
407 * @retval false Calibration failed.
408 */
409 bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency);
410 #endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */
411 #endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */
412
413 #if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL)
414 /*!
415 * @brief Enable the internal temperature sensor measurement.
416 *
417 * When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
418 * instead of external pin.
419 *
420 * @param base ADC peripheral base address.
421 * @param enable Switcher to enable the feature or not.
422 */
423 #if defined(FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) && (FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP)
424 void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable);
425 #else
ADC_EnableTemperatureSensor(ADC_Type * base,bool enable)426 static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
427 {
428 if (enable)
429 {
430 base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
431 }
432 else
433 {
434 base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
435 }
436 }
437 #endif /* FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP. */
438 #endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */
439 /*! @} */
440
441 /*!
442 * @name Control conversion sequence A.
443 * @{
444 */
445
446 /*!
447 * @brief Enable the conversion sequence A.
448 *
449 * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
450 * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
451 * sequence during changing the sequence's setting.
452 *
453 * @param base ADC peripheral base address.
454 * @param enable Switcher to enable the feature or not.
455 */
ADC_EnableConvSeqA(ADC_Type * base,bool enable)456 static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
457 {
458 if (enable)
459 {
460 base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
461 }
462 else
463 {
464 base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
465 }
466 }
467
468 /*!
469 * @brief Configure the conversion sequence A.
470 *
471 * @param base ADC peripheral base address.
472 * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
473 */
474 void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
475
476 /*!
477 * @brief Do trigger the sequence's conversion by software.
478 *
479 * @param base ADC peripheral base address.
480 */
ADC_DoSoftwareTriggerConvSeqA(ADC_Type * base)481 static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
482 {
483 base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
484 }
485
486 /*!
487 * @brief Enable the burst conversion of sequence A.
488 *
489 * Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
490 * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
491 * currently in process will be completed before cnversions are terminated.
492 * Note that a new sequence could begin just before the burst mode is disabled.
493 *
494 * @param base ADC peripheral base address.
495 * @param enable Switcher to enable this feature.
496 */
ADC_EnableConvSeqABurstMode(ADC_Type * base,bool enable)497 static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
498 {
499 if (enable)
500 {
501 base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
502 }
503 else
504 {
505 base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
506 }
507 }
508
509 #if !(defined(FSL_FEATURE_ADC_HAS_SINGLE_SEQ) && FSL_FEATURE_ADC_HAS_SINGLE_SEQ)
510 /*!
511 * @brief Set the high priority for conversion sequence A.
512 *
513 * @param base ADC peripheral bass address.
514 */
ADC_SetConvSeqAHighPriority(ADC_Type * base)515 static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
516 {
517 base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
518 }
519 #endif /* FSL_FEATURE_ADC_HAS_SINGLE_SEQ */
520
521 /*! @} */
522
523 #if !(defined(FSL_FEATURE_ADC_HAS_SINGLE_SEQ) && FSL_FEATURE_ADC_HAS_SINGLE_SEQ)
524 /*!
525 * @name Control conversion sequence B.
526 * @{
527 */
528
529 /*!
530 * @brief Enable the conversion sequence B.
531 *
532 * In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
533 * sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
534 * sequence during changing the sequence's setting.
535 *
536 * @param base ADC peripheral base address.
537 * @param enable Switcher to enable the feature or not.
538 */
ADC_EnableConvSeqB(ADC_Type * base,bool enable)539 static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
540 {
541 if (enable)
542 {
543 base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
544 }
545 else
546 {
547 base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
548 }
549 }
550
551 /*!
552 * @brief Configure the conversion sequence B.
553 *
554 * @param base ADC peripheral base address.
555 * @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
556 */
557 void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
558
559 /*!
560 * @brief Do trigger the sequence's conversion by software.
561 *
562 * @param base ADC peripheral base address.
563 */
ADC_DoSoftwareTriggerConvSeqB(ADC_Type * base)564 static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
565 {
566 base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
567 }
568
569 /*!
570 * @brief Enable the burst conversion of sequence B.
571 *
572 * Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
573 * ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
574 * currently in process will be completed before cnversions are terminated.
575 * Note that a new sequence could begin just before the burst mode is disabled.
576 *
577 * @param base ADC peripheral base address.
578 * @param enable Switcher to enable this feature.
579 */
ADC_EnableConvSeqBBurstMode(ADC_Type * base,bool enable)580 static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
581 {
582 if (enable)
583 {
584 base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
585 }
586 else
587 {
588 base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
589 }
590 }
591
592 /*!
593 * @brief Set the high priority for conversion sequence B.
594 *
595 * @param base ADC peripheral bass address.
596 */
ADC_SetConvSeqBHighPriority(ADC_Type * base)597 static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
598 {
599 base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
600 }
601
602 /*! @} */
603 #endif /* FSL_FEATURE_ADC_HAS_SINGLE_SEQ */
604
605 /*!
606 * @name Data result.
607 * @{
608 */
609
610 /*!
611 * @brief Get the global ADC conversion infomation of sequence A.
612 *
613 * @param base ADC peripheral base address.
614 * @param info Pointer to information structure, see to #adc_result_info_t;
615 * @retval true The conversion result is ready.
616 * @retval false The conversion result is not ready yet.
617 */
618 bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
619
620 #if !(defined(FSL_FEATURE_ADC_HAS_SINGLE_SEQ) && FSL_FEATURE_ADC_HAS_SINGLE_SEQ)
621 /*!
622 * @brief Get the global ADC conversion infomation of sequence B.
623 *
624 * @param base ADC peripheral base address.
625 * @param info Pointer to information structure, see to #adc_result_info_t;
626 * @retval true The conversion result is ready.
627 * @retval false The conversion result is not ready yet.
628 */
629 bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
630 #endif /* FSL_FEATURE_ADC_HAS_SINGLE_SEQ */
631
632 /*!
633 * @brief Get the channel's ADC conversion completed under each conversion sequence.
634 *
635 * @param base ADC peripheral base address.
636 * @param channel The indicated channel number.
637 * @param info Pointer to information structure, see to #adc_result_info_t;
638 * @retval true The conversion result is ready.
639 * @retval false The conversion result is not ready yet.
640 */
641 bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
642
643 /*! @} */
644
645 /*!
646 * @name Threshold function.
647 * @{
648 */
649
650 /*!
651 * @brief Set the threshhold pair 0 with low and high value.
652 *
653 * @param base ADC peripheral base address.
654 * @param lowValue LOW threshold value.
655 * @param highValue HIGH threshold value.
656 */
ADC_SetThresholdPair0(ADC_Type * base,uint32_t lowValue,uint32_t highValue)657 static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
658 {
659 base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
660 base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
661 }
662
663 /*!
664 * @brief Set the threshhold pair 1 with low and high value.
665 *
666 * @param base ADC peripheral base address.
667 * @param lowValue LOW threshold value. The available value is with 12-bit.
668 * @param highValue HIGH threshold value. The available value is with 12-bit.
669 */
ADC_SetThresholdPair1(ADC_Type * base,uint32_t lowValue,uint32_t highValue)670 static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
671 {
672 base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
673 base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
674 }
675
676 /*!
677 * @brief Set given channels to apply the threshold pare 0.
678 *
679 * @param base ADC peripheral base address.
680 * @param channelMask Indicated channels' mask.
681 */
ADC_SetChannelWithThresholdPair0(ADC_Type * base,uint32_t channelMask)682 static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
683 {
684 base->CHAN_THRSEL &= ~(channelMask);
685 }
686
687 /*!
688 * @brief Set given channels to apply the threshold pare 1.
689 *
690 * @param base ADC peripheral base address.
691 * @param channelMask Indicated channels' mask.
692 */
ADC_SetChannelWithThresholdPair1(ADC_Type * base,uint32_t channelMask)693 static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
694 {
695 base->CHAN_THRSEL |= channelMask;
696 }
697
698 /*! @} */
699
700 /*!
701 * @name Interrupts.
702 * @{
703 */
704
705 /*!
706 * @brief Enable interrupts for conversion sequences.
707 *
708 * @param base ADC peripheral base address.
709 * @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
710 */
ADC_EnableInterrupts(ADC_Type * base,uint32_t mask)711 static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
712 {
713 base->INTEN |= (0x7UL & mask);
714 }
715
716 /*!
717 * @brief Disable interrupts for conversion sequence.
718 *
719 * @param base ADC peripheral base address.
720 * @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
721 */
ADC_DisableInterrupts(ADC_Type * base,uint32_t mask)722 static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
723 {
724 base->INTEN &= ~(0x7UL & mask);
725 }
726
727 /*!
728 * @brief Enable the interrupt of threshold compare event for each channel.
729 *
730 * @param base ADC peripheral base address.
731 * @param channel Channel number.
732 * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
733 */
ADC_EnableThresholdCompareInterrupt(ADC_Type * base,uint32_t channel,adc_threshold_interrupt_mode_t mode)734 static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base,
735 uint32_t channel,
736 adc_threshold_interrupt_mode_t mode)
737 {
738 base->INTEN = (base->INTEN & ~(0x3UL << ((channel << 1UL) + 3UL))) | ((uint32_t)(mode) << ((channel << 1UL) + 3UL));
739 }
740
741 /*! @} */
742
743 /*!
744 * @name Status.
745 * @{
746 */
747
748 /*!
749 * @brief Get status flags of ADC module.
750 *
751 * @param base ADC peripheral base address.
752 * @return Mask of status flags of module, see to #_adc_status_flags.
753 */
ADC_GetStatusFlags(ADC_Type * base)754 static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
755 {
756 return base->FLAGS;
757 }
758
759 /*!
760 * @brief Clear status flags of ADC module.
761 *
762 * @param base ADC peripheral base address.
763 * @param mask Mask of status flags of module, see to #_adc_status_flags.
764 */
ADC_ClearStatusFlags(ADC_Type * base,uint32_t mask)765 static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
766 {
767 base->FLAGS = mask; /* Write 1 to clear. */
768 }
769
770 /*! @} */
771
772 #if defined(__cplusplus)
773 }
774 #endif
775
776 /*! @} */
777
778 #endif /* FSL_ADC_H__ */
779
