1/*
2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
3 * an affiliate of Cypress Semiconductor Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9/ {
10	clocks {
11
12		/* imo */
13		clk_imo: clk_imo {
14			#clock-cells = <0>;
15			compatible = "fixed-clock";
16			clock-frequency = <8000000>;
17			status = "okay";
18		};
19
20		/* path mux0 */
21		path_mux0: path_mux0 {
22			#clock-cells = <0>;
23			compatible = "fixed-factor-clock";
24			clocks = <&clk_imo>;
25			status = "okay";
26		};
27
28		/* path mux1 */
29		path_mux1: path_mux1 {
30			#clock-cells = <0>;
31			compatible = "fixed-factor-clock";
32			clocks = <&clk_imo>;
33			status = "okay";
34		};
35
36		/* path mux2 */
37		path_mux2: path_mux2 {
38			#clock-cells = <0>;
39			compatible = "fixed-factor-clock";
40			clocks = <&clk_imo>;
41			status = "disabled";
42		};
43
44		/* path mux3 */
45		path_mux3: path_mux3 {
46			#clock-cells = <0>;
47			compatible = "fixed-factor-clock";
48			clocks = <&clk_imo>;
49			status = "disabled";
50		};
51
52		/* path mux4 */
53		path_mux4: path_mux4 {
54			#clock-cells = <0>;
55			compatible = "fixed-factor-clock";
56			clocks = <&clk_imo>;
57			status = "disabled";
58		};
59
60		/* fll */
61		fll0: fll0 {
62			#clock-cells = <0>;
63			compatible = "fixed-clock";
64			/* clock-frequency = <100000000>; */
65			status = "okay";
66		};
67
68		/* pll0 configuration */
69		pll0: pll0 {
70			#clock-cells = <0>;
71			compatible = "fixed-clock";
72			/* clock-frequency = <150000000>; */
73			status = "disabled";
74		};
75
76		/* clk_hf0 */
77		clk_hf0: clk_hf0 {
78			#clock-cells = <0>;
79			compatible = "fixed-factor-clock";
80			clock-div = <1>;
81			clocks = <&fll0>;
82			status = "okay";
83		};
84
85		/* clk_hf1 */
86		clk_hf1: clk_hf1 {
87			#clock-cells = <0>;
88			compatible = "fixed-factor-clock";
89			clock-div = <1>;
90			clocks = <&path_mux1>;
91			status = "disabled";
92		};
93
94		/* clk_hf2 */
95		clk_hf2: clk_hf2 {
96			#clock-cells = <0>;
97			compatible = "fixed-factor-clock";
98			clock-div = <1>;
99			clocks = <&path_mux2>;
100			status = "disabled";
101		};
102
103		/* clk_hf3 */
104		clk_hf3: clk_hf3 {
105			#clock-cells = <0>;
106			compatible = "fixed-factor-clock";
107			clock-div = <1>;
108			clocks = <&path_mux3>;
109			status = "disabled";
110		};
111
112		/* clk_hf4 */
113		clk_hf4: clk_hf4 {
114			#clock-cells = <0>;
115			compatible = "fixed-factor-clock";
116			clock-div = <1>;
117			clocks = <&path_mux4>;
118			status = "disabled";
119		};
120
121		/* clk_fast */
122		clk_fast: clk_fast {
123			#clock-cells = <0>;
124			compatible = "fixed-factor-clock";
125			clock-div = <1>;
126			status = "okay";
127		};
128
129		/* clk_slow */
130		clk_slow: clk_slow {
131			#clock-cells = <0>;
132			compatible = "fixed-factor-clock";
133			clock-div = <1>;
134			status = "okay";
135		};
136
137		/* clk_peri */
138		clk_peri: clk_peri {
139			#clock-cells = <0>;
140			compatible = "fixed-factor-clock";
141			clock-div = <1>;
142			status = "okay";
143		};
144	};
145
146};
147