1/* 2 * Copyright (c) 2023-2024 Analog Devices, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/clock/adi_max32_clock.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11#include <zephyr/dt-bindings/adc/adc.h> 12 13#include <freq.h> 14 15/ { 16 chosen { 17 zephyr,entropy = &trng; 18 zephyr,flash-controller = &flc0; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-m4f"; 28 reg = <0>; 29 }; 30 }; 31 32 clocks { 33 clk_ipo: clk_ipo { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <DT_FREQ_M(100)>; 37 status = "disabled"; 38 }; 39 40 clk_iso: clk_iso { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <DT_FREQ_M(60)>; 44 status = "disabled"; 45 }; 46 47 clk_inro: clk_inro { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <DT_FREQ_K(8)>; 51 status = "disabled"; 52 }; 53 54 clk_ibro: clk_ibro { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <7372800>; 58 status = "disabled"; 59 }; 60 61 clk_ertco: clk_ertco { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <32768>; 65 status = "disabled"; 66 }; 67 68 clk_erfo: clk_erfo { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <DT_FREQ_M(32)>; 72 status = "disabled"; 73 }; 74 }; 75 76 soc { 77 sram0: memory@20000000 { 78 compatible = "mmio-sram"; 79 reg = <0x20000000 DT_SIZE_K(32)>; 80 }; 81 82 flc0: flash_controller@40029000 { 83 compatible = "adi,max32-flash-controller"; 84 reg = <0x40029000 0x400>; 85 86 #address-cells = <1>; 87 #size-cells = <1>; 88 status = "okay"; 89 90 flash0: flash@10000000 { 91 compatible = "soc-nv-flash"; 92 reg = <0x10000000 DT_SIZE_K(512)>; 93 write-block-size = <16>; 94 erase-block-size = <8192>; 95 }; 96 }; 97 98 gcr: clock-controller@40000000 { 99 reg = <0x40000000 0x400>; 100 compatible = "adi,max32-gcr"; 101 #clock-cells = <2>; 102 clocks = <&clk_ipo>; 103 sysclk-prescaler = <1>; 104 status = "okay"; 105 }; 106 107 i2c0: i2c0@4001d000 { 108 compatible = "adi,max32-i2c"; 109 reg = <0x4001d000 0x1000>; 110 #address-cells = <1>; 111 #size-cells = <0>; 112 clock-frequency = <I2C_BITRATE_STANDARD>; 113 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 13>; 114 interrupts = <13 0>; 115 status = "disabled"; 116 }; 117 118 i2c1: i2c1@4001e000 { 119 compatible = "adi,max32-i2c"; 120 reg = <0x4001e000 0x1000>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 clock-frequency = <I2C_BITRATE_STANDARD>; 124 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 28>; 125 interrupts = <36 0>; 126 status = "disabled"; 127 }; 128 129 i2c2: i2c2@4001f000 { 130 compatible = "adi,max32-i2c"; 131 reg = <0x4001f000 0x1000>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 clock-frequency = <I2C_BITRATE_STANDARD>; 135 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 24>; 136 interrupts = <62 0>; 137 status = "disabled"; 138 }; 139 140 pinctrl: pin-controller@40008000 { 141 compatible = "adi,max32-pinctrl"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 reg = <0x40008000 0x2000>; 145 146 gpio0: gpio@40008000 { 147 reg = <0x40008000 0x1000>; 148 compatible = "adi,max32-gpio"; 149 gpio-controller; 150 #gpio-cells = <2>; 151 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>; 152 interrupts = <24 0>; 153 status = "disabled"; 154 }; 155 156 gpio1: gpio@40009000 { 157 reg = <0x40009000 0x1000>; 158 compatible = "adi,max32-gpio"; 159 gpio-controller; 160 #gpio-cells = <2>; 161 interrupts = <25 0>; 162 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 1>; 163 status = "disabled"; 164 }; 165 }; 166 167 uart0: serial@40042000 { 168 compatible = "adi,max32-uart"; 169 reg = <0x40042000 0x1000>; 170 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>; 171 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 172 interrupts = <14 0>; 173 status = "disabled"; 174 }; 175 176 uart1: serial@40043000 { 177 compatible = "adi,max32-uart"; 178 reg = <0x40043000 0x1000>; 179 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 10>; 180 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 181 interrupts = <15 0>; 182 status = "disabled"; 183 }; 184 185 uart2: serial@40044000 { 186 compatible = "adi,max32-uart"; 187 reg = <0x40044000 0x1000>; 188 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 1>; 189 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 190 interrupts = <34 0>; 191 status = "disabled"; 192 }; 193 194 trng: trng@4004d000 { 195 compatible = "adi,max32-trng"; 196 reg = <0x4004d000 0x1000>; 197 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>; 198 status = "disabled"; 199 }; 200 201 wdt0: watchdog@40003000 { 202 compatible = "adi,max32-watchdog"; 203 reg = <0x40003000 0x400>; 204 interrupts = <1 0>; 205 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 27>; 206 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 207 status = "disabled"; 208 }; 209 210 adc: adc@40034000 { 211 compatible = "adi,max32-adc-10b", "adi,max32-adc"; 212 reg = <0x40034000 0x1000>; 213 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 23>; 214 channel-count = <17>; 215 #io-channel-cells = <1>; 216 interrupts = <20 0>; 217 resolution = <10>; 218 vref-mv = <1220>; 219 status = "disabled"; 220 }; 221 222 timer0: timer@40010000 { 223 compatible = "adi,max32-timer"; 224 reg = <0x40010000 0x1000>; 225 interrupts = <5 0>; 226 status = "disabled"; 227 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 15>; 228 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 229 prescaler = <1>; 230 counter { 231 compatible = "adi,max32-counter"; 232 status = "disabled"; 233 }; 234 pwm { 235 compatible = "adi,max32-pwm"; 236 status = "disabled"; 237 #pwm-cells = <3>; 238 }; 239 }; 240 241 timer1: timer@40011000 { 242 compatible = "adi,max32-timer"; 243 reg = <0x40011000 0x1000>; 244 interrupts = <6 0>; 245 status = "disabled"; 246 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 16>; 247 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 248 prescaler = <1>; 249 counter { 250 compatible = "adi,max32-counter"; 251 status = "disabled"; 252 }; 253 pwm { 254 compatible = "adi,max32-pwm"; 255 status = "disabled"; 256 #pwm-cells = <3>; 257 }; 258 }; 259 260 timer2: timer@40012000 { 261 compatible = "adi,max32-timer"; 262 reg = <0x40012000 0x1000>; 263 interrupts = <7 0>; 264 status = "disabled"; 265 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 17>; 266 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 267 prescaler = <1>; 268 counter { 269 compatible = "adi,max32-counter"; 270 status = "disabled"; 271 }; 272 pwm { 273 compatible = "adi,max32-pwm"; 274 status = "disabled"; 275 #pwm-cells = <3>; 276 }; 277 }; 278 279 timer3: timer@40013000 { 280 compatible = "adi,max32-timer"; 281 reg = <0x40013000 0x1000>; 282 interrupts = <8 0>; 283 status = "disabled"; 284 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 18>; 285 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 286 prescaler = <1>; 287 counter { 288 compatible = "adi,max32-counter"; 289 status = "disabled"; 290 }; 291 pwm { 292 compatible = "adi,max32-pwm"; 293 status = "disabled"; 294 #pwm-cells = <3>; 295 }; 296 }; 297 298 rtc_counter: rtc_counter@40006000 { 299 compatible = "adi,max32-rtc-counter"; 300 reg = <0x40006000 0x400>; 301 interrupts = <3 0>; 302 status = "disabled"; 303 }; 304 }; 305}; 306 307&nvic { 308 arm,num-irq-priority-bits = <3>; 309}; 310
