1/* 2 * Copyright (c) 2023-2024 Analog Devices, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <mem.h> 8#include <zephyr/dt-bindings/gpio/gpio.h> 9#include <zephyr/dt-bindings/clock/adi_max32_clock.h> 10#include <zephyr/dt-bindings/i2c/i2c.h> 11 12#include <freq.h> 13 14/ { 15 chosen { 16 zephyr,entropy = &trng; 17 zephyr,flash-controller = &flc0; 18 }; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-m4f"; 27 reg = <0>; 28 }; 29 }; 30 31 clocks { 32 clk_ipo: clk_ipo { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <DT_FREQ_M(100)>; 36 status = "disabled"; 37 }; 38 39 clk_iso: clk_iso { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <DT_FREQ_M(60)>; 43 status = "disabled"; 44 }; 45 46 clk_inro: clk_inro { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <DT_FREQ_K(8)>; 50 status = "disabled"; 51 }; 52 53 clk_ibro: clk_ibro { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <7372800>; 57 status = "disabled"; 58 }; 59 60 clk_ertco: clk_ertco { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <32768>; 64 status = "disabled"; 65 }; 66 67 clk_erfo: clk_erfo { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <DT_FREQ_M(32)>; 71 status = "disabled"; 72 }; 73 }; 74 75 soc { 76 sram0: memory@20000000 { 77 compatible = "mmio-sram"; 78 reg = <0x20000000 DT_SIZE_K(32)>; 79 }; 80 81 flc0: flash_controller@40029000 { 82 compatible = "flash-controller"; 83 reg = <0x40029000 0x400>; 84 85 #address-cells = <1>; 86 #size-cells = <1>; 87 status = "okay"; 88 89 flash0: flash@10000000 { 90 compatible = "soc-nv-flash"; 91 reg = <0x10000000 DT_SIZE_K(512)>; 92 write-block-size = <16>; 93 erase-block-size = <8192>; 94 }; 95 }; 96 97 gcr: clock-controller@40000000 { 98 reg = <0x40000000 0x400>; 99 compatible = "adi,max32-gcr"; 100 #clock-cells = <2>; 101 clocks = <&clk_ipo>; 102 sysclk-prescaler = <1>; 103 status = "okay"; 104 }; 105 106 i2c0: i2c0@4001d000 { 107 compatible = "adi,max32-i2c"; 108 reg = <0x4001d000 0x1000>; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 clock-frequency = <I2C_BITRATE_STANDARD>; 112 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 13>; 113 interrupts = <13 0>; 114 status = "disabled"; 115 }; 116 117 i2c1: i2c1@4001e000 { 118 compatible = "adi,max32-i2c"; 119 reg = <0x4001e000 0x1000>; 120 #address-cells = <1>; 121 #size-cells = <0>; 122 clock-frequency = <I2C_BITRATE_STANDARD>; 123 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 28>; 124 interrupts = <36 0>; 125 status = "disabled"; 126 }; 127 128 i2c2: i2c2@4001f000 { 129 compatible = "adi,max32-i2c"; 130 reg = <0x4001f000 0x1000>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 clock-frequency = <I2C_BITRATE_STANDARD>; 134 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 24>; 135 interrupts = <62 0>; 136 status = "disabled"; 137 }; 138 139 pinctrl: pin-controller@40008000 { 140 compatible = "adi,max32-pinctrl"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 reg = <0x40008000 0x2000>; 144 145 gpio0: gpio@40008000 { 146 reg = <0x40008000 0x1000>; 147 compatible = "adi,max32-gpio"; 148 gpio-controller; 149 #gpio-cells = <2>; 150 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 0>; 151 interrupts = <24 0>; 152 status = "disabled"; 153 }; 154 155 gpio1: gpio@40009000 { 156 reg = <0x40009000 0x1000>; 157 compatible = "adi,max32-gpio"; 158 gpio-controller; 159 #gpio-cells = <2>; 160 interrupts = <25 0>; 161 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 1>; 162 status = "disabled"; 163 }; 164 }; 165 166 uart0: serial@40042000 { 167 compatible = "adi,max32-uart"; 168 reg = <0x40042000 0x1000>; 169 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 9>; 170 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 171 interrupts = <14 0>; 172 status = "disabled"; 173 }; 174 175 uart1: serial@40043000 { 176 compatible = "adi,max32-uart"; 177 reg = <0x40043000 0x1000>; 178 clocks = <&gcr ADI_MAX32_CLOCK_BUS0 10>; 179 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 180 interrupts = <15 0>; 181 status = "disabled"; 182 }; 183 184 uart2: serial@40044000 { 185 compatible = "adi,max32-uart"; 186 reg = <0x40044000 0x1000>; 187 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 1>; 188 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>; 189 interrupts = <34 0>; 190 status = "disabled"; 191 }; 192 193 trng: trng@4004d000 { 194 compatible = "adi,max32-trng"; 195 reg = <0x4004d000 0x1000>; 196 clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>; 197 status = "disabled"; 198 }; 199 }; 200}; 201 202&nvic { 203 arm,num-irq-priority-bits = <3>; 204}; 205
