Searched defs:clkDiv (Results 1 – 9 of 9) sorted by relevance
| /hal_infineon-3.6.0/mtb-pdl-cat1/drivers/include/ |
| D | cy_crypto_core_trng.h | 174 #define CY_CRYPTO_IS_SMPL_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 255U) argument
175 #define CY_CRYPTO_IS_RED_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 255U) argument
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| D | cy_tdm.h | 325 …uint16_t clkDiv; /**< Should be set to an even value ({2, 4, 6, … member
350 …uint16_t clkDiv; /**< Should be set to an even value ({2, 4, 6, … member
435 #define CY_TDM_IS_CLK_DIV_VALID(clkDiv) (clkDiv <= 255U) argument
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| D | cy_pdm_pcm.h | 332 …cy_en_pdm_pcm_clk_div_t clkDiv; /**< PDM Clock Divider (1st divider), see #cy_en_pdm… member
413 #define CY_PDM_PCM_IS_CLK_DIV_VALID(clkDiv) (((clkDiv) == CY_PDM_PCM_CLK_DIV_BYPASS) || \ argument
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| D | cy_cryptolite_trng.h | 228 #define CY_CRYPTOLITE_IS_SMPL_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 255U) argument
229 #define CY_CRYPTOLITE_IS_RED_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 255U) argument
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| D | cy_i2s.h | 329 …uint8_t clkDiv; /**< CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, ..., 64… member
498 #define CY_I2S_IS_CLK_DIV_VALID(clkDiv) ((clkDiv) <= 63U) argument
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| D | cy_pdm_pcm_v2.h | 366 uint8_t clkDiv; /**< PDM Clock Divider member
479 #define CY_PDM_PCM_IS_CLK_DIV_VALID(clkDiv) (((clkDiv) >= 1U) && ((clkDiv) <= CY_PDM_PCM_CLK_DI… argument
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| /hal_infineon-3.6.0/mtb-hal-cat1/source/ |
| D | cyhal_pdmpcm.c | 905 … uint8_t clkDiv = 0u; /* Per hw definition, this should be 1 less than the actual desired divide */ in _cyhal_pdm_pcm_set_pdl_config_struct() local
1520 uint8_t clkDiv = _FLD2VAL(PDM_CLOCK_CTL_CLOCK_DIV, PDM_PCM_CLOCK_CTL(obj->base)); in cyhal_pdm_pcm_set_gain() local
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| /hal_infineon-3.6.0/mtb-pdl-cat1/drivers/source/ |
| D | cy_ethif.c | 1261 uint32_t mode, srcSel, clkDiv; in Cy_ETHIF_WrapperConfig() local
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| D | cy_sd_host.c | 2852 uint32_t clkDiv; in Cy_SD_Host_SdCardChangeClock() local
4295 cy_en_sd_host_status_t Cy_SD_Host_SetSdClkDiv(SDHC_Type *base, uint16_t clkDiv) in Cy_SD_Host_SetSdClkDiv()
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