1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Type of blk0_rdata0 register */ 14 typedef union { 15 struct { 16 /** rd_efuse_wr_dis : R; bitpos: [15:0]; default: 0; 17 * read for efuse_wr_disable 18 */ 19 uint32_t rd_efuse_wr_dis:16; 20 /** rd_efuse_rd_dis : R; bitpos: [19:16]; default: 0; 21 * read for efuse_rd_disable 22 */ 23 uint32_t rd_efuse_rd_dis:4; 24 /** rd_flash_crypt_cnt : R; bitpos: [26:20]; default: 0; 25 * read for flash_crypt_cnt 26 */ 27 uint32_t rd_flash_crypt_cnt:7; 28 /** rd_uart_download_dis : R; bitpos: [27]; default: 0; 29 * Disable UART download mode. Valid for ESP32 V3 and newer, only 30 */ 31 uint32_t rd_uart_download_dis:1; 32 /** reserved_0_28 : R; bitpos: [31:28]; default: 0; 33 * reserved 34 */ 35 uint32_t reserved_0_28:4; 36 }; 37 uint32_t val; 38 } efuse_blk0_rdata0_reg_t; 39 40 /** Type of blk0_rdata1 register */ 41 typedef union { 42 struct { 43 /** rd_mac : R; bitpos: [31:0]; default: 0; 44 * MAC address 45 */ 46 uint32_t rd_mac:32; 47 }; 48 uint32_t val; 49 } efuse_blk0_rdata1_reg_t; 50 51 /** Type of blk0_rdata2 register */ 52 typedef union { 53 struct { 54 /** rd_mac_1 : R; bitpos: [15:0]; default: 0; 55 * MAC address 56 */ 57 uint32_t rd_mac_1:16; 58 /** rd_mac_crc : R; bitpos: [23:16]; default: 0; 59 * CRC8 for MAC address 60 */ 61 uint32_t rd_mac_crc:8; 62 /** rd_reserve_0_88 : RW; bitpos: [31:24]; default: 0; 63 * Reserved, it was created by set_missed_fields_in_regs func 64 */ 65 uint32_t rd_reserve_0_88:8; 66 }; 67 uint32_t val; 68 } efuse_blk0_rdata2_reg_t; 69 70 /** Type of blk0_rdata3 register */ 71 typedef union { 72 struct { 73 /** rd_disable_app_cpu : R; bitpos: [0]; default: 0; 74 * Disables APP CPU 75 */ 76 uint32_t rd_disable_app_cpu:1; 77 /** rd_disable_bt : R; bitpos: [1]; default: 0; 78 * Disables Bluetooth 79 */ 80 uint32_t rd_disable_bt:1; 81 /** rd_chip_package_4bit : R; bitpos: [2]; default: 0; 82 * Chip package identifier #4bit 83 */ 84 uint32_t rd_chip_package_4bit:1; 85 /** rd_dis_cache : R; bitpos: [3]; default: 0; 86 * Disables cache 87 */ 88 uint32_t rd_dis_cache:1; 89 /** rd_spi_pad_config_hd : R; bitpos: [8:4]; default: 0; 90 * read for SPI_pad_config_hd 91 */ 92 uint32_t rd_spi_pad_config_hd:5; 93 /** rd_chip_package : RW; bitpos: [11:9]; default: 0; 94 * Chip package identifier 95 */ 96 uint32_t rd_chip_package:3; 97 /** rd_chip_cpu_freq_low : RW; bitpos: [12]; default: 0; 98 * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is 99 * rated for 160MHz. 240MHz otherwise 100 */ 101 uint32_t rd_chip_cpu_freq_low:1; 102 /** rd_chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; 103 * If set, the ESP32's maximum CPU frequency has been rated 104 */ 105 uint32_t rd_chip_cpu_freq_rated:1; 106 /** rd_blk3_part_reserve : RW; bitpos: [14]; default: 0; 107 * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 108 */ 109 uint32_t rd_blk3_part_reserve:1; 110 /** rd_chip_ver_rev1 : RW; bitpos: [15]; default: 0; 111 * bit is set to 1 for rev1 silicon 112 */ 113 uint32_t rd_chip_ver_rev1:1; 114 /** rd_reserve_0_112 : RW; bitpos: [31:16]; default: 0; 115 * Reserved, it was created by set_missed_fields_in_regs func 116 */ 117 uint32_t rd_reserve_0_112:16; 118 }; 119 uint32_t val; 120 } efuse_blk0_rdata3_reg_t; 121 122 /** Type of blk0_rdata4 register */ 123 typedef union { 124 struct { 125 /** rd_clk8m_freq : R; bitpos: [7:0]; default: 0; 126 * 8MHz clock freq override 127 */ 128 uint32_t rd_clk8m_freq:8; 129 /** rd_adc_vref : RW; bitpos: [12:8]; default: 0; 130 * True ADC reference voltage 131 */ 132 uint32_t rd_adc_vref:5; 133 /** rd_reserve_0_141 : RW; bitpos: [13]; default: 0; 134 * Reserved, it was created by set_missed_fields_in_regs func 135 */ 136 uint32_t rd_reserve_0_141:1; 137 /** rd_xpd_sdio_reg : R; bitpos: [14]; default: 0; 138 * read for XPD_SDIO_REG 139 */ 140 uint32_t rd_xpd_sdio_reg:1; 141 /** rd_xpd_sdio_tieh : R; bitpos: [15]; default: 0; 142 * If XPD_SDIO_FORCE & XPD_SDIO_REG 143 */ 144 uint32_t rd_xpd_sdio_tieh:1; 145 /** rd_xpd_sdio_force : R; bitpos: [16]; default: 0; 146 * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset 147 */ 148 uint32_t rd_xpd_sdio_force:1; 149 /** rd_reserve_0_145 : RW; bitpos: [31:17]; default: 0; 150 * Reserved, it was created by set_missed_fields_in_regs func 151 */ 152 uint32_t rd_reserve_0_145:15; 153 }; 154 uint32_t val; 155 } efuse_blk0_rdata4_reg_t; 156 157 /** Type of blk0_rdata5 register */ 158 typedef union { 159 struct { 160 /** rd_spi_pad_config_clk : R; bitpos: [4:0]; default: 0; 161 * read for SPI_pad_config_clk 162 */ 163 uint32_t rd_spi_pad_config_clk:5; 164 /** rd_spi_pad_config_q : R; bitpos: [9:5]; default: 0; 165 * read for SPI_pad_config_q 166 */ 167 uint32_t rd_spi_pad_config_q:5; 168 /** rd_spi_pad_config_d : R; bitpos: [14:10]; default: 0; 169 * read for SPI_pad_config_d 170 */ 171 uint32_t rd_spi_pad_config_d:5; 172 /** rd_spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; 173 * read for SPI_pad_config_cs0 174 */ 175 uint32_t rd_spi_pad_config_cs0:5; 176 /** rd_chip_ver_rev2 : R; bitpos: [20]; default: 0; */ 177 uint32_t rd_chip_ver_rev2:1; 178 /** rd_reserve_0_181 : RW; bitpos: [21]; default: 0; 179 * Reserved, it was created by set_missed_fields_in_regs func 180 */ 181 uint32_t rd_reserve_0_181:1; 182 /** rd_vol_level_hp_inv : R; bitpos: [23:22]; default: 0; 183 * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM 184 * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 185 */ 186 uint32_t rd_vol_level_hp_inv:2; 187 /** rd_wafer_version_minor : R; bitpos: [25:24]; default: 0; */ 188 uint32_t rd_wafer_version_minor:2; 189 /** rd_reserve_0_186 : RW; bitpos: [27:26]; default: 0; 190 * Reserved, it was created by set_missed_fields_in_regs func 191 */ 192 uint32_t rd_reserve_0_186:2; 193 /** rd_flash_crypt_config : R; bitpos: [31:28]; default: 0; 194 * read for flash_crypt_config 195 */ 196 uint32_t rd_flash_crypt_config:4; 197 }; 198 uint32_t val; 199 } efuse_blk0_rdata5_reg_t; 200 201 /** Type of blk0_rdata6 register */ 202 typedef union { 203 struct { 204 /** rd_coding_scheme : R; bitpos: [1:0]; default: 0; 205 * read for coding_scheme 206 */ 207 uint32_t rd_coding_scheme:2; 208 /** rd_console_debug_disable : R; bitpos: [2]; default: 0; 209 * read for console_debug_disable 210 */ 211 uint32_t rd_console_debug_disable:1; 212 /** rd_disable_sdio_host : R; bitpos: [3]; default: 0; */ 213 uint32_t rd_disable_sdio_host:1; 214 /** rd_abs_done_0 : R; bitpos: [4]; default: 0; 215 * read for abstract_done_0 216 */ 217 uint32_t rd_abs_done_0:1; 218 /** rd_abs_done_1 : R; bitpos: [5]; default: 0; 219 * read for abstract_done_1 220 */ 221 uint32_t rd_abs_done_1:1; 222 /** rd_jtag_disable : R; bitpos: [6]; default: 0; 223 * Disable JTAG 224 */ 225 uint32_t rd_jtag_disable:1; 226 /** rd_disable_dl_encrypt : R; bitpos: [7]; default: 0; 227 * read for download_dis_encrypt 228 */ 229 uint32_t rd_disable_dl_encrypt:1; 230 /** rd_disable_dl_decrypt : R; bitpos: [8]; default: 0; 231 * read for download_dis_decrypt 232 */ 233 uint32_t rd_disable_dl_decrypt:1; 234 /** rd_disable_dl_cache : R; bitpos: [9]; default: 0; 235 * read for download_dis_cache 236 */ 237 uint32_t rd_disable_dl_cache:1; 238 /** rd_key_status : R; bitpos: [10]; default: 0; 239 * read for key_status 240 */ 241 uint32_t rd_key_status:1; 242 /** rd_reserve_0_203 : RW; bitpos: [31:11]; default: 0; 243 * Reserved, it was created by set_missed_fields_in_regs func 244 */ 245 uint32_t rd_reserve_0_203:21; 246 }; 247 uint32_t val; 248 } efuse_blk0_rdata6_reg_t; 249 250 /** Type of blk0_wdata0 register */ 251 typedef union { 252 struct { 253 /** wr_dis : RW; bitpos: [15:0]; default: 0; 254 * program for efuse_wr_disable 255 */ 256 uint32_t wr_dis:16; 257 /** rd_dis : RW; bitpos: [19:16]; default: 0; 258 * program for efuse_rd_disable 259 */ 260 uint32_t rd_dis:4; 261 /** flash_crypt_cnt : RW; bitpos: [26:20]; default: 0; 262 * program for flash_crypt_cnt 263 */ 264 uint32_t flash_crypt_cnt:7; 265 uint32_t reserved_27:5; 266 }; 267 uint32_t val; 268 } efuse_blk0_wdata0_reg_t; 269 270 /** Type of blk0_wdata1 register */ 271 typedef union { 272 struct { 273 /** wifi_mac_crc_low : RW; bitpos: [31:0]; default: 0; 274 * program for low 32bit WIFI_MAC_Address 275 */ 276 uint32_t wifi_mac_crc_low:32; 277 }; 278 uint32_t val; 279 } efuse_blk0_wdata1_reg_t; 280 281 /** Type of blk0_wdata2 register */ 282 typedef union { 283 struct { 284 /** wifi_mac_crc_high : RW; bitpos: [23:0]; default: 0; 285 * program for high 24bit WIFI_MAC_Address 286 */ 287 uint32_t wifi_mac_crc_high:24; 288 uint32_t reserved_24:8; 289 }; 290 uint32_t val; 291 } efuse_blk0_wdata2_reg_t; 292 293 /** Type of blk0_wdata3 register */ 294 typedef union { 295 struct { 296 /** disable_app_cpu : R; bitpos: [0]; default: 0; 297 * Disables APP CPU 298 */ 299 uint32_t disable_app_cpu:1; 300 /** disable_bt : R; bitpos: [1]; default: 0; 301 * Disables Bluetooth 302 */ 303 uint32_t disable_bt:1; 304 /** chip_package_4bit : R; bitpos: [2]; default: 0; 305 * Chip package identifier #4bit 306 */ 307 uint32_t chip_package_4bit:1; 308 /** dis_cache : R; bitpos: [3]; default: 0; 309 * Disables cache 310 */ 311 uint32_t dis_cache:1; 312 /** spi_pad_config_hd : R; bitpos: [8:4]; default: 0; 313 * program for SPI_pad_config_hd 314 */ 315 uint32_t spi_pad_config_hd:5; 316 /** chip_package : RW; bitpos: [11:9]; default: 0; 317 * Chip package identifier 318 */ 319 uint32_t chip_package:3; 320 /** chip_cpu_freq_low : RW; bitpos: [12]; default: 0; 321 * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is 322 * rated for 160MHz. 240MHz otherwise 323 */ 324 uint32_t chip_cpu_freq_low:1; 325 /** chip_cpu_freq_rated : RW; bitpos: [13]; default: 0; 326 * If set, the ESP32's maximum CPU frequency has been rated 327 */ 328 uint32_t chip_cpu_freq_rated:1; 329 /** blk3_part_reserve : RW; bitpos: [14]; default: 0; 330 * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 331 */ 332 uint32_t blk3_part_reserve:1; 333 /** chip_ver_rev1 : RW; bitpos: [15]; default: 0; 334 * bit is set to 1 for rev1 silicon 335 */ 336 uint32_t chip_ver_rev1:1; 337 /** reserve_0_112 : RW; bitpos: [31:16]; default: 0; 338 * Reserved, it was created by set_missed_fields_in_regs func 339 */ 340 uint32_t reserve_0_112:16; 341 }; 342 uint32_t val; 343 } efuse_blk0_wdata3_reg_t; 344 345 /** Type of blk0_wdata4 register */ 346 typedef union { 347 struct { 348 /** clk8m_freq : R; bitpos: [7:0]; default: 0; 349 * 8MHz clock freq override 350 */ 351 uint32_t clk8m_freq:8; 352 /** adc_vref : RW; bitpos: [12:8]; default: 0; 353 * True ADC reference voltage 354 */ 355 uint32_t adc_vref:5; 356 /** reserve_0_141 : RW; bitpos: [13]; default: 0; 357 * Reserved, it was created by set_missed_fields_in_regs func 358 */ 359 uint32_t reserve_0_141:1; 360 /** xpd_sdio_reg : R; bitpos: [14]; default: 0; 361 * program for XPD_SDIO_REG 362 */ 363 uint32_t xpd_sdio_reg:1; 364 /** xpd_sdio_tieh : R; bitpos: [15]; default: 0; 365 * If XPD_SDIO_FORCE & XPD_SDIO_REG 366 */ 367 uint32_t xpd_sdio_tieh:1; 368 /** xpd_sdio_force : R; bitpos: [16]; default: 0; 369 * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset 370 */ 371 uint32_t xpd_sdio_force:1; 372 /** reserve_0_145 : RW; bitpos: [31:17]; default: 0; 373 * Reserved, it was created by set_missed_fields_in_regs func 374 */ 375 uint32_t reserve_0_145:15; 376 }; 377 uint32_t val; 378 } efuse_blk0_wdata4_reg_t; 379 380 /** Type of blk0_wdata5 register */ 381 typedef union { 382 struct { 383 /** spi_pad_config_clk : R; bitpos: [4:0]; default: 0; 384 * program for SPI_pad_config_clk 385 */ 386 uint32_t spi_pad_config_clk:5; 387 /** spi_pad_config_q : R; bitpos: [9:5]; default: 0; 388 * program for SPI_pad_config_q 389 */ 390 uint32_t spi_pad_config_q:5; 391 /** spi_pad_config_d : R; bitpos: [14:10]; default: 0; 392 * program for SPI_pad_config_d 393 */ 394 uint32_t spi_pad_config_d:5; 395 /** spi_pad_config_cs0 : R; bitpos: [19:15]; default: 0; 396 * program for SPI_pad_config_cs0 397 */ 398 uint32_t spi_pad_config_cs0:5; 399 /** chip_ver_rev2 : R; bitpos: [20]; default: 0; */ 400 uint32_t chip_ver_rev2:1; 401 /** reserve_0_181 : RW; bitpos: [21]; default: 0; 402 * Reserved, it was created by set_missed_fields_in_regs func 403 */ 404 uint32_t reserve_0_181:1; 405 /** vol_level_hp_inv : R; bitpos: [23:22]; default: 0; 406 * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM 407 * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 408 */ 409 uint32_t vol_level_hp_inv:2; 410 /** wafer_version_minor : R; bitpos: [25:24]; default: 0; */ 411 uint32_t wafer_version_minor:2; 412 /** reserve_0_186 : RW; bitpos: [27:26]; default: 0; 413 * Reserved, it was created by set_missed_fields_in_regs func 414 */ 415 uint32_t reserve_0_186:2; 416 /** flash_crypt_config : R; bitpos: [31:28]; default: 0; 417 * program for flash_crypt_config 418 */ 419 uint32_t flash_crypt_config:4; 420 }; 421 uint32_t val; 422 } efuse_blk0_wdata5_reg_t; 423 424 /** Type of blk0_wdata6 register */ 425 typedef union { 426 struct { 427 /** coding_scheme : RW; bitpos: [1:0]; default: 0; 428 * program for coding_scheme 429 */ 430 uint32_t coding_scheme:2; 431 /** console_debug_disable : RW; bitpos: [2]; default: 0; 432 * program for console_debug_disable 433 */ 434 uint32_t console_debug_disable:1; 435 /** disable_sdio_host : RW; bitpos: [3]; default: 0; */ 436 uint32_t disable_sdio_host:1; 437 /** abs_done_0 : RW; bitpos: [4]; default: 0; 438 * program for abstract_done_0 439 */ 440 uint32_t abs_done_0:1; 441 /** abs_done_1 : RW; bitpos: [5]; default: 0; 442 * program for abstract_done_1 443 */ 444 uint32_t abs_done_1:1; 445 /** disable_jtag : RW; bitpos: [6]; default: 0; 446 * program for JTAG_disable 447 */ 448 uint32_t disable_jtag:1; 449 /** disable_dl_encrypt : RW; bitpos: [7]; default: 0; 450 * program for download_dis_encrypt 451 */ 452 uint32_t disable_dl_encrypt:1; 453 /** disable_dl_decrypt : RW; bitpos: [8]; default: 0; 454 * program for download_dis_decrypt 455 */ 456 uint32_t disable_dl_decrypt:1; 457 /** disable_dl_cache : RW; bitpos: [9]; default: 0; 458 * program for download_dis_cache 459 */ 460 uint32_t disable_dl_cache:1; 461 /** key_status : RW; bitpos: [10]; default: 0; 462 * program for key_status 463 */ 464 uint32_t key_status:1; 465 uint32_t reserved_11:21; 466 }; 467 uint32_t val; 468 } efuse_blk0_wdata6_reg_t; 469 470 /** Type of blk1_rdata0 register */ 471 typedef union { 472 struct { 473 /** rd_block1 : R; bitpos: [31:0]; default: 0; 474 * Flash encryption key 475 */ 476 uint32_t rd_block1:32; 477 }; 478 uint32_t val; 479 } efuse_blk1_rdata0_reg_t; 480 481 /** Type of blk1_rdata1 register */ 482 typedef union { 483 struct { 484 /** rd_block1_1 : R; bitpos: [31:0]; default: 0; 485 * Flash encryption key 486 */ 487 uint32_t rd_block1_1:32; 488 }; 489 uint32_t val; 490 } efuse_blk1_rdata1_reg_t; 491 492 /** Type of blk1_rdata2 register */ 493 typedef union { 494 struct { 495 /** rd_block1_2 : R; bitpos: [31:0]; default: 0; 496 * Flash encryption key 497 */ 498 uint32_t rd_block1_2:32; 499 }; 500 uint32_t val; 501 } efuse_blk1_rdata2_reg_t; 502 503 /** Type of blk1_rdata3 register */ 504 typedef union { 505 struct { 506 /** rd_block1_3 : R; bitpos: [31:0]; default: 0; 507 * Flash encryption key 508 */ 509 uint32_t rd_block1_3:32; 510 }; 511 uint32_t val; 512 } efuse_blk1_rdata3_reg_t; 513 514 /** Type of blk1_rdata4 register */ 515 typedef union { 516 struct { 517 /** rd_block1_4 : R; bitpos: [31:0]; default: 0; 518 * Flash encryption key 519 */ 520 uint32_t rd_block1_4:32; 521 }; 522 uint32_t val; 523 } efuse_blk1_rdata4_reg_t; 524 525 /** Type of blk1_rdata5 register */ 526 typedef union { 527 struct { 528 /** rd_block1_5 : R; bitpos: [31:0]; default: 0; 529 * Flash encryption key 530 */ 531 uint32_t rd_block1_5:32; 532 }; 533 uint32_t val; 534 } efuse_blk1_rdata5_reg_t; 535 536 /** Type of blk1_rdata6 register */ 537 typedef union { 538 struct { 539 /** rd_block1_6 : R; bitpos: [31:0]; default: 0; 540 * Flash encryption key 541 */ 542 uint32_t rd_block1_6:32; 543 }; 544 uint32_t val; 545 } efuse_blk1_rdata6_reg_t; 546 547 /** Type of blk1_rdata7 register */ 548 typedef union { 549 struct { 550 /** rd_block1_7 : R; bitpos: [31:0]; default: 0; 551 * Flash encryption key 552 */ 553 uint32_t rd_block1_7:32; 554 }; 555 uint32_t val; 556 } efuse_blk1_rdata7_reg_t; 557 558 /** Type of blk2_rdata0 register */ 559 typedef union { 560 struct { 561 /** rd_block2 : R; bitpos: [31:0]; default: 0; 562 * Security boot key 563 */ 564 uint32_t rd_block2:32; 565 }; 566 uint32_t val; 567 } efuse_blk2_rdata0_reg_t; 568 569 /** Type of blk2_rdata1 register */ 570 typedef union { 571 struct { 572 /** rd_block2_1 : R; bitpos: [31:0]; default: 0; 573 * Security boot key 574 */ 575 uint32_t rd_block2_1:32; 576 }; 577 uint32_t val; 578 } efuse_blk2_rdata1_reg_t; 579 580 /** Type of blk2_rdata2 register */ 581 typedef union { 582 struct { 583 /** rd_block2_2 : R; bitpos: [31:0]; default: 0; 584 * Security boot key 585 */ 586 uint32_t rd_block2_2:32; 587 }; 588 uint32_t val; 589 } efuse_blk2_rdata2_reg_t; 590 591 /** Type of blk2_rdata3 register */ 592 typedef union { 593 struct { 594 /** rd_block2_3 : R; bitpos: [31:0]; default: 0; 595 * Security boot key 596 */ 597 uint32_t rd_block2_3:32; 598 }; 599 uint32_t val; 600 } efuse_blk2_rdata3_reg_t; 601 602 /** Type of blk2_rdata4 register */ 603 typedef union { 604 struct { 605 /** rd_block2_4 : R; bitpos: [31:0]; default: 0; 606 * Security boot key 607 */ 608 uint32_t rd_block2_4:32; 609 }; 610 uint32_t val; 611 } efuse_blk2_rdata4_reg_t; 612 613 /** Type of blk2_rdata5 register */ 614 typedef union { 615 struct { 616 /** rd_block2_5 : R; bitpos: [31:0]; default: 0; 617 * Security boot key 618 */ 619 uint32_t rd_block2_5:32; 620 }; 621 uint32_t val; 622 } efuse_blk2_rdata5_reg_t; 623 624 /** Type of blk2_rdata6 register */ 625 typedef union { 626 struct { 627 /** rd_block2_6 : R; bitpos: [31:0]; default: 0; 628 * Security boot key 629 */ 630 uint32_t rd_block2_6:32; 631 }; 632 uint32_t val; 633 } efuse_blk2_rdata6_reg_t; 634 635 /** Type of blk2_rdata7 register */ 636 typedef union { 637 struct { 638 /** rd_block2_7 : R; bitpos: [31:0]; default: 0; 639 * Security boot key 640 */ 641 uint32_t rd_block2_7:32; 642 }; 643 uint32_t val; 644 } efuse_blk2_rdata7_reg_t; 645 646 /** Type of blk3_rdata0 register */ 647 typedef union { 648 struct { 649 /** rd_custom_mac_crc : R; bitpos: [7:0]; default: 0; 650 * CRC8 for custom MAC address 651 */ 652 uint32_t rd_custom_mac_crc:8; 653 /** rd_custom_mac : R; bitpos: [31:8]; default: 0; 654 * Custom MAC address 655 */ 656 uint32_t rd_custom_mac:24; 657 }; 658 uint32_t val; 659 } efuse_blk3_rdata0_reg_t; 660 661 /** Type of blk3_rdata1 register */ 662 typedef union { 663 struct { 664 /** rd_custom_mac_1 : R; bitpos: [23:0]; default: 0; 665 * Custom MAC address 666 */ 667 uint32_t rd_custom_mac_1:24; 668 /** reserved_3_56 : R; bitpos: [31:24]; default: 0; 669 * reserved 670 */ 671 uint32_t reserved_3_56:8; 672 }; 673 uint32_t val; 674 } efuse_blk3_rdata1_reg_t; 675 676 /** Type of blk3_rdata2 register */ 677 typedef union { 678 struct { 679 /** rd_blk3_reserved_2 : R; bitpos: [31:0]; default: 0; 680 * read for BLOCK3 681 */ 682 uint32_t rd_blk3_reserved_2:32; 683 }; 684 uint32_t val; 685 } efuse_blk3_rdata2_reg_t; 686 687 /** Type of blk3_rdata3 register */ 688 typedef union { 689 struct { 690 /** rd_adc1_tp_low : RW; bitpos: [6:0]; default: 0; 691 * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 692 */ 693 uint32_t rd_adc1_tp_low:7; 694 /** rd_adc1_tp_high : RW; bitpos: [15:7]; default: 0; 695 * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 696 */ 697 uint32_t rd_adc1_tp_high:9; 698 /** rd_adc2_tp_low : RW; bitpos: [22:16]; default: 0; 699 * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 700 */ 701 uint32_t rd_adc2_tp_low:7; 702 /** rd_adc2_tp_high : RW; bitpos: [31:23]; default: 0; 703 * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 704 */ 705 uint32_t rd_adc2_tp_high:9; 706 }; 707 uint32_t val; 708 } efuse_blk3_rdata3_reg_t; 709 710 /** Type of blk3_rdata4 register */ 711 typedef union { 712 struct { 713 /** rd_secure_version : R; bitpos: [31:0]; default: 0; 714 * Secure version for anti-rollback 715 */ 716 uint32_t rd_secure_version:32; 717 }; 718 uint32_t val; 719 } efuse_blk3_rdata4_reg_t; 720 721 /** Type of blk3_rdata5 register */ 722 typedef union { 723 struct { 724 /** reserved_3_160 : R; bitpos: [23:0]; default: 0; 725 * reserved 726 */ 727 uint32_t reserved_3_160:24; 728 /** rd_mac_version : R; bitpos: [31:24]; default: 0; 729 * Custom MAC version 730 */ 731 uint32_t rd_mac_version:8; 732 }; 733 uint32_t val; 734 } efuse_blk3_rdata5_reg_t; 735 736 /** Type of blk3_rdata6 register */ 737 typedef union { 738 struct { 739 /** rd_blk3_reserved_6 : R; bitpos: [31:0]; default: 0; 740 * read for BLOCK3 741 */ 742 uint32_t rd_blk3_reserved_6:32; 743 }; 744 uint32_t val; 745 } efuse_blk3_rdata6_reg_t; 746 747 /** Type of blk3_rdata7 register */ 748 typedef union { 749 struct { 750 /** rd_blk3_reserved_7 : R; bitpos: [31:0]; default: 0; 751 * read for BLOCK3 752 */ 753 uint32_t rd_blk3_reserved_7:32; 754 }; 755 uint32_t val; 756 } efuse_blk3_rdata7_reg_t; 757 758 /** Type of blk1_wdata0 register */ 759 typedef union { 760 struct { 761 /** blk1_din0 : RW; bitpos: [31:0]; default: 0; 762 * program for BLOCK1 763 */ 764 uint32_t blk1_din0:32; 765 }; 766 uint32_t val; 767 } efuse_blk1_wdata0_reg_t; 768 769 /** Type of blk1_wdata1 register */ 770 typedef union { 771 struct { 772 /** blk1_din1 : RW; bitpos: [31:0]; default: 0; 773 * program for BLOCK1 774 */ 775 uint32_t blk1_din1:32; 776 }; 777 uint32_t val; 778 } efuse_blk1_wdata1_reg_t; 779 780 /** Type of blk1_wdata2 register */ 781 typedef union { 782 struct { 783 /** blk1_din2 : RW; bitpos: [31:0]; default: 0; 784 * program for BLOCK1 785 */ 786 uint32_t blk1_din2:32; 787 }; 788 uint32_t val; 789 } efuse_blk1_wdata2_reg_t; 790 791 /** Type of blk1_wdata3 register */ 792 typedef union { 793 struct { 794 /** blk1_din3 : RW; bitpos: [31:0]; default: 0; 795 * program for BLOCK1 796 */ 797 uint32_t blk1_din3:32; 798 }; 799 uint32_t val; 800 } efuse_blk1_wdata3_reg_t; 801 802 /** Type of blk1_wdata4 register */ 803 typedef union { 804 struct { 805 /** blk1_din4 : RW; bitpos: [31:0]; default: 0; 806 * program for BLOCK1 807 */ 808 uint32_t blk1_din4:32; 809 }; 810 uint32_t val; 811 } efuse_blk1_wdata4_reg_t; 812 813 /** Type of blk1_wdata5 register */ 814 typedef union { 815 struct { 816 /** blk1_din5 : RW; bitpos: [31:0]; default: 0; 817 * program for BLOCK1 818 */ 819 uint32_t blk1_din5:32; 820 }; 821 uint32_t val; 822 } efuse_blk1_wdata5_reg_t; 823 824 /** Type of blk1_wdata6 register */ 825 typedef union { 826 struct { 827 /** blk1_din6 : RW; bitpos: [31:0]; default: 0; 828 * program for BLOCK1 829 */ 830 uint32_t blk1_din6:32; 831 }; 832 uint32_t val; 833 } efuse_blk1_wdata6_reg_t; 834 835 /** Type of blk1_wdata7 register */ 836 typedef union { 837 struct { 838 /** blk1_din7 : RW; bitpos: [31:0]; default: 0; 839 * program for BLOCK1 840 */ 841 uint32_t blk1_din7:32; 842 }; 843 uint32_t val; 844 } efuse_blk1_wdata7_reg_t; 845 846 /** Type of blk2_wdata0 register */ 847 typedef union { 848 struct { 849 /** blk2_din0 : RW; bitpos: [31:0]; default: 0; 850 * program for BLOCK2 851 */ 852 uint32_t blk2_din0:32; 853 }; 854 uint32_t val; 855 } efuse_blk2_wdata0_reg_t; 856 857 /** Type of blk2_wdata1 register */ 858 typedef union { 859 struct { 860 /** blk2_din1 : RW; bitpos: [31:0]; default: 0; 861 * program for BLOCK2 862 */ 863 uint32_t blk2_din1:32; 864 }; 865 uint32_t val; 866 } efuse_blk2_wdata1_reg_t; 867 868 /** Type of blk2_wdata2 register */ 869 typedef union { 870 struct { 871 /** blk2_din2 : RW; bitpos: [31:0]; default: 0; 872 * program for BLOCK2 873 */ 874 uint32_t blk2_din2:32; 875 }; 876 uint32_t val; 877 } efuse_blk2_wdata2_reg_t; 878 879 /** Type of blk2_wdata3 register */ 880 typedef union { 881 struct { 882 /** blk2_din3 : RW; bitpos: [31:0]; default: 0; 883 * program for BLOCK2 884 */ 885 uint32_t blk2_din3:32; 886 }; 887 uint32_t val; 888 } efuse_blk2_wdata3_reg_t; 889 890 /** Type of blk2_wdata4 register */ 891 typedef union { 892 struct { 893 /** blk2_din4 : RW; bitpos: [31:0]; default: 0; 894 * program for BLOCK2 895 */ 896 uint32_t blk2_din4:32; 897 }; 898 uint32_t val; 899 } efuse_blk2_wdata4_reg_t; 900 901 /** Type of blk2_wdata5 register */ 902 typedef union { 903 struct { 904 /** blk2_din5 : RW; bitpos: [31:0]; default: 0; 905 * program for BLOCK2 906 */ 907 uint32_t blk2_din5:32; 908 }; 909 uint32_t val; 910 } efuse_blk2_wdata5_reg_t; 911 912 /** Type of blk2_wdata6 register */ 913 typedef union { 914 struct { 915 /** blk2_din6 : RW; bitpos: [31:0]; default: 0; 916 * program for BLOCK2 917 */ 918 uint32_t blk2_din6:32; 919 }; 920 uint32_t val; 921 } efuse_blk2_wdata6_reg_t; 922 923 /** Type of blk2_wdata7 register */ 924 typedef union { 925 struct { 926 /** blk2_din7 : RW; bitpos: [31:0]; default: 0; 927 * program for BLOCK2 928 */ 929 uint32_t blk2_din7:32; 930 }; 931 uint32_t val; 932 } efuse_blk2_wdata7_reg_t; 933 934 /** Type of blk3_wdata0 register */ 935 typedef union { 936 struct { 937 /** blk3_din0 : RW; bitpos: [31:0]; default: 0; 938 * program for BLOCK3 939 */ 940 uint32_t blk3_din0:32; 941 }; 942 uint32_t val; 943 } efuse_blk3_wdata0_reg_t; 944 945 /** Type of blk3_wdata1 register */ 946 typedef union { 947 struct { 948 /** blk3_din1 : RW; bitpos: [31:0]; default: 0; 949 * program for BLOCK3 950 */ 951 uint32_t blk3_din1:32; 952 }; 953 uint32_t val; 954 } efuse_blk3_wdata1_reg_t; 955 956 /** Type of blk3_wdata2 register */ 957 typedef union { 958 struct { 959 /** blk3_din2 : RW; bitpos: [31:0]; default: 0; 960 * program for BLOCK3 961 */ 962 uint32_t blk3_din2:32; 963 }; 964 uint32_t val; 965 } efuse_blk3_wdata2_reg_t; 966 967 /** Type of blk3_wdata3 register */ 968 typedef union { 969 struct { 970 /** adc1_tp_low : RW; bitpos: [6:0]; default: 0; 971 * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 972 */ 973 uint32_t adc1_tp_low:7; 974 /** adc1_tp_high : RW; bitpos: [15:7]; default: 0; 975 * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 976 */ 977 uint32_t adc1_tp_high:9; 978 /** adc2_tp_low : RW; bitpos: [22:16]; default: 0; 979 * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 980 */ 981 uint32_t adc2_tp_low:7; 982 /** adc2_tp_high : RW; bitpos: [31:23]; default: 0; 983 * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 984 */ 985 uint32_t adc2_tp_high:9; 986 }; 987 uint32_t val; 988 } efuse_blk3_wdata3_reg_t; 989 990 /** Type of blk3_wdata4 register */ 991 typedef union { 992 struct { 993 /** secure_version : R; bitpos: [31:0]; default: 0; 994 * Secure version for anti-rollback 995 */ 996 uint32_t secure_version:32; 997 }; 998 uint32_t val; 999 } efuse_blk3_wdata4_reg_t; 1000 1001 /** Type of blk3_wdata5 register */ 1002 typedef union { 1003 struct { 1004 /** blk3_din5 : RW; bitpos: [31:0]; default: 0; 1005 * program for BLOCK3 1006 */ 1007 uint32_t blk3_din5:32; 1008 }; 1009 uint32_t val; 1010 } efuse_blk3_wdata5_reg_t; 1011 1012 /** Type of blk3_wdata6 register */ 1013 typedef union { 1014 struct { 1015 /** blk3_din6 : RW; bitpos: [31:0]; default: 0; 1016 * program for BLOCK3 1017 */ 1018 uint32_t blk3_din6:32; 1019 }; 1020 uint32_t val; 1021 } efuse_blk3_wdata6_reg_t; 1022 1023 /** Type of blk3_wdata7 register */ 1024 typedef union { 1025 struct { 1026 /** blk3_din7 : RW; bitpos: [31:0]; default: 0; 1027 * program for BLOCK3 1028 */ 1029 uint32_t blk3_din7:32; 1030 }; 1031 uint32_t val; 1032 } efuse_blk3_wdata7_reg_t; 1033 1034 /** Type of clk register */ 1035 typedef union { 1036 struct { 1037 /** clk_sel0 : RW; bitpos: [7:0]; default: 82; 1038 * efuse timing configure 1039 */ 1040 uint32_t clk_sel0:8; 1041 /** clk_sel1 : RW; bitpos: [15:8]; default: 64; 1042 * efuse timing configure 1043 */ 1044 uint32_t clk_sel1:8; 1045 /** clk_en : RW; bitpos: [16]; default: 0; */ 1046 uint32_t clk_en:1; 1047 uint32_t reserved_17:15; 1048 }; 1049 uint32_t val; 1050 } efuse_clk_reg_t; 1051 1052 /** Type of conf register */ 1053 typedef union { 1054 struct { 1055 /** op_code : RW; bitpos: [15:0]; default: 0; 1056 * efuse operation code 1057 */ 1058 uint32_t op_code:16; 1059 /** force_no_wr_rd_dis : RW; bitpos: [16]; default: 1; */ 1060 uint32_t force_no_wr_rd_dis:1; 1061 uint32_t reserved_17:15; 1062 }; 1063 uint32_t val; 1064 } efuse_conf_reg_t; 1065 1066 /** Type of status register */ 1067 typedef union { 1068 struct { 1069 /** debug : R; bitpos: [31:0]; default: 0; */ 1070 uint32_t debug:32; 1071 }; 1072 uint32_t val; 1073 } efuse_status_reg_t; 1074 1075 /** Type of cmd register */ 1076 typedef union { 1077 struct { 1078 /** read_cmd : RW; bitpos: [0]; default: 0; 1079 * command for read 1080 */ 1081 uint32_t read_cmd:1; 1082 /** pgm_cmd : RW; bitpos: [1]; default: 0; 1083 * command for program 1084 */ 1085 uint32_t pgm_cmd:1; 1086 uint32_t reserved_2:30; 1087 }; 1088 uint32_t val; 1089 } efuse_cmd_reg_t; 1090 1091 /** Type of int_raw register */ 1092 typedef union { 1093 struct { 1094 /** read_done_int_raw : R; bitpos: [0]; default: 0; 1095 * read done interrupt raw status 1096 */ 1097 uint32_t read_done_int_raw:1; 1098 /** pgm_done_int_raw : R; bitpos: [1]; default: 0; 1099 * program done interrupt raw status 1100 */ 1101 uint32_t pgm_done_int_raw:1; 1102 uint32_t reserved_2:30; 1103 }; 1104 uint32_t val; 1105 } efuse_int_raw_reg_t; 1106 1107 /** Type of int_st register */ 1108 typedef union { 1109 struct { 1110 /** read_done_int_st : R; bitpos: [0]; default: 0; 1111 * read done interrupt status 1112 */ 1113 uint32_t read_done_int_st:1; 1114 /** pgm_done_int_st : R; bitpos: [1]; default: 0; 1115 * program done interrupt status 1116 */ 1117 uint32_t pgm_done_int_st:1; 1118 uint32_t reserved_2:30; 1119 }; 1120 uint32_t val; 1121 } efuse_int_st_reg_t; 1122 1123 /** Type of int_ena register */ 1124 typedef union { 1125 struct { 1126 /** read_done_int_ena : RW; bitpos: [0]; default: 0; 1127 * read done interrupt enable 1128 */ 1129 uint32_t read_done_int_ena:1; 1130 /** pgm_done_int_ena : RW; bitpos: [1]; default: 0; 1131 * program done interrupt enable 1132 */ 1133 uint32_t pgm_done_int_ena:1; 1134 uint32_t reserved_2:30; 1135 }; 1136 uint32_t val; 1137 } efuse_int_ena_reg_t; 1138 1139 /** Type of int_clr register */ 1140 typedef union { 1141 struct { 1142 /** read_done_int_clr : W; bitpos: [0]; default: 0; 1143 * read done interrupt clear 1144 */ 1145 uint32_t read_done_int_clr:1; 1146 /** pgm_done_int_clr : W; bitpos: [1]; default: 0; 1147 * program done interrupt clear 1148 */ 1149 uint32_t pgm_done_int_clr:1; 1150 uint32_t reserved_2:30; 1151 }; 1152 uint32_t val; 1153 } efuse_int_clr_reg_t; 1154 1155 /** Type of dac_conf register */ 1156 typedef union { 1157 struct { 1158 /** dac_clk_div : RW; bitpos: [7:0]; default: 40; 1159 * efuse timing configure 1160 */ 1161 uint32_t dac_clk_div:8; 1162 /** dac_clk_pad_sel : RW; bitpos: [8]; default: 0; */ 1163 uint32_t dac_clk_pad_sel:1; 1164 uint32_t reserved_9:23; 1165 }; 1166 uint32_t val; 1167 } efuse_dac_conf_reg_t; 1168 1169 /** Type of dec_status register */ 1170 typedef union { 1171 struct { 1172 /** dec_warnings : R; bitpos: [11:0]; default: 0; 1173 * the decode result of 3/4 coding scheme has warning 1174 */ 1175 uint32_t dec_warnings:12; 1176 uint32_t reserved_12:20; 1177 }; 1178 uint32_t val; 1179 } efuse_dec_status_reg_t; 1180 1181 /** Type of date register */ 1182 typedef union { 1183 struct { 1184 /** date : RW; bitpos: [31:0]; default: 369370624; */ 1185 uint32_t date:32; 1186 }; 1187 uint32_t val; 1188 } efuse_date_reg_t; 1189 1190 1191 typedef struct { 1192 volatile efuse_blk0_rdata0_reg_t blk0_rdata0; 1193 volatile efuse_blk0_rdata1_reg_t blk0_rdata1; 1194 volatile efuse_blk0_rdata2_reg_t blk0_rdata2; 1195 volatile efuse_blk0_rdata3_reg_t blk0_rdata3; 1196 volatile efuse_blk0_rdata4_reg_t blk0_rdata4; 1197 volatile efuse_blk0_rdata5_reg_t blk0_rdata5; 1198 volatile efuse_blk0_rdata6_reg_t blk0_rdata6; 1199 volatile efuse_blk0_wdata0_reg_t blk0_wdata0; 1200 volatile efuse_blk0_wdata1_reg_t blk0_wdata1; 1201 volatile efuse_blk0_wdata2_reg_t blk0_wdata2; 1202 volatile efuse_blk0_wdata3_reg_t blk0_wdata3; 1203 volatile efuse_blk0_wdata4_reg_t blk0_wdata4; 1204 volatile efuse_blk0_wdata5_reg_t blk0_wdata5; 1205 volatile efuse_blk0_wdata6_reg_t blk0_wdata6; 1206 volatile efuse_blk1_rdata0_reg_t blk1_rdata0; 1207 volatile efuse_blk1_rdata1_reg_t blk1_rdata1; 1208 volatile efuse_blk1_rdata2_reg_t blk1_rdata2; 1209 volatile efuse_blk1_rdata3_reg_t blk1_rdata3; 1210 volatile efuse_blk1_rdata4_reg_t blk1_rdata4; 1211 volatile efuse_blk1_rdata5_reg_t blk1_rdata5; 1212 volatile efuse_blk1_rdata6_reg_t blk1_rdata6; 1213 volatile efuse_blk1_rdata7_reg_t blk1_rdata7; 1214 volatile efuse_blk2_rdata0_reg_t blk2_rdata0; 1215 volatile efuse_blk2_rdata1_reg_t blk2_rdata1; 1216 volatile efuse_blk2_rdata2_reg_t blk2_rdata2; 1217 volatile efuse_blk2_rdata3_reg_t blk2_rdata3; 1218 volatile efuse_blk2_rdata4_reg_t blk2_rdata4; 1219 volatile efuse_blk2_rdata5_reg_t blk2_rdata5; 1220 volatile efuse_blk2_rdata6_reg_t blk2_rdata6; 1221 volatile efuse_blk2_rdata7_reg_t blk2_rdata7; 1222 volatile efuse_blk3_rdata0_reg_t blk3_rdata0; 1223 volatile efuse_blk3_rdata1_reg_t blk3_rdata1; 1224 volatile efuse_blk3_rdata2_reg_t blk3_rdata2; 1225 volatile efuse_blk3_rdata3_reg_t blk3_rdata3; 1226 volatile efuse_blk3_rdata4_reg_t blk3_rdata4; 1227 volatile efuse_blk3_rdata5_reg_t blk3_rdata5; 1228 volatile efuse_blk3_rdata6_reg_t blk3_rdata6; 1229 volatile efuse_blk3_rdata7_reg_t blk3_rdata7; 1230 volatile efuse_blk1_wdata0_reg_t blk1_wdata0; 1231 volatile efuse_blk1_wdata1_reg_t blk1_wdata1; 1232 volatile efuse_blk1_wdata2_reg_t blk1_wdata2; 1233 volatile efuse_blk1_wdata3_reg_t blk1_wdata3; 1234 volatile efuse_blk1_wdata4_reg_t blk1_wdata4; 1235 volatile efuse_blk1_wdata5_reg_t blk1_wdata5; 1236 volatile efuse_blk1_wdata6_reg_t blk1_wdata6; 1237 volatile efuse_blk1_wdata7_reg_t blk1_wdata7; 1238 volatile efuse_blk2_wdata0_reg_t blk2_wdata0; 1239 volatile efuse_blk2_wdata1_reg_t blk2_wdata1; 1240 volatile efuse_blk2_wdata2_reg_t blk2_wdata2; 1241 volatile efuse_blk2_wdata3_reg_t blk2_wdata3; 1242 volatile efuse_blk2_wdata4_reg_t blk2_wdata4; 1243 volatile efuse_blk2_wdata5_reg_t blk2_wdata5; 1244 volatile efuse_blk2_wdata6_reg_t blk2_wdata6; 1245 volatile efuse_blk2_wdata7_reg_t blk2_wdata7; 1246 volatile efuse_blk3_wdata0_reg_t blk3_wdata0; 1247 volatile efuse_blk3_wdata1_reg_t blk3_wdata1; 1248 volatile efuse_blk3_wdata2_reg_t blk3_wdata2; 1249 volatile efuse_blk3_wdata3_reg_t blk3_wdata3; 1250 volatile efuse_blk3_wdata4_reg_t blk3_wdata4; 1251 volatile efuse_blk3_wdata5_reg_t blk3_wdata5; 1252 volatile efuse_blk3_wdata6_reg_t blk3_wdata6; 1253 volatile efuse_blk3_wdata7_reg_t blk3_wdata7; 1254 volatile efuse_clk_reg_t clk; 1255 volatile efuse_conf_reg_t conf; 1256 volatile efuse_status_reg_t status; 1257 volatile efuse_cmd_reg_t cmd; 1258 volatile efuse_int_raw_reg_t int_raw; 1259 volatile efuse_int_st_reg_t int_st; 1260 volatile efuse_int_ena_reg_t int_ena; 1261 volatile efuse_int_clr_reg_t int_clr; 1262 volatile efuse_dac_conf_reg_t dac_conf; 1263 volatile efuse_dec_status_reg_t dec_status; 1264 uint32_t reserved_120[55]; 1265 volatile efuse_date_reg_t date; 1266 } efuse_dev_t; 1267 1268 extern efuse_dev_t EFUSE; 1269 1270 #ifndef __cplusplus 1271 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 1272 #endif 1273 1274 #ifdef __cplusplus 1275 } 1276 #endif 1277