1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include <zephyr/arch/riscv/csr.h>
9 #include <zephyr/kernel.h>
10 #include <zephyr/device.h>
11 #include <zephyr/init.h>
12 #include "ilm.h"
13 #include <soc_common.h>
14 #include "soc_espi.h"
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
16
17 /*
18 * This define gets the total number of USBPD ports available on the
19 * ITE EC chip from dtsi (include status disable). Both it81202 and
20 * it81302 support two USBPD ports.
21 */
22 #define SOC_USBPD_ITE_PHY_PORT_COUNT \
23 COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
24
25 /*
26 * This define gets the number of active USB Power Delivery (USB PD)
27 * ports in use on the ITE microcontroller from dts (only status okay).
28 * The active port usage should follow the order of ITE TCPC port index,
29 * ex. if we're active only one ITE USB PD port, then the port should be
30 * 0x3700 (port0 register base), instead of 0x3800 (port1 register base).
31 */
32 #define SOC_USBPD_ITE_ACTIVE_PORT_COUNT DT_NUM_INST_STATUS_OKAY(ite_it8xxx2_usbpd)
33
chip_get_pll_freq(void)34 uint32_t chip_get_pll_freq(void)
35 {
36 uint32_t pllfreq;
37
38 switch (IT8XXX2_ECPM_PLLFREQR & 0x0F) {
39 case 0:
40 pllfreq = MHZ(8);
41 break;
42 case 1:
43 pllfreq = MHZ(16);
44 break;
45 case 2:
46 pllfreq = MHZ(24);
47 break;
48 case 3:
49 pllfreq = MHZ(32);
50 break;
51 case 4:
52 pllfreq = MHZ(48);
53 break;
54 case 5:
55 pllfreq = MHZ(64);
56 break;
57 case 6:
58 pllfreq = MHZ(72);
59 break;
60 case 7:
61 pllfreq = MHZ(96);
62 break;
63 default:
64 return -ERANGE;
65 }
66
67 return pllfreq;
68 }
69
chip_pll_ctrl(enum chip_pll_mode mode)70 void __soc_ram_code chip_pll_ctrl(enum chip_pll_mode mode)
71 {
72 volatile uint8_t _pll_ctrl __unused;
73
74 IT8XXX2_ECPM_PLLCTRL = mode;
75 /*
76 * for deep doze / sleep mode
77 * This load operation will ensure PLL setting is taken into
78 * control register before wait for interrupt instruction.
79 */
80 _pll_ctrl = IT8XXX2_ECPM_PLLCTRL;
81 }
82
83 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
84 struct pll_config_t {
85 uint8_t pll_freq;
86 uint8_t div_fnd;
87 uint8_t div_uart;
88 uint8_t div_smb;
89 uint8_t div_sspi;
90 uint8_t div_ec;
91 uint8_t div_jtag;
92 uint8_t div_pwm;
93 uint8_t div_usbpd;
94 };
95
96 static const struct pll_config_t pll_configuration[] = {
97 /*
98 * PLL frequency setting = 4 (48MHz)
99 * FND div = 0 (PLL / 1 = 48 mhz)
100 * UART div = 1 (PLL / 2 = 24 mhz)
101 * SMB div = 1 (PLL / 2 = 24 mhz)
102 * SSPI div = 1 (PLL / 2 = 24 mhz)
103 * EC div = 6 (FND / 6 = 8 mhz)
104 * JTAG div = 1 (PLL / 2 = 24 mhz)
105 * PWM div = 0 (PLL / 1 = 48 mhz)
106 * USBPD div = 5 (PLL / 6 = 8 mhz)
107 */
108 {.pll_freq = 4,
109 .div_fnd = 0,
110 .div_uart = 1,
111 .div_smb = 1,
112 .div_sspi = 1,
113 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
114 .div_ec = 1,
115 #else
116 .div_ec = 6,
117 #endif
118 .div_jtag = 1,
119 .div_pwm = 0,
120 .div_usbpd = 5}
121 };
122
chip_run_pll_sequence(const struct pll_config_t * pll)123 void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll)
124 {
125 /* Enable HW timer to wakeup chip from the sleep mode */
126 timer_5ms_one_shot();
127 /*
128 * Configure PLL clock dividers.
129 * Writing data to these registers doesn't change the
130 * PLL frequency immediately until the status is changed
131 * into wakeup from the sleep mode.
132 * The following code is intended to make the system
133 * enter sleep mode, and wait HW timer to wakeup chip to
134 * complete PLL update.
135 */
136 IT8XXX2_ECPM_PLLFREQR = pll->pll_freq;
137 /* Pre-set FND clock frequency = PLL / 3 */
138 IT8XXX2_ECPM_SCDCR0 = (2 << 4);
139 /* JTAG and EC */
140 IT8XXX2_ECPM_SCDCR3 = (pll->div_jtag << 4) | pll->div_ec;
141 /* Chip sleep after wait for interrupt (wfi) instruction */
142 chip_pll_ctrl(CHIP_PLL_SLEEP);
143 /* Chip sleep and wait timer wake it up */
144 __asm__ volatile ("wfi");
145 /* New FND clock frequency */
146 IT8XXX2_ECPM_SCDCR0 = pll->div_fnd << 4;
147 /* Chip doze after wfi instruction */
148 chip_pll_ctrl(CHIP_PLL_DOZE);
149 /* UART */
150 IT8XXX2_ECPM_SCDCR1 = pll->div_uart;
151 /* SSPI and SMB */
152 IT8XXX2_ECPM_SCDCR2 = (pll->div_sspi << 4) | pll->div_smb;
153 /* USBPD and PWM */
154 IT8XXX2_ECPM_SCDCR4 = (pll->div_usbpd << 4) | pll->div_pwm;
155 }
156
chip_configure_pll(const struct pll_config_t * pll)157 static void chip_configure_pll(const struct pll_config_t *pll)
158 {
159 /* Re-configure PLL clock or not. */
160 if (((IT8XXX2_ECPM_PLLFREQR & 0xf) != pll->pll_freq) ||
161 ((IT8XXX2_ECPM_SCDCR0 & 0xf0) != (pll->div_fnd << 4)) ||
162 ((IT8XXX2_ECPM_SCDCR3 & 0xf) != pll->div_ec)) {
163 #ifdef CONFIG_ESPI
164 /*
165 * We have to disable eSPI pad before changing
166 * PLL sequence or sequence will fail if CS# pin is low.
167 */
168 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, false);
169 #endif
170 /* Run change PLL sequence */
171 chip_run_pll_sequence(pll);
172 #ifdef CONFIG_ESPI
173 /* Enable eSPI pad after changing PLL sequence */
174 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, true);
175 #endif
176 }
177 }
178
chip_change_pll(void)179 static int chip_change_pll(void)
180 {
181
182 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
183 ite_intc_save_and_disable_interrupts();
184 }
185 /* configure PLL/CPU/flash clock */
186 chip_configure_pll(&pll_configuration[0]);
187 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
188 ite_intc_restore_interrupts();
189 }
190
191 return 0;
192 }
193 SYS_INIT(chip_change_pll, PRE_KERNEL_1, CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY);
194 BUILD_ASSERT(CONFIG_FLASH_INIT_PRIORITY < CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY,
195 "CONFIG_FLASH_INIT_PRIORITY must be less than CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY");
196 #endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
197
198 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
199 /* Preventing CPU going into idle mode during command queue. */
200 static atomic_t cpu_idle_disabled;
201
chip_permit_idle(void)202 void chip_permit_idle(void)
203 {
204 atomic_dec(&cpu_idle_disabled);
205 }
206
chip_block_idle(void)207 void chip_block_idle(void)
208 {
209 atomic_inc(&cpu_idle_disabled);
210 }
211
cpu_idle_not_allowed(void)212 bool cpu_idle_not_allowed(void)
213 {
214 return !!(atomic_get(&cpu_idle_disabled));
215 }
216 #endif
217
218 /* The routine must be called with interrupts locked */
riscv_idle(enum chip_pll_mode mode,unsigned int key)219 void riscv_idle(enum chip_pll_mode mode, unsigned int key)
220 {
221 /*
222 * The routine is called with interrupts locked (in kernel/idle()).
223 * But on kernel/context test_kernel_cpu_idle test, the routine will be
224 * called without interrupts locked. Hence we disable M-mode external
225 * interrupt here to protect the below content.
226 */
227 csr_clear(mie, MIP_MEIP);
228 sys_trace_idle();
229 #ifdef CONFIG_ESPI
230 /*
231 * H2RAM feature requires RAM clock to be active. Since the below doze
232 * mode will disable CPU and RAM clocks, enable eSPI transaction
233 * interrupt to restore clocks. With this interrupt, EC will not defer
234 * eSPI bus while transaction is accepted.
235 */
236 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, true);
237 #endif
238 /* Chip doze after wfi instruction */
239 chip_pll_ctrl(mode);
240
241 do {
242 /* Wait for interrupt */
243 __asm__ volatile ("wfi");
244 /*
245 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
246 * register is non-zero.
247 * If the ite_intc_no_irq() is true at this point,
248 * it means that EC waked-up by the above issue not an
249 * interrupt. Hence we loop running wfi instruction here until
250 * wfi success.
251 */
252 } while (ite_intc_no_irq());
253
254 #ifdef CONFIG_ESPI
255 /* CPU has been woken up, the interrupt is no longer needed */
256 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, false);
257 #endif
258 /*
259 * Enable M-mode external interrupt
260 * An interrupt can not be fired yet until we enable global interrupt
261 */
262 csr_set(mie, MIP_MEIP);
263 /* Restore global interrupt lockout state */
264 irq_unlock(key);
265 }
266
arch_cpu_idle(void)267 void arch_cpu_idle(void)
268 {
269 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
270 /*
271 * The EC processor(CPU) cannot be in the k_cpu_idle() during
272 * the transactions with the CQ mode(DMA mode). Otherwise,
273 * the EC processor would be clock gated.
274 */
275 if (cpu_idle_not_allowed()) {
276 /* Restore global interrupt lockout state */
277 irq_unlock(MSTATUS_IEN);
278 } else
279 #endif
280 {
281 riscv_idle(CHIP_PLL_DOZE, MSTATUS_IEN);
282 }
283 }
284
arch_cpu_atomic_idle(unsigned int key)285 void arch_cpu_atomic_idle(unsigned int key)
286 {
287 riscv_idle(CHIP_PLL_DOZE, key);
288 }
289
ite_it8xxx2_init(void)290 static int ite_it8xxx2_init(void)
291 {
292 struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;
293 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
294
295 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb0), disabled)
296 struct usb_it82xx2_regs *const usb_regs = USB_IT82XX2_REGS_BASE;
297
298 usb_regs->port0_misc_control &= ~PULL_DOWN_EN;
299 usb_regs->port1_misc_control &= ~PULL_DOWN_EN;
300 #endif
301
302 /*
303 * bit7: wake up CPU if it is in low power mode and
304 * an interrupt is pending.
305 */
306 gctrl_regs->GCTRL_WMCR |= BIT(7);
307
308 /*
309 * Disable this feature that can detect pre-define hardware
310 * target A through I2C0. This is for debugging use, so it
311 * can be disabled to avoid illegal access.
312 */
313 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
314 IT8XXX2_SMB_SFFCTL &= ~IT8XXX2_SMB_HSAPE;
315 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
316 IT8XXX2_SMB_SCLKTS_BRGS &= ~IT8XXX2_SMB_PREDEN;
317 /*
318 * Setting this bit will disable EGAD pin output driving to avoid
319 * leakage when GPIO E1/E2 on it82002 are set to alternate function.
320 */
321 IT8XXX2_EGPIO_EGCR |= IT8XXX2_EGPIO_EEPODD;
322 #endif
323
324 #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
325 /* UART1 board init */
326 /* bit2: clocks to UART1 modules are not gated. */
327 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
328 IT8XXX2_ECPM_AUTOCG &= ~BIT(6);
329
330 /* bit3: UART1 belongs to the EC side. */
331 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART1SD;
332 /* reset UART before config it */
333 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART1;
334
335 /* switch UART1 on without hardware flow control */
336 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN;
337
338 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
339
340 #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
341 /* UART2 board init */
342 /* setting voltage 3.3v */
343 gpio_regs->GPIO_GCR21 &= ~(IT8XXX2_GPIO_GPH1VS | IT8XXX2_GPIO_GPH2VS);
344 /* bit2: clocks to UART2 modules are not gated. */
345 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
346 IT8XXX2_ECPM_AUTOCG &= ~BIT(5);
347
348 /* bit3: UART2 belongs to the EC side. */
349 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART2SD;
350 /* reset UART before config it */
351 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART2;
352
353 /* switch UART2 on without hardware flow control */
354 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN;
355
356 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
357
358 #if (SOC_USBPD_ITE_PHY_PORT_COUNT > 0)
359 int port;
360
361 /*
362 * To prevent cc pins leakage, we disable board not active ITE
363 * TCPC port cc modules, then cc pins can be used as gpio if needed.
364 */
365 for (port = SOC_USBPD_ITE_ACTIVE_PORT_COUNT;
366 port < SOC_USBPD_ITE_PHY_PORT_COUNT; port++) {
367 struct usbpd_it8xxx2_regs *base;
368
369 if (port == 0) {
370 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd0));
371 } else if (port == 1) {
372 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd1));
373 } else {
374 /* Currently all ITE embedded pd chip support max two ports */
375 break;
376 }
377
378 /* Power down all CC, and disable CC voltage detector */
379 base->CCGCR |= (IT8XXX2_USBPD_DISABLE_CC |
380 IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR);
381 /*
382 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
383 * disconnect CC 5.1K to GND
384 */
385 base->CCCSR |= (IT8XXX2_USBPD_CC2_DISCONNECT |
386 IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND |
387 IT8XXX2_USBPD_CC1_DISCONNECT |
388 IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND);
389 /* Disconnect CC 5V tolerant */
390 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_POWER_CC2 |
391 IT8XXX2_USBPD_DISCONNECT_POWER_CC1);
392 /* Dis-connect 5.1K dead battery resistor to CC */
393 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB |
394 IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB);
395 }
396 #endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
397
398 return 0;
399 }
400 SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
401
