1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include <zephyr/arch/riscv/csr.h>
9 #include <zephyr/kernel.h>
10 #include <zephyr/device.h>
11 #include <zephyr/init.h>
12 #include "ilm.h"
13 #include <soc.h>
14 #include "soc_espi.h"
15 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
16
17
chip_get_pll_freq(void)18 uint32_t chip_get_pll_freq(void)
19 {
20 uint32_t pllfreq;
21
22 switch (IT8XXX2_ECPM_PLLFREQR & 0x0F) {
23 case 0:
24 pllfreq = MHZ(8);
25 break;
26 case 1:
27 pllfreq = MHZ(16);
28 break;
29 case 2:
30 pllfreq = MHZ(24);
31 break;
32 case 3:
33 pllfreq = MHZ(32);
34 break;
35 case 4:
36 pllfreq = MHZ(48);
37 break;
38 case 5:
39 pllfreq = MHZ(64);
40 break;
41 case 6:
42 pllfreq = MHZ(72);
43 break;
44 case 7:
45 pllfreq = MHZ(96);
46 break;
47 default:
48 return -ERANGE;
49 }
50
51 return pllfreq;
52 }
53
chip_pll_ctrl(enum chip_pll_mode mode)54 void __soc_ram_code chip_pll_ctrl(enum chip_pll_mode mode)
55 {
56 volatile uint8_t _pll_ctrl __unused;
57
58 IT8XXX2_ECPM_PLLCTRL = mode;
59 /*
60 * for deep doze / sleep mode
61 * This load operation will ensure PLL setting is taken into
62 * control register before wait for interrupt instruction.
63 */
64 _pll_ctrl = IT8XXX2_ECPM_PLLCTRL;
65 }
66
67 #ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
68 struct pll_config_t {
69 uint8_t pll_freq;
70 uint8_t div_fnd;
71 uint8_t div_uart;
72 uint8_t div_smb;
73 uint8_t div_sspi;
74 uint8_t div_ec;
75 uint8_t div_jtag;
76 uint8_t div_pwm;
77 uint8_t div_usbpd;
78 };
79
80 static const struct pll_config_t pll_configuration[] = {
81 /*
82 * PLL frequency setting = 4 (48MHz)
83 * FND div = 0 (PLL / 1 = 48 mhz)
84 * UART div = 1 (PLL / 2 = 24 mhz)
85 * SMB div = 1 (PLL / 2 = 24 mhz)
86 * SSPI div = 1 (PLL / 2 = 24 mhz)
87 * EC div = 6 (FND / 6 = 8 mhz)
88 * JTAG div = 1 (PLL / 2 = 24 mhz)
89 * PWM div = 0 (PLL / 1 = 48 mhz)
90 * USBPD div = 5 (PLL / 6 = 8 mhz)
91 */
92 {.pll_freq = 4,
93 .div_fnd = 0,
94 .div_uart = 1,
95 .div_smb = 1,
96 .div_sspi = 1,
97 .div_ec = 6,
98 .div_jtag = 1,
99 .div_pwm = 0,
100 .div_usbpd = 5}
101 };
102
chip_run_pll_sequence(const struct pll_config_t * pll)103 void __soc_ram_code chip_run_pll_sequence(const struct pll_config_t *pll)
104 {
105 /* Enable HW timer to wakeup chip from the sleep mode */
106 timer_5ms_one_shot();
107 /*
108 * Configure PLL clock dividers.
109 * Writing data to these registers doesn't change the
110 * PLL frequency immediately until the status is changed
111 * into wakeup from the sleep mode.
112 * The following code is intended to make the system
113 * enter sleep mode, and wait HW timer to wakeup chip to
114 * complete PLL update.
115 */
116 IT8XXX2_ECPM_PLLFREQR = pll->pll_freq;
117 /* Pre-set FND clock frequency = PLL / 3 */
118 IT8XXX2_ECPM_SCDCR0 = (2 << 4);
119 /* JTAG and EC */
120 IT8XXX2_ECPM_SCDCR3 = (pll->div_jtag << 4) | pll->div_ec;
121 /* Chip sleep after wait for interrupt (wfi) instruction */
122 chip_pll_ctrl(CHIP_PLL_SLEEP);
123 /* Chip sleep and wait timer wake it up */
124 __asm__ volatile ("wfi");
125 /* New FND clock frequency */
126 IT8XXX2_ECPM_SCDCR0 = pll->div_fnd << 4;
127 /* Chip doze after wfi instruction */
128 chip_pll_ctrl(CHIP_PLL_DOZE);
129 /* UART */
130 IT8XXX2_ECPM_SCDCR1 = pll->div_uart;
131 /* SSPI and SMB */
132 IT8XXX2_ECPM_SCDCR2 = (pll->div_sspi << 4) | pll->div_smb;
133 /* USBPD and PWM */
134 IT8XXX2_ECPM_SCDCR4 = (pll->div_usbpd << 4) | pll->div_pwm;
135 }
136
chip_configure_pll(const struct pll_config_t * pll)137 static void chip_configure_pll(const struct pll_config_t *pll)
138 {
139 /* Re-configure PLL clock or not. */
140 if (((IT8XXX2_ECPM_PLLFREQR & 0xf) != pll->pll_freq) ||
141 ((IT8XXX2_ECPM_SCDCR0 & 0xf0) != (pll->div_fnd << 4)) ||
142 ((IT8XXX2_ECPM_SCDCR3 & 0xf) != pll->div_ec)) {
143 #ifdef CONFIG_ESPI
144 /*
145 * We have to disable eSPI pad before changing
146 * PLL sequence or sequence will fail if CS# pin is low.
147 */
148 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, false);
149 #endif
150 /* Run change PLL sequence */
151 chip_run_pll_sequence(pll);
152 #ifdef CONFIG_ESPI
153 /* Enable eSPI pad after changing PLL sequence */
154 espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, true);
155 #endif
156 }
157 }
158
chip_change_pll(void)159 static int chip_change_pll(void)
160 {
161
162 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
163 ite_intc_save_and_disable_interrupts();
164 }
165 /* configure PLL/CPU/flash clock */
166 chip_configure_pll(&pll_configuration[0]);
167 if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
168 ite_intc_restore_interrupts();
169 }
170
171 return 0;
172 }
173 SYS_INIT(chip_change_pll, PRE_KERNEL_1, CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY);
174 BUILD_ASSERT(CONFIG_FLASH_INIT_PRIORITY < CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY,
175 "CONFIG_FLASH_INIT_PRIORITY must be less than CONFIG_IT8XXX2_PLL_SEQUENCE_PRIORITY");
176 #endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
177
178 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
179 /* Preventing CPU going into idle mode during command queue. */
180 static atomic_t cpu_idle_disabled;
181
chip_permit_idle(void)182 void chip_permit_idle(void)
183 {
184 atomic_dec(&cpu_idle_disabled);
185 }
186
chip_block_idle(void)187 void chip_block_idle(void)
188 {
189 atomic_inc(&cpu_idle_disabled);
190 }
191
cpu_idle_not_allowed(void)192 bool cpu_idle_not_allowed(void)
193 {
194 return !!(atomic_get(&cpu_idle_disabled));
195 }
196 #endif
197
198 /* The routine must be called with interrupts locked */
riscv_idle(enum chip_pll_mode mode,unsigned int key)199 void riscv_idle(enum chip_pll_mode mode, unsigned int key)
200 {
201 /*
202 * The routine is called with interrupts locked (in kernel/idle()).
203 * But on kernel/context test_kernel_cpu_idle test, the routine will be
204 * called without interrupts locked. Hence we disable M-mode external
205 * interrupt here to protect the below content.
206 */
207 csr_clear(mie, MIP_MEIP);
208 sys_trace_idle();
209 #ifdef CONFIG_ESPI
210 /*
211 * H2RAM feature requires RAM clock to be active. Since the below doze
212 * mode will disable CPU and RAM clocks, enable eSPI transaction
213 * interrupt to restore clocks. With this interrupt, EC will not defer
214 * eSPI bus while transaction is accepted.
215 */
216 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, true);
217 #endif
218 /* Chip doze after wfi instruction */
219 chip_pll_ctrl(mode);
220
221 do {
222 /* Wait for interrupt */
223 __asm__ volatile ("wfi");
224 /*
225 * Sometimes wfi instruction may fail due to CPU's MTIP@mip
226 * register is non-zero.
227 * If the ite_intc_no_irq() is true at this point,
228 * it means that EC waked-up by the above issue not an
229 * interrupt. Hence we loop running wfi instruction here until
230 * wfi success.
231 */
232 } while (ite_intc_no_irq());
233
234 #ifdef CONFIG_ESPI
235 /* CPU has been woken up, the interrupt is no longer needed */
236 espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, false);
237 #endif
238 /*
239 * Enable M-mode external interrupt
240 * An interrupt can not be fired yet until we enable global interrupt
241 */
242 csr_set(mie, MIP_MEIP);
243 /* Restore global interrupt lockout state */
244 irq_unlock(key);
245 }
246
arch_cpu_idle(void)247 void arch_cpu_idle(void)
248 {
249 #ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
250 /*
251 * The EC processor(CPU) cannot be in the k_cpu_idle() during
252 * the transactions with the CQ mode(DMA mode). Otherwise,
253 * the EC processor would be clock gated.
254 */
255 if (cpu_idle_not_allowed()) {
256 /* Restore global interrupt lockout state */
257 irq_unlock(MSTATUS_IEN);
258 } else
259 #endif
260 {
261 riscv_idle(CHIP_PLL_DOZE, MSTATUS_IEN);
262 }
263 }
264
arch_cpu_atomic_idle(unsigned int key)265 void arch_cpu_atomic_idle(unsigned int key)
266 {
267 riscv_idle(CHIP_PLL_DOZE, key);
268 }
269
ite_it8xxx2_init(void)270 static int ite_it8xxx2_init(void)
271 {
272 struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;
273 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
274
275 /*
276 * bit7: wake up CPU if it is in low power mode and
277 * an interrupt is pending.
278 */
279 gctrl_regs->GCTRL_WMCR |= BIT(7);
280
281 /*
282 * Disable this feature that can detect pre-define hardware
283 * target A through I2C0. This is for debugging use, so it
284 * can be disabled to avoid illegal access.
285 */
286 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
287 IT8XXX2_SMB_SFFCTL &= ~IT8XXX2_SMB_HSAPE;
288 #elif CONFIG_SOC_IT8XXX2_REG_SET_V2
289 IT8XXX2_SMB_SCLKTS_BRGS &= ~IT8XXX2_SMB_PREDEN;
290 #endif
291
292 #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
293 /* UART1 board init */
294 /* bit2: clocks to UART1 modules are not gated. */
295 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
296 IT8XXX2_ECPM_AUTOCG &= ~BIT(6);
297
298 /* bit3: UART1 belongs to the EC side. */
299 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART1SD;
300 /* reset UART before config it */
301 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART1;
302
303 /* switch UART1 on without hardware flow control */
304 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN;
305
306 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) */
307
308 #if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
309 /* UART2 board init */
310 /* setting voltage 3.3v */
311 gpio_regs->GPIO_GCR21 &= ~(IT8XXX2_GPIO_GPH1VS | IT8XXX2_GPIO_GPH2VS);
312 /* bit2: clocks to UART2 modules are not gated. */
313 IT8XXX2_ECPM_CGCTRL3R &= ~BIT(2);
314 IT8XXX2_ECPM_AUTOCG &= ~BIT(5);
315
316 /* bit3: UART2 belongs to the EC side. */
317 gctrl_regs->GCTRL_RSTDMMC |= IT8XXX2_GCTRL_UART2SD;
318 /* reset UART before config it */
319 gctrl_regs->GCTRL_RSTC4 = IT8XXX2_GCTRL_RUART2;
320
321 /* switch UART2 on without hardware flow control */
322 gpio_regs->GPIO_GCR1 |= IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN;
323
324 #endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) */
325
326 #if (SOC_USBPD_ITE_PHY_PORT_COUNT > 0)
327 int port;
328
329 /*
330 * To prevent cc pins leakage, we disable board not active ITE
331 * TCPC port cc modules, then cc pins can be used as gpio if needed.
332 */
333 for (port = SOC_USBPD_ITE_ACTIVE_PORT_COUNT;
334 port < SOC_USBPD_ITE_PHY_PORT_COUNT; port++) {
335 struct usbpd_it8xxx2_regs *base;
336
337 if (port == 0) {
338 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd0));
339 } else if (port == 1) {
340 base = (struct usbpd_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(usbpd1));
341 } else {
342 /* Currently all ITE embedded pd chip support max two ports */
343 break;
344 }
345
346 /* Power down all CC, and disable CC voltage detector */
347 base->CCGCR |= (IT8XXX2_USBPD_DISABLE_CC |
348 IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR);
349 /*
350 * Disconnect CC analog module (ex.UP/RD/DET/TX/RX), and
351 * disconnect CC 5.1K to GND
352 */
353 base->CCCSR |= (IT8XXX2_USBPD_CC2_DISCONNECT |
354 IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND |
355 IT8XXX2_USBPD_CC1_DISCONNECT |
356 IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND);
357 /* Disconnect CC 5V tolerant */
358 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_POWER_CC2 |
359 IT8XXX2_USBPD_DISCONNECT_POWER_CC1);
360 /* Dis-connect 5.1K dead battery resistor to CC */
361 base->CCPSR |= (IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB |
362 IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB);
363 }
364 #endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
365
366 return 0;
367 }
368 SYS_INIT(ite_it8xxx2_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
369
