1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include <stdint.h> 18 #include <stdlib.h> 19 #include <stddef.h> 20 #include "soc/soc_caps.h" 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /** 27 * @brief I2S port number, the max port number is (I2S_NUM_MAX -1). 28 */ 29 typedef enum { 30 I2S_NUM_0 = 0, /*!< I2S port 0 */ 31 #if SOC_I2S_NUM > 1 32 I2S_NUM_1 = 1, /*!< I2S port 1 */ 33 #endif 34 I2S_NUM_MAX, /*!< I2S port max */ 35 } i2s_port_t; 36 37 /** 38 * @brief I2S bit width per sample. 39 * 40 */ 41 typedef enum { 42 I2S_BITS_PER_SAMPLE_8BIT = 8, /*!< I2S bits per sample: 8-bits*/ 43 I2S_BITS_PER_SAMPLE_16BIT = 16, /*!< I2S bits per sample: 16-bits*/ 44 I2S_BITS_PER_SAMPLE_24BIT = 24, /*!< I2S bits per sample: 24-bits*/ 45 I2S_BITS_PER_SAMPLE_32BIT = 32, /*!< I2S bits per sample: 32-bits*/ 46 } i2s_bits_per_sample_t; 47 48 /** 49 * @brief I2S channel. 50 * 51 */ 52 typedef enum { 53 I2S_CHANNEL_MONO = 1, /*!< I2S 1 channel (mono)*/ 54 I2S_CHANNEL_STEREO = 2 /*!< I2S 2 channel (stereo)*/ 55 } i2s_channel_t; 56 57 /** 58 * @brief I2S communication standard format 59 * 60 */ 61 typedef enum { 62 // In order to keep compatibility, remain the old definitions and introduce new definitions, 63 I2S_COMM_FORMAT_STAND_I2S = 0X01, /*!< I2S communication I2S Philips standard, data launch at second BCK*/ 64 I2S_COMM_FORMAT_STAND_MSB = 0X03, /*!< I2S communication MSB alignment standard, data launch at first BCK*/ 65 I2S_COMM_FORMAT_STAND_PCM_SHORT = 0x04, /*!< PCM Short standard, also known as DSP mode. The period of synchronization signal (WS) is 1 bck cycle.*/ 66 I2S_COMM_FORMAT_STAND_PCM_LONG = 0x0C, /*!< PCM Long standard. The period of synchronization signal (WS) is channel_bit*bck cycles.*/ 67 I2S_COMM_FORMAT_STAND_MAX, /*!< standard max*/ 68 69 //old definition will be removed in the future. 70 I2S_COMM_FORMAT_I2S __attribute__((deprecated)) = 0x01, /*!< I2S communication format I2S, correspond to `I2S_COMM_FORMAT_STAND_I2S`*/ 71 I2S_COMM_FORMAT_I2S_MSB __attribute__((deprecated)) = 0x01, /*!< I2S format MSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_MSB) correspond to `I2S_COMM_FORMAT_STAND_I2S`*/ 72 I2S_COMM_FORMAT_I2S_LSB __attribute__((deprecated)) = 0x02, /*!< I2S format LSB, (I2S_COMM_FORMAT_I2S |I2S_COMM_FORMAT_I2S_LSB) correspond to `I2S_COMM_FORMAT_STAND_MSB`*/ 73 I2S_COMM_FORMAT_PCM __attribute__((deprecated)) = 0x04, /*!< I2S communication format PCM, correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/ 74 I2S_COMM_FORMAT_PCM_SHORT __attribute__((deprecated)) = 0x04, /*!< PCM Short, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_SHORT) correspond to `I2S_COMM_FORMAT_STAND_PCM_SHORT`*/ 75 I2S_COMM_FORMAT_PCM_LONG __attribute__((deprecated)) = 0x08, /*!< PCM Long, (I2S_COMM_FORMAT_PCM | I2S_COMM_FORMAT_PCM_LONG) correspond to `I2S_COMM_FORMAT_STAND_PCM_LONG`*/ 76 } i2s_comm_format_t; 77 78 /** 79 * @brief I2S channel format type 80 */ 81 typedef enum { 82 I2S_CHANNEL_FMT_RIGHT_LEFT = 0x00, 83 I2S_CHANNEL_FMT_ALL_RIGHT, 84 I2S_CHANNEL_FMT_ALL_LEFT, 85 I2S_CHANNEL_FMT_ONLY_RIGHT, 86 I2S_CHANNEL_FMT_ONLY_LEFT, 87 } i2s_channel_fmt_t; 88 89 /** 90 * @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX 91 * 92 * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip. 93 * 94 */ 95 typedef enum { 96 I2S_MODE_MASTER = 1, /*!< Master mode*/ 97 I2S_MODE_SLAVE = 2, /*!< Slave mode*/ 98 I2S_MODE_TX = 4, /*!< TX mode*/ 99 I2S_MODE_RX = 8, /*!< RX mode*/ 100 #if SOC_I2S_SUPPORTS_ADC_DAC 101 I2S_MODE_DAC_BUILT_IN = 16, /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/ 102 I2S_MODE_ADC_BUILT_IN = 32, /*!< Input I2S data from built-in ADC, each data can be 12-bit width at most*/ 103 #endif 104 #if SOC_I2S_SUPPORTS_PDM 105 I2S_MODE_PDM = 64, /*!< PDM mode*/ 106 #endif 107 } i2s_mode_t; 108 109 /** 110 * @brief I2S source clock 111 * 112 */ 113 typedef enum { 114 I2S_CLK_D2CLK = 0, /*!< Clock from PLL_D2_CLK(160M)*/ 115 I2S_CLK_APLL, /*!< Clock from APLL*/ 116 } i2s_clock_src_t; 117 118 119 /** 120 * @brief I2S configuration parameters for i2s_param_config function 121 * 122 */ 123 typedef struct { 124 i2s_mode_t mode; /*!< I2S work mode*/ 125 int sample_rate; /*!< I2S sample rate*/ 126 i2s_bits_per_sample_t bits_per_sample; /*!< I2S bits per sample*/ 127 i2s_channel_fmt_t channel_format; /*!< I2S channel format */ 128 i2s_comm_format_t communication_format; /*!< I2S communication format */ 129 int intr_alloc_flags; /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */ 130 int dma_buf_count; /*!< I2S DMA Buffer Count */ 131 int dma_buf_len; /*!< I2S DMA Buffer Length */ 132 bool use_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */ 133 bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */ 134 int fixed_mclk; /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value.*/ 135 } i2s_config_t; 136 137 /** 138 * @brief I2S event types 139 * 140 */ 141 typedef enum { 142 I2S_EVENT_DMA_ERROR, 143 I2S_EVENT_TX_DONE, /*!< I2S DMA finish sent 1 buffer*/ 144 I2S_EVENT_RX_DONE, /*!< I2S DMA finish received 1 buffer*/ 145 I2S_EVENT_MAX, /*!< I2S event max index*/ 146 } i2s_event_type_t; 147 148 /** 149 * @brief I2S DAC mode for i2s_set_dac_mode. 150 * 151 * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip. 152 */ 153 typedef enum { 154 I2S_DAC_CHANNEL_DISABLE = 0, /*!< Disable I2S built-in DAC signals*/ 155 I2S_DAC_CHANNEL_RIGHT_EN = 1, /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/ 156 I2S_DAC_CHANNEL_LEFT_EN = 2, /*!< Enable I2S built-in DAC left channel, maps to DAC channel 2 on GPIO26*/ 157 I2S_DAC_CHANNEL_BOTH_EN = 0x3, /*!< Enable both of the I2S built-in DAC channels.*/ 158 I2S_DAC_CHANNEL_MAX = 0x4, /*!< I2S built-in DAC mode max index*/ 159 } i2s_dac_mode_t; 160 161 /** 162 * @brief Event structure used in I2S event queue 163 * 164 */ 165 typedef struct { 166 i2s_event_type_t type; /*!< I2S event type */ 167 size_t size; /*!< I2S data size for I2S_DATA event*/ 168 } i2s_event_t; 169 170 /** 171 * @brief I2S pin number for i2s_set_pin 172 * 173 */ 174 typedef struct { 175 int bck_io_num; /*!< BCK in out pin*/ 176 int ws_io_num; /*!< WS in out pin*/ 177 int data_out_num; /*!< DATA out pin*/ 178 int data_in_num; /*!< DATA in pin*/ 179 } i2s_pin_config_t; 180 181 #if SOC_I2S_SUPPORTS_PDM 182 /** 183 * @brief I2S PDM RX downsample mode 184 */ 185 typedef enum { 186 I2S_PDM_DSR_8S = 0, /*!< downsampling number is 8 for PDM RX mode*/ 187 I2S_PDM_DSR_16S, /*!< downsampling number is 16 for PDM RX mode*/ 188 I2S_PDM_DSR_MAX, 189 } i2s_pdm_dsr_t; 190 191 /** 192 * @brief PDM PCM convter enable/disable. 193 * 194 */ 195 typedef enum { 196 PDM_PCM_CONV_ENABLE, /*!< Enable PDM PCM convert*/ 197 PDM_PCM_CONV_DISABLE, /*!< Disable PDM PCM convert*/ 198 } pdm_pcm_conv_t; 199 #endif 200 201 202 #ifdef __cplusplus 203 } 204 #endif 205
