1 /*
2  * Copyright (c) 2023 Intel Corporation
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _DMA_ANN_1P0_H_
8 #define _DMA_ANN_1P0_H_
9 
10 #include "sedi_driver_common.h"
11 #include "sedi_driver_dma.h"
12 
13 /* driver version */
14 #define SEDI_DMA_DRIVER_VERSION SEDI_DRIVER_VERSION_MAJOR_MINOR(0, 1)
15 
16 #define DMA_MAX_BLOCK_SIZE 4096
17 #define DMA_MISC_REG_OFFSET 0x1000
18 
19 /** DMA channel register map. */
20 typedef struct {
21 	__IO_RW uint32_t sar_low;                       /**< SAR */
22 	__IO_RW uint32_t sar_high;                      /**< SAR */
23 	__IO_RW uint32_t dar_low;                       /**< DAR */
24 	__IO_RW uint32_t dar_high;                      /**< DAR */
25 	__IO_RW uint32_t llp_low;                       /**< LLP */
26 	__IO_RW uint32_t llp_high;                      /**< LLP */
27 	__IO_RW uint32_t ctrl_low;                      /**< CTL */
28 	__IO_RW uint32_t ctrl_high;                     /**< CTL */
29 	__IO_RW uint32_t src_stat_low;                  /**< SSTAT */
30 	__IO_RW uint32_t src_stat_high;                 /**< SSTAT */
31 	__IO_RW uint32_t dst_stat_low;                  /**< DSTAT */
32 	__IO_RW uint32_t dst_stat_high;                 /**< DSTAT */
33 	__IO_RW uint32_t src_stat_addr_low;             /**< SSTATAR */
34 	__IO_RW uint32_t src_stat_addr_high;            /**< SSTATAR */
35 	__IO_RW uint32_t dst_stat_addr_low;             /**< DSTATAR */
36 	__IO_RW uint32_t dst_stat_addr_high;            /**< DSTATAR */
37 	__IO_RW uint32_t cfg_low;                       /**< CFG */
38 	__IO_RW uint32_t cfg_high;                      /**< CFG */
39 	__IO_R uint32_t reserved0[(0x58 - 0x48) >> 2];  /**< Reserved (SW HS) */
40 } dma_chan_reg_t;
41 
42 /** DMA interrupt register map. */
43 typedef struct {
44 	__IO_RW uint32_t raw_tfr_low;           /**< RawTfr */
45 	__IO_RW uint32_t raw_tfr_high;          /**< RawTfr */
46 	__IO_RW uint32_t raw_block_low;         /**< RawBlock */
47 	__IO_RW uint32_t raw_block_high;        /**< RawBlock */
48 	__IO_RW uint32_t raw_src_trans_low;     /**< RawSrcTran */
49 	__IO_RW uint32_t raw_src_trans_high;    /**< RawSrcTran */
50 	__IO_RW uint32_t raw_dst_trans_low;     /**< RawDstTran */
51 	__IO_RW uint32_t raw_dst_trans_high;    /**< RawDstTran */
52 	__IO_RW uint32_t raw_err_low;           /**< RawErr */
53 	__IO_RW uint32_t raw_err_high;          /**< RawErr */
54 	__IO_RW uint32_t status_tfr_low;        /**< StatusTfr */
55 	__IO_RW uint32_t status_tfr_high;       /**< StatusTfr */
56 	__IO_RW uint32_t status_block_low;      /**< StatusBlock */
57 	__IO_RW uint32_t status_block_high;     /**< StatusBlock */
58 	__IO_RW uint32_t status_src_trans_low;  /**< StatusSrcTran */
59 	__IO_RW uint32_t status_src_trans_high; /**< StatusSrcTran */
60 	__IO_RW uint32_t status_dst_trans_low;  /**< StatusDstTran */
61 	__IO_RW uint32_t status_dst_trans_high; /**< StatusDstTran */
62 	__IO_RW uint32_t status_err_low;        /**< StatusErr */
63 	__IO_RW uint32_t status_err_high;       /**< StatusErr */
64 	__IO_RW uint32_t mask_tfr_low;          /**< MaskTfr */
65 	__IO_RW uint32_t mask_tfr_high;         /**< MaskTfr */
66 	__IO_RW uint32_t mask_block_low;        /**< MaskBlock */
67 	__IO_RW uint32_t mask_block_high;       /**< MaskBlock */
68 	__IO_RW uint32_t mask_src_trans_low;    /**< MaskSrcTran */
69 	__IO_RW uint32_t mask_src_trans_high;   /**< MaskSrcTran */
70 	__IO_RW uint32_t mask_dst_trans_low;    /**< MaskDstTran */
71 	__IO_RW uint32_t mask_dst_trans_high;   /**< MaskDstTran */
72 	__IO_RW uint32_t mask_err_low;          /**< MaskErr */
73 	__IO_RW uint32_t mask_err_high;         /**< MaskErr */
74 	__IO_RW uint32_t clear_tfr_low;         /**< ClearTfr */
75 	__IO_RW uint32_t clear_tfr_high;        /**< ClearTfr */
76 	__IO_RW uint32_t clear_block_low;       /**< ClearBlock */
77 	__IO_RW uint32_t clear_block_high;      /**< ClearBlock */
78 	__IO_RW uint32_t clear_src_trans_low;   /**< ClearSrcTran */
79 	__IO_RW uint32_t clear_src_trans_high;  /**< ClearSrcTran */
80 	__IO_RW uint32_t clear_dst_trans_low;   /**< ClearDstTran */
81 	__IO_RW uint32_t clear_dst_trans_high;  /**< ClearDstTran */
82 	__IO_RW uint32_t clear_err_low;         /**< ClearErr */
83 	__IO_RW uint32_t clear_err_high;        /**< ClearErr */
84 	__IO_RW uint32_t status_int_low;        /**< StatusInt */
85 	__IO_RW uint32_t status_int_high;       /**< StatusInt */
86 } dma_int_reg_t;
87 
88 /** DMA miscellaneous register map. */
89 typedef struct {
90 	__IO_RW uint32_t cfg_low;                       /**< DmaCfgReg */
91 	__IO_RW uint32_t cfg_high;                      /**< DmaCfgReg */
92 	__IO_RW uint32_t chan_en_low;                   /**< ChEnReg */
93 	__IO_RW uint32_t chan_en_high;                  /**< ChEnReg */
94 	__IO_R uint32_t
95 		reserved0[(0x3b8 - 0x3a8) >> 2];        /**< Reserved (SW HS) */
96 	__IO_RW uint32_t class_pri0_low;                /**< ClassPriority0 */
97 	__IO_RW uint32_t class_pri0_high;               /**< ClassPriority0 */
98 	__IO_RW uint32_t class_pri1_low;                /**< ClassPriority1 */
99 	__IO_RW uint32_t class_pri1_hign;               /**< ClassPriority1 */
100 	__IO_R uint32_t
101 		reserved1[(0x400 - 0x3c8) >> 2];        /**< Reserved (SW HS) */
102 	__IO_RW uint32_t fifo_pri0_low;                 /**< FifoPriority0 */
103 	__IO_RW uint32_t fifo_pri0_high;                /**< FifoPriority0 */
104 	__IO_RW uint32_t fifo_pri1_low;                 /**< FifoPriority1 */
105 	__IO_RW uint32_t fifo_pri1_hign;                /**< FifoPriority1 */
106 	__IO_RW uint32_t sar_err_low;                   /**< SAR_ERR */
107 	__IO_RW uint32_t sar_err_high;                  /**< SAR_ERR */
108 	__IO_RW uint32_t global_cfg_low;                /**< GLOBAL_CFG */
109 	__IO_RW uint32_t global_cfg_high;               /**< GLOBAL_CFG */
110 } dma_chann_misc_reg_t;
111 
112 /* dma misc register*/
113 typedef struct {
114 	__IO_RW uint32_t dma_ctl_ch[DMA_CHANNEL_NUM]; /**< DMA_CTL_CH> */
115 	__IO_R uint32_t reserved0[(0x100 - 0x20) >> 2];
116 	__IO_RW uint32_t iosf_addr_fillin_dma_ch[DMA_CHANNEL_NUM];
117 	/**< IOSF_ADDR_FILLIN_DMA_CH> */
118 	__IO_R uint32_t reserved1[(0x200 - 0x120) >> 2];
119 	__IO_RW uint32_t iosf_dest_addr_fillin_dma_ch[DMA_CHANNEL_NUM];
120 	/** <IOSF_DEST_ADDR_FILLIN_DMA_CH> */
121 	__IO_R uint32_t reserved2[(0x300 - 0x220) >> 2];
122 	__IO_RW uint32_t dma_xbar_sel[DMA_CHANNEL_NUM]; /**< DMA_XBAR_SEL>*/
123 	__IO_R uint32_t reserved3[(0x400 - 0x320) >> 2];
124 	/**<DMA_REGACCESS_CHID >*/
125 	__IO_RW uint32_t dma_regaccess_chid;
126 	/**<DMA_ECC_ERR_SRESP >*/
127 	__IO_RW uint32_t dma_ecc_err_sresp;
128 	__IO_RW uint32_t d0i3c;                         /**<D0I3C>*/
129 } dma_misc_regs_t;
130 
131 /*dma registers address map structure */
132 typedef struct {
133 	/**< Channel Register */
134 	__IO_RW dma_chan_reg_t chan_reg[DMA_CHANNEL_NUM];
135 	/**< Interrupt Register */
136 	__IO_RW dma_int_reg_t int_reg;
137 	__IO_R uint32_t reserved0[(0x398 - 0x368) >> 2];
138 	/**< Miscellaneous Register */
139 	__IO_RW dma_chann_misc_reg_t misc_reg;
140 	__IO_R uint32_t reserved1[(0x1000 - 0x420) >> 2];
141 	__IO_RW dma_misc_regs_t dev_misc_reg;
142 } dma_ann_1p0_regs_t;
143 
144 /* dma channel control register bit map details*/
145 /* location, part of bits are defined in sedi_driver_dma.h*/
146 #define CH_CLASS_LOC 29
147 #define CH_WEIGHT_LOC 18
148 #define DONE_LOC 17
149 #define BLOCK_TS_LOC 0
150 #define DST_SCATTER_EN_LOC 18
151 #define SRC_GATHER_EN_LOC 17
152 /* bit field length */
153 #define CH_CLASS_LEN 3
154 #define CH_WEIGHT_LEN 11
155 #define DONE_LEN 1
156 #define BLOCK_TS_LEN 17
157 #define LLP_SRC_EN_LEN 1
158 #define LLP_DST_EN_LEN 1
159 #define TT_FC_LEN 2
160 #define DST_SCATTER_EN_LEN 1
161 #define SRC_GATHER_EN_LEN 1
162 #define SRC_MSIZE_LEN 3
163 #define DEST_MSIZE_LEN 3
164 #define SINC_LEN 1
165 #define DINC_LEN 1
166 #define SRC_TR_WIDTH_LEN 3
167 #define DST_TR_WIDTH_LEN 3
168 #define INT_EN_LEN 1
169 
170 /* dma channel config register bit map details*/
171 /* location */
172 #define DST_PER_EXT_LOC 30
173 #define SRC_PER_EXT_LOC 28
174 #define WR_ISSUE_THD_LOC 18
175 #define ED_ISSUE_THD_LOC 8
176 #define DST_PER_LOC 4
177 #define SRC_PER_LOC 0
178 #define RELOAD_DST_LOC 31
179 #define RELOAD_SRC_LOC 30
180 #define SRC_OPT_BL_LOC 21
181 #define DST_OPT_BL_LOC 20
182 #define SRC_HS_POL_LOC 19
183 #define DST_HS_POL_LOC 18
184 #define WR_CTLHI_SNP_LOC 17
185 #define WR_STAT_SNP_LOC 16
186 #define RD_STAT_SNP_LOC 15
187 #define RD_LLP_SNP_LOC 14
188 #define WR_SNP_LOC 13
189 #define RD_SNP_LOC 12
190 #define CH_DRAIN_LOC 10
191 #define FIFO_EMPTY_LOC 9
192 #define CH_SUSP_LOC 8
193 #define SS_UPD_EN_LOC 7
194 #define DS_UPD_EN_LOC 6
195 #define CTL_HI_UPD_EN_LOC 5
196 #define HSHAKE_NP_WR_LOC 3
197 #define ALL_NP_WR_LOC 2
198 #define SRC_BURST_ALIGN_LOC 1
199 #define DST_BURST_ALIGN_LOC 0
200 /* bit field length */
201 #define DST_PER_EXT_LEN 2
202 #define SRC_PER_EXT_LEN 2
203 #define WR_ISSUE_THD_LEN 10
204 #define ED_ISSUE_THD_LEN 10
205 #define DST_PER_LEN 4
206 #define SRC_PER_LEN 4
207 #define RELOAD_DST_LEN 1
208 #define RELOAD_SRC_LEN 1
209 #define SRC_OPT_BL_LEN 1
210 #define DST_OPT_BL_LEN 1
211 #define SRC_HS_POL_LEN 1
212 #define DST_HS_POL_LEN 1
213 #define WR_CTLHI_SNP_LEN 1
214 #define WR_STAT_SNP_LEN 1
215 #define RD_STAT_SNP_LEN 1
216 #define RD_LLP_SNP_LEN 1
217 #define WR_SNP_LEN 1
218 #define RD_SNP_LEN 1
219 #define CH_DRAIN_LEN 1
220 #define FIFO_EMPTY_LEN 1
221 #define CH_SUSP_LEN 1
222 #define SS_UPD_EN_LEN 1
223 #define DS_UPD_EN_LEN 1
224 #define CTL_HI_UPD_EN_LEN 1
225 #define HSHAKE_NP_WR_LEN 1
226 #define ALL_NP_WR_LEN 1
227 #define SRC_BURST_ALIGN_LEN 1
228 #define DST_BURST_ALIGN_LEN 1
229 
230 /* dma controller config reg bit map */
231 #define DMA_EN_LOC 1
232 #define DMA_EN_LEN 1
233 
234 /* dma crossbar hs interface select register bit map */
235 #define RX_TX_LOC 16
236 #define DEVID_LOC 0
237 #define RX_TX_LEN 1
238 #define DEVID_LEN 16
239 
240 /* dma misc control channel reg content */
241 /* location*/
242 #define IOSF_WR_VC01_LOC 11
243 #define IOSF_RD_VC01_LOC 10
244 #define WR_NON_SNOOP_LOC 9
245 #define RD_NON_SNOOP_LOC 8
246 #define WR_RS_LOC 5
247 #define RD_RS_LOC 3
248 #define NON_SNOOP_LOC 2
249 #define M2M_TYPE_LOC 0
250 
251 /* bit field length*/
252 #define IOSF_WR_VC01_LEN 1
253 #define IOSF_RD_VC01_LEN 1
254 #define WR_NON_SNOOP_LEN 1
255 #define RD_NON_SNOOP_LEN 1
256 #define NON_SNOOP_LEN 1
257 #define WR_RS_LEN 2
258 #define RD_RS_LEN 2
259 #define M2M_TYPE_LEN 2
260 
261 #endif /* _DMA_ANN_1P0_H_ */
262