1 /*
2 * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdint.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/delay_timer.h>
13 #include <drivers/st/stm32mp1_usb.h>
14 #include <lib/mmio.h>
15
16 #include <platform_def.h>
17
18 #define USB_OTG_MODE_DEVICE 0U
19 #define USB_OTG_MODE_HOST 1U
20 #define USB_OTG_MODE_DRD 2U
21
22 #define EP_TYPE_CTRL 0U
23 #define EP_TYPE_ISOC 1U
24 #define EP_TYPE_BULK 2U
25 #define EP_TYPE_INTR 3U
26
27 #define USBD_FIFO_FLUSH_TIMEOUT_US 1000U
28 #define EP0_FIFO_SIZE 64U
29
30 /* OTG registers offsets */
31 #define OTG_GOTGINT 0x004U
32 #define OTG_GAHBCFG 0x008U
33 #define OTG_GUSBCFG 0x00CU
34 #define OTG_GRSTCTL 0x010U
35 #define OTG_GINTSTS 0x014U
36 #define OTG_GINTMSK 0x018U
37 #define OTG_GRXSTSP 0x020U
38 #define OTG_GLPMCFG 0x054U
39 #define OTG_DCFG 0x800U
40 #define OTG_DCTL 0x804U
41 #define OTG_DSTS 0x808U
42 #define OTG_DIEPMSK 0x810U
43 #define OTG_DOEPMSK 0x814U
44 #define OTG_DAINT 0x818U
45 #define OTG_DAINTMSK 0x81CU
46 #define OTG_DIEPEMPMSK 0x834U
47
48 /* Definitions for OTG_DIEPx registers */
49 #define OTG_DIEP_BASE 0x900U
50 #define OTG_DIEP_SIZE 0x20U
51 #define OTG_DIEPCTL 0x00U
52 #define OTG_DIEPINT 0x08U
53 #define OTG_DIEPTSIZ 0x10U
54 #define OTG_DIEPDMA 0x14U
55 #define OTG_DTXFSTS 0x18U
56 #define OTG_DIEP_MAX_NB 9U
57
58 /* Definitions for OTG_DOEPx registers */
59 #define OTG_DOEP_BASE 0xB00U
60 #define OTG_DOEP_SIZE 0x20U
61 #define OTG_DOEPCTL 0x00U
62 #define OTG_DOEPINT 0x08U
63 #define OTG_DOEPTSIZ 0x10U
64 #define OTG_DOEPDMA 0x14U
65 #define OTG_D0EP_MAX_NB 9U
66
67 /* Definitions for OTG_DAINT registers */
68 #define OTG_DAINT_OUT_MASK GENMASK(31, 16)
69 #define OTG_DAINT_OUT_SHIFT 16U
70 #define OTG_DAINT_IN_MASK GENMASK(15, 0)
71 #define OTG_DAINT_IN_SHIFT 0U
72
73 #define OTG_DAINT_EP0_IN BIT(16)
74 #define OTG_DAINT_EP0_OUT BIT(0)
75
76 /* Definitions for FIFOs */
77 #define OTG_FIFO_BASE 0x1000U
78 #define OTG_FIFO_SIZE 0x1000U
79
80 /* Bit definitions for OTG_GOTGINT register */
81 #define OTG_GOTGINT_SEDET BIT(2)
82
83 /* Bit definitions for OTG_GAHBCFG register */
84 #define OTG_GAHBCFG_GINT BIT(0)
85
86 /* Bit definitions for OTG_GUSBCFG register */
87 #define OTG_GUSBCFG_TRDT GENMASK(13, 10)
88 #define OTG_GUSBCFG_TRDT_SHIFT 10U
89
90 #define USBD_HS_TRDT_VALUE 9U
91
92 /* Bit definitions for OTG_GRSTCTL register */
93 #define OTG_GRSTCTL_RXFFLSH BIT(4)
94 #define OTG_GRSTCTL_TXFFLSH BIT(5)
95 #define OTG_GRSTCTL_TXFNUM_SHIFT 6U
96
97 /* Bit definitions for OTG_GINTSTS register */
98 #define OTG_GINTSTS_CMOD BIT(0)
99 #define OTG_GINTSTS_MMIS BIT(1)
100 #define OTG_GINTSTS_OTGINT BIT(2)
101 #define OTG_GINTSTS_SOF BIT(3)
102 #define OTG_GINTSTS_RXFLVL BIT(4)
103 #define OTG_GINTSTS_USBSUSP BIT(11)
104 #define OTG_GINTSTS_USBRST BIT(12)
105 #define OTG_GINTSTS_ENUMDNE BIT(13)
106 #define OTG_GINTSTS_IEPINT BIT(18)
107 #define OTG_GINTSTS_OEPINT BIT(19)
108 #define OTG_GINTSTS_IISOIXFR BIT(20)
109 #define OTG_GINTSTS_IPXFR_INCOMPISOOUT BIT(21)
110 #define OTG_GINTSTS_LPMINT BIT(27)
111 #define OTG_GINTSTS_SRQINT BIT(30)
112 #define OTG_GINTSTS_WKUPINT BIT(31)
113
114 /* Bit definitions for OTG_GRXSTSP register */
115 #define OTG_GRXSTSP_EPNUM GENMASK(3, 0)
116 #define OTG_GRXSTSP_BCNT GENMASK(14, 4)
117 #define OTG_GRXSTSP_BCNT_SHIFT 4U
118 #define OTG_GRXSTSP_PKTSTS GENMASK(20, 17)
119 #define OTG_GRXSTSP_PKTSTS_SHIFT 17U
120
121 #define STS_GOUT_NAK 1U
122 #define STS_DATA_UPDT 2U
123 #define STS_XFER_COMP 3U
124 #define STS_SETUP_COMP 4U
125 #define STS_SETUP_UPDT 6U
126
127 /* Bit definitions for OTG_GLPMCFG register */
128 #define OTG_GLPMCFG_BESL GENMASK(5, 2)
129
130 /* Bit definitions for OTG_DCFG register */
131 #define OTG_DCFG_DAD GENMASK(10, 4)
132 #define OTG_DCFG_DAD_SHIFT 4U
133
134 /* Bit definitions for OTG_DCTL register */
135 #define OTG_DCTL_RWUSIG BIT(0)
136 #define OTG_DCTL_SDIS BIT(1)
137 #define OTG_DCTL_CGINAK BIT(8)
138
139 /* Bit definitions for OTG_DSTS register */
140 #define OTG_DSTS_SUSPSTS BIT(0)
141 #define OTG_DSTS_ENUMSPD_MASK GENMASK(2, 1)
142 #define OTG_DSTS_FNSOF0 BIT(8)
143
144 #define OTG_DSTS_ENUMSPD(val) ((val) << 1)
145 #define OTG_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(0U)
146 #define OTG_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ OTG_DSTS_ENUMSPD(1U)
147 #define OTG_DSTS_ENUMSPD_LS_PHY_6MHZ OTG_DSTS_ENUMSPD(2U)
148 #define OTG_DSTS_ENUMSPD_FS_PHY_48MHZ OTG_DSTS_ENUMSPD(3U)
149
150 /* Bit definitions for OTG_DIEPMSK register */
151 #define OTG_DIEPMSK_XFRCM BIT(0)
152 #define OTG_DIEPMSK_EPDM BIT(1)
153 #define OTG_DIEPMSK_TOM BIT(3)
154
155 /* Bit definitions for OTG_DOEPMSK register */
156 #define OTG_DOEPMSK_XFRCM BIT(0)
157 #define OTG_DOEPMSK_EPDM BIT(1)
158 #define OTG_DOEPMSK_STUPM BIT(3)
159
160 /* Bit definitions for OTG_DIEPCTLx registers */
161 #define OTG_DIEPCTL_MPSIZ GENMASK(10, 0)
162 #define OTG_DIEPCTL_STALL BIT(21)
163 #define OTG_DIEPCTL_CNAK BIT(26)
164 #define OTG_DIEPCTL_SD0PID_SEVNFRM BIT(28)
165 #define OTG_DIEPCTL_SODDFRM BIT(29)
166 #define OTG_DIEPCTL_EPDIS BIT(30)
167 #define OTG_DIEPCTL_EPENA BIT(31)
168
169 /* Bit definitions for OTG_DIEPINTx registers */
170 #define OTG_DIEPINT_XFRC BIT(0)
171 #define OTG_DIEPINT_EPDISD BIT(1)
172 #define OTG_DIEPINT_TOC BIT(3)
173 #define OTG_DIEPINT_ITTXFE BIT(4)
174 #define OTG_DIEPINT_INEPNE BIT(6)
175 #define OTG_DIEPINT_TXFE BIT(7)
176 #define OTG_DIEPINT_TXFE_SHIFT 7U
177
178 #define OTG_DIEPINT_MASK (BIT(13) | BIT(11) | GENMASK(9, 0))
179
180 /* Bit definitions for OTG_DIEPTSIZx registers */
181 #define OTG_DIEPTSIZ_XFRSIZ GENMASK(18, 0)
182 #define OTG_DIEPTSIZ_PKTCNT GENMASK(28, 19)
183 #define OTG_DIEPTSIZ_PKTCNT_SHIFT 19U
184 #define OTG_DIEPTSIZ_MCNT_MASK GENMASK(30, 29)
185 #define OTG_DIEPTSIZ_MCNT_DATA0 BIT(29)
186
187 #define OTG_DIEPTSIZ_PKTCNT_1 BIT(19)
188
189 /* Bit definitions for OTG_DTXFSTSx registers */
190 #define OTG_DTXFSTS_INEPTFSAV GENMASK(15, 0)
191
192 /* Bit definitions for OTG_DOEPCTLx registers */
193 #define OTG_DOEPCTL_STALL BIT(21)
194 #define OTG_DOEPCTL_CNAK BIT(26)
195 #define OTG_DOEPCTL_SD0PID_SEVNFRM BIT(28) /* other than endpoint 0 */
196 #define OTG_DOEPCTL_SD1PID_SODDFRM BIT(29) /* other than endpoint 0 */
197 #define OTG_DOEPCTL_EPDIS BIT(30)
198 #define OTG_DOEPCTL_EPENA BIT(31)
199
200 /* Bit definitions for OTG_DOEPTSIZx registers */
201 #define OTG_DOEPTSIZ_XFRSIZ GENMASK(18, 0)
202 #define OTG_DOEPTSIZ_PKTCNT GENMASK(28, 19)
203 #define OTG_DOEPTSIZ_RXDPID_STUPCNT GENMASK(30, 29)
204
205 /* Bit definitions for OTG_DOEPINTx registers */
206 #define OTG_DOEPINT_XFRC BIT(0)
207 #define OTG_DOEPINT_STUP BIT(3)
208 #define OTG_DOEPINT_OTEPDIS BIT(4)
209
210 #define OTG_DOEPINT_MASK (GENMASK(15, 12) | GENMASK(9, 8) | GENMASK(6, 0))
211
212 #define EP_NB 15U
213 #define EP_ALL 0x10U
214
215 /*
216 * Flush TX FIFO.
217 * handle: PCD handle.
218 * num: FIFO number.
219 * This parameter can be a value from 1 to 15 or EP_ALL.
220 * EP_ALL= 0x10 means Flush all TX FIFOs
221 * return: USB status.
222 */
usb_dwc2_flush_tx_fifo(void * handle,uint32_t num)223 static enum usb_status usb_dwc2_flush_tx_fifo(void *handle, uint32_t num)
224 {
225 uintptr_t usb_base_addr = (uintptr_t)handle;
226 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
227
228 mmio_write_32(usb_base_addr + OTG_GRSTCTL,
229 OTG_GRSTCTL_TXFFLSH | (uint32_t)(num << OTG_GRSTCTL_TXFNUM_SHIFT));
230
231 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
232 OTG_GRSTCTL_TXFFLSH) == OTG_GRSTCTL_TXFFLSH) {
233 if (timeout_elapsed(timeout)) {
234 return USBD_TIMEOUT;
235 }
236 }
237
238 return USBD_OK;
239 }
240
241 /*
242 * Flush RX FIFO.
243 * handle: PCD handle.
244 * return: USB status.
245 */
usb_dwc2_flush_rx_fifo(void * handle)246 static enum usb_status usb_dwc2_flush_rx_fifo(void *handle)
247 {
248 uintptr_t usb_base_addr = (uintptr_t)handle;
249 uint64_t timeout = timeout_init_us(USBD_FIFO_FLUSH_TIMEOUT_US);
250
251 mmio_write_32(usb_base_addr + OTG_GRSTCTL, OTG_GRSTCTL_RXFFLSH);
252
253 while ((mmio_read_32(usb_base_addr + OTG_GRSTCTL) &
254 OTG_GRSTCTL_RXFFLSH) == OTG_GRSTCTL_RXFFLSH) {
255 if (timeout_elapsed(timeout)) {
256 return USBD_TIMEOUT;
257 }
258 }
259
260 return USBD_OK;
261 }
262
263 /*
264 * Return the global USB interrupt status.
265 * handle: PCD handle.
266 * return: Interrupt register value.
267 */
usb_dwc2_read_int(void * handle)268 static uint32_t usb_dwc2_read_int(void *handle)
269 {
270 uintptr_t usb_base_addr = (uintptr_t)handle;
271
272 return mmio_read_32(usb_base_addr + OTG_GINTSTS) &
273 mmio_read_32(usb_base_addr + OTG_GINTMSK);
274 }
275
276 /*
277 * Return the USB device OUT endpoints interrupt.
278 * handle: PCD handle.
279 * return: Device OUT endpoint interrupts.
280 */
usb_dwc2_all_out_ep_int(void * handle)281 static uint32_t usb_dwc2_all_out_ep_int(void *handle)
282 {
283 uintptr_t usb_base_addr = (uintptr_t)handle;
284
285 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
286 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
287 OTG_DAINT_OUT_MASK) >> OTG_DAINT_OUT_SHIFT;
288 }
289
290 /*
291 * Return the USB device IN endpoints interrupt.
292 * handle: PCD handle.
293 * return: Device IN endpoint interrupts.
294 */
usb_dwc2_all_in_ep_int(void * handle)295 static uint32_t usb_dwc2_all_in_ep_int(void *handle)
296 {
297 uintptr_t usb_base_addr = (uintptr_t)handle;
298
299 return ((mmio_read_32(usb_base_addr + OTG_DAINT) &
300 mmio_read_32(usb_base_addr + OTG_DAINTMSK)) &
301 OTG_DAINT_IN_MASK) >> OTG_DAINT_IN_SHIFT;
302 }
303
304 /*
305 * Return Device OUT EP interrupt register.
306 * handle: PCD handle.
307 * epnum: Endpoint number.
308 * This parameter can be a value from 0 to 15.
309 * return: Device OUT EP Interrupt register.
310 */
usb_dwc2_out_ep_int(void * handle,uint8_t epnum)311 static uint32_t usb_dwc2_out_ep_int(void *handle, uint8_t epnum)
312 {
313 uintptr_t usb_base_addr = (uintptr_t)handle;
314
315 return mmio_read_32(usb_base_addr + OTG_DOEP_BASE +
316 (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT) &
317 mmio_read_32(usb_base_addr + OTG_DOEPMSK);
318 }
319
320 /*
321 * Return Device IN EP interrupt register.
322 * handle: PCD handle.
323 * epnum: Endpoint number.
324 * This parameter can be a value from 0 to 15.
325 * return: Device IN EP Interrupt register.
326 */
usb_dwc2_in_ep_int(void * handle,uint8_t epnum)327 static uint32_t usb_dwc2_in_ep_int(void *handle, uint8_t epnum)
328 {
329 uintptr_t usb_base_addr = (uintptr_t)handle;
330 uint32_t msk;
331 uint32_t emp;
332
333 msk = mmio_read_32(usb_base_addr + OTG_DIEPMSK);
334 emp = mmio_read_32(usb_base_addr + OTG_DIEPEMPMSK);
335 msk |= ((emp >> epnum) << OTG_DIEPINT_TXFE_SHIFT) & OTG_DIEPINT_TXFE;
336
337 return mmio_read_32(usb_base_addr + OTG_DIEP_BASE +
338 (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT) & msk;
339 }
340
341 /*
342 * Return USB core mode.
343 * handle: PCD handle.
344 * return: Core mode.
345 * This parameter can be 0 (host) or 1 (device).
346 */
usb_dwc2_get_mode(void * handle)347 static uint32_t usb_dwc2_get_mode(void *handle)
348 {
349 uintptr_t usb_base_addr = (uintptr_t)handle;
350
351 return mmio_read_32(usb_base_addr + OTG_GINTSTS) & OTG_GINTSTS_CMOD;
352 }
353
354 /*
355 * Activate EP0 for detup transactions.
356 * handle: PCD handle.
357 * return: USB status.
358 */
usb_dwc2_activate_setup(void * handle)359 static enum usb_status usb_dwc2_activate_setup(void *handle)
360 {
361 uintptr_t usb_base_addr = (uintptr_t)handle;
362 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE;
363
364 /* Set the MPS of the IN EP based on the enumeration speed */
365 mmio_clrbits_32(reg_offset + OTG_DIEPCTL, OTG_DIEPCTL_MPSIZ);
366
367 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_ENUMSPD_MASK) ==
368 OTG_DSTS_ENUMSPD_LS_PHY_6MHZ) {
369 mmio_setbits_32(reg_offset + OTG_DIEPCTL, 3U);
370 }
371
372 mmio_setbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_CGINAK);
373
374 return USBD_OK;
375 }
376
377 /*
378 * Prepare the EP0 to start the first control setup.
379 * handle: Selected device.
380 * return: USB status.
381 */
usb_dwc2_ep0_out_start(void * handle)382 static enum usb_status usb_dwc2_ep0_out_start(void *handle)
383 {
384 uintptr_t usb_base_addr = (uintptr_t)handle;
385 uintptr_t reg_offset = usb_base_addr + OTG_DIEP_BASE + OTG_DIEPTSIZ;
386 uint32_t reg_value = 0U;
387
388 /* PKTCNT = 1 and XFRSIZ = 24 bytes for endpoint 0 */
389 reg_value |= OTG_DIEPTSIZ_PKTCNT_1;
390 reg_value |= (EP0_FIFO_SIZE & OTG_DIEPTSIZ_XFRSIZ);
391 reg_value |= OTG_DOEPTSIZ_RXDPID_STUPCNT;
392
393 mmio_write_32(reg_offset, reg_value);
394
395 return USBD_OK;
396 }
397
398 /*
399 * Write a packet into the TX FIFO associated with the EP/channel.
400 * handle: Selected device.
401 * src: Pointer to source buffer.
402 * ch_ep_num: Endpoint or host channel number.
403 * len: Number of bytes to write.
404 * return: USB status.
405 */
usb_dwc2_write_packet(void * handle,uint8_t * src,uint8_t ch_ep_num,uint16_t len)406 static enum usb_status usb_dwc2_write_packet(void *handle, uint8_t *src,
407 uint8_t ch_ep_num, uint16_t len)
408 {
409 uint32_t reg_offset;
410 uint32_t count32b = (len + 3U) / 4U;
411 uint32_t i;
412
413 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE +
414 (ch_ep_num * OTG_FIFO_SIZE);
415
416 for (i = 0U; i < count32b; i++) {
417 uint32_t src_copy = 0U;
418 uint32_t j;
419
420 /* Data written to FIFO need to be 4 bytes aligned */
421 for (j = 0U; j < 4U; j++) {
422 src_copy += (*(src + j)) << (8U * j);
423 }
424
425 mmio_write_32(reg_offset, src_copy);
426 src += 4U;
427 }
428
429 return USBD_OK;
430 }
431
432 /*
433 * Read a packet from the RX FIFO associated with the EP/channel.
434 * handle: Selected device.
435 * dst: Destination pointer.
436 * len: Number of bytes to read.
437 * return: Pointer to destination buffer.
438 */
usb_dwc2_read_packet(void * handle,uint8_t * dest,uint16_t len)439 static void *usb_dwc2_read_packet(void *handle, uint8_t *dest, uint16_t len)
440 {
441 uint32_t reg_offset;
442 uint32_t count32b = (len + 3U) / 4U;
443 uint32_t i;
444
445 VERBOSE("read packet length %i to 0x%lx\n", len, (uintptr_t)dest);
446
447 reg_offset = (uintptr_t)handle + OTG_FIFO_BASE;
448
449 for (i = 0U; i < count32b; i++) {
450 *(uint32_t *)dest = mmio_read_32(reg_offset);
451 dest += 4U;
452 dsb();
453 }
454
455 return (void *)dest;
456 }
457
458 /*
459 * Setup and start a transfer over an EP.
460 * handle: Selected device
461 * ep: Pointer to endpoint structure.
462 * return: USB status.
463 */
usb_dwc2_ep_start_xfer(void * handle,struct usbd_ep * ep)464 static enum usb_status usb_dwc2_ep_start_xfer(void *handle, struct usbd_ep *ep)
465 {
466 uintptr_t usb_base_addr = (uintptr_t)handle;
467 uint32_t reg_offset;
468 uint32_t reg_value;
469 uint32_t clear_value;
470
471 if (ep->is_in) {
472 reg_offset = usb_base_addr + OTG_DIEP_BASE + (ep->num * OTG_DIEP_SIZE);
473 clear_value = OTG_DIEPTSIZ_PKTCNT | OTG_DIEPTSIZ_XFRSIZ;
474 if (ep->xfer_len == 0U) {
475 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
476 } else {
477 /*
478 * Program the transfer size and packet count
479 * as follows:
480 * xfersize = N * maxpacket + short_packet
481 * pktcnt = N + (short_packet exist ? 1 : 0)
482 */
483 reg_value = (OTG_DIEPTSIZ_PKTCNT &
484 (((ep->xfer_len + ep->maxpacket - 1U) /
485 ep->maxpacket) << OTG_DIEPTSIZ_PKTCNT_SHIFT))
486 | ep->xfer_len;
487
488 if (ep->type == EP_TYPE_ISOC) {
489 clear_value |= OTG_DIEPTSIZ_MCNT_MASK;
490 reg_value |= OTG_DIEPTSIZ_MCNT_DATA0;
491 }
492 }
493
494 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ, clear_value, reg_value);
495
496 if ((ep->type != EP_TYPE_ISOC) && (ep->xfer_len > 0U)) {
497 /* Enable the TX FIFO empty interrupt for this EP */
498 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(ep->num));
499 }
500
501 /* EP enable, IN data in FIFO */
502 reg_value = OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA;
503
504 if (ep->type == EP_TYPE_ISOC) {
505 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
506 reg_value |= OTG_DIEPCTL_SODDFRM;
507 } else {
508 reg_value |= OTG_DIEPCTL_SD0PID_SEVNFRM;
509 }
510 }
511
512 mmio_setbits_32(reg_offset + OTG_DIEPCTL, reg_value);
513
514 if (ep->type == EP_TYPE_ISOC) {
515 usb_dwc2_write_packet(handle, ep->xfer_buff, ep->num, ep->xfer_len);
516 }
517 } else {
518 reg_offset = usb_base_addr + OTG_DOEP_BASE + (ep->num * OTG_DOEP_SIZE);
519 /*
520 * Program the transfer size and packet count as follows:
521 * pktcnt = N
522 * xfersize = N * maxpacket
523 */
524 if (ep->xfer_len == 0U) {
525 reg_value = ep->maxpacket | OTG_DIEPTSIZ_PKTCNT_1;
526 } else {
527 uint16_t pktcnt = (ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket;
528
529 reg_value = (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT) |
530 (ep->maxpacket * pktcnt);
531 }
532
533 mmio_clrsetbits_32(reg_offset + OTG_DOEPTSIZ,
534 OTG_DOEPTSIZ_XFRSIZ & OTG_DOEPTSIZ_PKTCNT,
535 reg_value);
536
537 /* EP enable */
538 reg_value = OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA;
539
540 if (ep->type == EP_TYPE_ISOC) {
541 if ((mmio_read_32(usb_base_addr + OTG_DSTS) & OTG_DSTS_FNSOF0) == 0U) {
542 reg_value |= OTG_DOEPCTL_SD1PID_SODDFRM;
543 } else {
544 reg_value |= OTG_DOEPCTL_SD0PID_SEVNFRM;
545 }
546 }
547
548 mmio_setbits_32(reg_offset + OTG_DOEPCTL, reg_value);
549 }
550
551 return USBD_OK;
552 }
553
554 /*
555 * Setup and start a transfer over the EP0.
556 * handle: Selected device.
557 * ep: Pointer to endpoint structure.
558 * return: USB status.
559 */
usb_dwc2_ep0_start_xfer(void * handle,struct usbd_ep * ep)560 static enum usb_status usb_dwc2_ep0_start_xfer(void *handle, struct usbd_ep *ep)
561 {
562 uintptr_t usb_base_addr = (uintptr_t)handle;
563 uint32_t reg_offset;
564 uint32_t reg_value;
565
566 if (ep->is_in) {
567 reg_offset = usb_base_addr + OTG_DIEP_BASE +
568 (ep->num * OTG_DIEP_SIZE);
569
570 if (ep->xfer_len == 0U) {
571 reg_value = OTG_DIEPTSIZ_PKTCNT_1;
572 } else {
573 /*
574 * Program the transfer size and packet count
575 * as follows:
576 * xfersize = N * maxpacket + short_packet
577 * pktcnt = N + (short_packet exist ? 1 : 0)
578 */
579
580 if (ep->xfer_len > ep->maxpacket) {
581 ep->xfer_len = ep->maxpacket;
582 }
583
584 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->xfer_len;
585 }
586
587 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
588 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
589 reg_value);
590
591 /* Enable the TX FIFO empty interrupt for this EP */
592 if (ep->xfer_len > 0U) {
593 mmio_setbits_32(usb_base_addr + OTG_DIEPEMPMSK,
594 BIT(ep->num));
595 }
596
597 /* EP enable, IN data in FIFO */
598 mmio_setbits_32(reg_offset + OTG_DIEPCTL,
599 OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA);
600 } else {
601 reg_offset = usb_base_addr + OTG_DOEP_BASE +
602 (ep->num * OTG_DOEP_SIZE);
603
604 /*
605 * Program the transfer size and packet count as follows:
606 * pktcnt = N
607 * xfersize = N * maxpacket
608 */
609 if (ep->xfer_len > 0U) {
610 ep->xfer_len = ep->maxpacket;
611 }
612
613 reg_value = OTG_DIEPTSIZ_PKTCNT_1 | ep->maxpacket;
614
615 mmio_clrsetbits_32(reg_offset + OTG_DIEPTSIZ,
616 OTG_DIEPTSIZ_XFRSIZ | OTG_DIEPTSIZ_PKTCNT,
617 reg_value);
618
619 /* EP enable */
620 mmio_setbits_32(reg_offset + OTG_DOEPCTL,
621 OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA);
622 }
623
624 return USBD_OK;
625 }
626
627 /*
628 * Set a stall condition over an EP.
629 * handle: Selected device.
630 * ep: Pointer to endpoint structure.
631 * return: USB status.
632 */
usb_dwc2_ep_set_stall(void * handle,struct usbd_ep * ep)633 static enum usb_status usb_dwc2_ep_set_stall(void *handle, struct usbd_ep *ep)
634 {
635 uintptr_t usb_base_addr = (uintptr_t)handle;
636 uint32_t reg_offset;
637 uint32_t reg_value;
638
639 if (ep->is_in) {
640 reg_offset = usb_base_addr + OTG_DIEP_BASE +
641 (ep->num * OTG_DIEP_SIZE);
642 reg_value = mmio_read_32(reg_offset + OTG_DIEPCTL);
643
644 if ((reg_value & OTG_DIEPCTL_EPENA) == 0U) {
645 reg_value &= ~OTG_DIEPCTL_EPDIS;
646 }
647
648 reg_value |= OTG_DIEPCTL_STALL;
649
650 mmio_write_32(reg_offset + OTG_DIEPCTL, reg_value);
651 } else {
652 reg_offset = usb_base_addr + OTG_DOEP_BASE +
653 (ep->num * OTG_DOEP_SIZE);
654 reg_value = mmio_read_32(reg_offset + OTG_DOEPCTL);
655
656 if ((reg_value & OTG_DOEPCTL_EPENA) == 0U) {
657 reg_value &= ~OTG_DOEPCTL_EPDIS;
658 }
659
660 reg_value |= OTG_DOEPCTL_STALL;
661
662 mmio_write_32(reg_offset + OTG_DOEPCTL, reg_value);
663 }
664
665 return USBD_OK;
666 }
667
668 /*
669 * Stop the USB device mode.
670 * handle: Selected device.
671 * return: USB status.
672 */
usb_dwc2_stop_device(void * handle)673 static enum usb_status usb_dwc2_stop_device(void *handle)
674 {
675 uintptr_t usb_base_addr = (uintptr_t)handle;
676 uint32_t i;
677
678 /* Disable Int */
679 mmio_clrbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
680
681 /* Clear pending interrupts */
682 for (i = 0U; i < EP_NB; i++) {
683 mmio_write_32(usb_base_addr + OTG_DIEP_BASE + (i * OTG_DIEP_SIZE) + OTG_DIEPINT,
684 OTG_DIEPINT_MASK);
685 mmio_write_32(usb_base_addr + OTG_DOEP_BASE + (i * OTG_DOEP_SIZE) + OTG_DOEPINT,
686 OTG_DOEPINT_MASK);
687 }
688
689 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
690
691 /* Clear interrupt masks */
692 mmio_write_32(usb_base_addr + OTG_DIEPMSK, 0U);
693 mmio_write_32(usb_base_addr + OTG_DOEPMSK, 0U);
694 mmio_write_32(usb_base_addr + OTG_DAINTMSK, 0U);
695
696 /* Flush the FIFO */
697 usb_dwc2_flush_rx_fifo(handle);
698 usb_dwc2_flush_tx_fifo(handle, EP_ALL);
699
700 /* Disconnect the USB device by disabling the pull-up/pull-down */
701 mmio_setbits_32((uintptr_t)handle + OTG_DCTL, OTG_DCTL_SDIS);
702
703 return USBD_OK;
704 }
705
706 /*
707 * Stop the USB device mode.
708 * handle: Selected device.
709 * address: New device address to be assigned.
710 * This parameter can be a value from 0 to 255.
711 * return: USB status.
712 */
usb_dwc2_set_address(void * handle,uint8_t address)713 static enum usb_status usb_dwc2_set_address(void *handle, uint8_t address)
714 {
715 uintptr_t usb_base_addr = (uintptr_t)handle;
716
717 mmio_clrsetbits_32(usb_base_addr + OTG_DCFG,
718 OTG_DCFG_DAD,
719 address << OTG_DCFG_DAD_SHIFT);
720
721 return USBD_OK;
722 }
723
724 /*
725 * Check FIFO for the next packet to be loaded.
726 * handle: Selected device.
727 * epnum : Endpoint number.
728 * xfer_len: Block length.
729 * xfer_count: Number of blocks.
730 * maxpacket: Max packet length.
731 * xfer_buff: Buffer pointer.
732 * return: USB status.
733 */
usb_dwc2_write_empty_tx_fifo(void * handle,uint32_t epnum,uint32_t xfer_len,uint32_t * xfer_count,uint32_t maxpacket,uint8_t ** xfer_buff)734 static enum usb_status usb_dwc2_write_empty_tx_fifo(void *handle,
735 uint32_t epnum,
736 uint32_t xfer_len,
737 uint32_t *xfer_count,
738 uint32_t maxpacket,
739 uint8_t **xfer_buff)
740 {
741 uintptr_t usb_base_addr = (uintptr_t)handle;
742 uint32_t reg_offset;
743 int32_t len;
744 uint32_t len32b;
745 enum usb_status ret;
746
747 len = xfer_len - *xfer_count;
748
749 if ((len > 0) && ((uint32_t)len > maxpacket)) {
750 len = maxpacket;
751 }
752
753 len32b = (len + 3U) / 4U;
754
755 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE);
756
757 while (((mmio_read_32(reg_offset + OTG_DTXFSTS) &
758 OTG_DTXFSTS_INEPTFSAV) > len32b) &&
759 (*xfer_count < xfer_len) && (xfer_len != 0U)) {
760 /* Write the FIFO */
761 len = xfer_len - *xfer_count;
762
763 if ((len > 0) && ((uint32_t)len > maxpacket)) {
764 len = maxpacket;
765 }
766
767 len32b = (len + 3U) / 4U;
768
769 ret = usb_dwc2_write_packet(handle, *xfer_buff, epnum, len);
770 if (ret != USBD_OK) {
771 return ret;
772 }
773
774 *xfer_buff += len;
775 *xfer_count += len;
776 }
777
778 if (len <= 0) {
779 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
780 }
781
782 return USBD_OK;
783 }
784
785 /*
786 * Handle PCD interrupt request.
787 * handle: PCD handle.
788 * param: Pointer to information updated by the IT handling.
789 * return: Action to do after IT handling.
790 */
usb_dwc2_it_handler(void * handle,uint32_t * param)791 static enum usb_action usb_dwc2_it_handler(void *handle, uint32_t *param)
792 {
793 uintptr_t usb_base_addr = (uintptr_t)handle;
794 uint32_t ep_intr;
795 uint32_t epint;
796 uint32_t epnum;
797 uint32_t temp;
798 enum usb_status __unused ret;
799
800 if (usb_dwc2_get_mode(handle) != USB_OTG_MODE_DEVICE) {
801 return USB_NOTHING;
802 }
803
804 /* Avoid spurious interrupt */
805 if (usb_dwc2_read_int(handle) == 0U) {
806 return USB_NOTHING;
807 }
808
809 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_MMIS) != 0U) {
810 /* Incorrect mode, acknowledge the interrupt */
811 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_MMIS);
812 }
813
814 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OEPINT) != 0U) {
815 uint32_t reg_offset;
816
817 /* Read in the device interrupt bits */
818 ep_intr = usb_dwc2_all_out_ep_int(handle);
819 epnum = 0U;
820 while ((ep_intr & BIT(0)) != BIT(0)) {
821 epnum++;
822 ep_intr >>= 1;
823 }
824
825 reg_offset = usb_base_addr + OTG_DOEP_BASE + (epnum * OTG_DOEP_SIZE) + OTG_DOEPINT;
826
827 epint = usb_dwc2_out_ep_int(handle, epnum);
828
829 if ((epint & OTG_DOEPINT_XFRC) == OTG_DOEPINT_XFRC) {
830 mmio_write_32(reg_offset, OTG_DOEPINT_XFRC);
831 *param = epnum;
832
833 return USB_DATA_OUT;
834 }
835
836 if ((epint & OTG_DOEPINT_STUP) == OTG_DOEPINT_STUP) {
837 /* Inform that a setup packet is available */
838 mmio_write_32(reg_offset, OTG_DOEPINT_STUP);
839
840 return USB_SETUP;
841 }
842
843 if ((epint & OTG_DOEPINT_OTEPDIS) == OTG_DOEPINT_OTEPDIS) {
844 mmio_write_32(reg_offset, OTG_DOEPINT_OTEPDIS);
845 }
846 }
847
848 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IEPINT) != 0U) {
849 uint32_t reg_offset;
850
851 /* Read in the device interrupt bits */
852 ep_intr = usb_dwc2_all_in_ep_int(handle);
853 epnum = 0U;
854 while ((ep_intr & BIT(0)) != BIT(0)) {
855 epnum++;
856 ep_intr >>= 1;
857 }
858
859 reg_offset = usb_base_addr + OTG_DIEP_BASE + (epnum * OTG_DIEP_SIZE) + OTG_DIEPINT;
860
861 epint = usb_dwc2_in_ep_int(handle, epnum);
862
863 if ((epint & OTG_DIEPINT_XFRC) == OTG_DIEPINT_XFRC) {
864 mmio_clrbits_32(usb_base_addr + OTG_DIEPEMPMSK, BIT(epnum));
865 mmio_write_32(reg_offset, OTG_DIEPINT_XFRC);
866 *param = epnum;
867
868 return USB_DATA_IN;
869 }
870
871 if ((epint & OTG_DIEPINT_TOC) == OTG_DIEPINT_TOC) {
872 mmio_write_32(reg_offset, OTG_DIEPINT_TOC);
873 }
874
875 if ((epint & OTG_DIEPINT_ITTXFE) == OTG_DIEPINT_ITTXFE) {
876 mmio_write_32(reg_offset, OTG_DIEPINT_ITTXFE);
877 }
878
879 if ((epint & OTG_DIEPINT_INEPNE) == OTG_DIEPINT_INEPNE) {
880 mmio_write_32(reg_offset, OTG_DIEPINT_INEPNE);
881 }
882
883 if ((epint & OTG_DIEPINT_EPDISD) == OTG_DIEPINT_EPDISD) {
884 mmio_write_32(reg_offset, OTG_DIEPINT_EPDISD);
885 }
886
887 if ((epint & OTG_DIEPINT_TXFE) == OTG_DIEPINT_TXFE) {
888 *param = epnum;
889
890 return USB_WRITE_EMPTY;
891 }
892 }
893
894 /* Handle resume interrupt */
895 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_WKUPINT) != 0U) {
896 INFO("handle USB : Resume\n");
897
898 /* Clear the remote wake-up signaling */
899 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
900 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_WKUPINT);
901
902 return USB_RESUME;
903 }
904
905 /* Handle suspend interrupt */
906 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBSUSP) != 0U) {
907 INFO("handle USB : Suspend int\n");
908
909 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBSUSP);
910
911 if ((mmio_read_32(usb_base_addr + OTG_DSTS) &
912 OTG_DSTS_SUSPSTS) == OTG_DSTS_SUSPSTS) {
913 return USB_SUSPEND;
914 }
915 }
916
917 /* Handle LPM interrupt */
918 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_LPMINT) != 0U) {
919 INFO("handle USB : LPM int enter in suspend\n");
920
921 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_LPMINT);
922 *param = (mmio_read_32(usb_base_addr + OTG_GLPMCFG) &
923 OTG_GLPMCFG_BESL) >> 2;
924
925 return USB_LPM;
926 }
927
928 /* Handle reset interrupt */
929 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_USBRST) != 0U) {
930 INFO("handle USB : Reset\n");
931
932 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_RWUSIG);
933
934 usb_dwc2_flush_tx_fifo(handle, 0U);
935
936 mmio_write_32(usb_base_addr + OTG_DAINT, OTG_DAINT_IN_MASK | OTG_DAINT_OUT_MASK);
937 mmio_setbits_32(usb_base_addr + OTG_DAINTMSK, OTG_DAINT_EP0_IN | OTG_DAINT_EP0_OUT);
938
939 mmio_setbits_32(usb_base_addr + OTG_DOEPMSK, OTG_DOEPMSK_STUPM |
940 OTG_DOEPMSK_XFRCM |
941 OTG_DOEPMSK_EPDM);
942 mmio_setbits_32(usb_base_addr + OTG_DIEPMSK, OTG_DIEPMSK_TOM |
943 OTG_DIEPMSK_XFRCM |
944 OTG_DIEPMSK_EPDM);
945
946 /* Set default address to 0 */
947 mmio_clrbits_32(usb_base_addr + OTG_DCFG, OTG_DCFG_DAD);
948
949 /* Setup EP0 to receive SETUP packets */
950 ret = usb_dwc2_ep0_out_start(handle);
951 assert(ret == USBD_OK);
952
953 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_USBRST);
954
955 return USB_RESET;
956 }
957
958 /* Handle enumeration done interrupt */
959 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_ENUMDNE) != 0U) {
960 ret = usb_dwc2_activate_setup(handle);
961 assert(ret == USBD_OK);
962
963 mmio_clrbits_32(usb_base_addr + OTG_GUSBCFG, OTG_GUSBCFG_TRDT);
964
965 mmio_setbits_32(usb_base_addr + OTG_GUSBCFG,
966 (USBD_HS_TRDT_VALUE << OTG_GUSBCFG_TRDT_SHIFT) & OTG_GUSBCFG_TRDT);
967
968 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_ENUMDNE);
969
970 return USB_ENUM_DONE;
971 }
972
973 /* Handle RXQLevel interrupt */
974 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_RXFLVL) != 0U) {
975 mmio_clrbits_32(usb_base_addr + OTG_GINTMSK,
976 OTG_GINTSTS_RXFLVL);
977
978 temp = mmio_read_32(usb_base_addr + OTG_GRXSTSP);
979
980 *param = temp & OTG_GRXSTSP_EPNUM;
981 *param |= (temp & OTG_GRXSTSP_BCNT) << (USBD_OUT_COUNT_SHIFT -
982 OTG_GRXSTSP_BCNT_SHIFT);
983
984 if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) == STS_DATA_UPDT) {
985 if ((temp & OTG_GRXSTSP_BCNT) != 0U) {
986 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
987
988 return USB_READ_DATA_PACKET;
989 }
990 } else if (((temp & OTG_GRXSTSP_PKTSTS) >> OTG_GRXSTSP_PKTSTS_SHIFT) ==
991 STS_SETUP_UPDT) {
992 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
993
994 return USB_READ_SETUP_PACKET;
995 }
996
997 mmio_setbits_32(usb_base_addr + OTG_GINTMSK, OTG_GINTSTS_RXFLVL);
998 }
999
1000 /* Handle SOF interrupt */
1001 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SOF) != 0U) {
1002 INFO("handle USB : SOF\n");
1003
1004 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SOF);
1005
1006 return USB_SOF;
1007 }
1008
1009 /* Handle incomplete ISO IN interrupt */
1010 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IISOIXFR) != 0U) {
1011 INFO("handle USB : ISO IN\n");
1012
1013 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1014 OTG_GINTSTS_IISOIXFR);
1015 }
1016
1017 /* Handle incomplete ISO OUT interrupt */
1018 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_IPXFR_INCOMPISOOUT) !=
1019 0U) {
1020 INFO("handle USB : ISO OUT\n");
1021
1022 mmio_write_32(usb_base_addr + OTG_GINTSTS,
1023 OTG_GINTSTS_IPXFR_INCOMPISOOUT);
1024 }
1025
1026 /* Handle connection event interrupt */
1027 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_SRQINT) != 0U) {
1028 INFO("handle USB : Connect\n");
1029
1030 mmio_write_32(usb_base_addr + OTG_GINTSTS, OTG_GINTSTS_SRQINT);
1031 }
1032
1033 /* Handle disconnection event interrupt */
1034 if ((usb_dwc2_read_int(handle) & OTG_GINTSTS_OTGINT) != 0U) {
1035 INFO("handle USB : Disconnect\n");
1036
1037 temp = mmio_read_32(usb_base_addr + OTG_GOTGINT);
1038
1039 if ((temp & OTG_GOTGINT_SEDET) == OTG_GOTGINT_SEDET) {
1040 return USB_DISCONNECT;
1041 }
1042 }
1043
1044 return USB_NOTHING;
1045 }
1046
1047 /*
1048 * Start the usb device mode
1049 * usb_core_handle: USB core driver handle.
1050 * return USB status.
1051 */
usb_dwc2_start_device(void * handle)1052 static enum usb_status usb_dwc2_start_device(void *handle)
1053 {
1054 uintptr_t usb_base_addr = (uintptr_t)handle;
1055
1056 mmio_clrbits_32(usb_base_addr + OTG_DCTL, OTG_DCTL_SDIS);
1057 mmio_setbits_32(usb_base_addr + OTG_GAHBCFG, OTG_GAHBCFG_GINT);
1058
1059 return USBD_OK;
1060 }
1061
1062 static const struct usb_driver usb_dwc2driver = {
1063 .ep0_out_start = usb_dwc2_ep0_out_start,
1064 .ep_start_xfer = usb_dwc2_ep_start_xfer,
1065 .ep0_start_xfer = usb_dwc2_ep0_start_xfer,
1066 .write_packet = usb_dwc2_write_packet,
1067 .read_packet = usb_dwc2_read_packet,
1068 .ep_set_stall = usb_dwc2_ep_set_stall,
1069 .start_device = usb_dwc2_start_device,
1070 .stop_device = usb_dwc2_stop_device,
1071 .set_address = usb_dwc2_set_address,
1072 .write_empty_tx_fifo = usb_dwc2_write_empty_tx_fifo,
1073 .it_handler = usb_dwc2_it_handler
1074 };
1075
1076 /*
1077 * Initialize USB DWC2 driver.
1078 * usb_core_handle: USB core driver handle.
1079 * pcd_handle: PCD handle.
1080 * base_register: USB global register base address.
1081 */
stm32mp1_usb_init_driver(struct usb_handle * usb_core_handle,struct pcd_handle * pcd_handle,void * base_register)1082 void stm32mp1_usb_init_driver(struct usb_handle *usb_core_handle,
1083 struct pcd_handle *pcd_handle,
1084 void *base_register)
1085 {
1086 register_usb_driver(usb_core_handle, pcd_handle, &usb_dwc2driver,
1087 base_register);
1088 }
1089
