| /trusted-firmware-a-latest/plat/rockchip/rk3399/include/shared/ |
| D | dram_regs.h | 75 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
76 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
77 #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch))) argument
78 #define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1) argument
83 #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16)) argument
84 #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1)) argument
85 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16)) argument
86 #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3)) argument
87 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16)) argument
88 #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1)) argument
[all …]
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| D | addressmap_shared.h | 91 #define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000) argument
92 #define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4) argument
95 #define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET) argument
96 #define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4) argument
99 #define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET) argument
100 #define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4) argument
102 #define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000) argument
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| /trusted-firmware-a-latest/plat/nvidia/tegra/drivers/bpmp/ |
| D | bpmp.c | 24 static uint32_t channel_field(unsigned int ch) in channel_field()
29 static bool master_free(unsigned int ch) in master_free()
34 static bool master_acked(unsigned int ch) in master_acked()
39 static void signal_slave(unsigned int ch) in signal_slave()
44 static void free_master(unsigned int ch) in free_master()
54 unsigned int ch = (unsigned int)plat_my_core_pos(); in tegra_bpmp_send_receive_atomic() local
119 unsigned int ch; in tegra_bpmp_init() local
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| /trusted-firmware-a-latest/drivers/arm/css/scmi/ |
| D | scmi_common.c | 29 void scmi_get_channel(scmi_channel_t *ch) in scmi_get_channel()
42 void scmi_send_sync_command(scmi_channel_t *ch) in scmi_send_sync_command()
77 void scmi_put_channel(scmi_channel_t *ch) in scmi_put_channel()
95 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_proto_version() local
128 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_proto_msg_attr() local
157 void *scmi_init(scmi_channel_t *ch) in scmi_init()
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| D | scmi_sys_pwr_proto.c | 23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_set() local
56 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_sys_pwr_state_get() local
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| D | scmi_pwr_dmn_proto.c | 30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_set() local
65 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_pwr_state_get() local
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| D | scmi_ap_core_proto.c | 23 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_set_reset_addr() local
57 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_ap_core_get_reset_addr() local
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| /trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/ |
| D | suspend.c | 27 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ argument
29 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ argument
136 static __pmusramfunc void phy_pctrl_reset(uint32_t ch) in phy_pctrl_reset()
146 static __pmusramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) in set_cs_training_index()
156 static __pmusramfunc void select_per_cs_training_index(uint32_t ch, in select_per_cs_training_index()
164 static __pmusramfunc void override_write_leveling_value(uint32_t ch) in override_write_leveling_value()
184 static __pmusramfunc int data_training(uint32_t ch, in data_training()
434 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; in set_ddrconfig() local
489 static __pmusramfunc void pctl_cfg(uint32_t ch, in pctl_cfg()
549 uint32_t ch, ch_count; in dram_switch_to_next_index() local
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| D | dram.c | 26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init() local
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| /trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram.c | 342 #define foreach_vch(ch) \ argument
345 #define foreach_ech(ch) \ argument
624 uint32_t ch; in reg_ddrphy_write_a() local
678 static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, in ddr_setval_s()
702 static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) in ddr_getval_s()
726 static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) in ddr_setval()
733 uint32_t ch; in ddr_setval_ach_s() local
752 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) in ddr_getval()
759 uint32_t ch; in ddr_getval_ach() local
768 uint32_t ch, slice; in ddr_getval_ach_as() local
[all …]
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| D | boot_init_dram_regdef.h | 31 #define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) argument
64 #define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch)) argument
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| /trusted-firmware-a-latest/lib/libc/ |
| D | strchr.c | 41 strchr(const char *p, int ch) in strchr()
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| D | strrchr.c | 36 strrchr(const char *p, int ch) in strrchr()
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| D | printf.c | 186 char ch = *fmt; in vprintf() local
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| D | snprintf.c | 23 #define CHECK_AND_PUT_CHAR(buf, size, chars_printed, ch) \ argument
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| /trusted-firmware-a-latest/plat/nvidia/tegra/include/drivers/ |
| D | bpmp.h | 22 #define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
23 #define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U)) argument
24 #define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U)) argument
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| /trusted-firmware-a-latest/drivers/renesas/common/ |
| D | ddr_regs.h | 16 #define DBSC_DBMEMCONF(ch, cs) (0xE6790030U + 0x10U * (ch) + 0x04U * (cs)) argument
96 #define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch)) argument
101 #define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch)) argument
106 #define DBSC_DBPDCNT0(ch) (0xE6790610U + 0x40U * (ch)) argument
111 #define DBSC_DBPDCNT1(ch) (0xE6790614U + 0x40U * (ch)) argument
116 #define DBSC_DBPDCNT2(ch) (0xE6790618U + 0x40U * (ch)) argument
121 #define DBSC_DBPDCNT3(ch) (0xE679061CU + 0x40U * (ch)) argument
126 #define DBSC_DBPDLK(ch) (0xE6790620U + 0x40U * (ch)) argument
131 #define DBSC_DBPDRGA(ch) (0xE6790624U + 0x40U * (ch)) argument
132 #define DBSC_DBPDRGD(ch) (0xE6790628U + 0x40U * (ch)) argument
[all …]
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| /trusted-firmware-a-latest/drivers/arm/css/scmi/vendor/ |
| D | scmi_sq.c | 30 scmi_channel_t *ch = (scmi_channel_t *)p; in scmi_get_draminfo() local
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| /trusted-firmware-a-latest/plat/nvidia/tegra/drivers/bpmp_ipc/ |
| D | ivc.c | 75 volatile const struct ivc_channel_header *ch) in ivc_channel_empty()
106 volatile const struct ivc_channel_header *ch) in ivc_channel_full()
121 volatile const struct ivc_channel_header *ch) in ivc_channel_avail_count()
222 volatile const struct ivc_channel_header *ch, in ivc_frame_pointer()
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| D | intf.c | 60 const struct ivc *ch = &ivc_ccplex_bpmp_channel; in tegra_bpmp_get_next_out_frame() local
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| /trusted-firmware-a-latest/services/spd/trusty/ |
| D | generic-arm64-smcall.c | 40 static void trusty_dputc(char ch, int secure) in trusty_dputc()
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| /trusted-firmware-a-latest/drivers/arm/dcc/ |
| D | dcc_console.c | 94 static int32_t dcc_console_putc(int32_t ch, struct console *console) in dcc_console_putc()
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| /trusted-firmware-a-latest/plat/socionext/synquacer/drivers/scp/ |
| D | sq_scmi.c | 202 static int scmi_ap_core_init(scmi_channel_t *ch) in scmi_ap_core_init()
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| /trusted-firmware-a-latest/drivers/marvell/mochi/ |
| D | apn806_setup.c | 70 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000) argument
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| D | ap807_setup.c | 75 #define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000) argument
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