1 /*
2  * Copyright (c) 2018, Diego Sueiro
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef __SOC_CLOCK_FREQ_H__
8 #define __SOC_CLOCK_FREQ_H__
9 
10 #include "device_imx.h"
11 #include <zephyr/types.h>
12 
13 #if defined(__cplusplus)
14 extern "C" {
15 #endif
16 
17 #ifdef CONFIG_PWM_IMX
18 /*!
19  * @brief Get clock frequency applies to the PWM module
20  *
21  * @param base PWM base pointer.
22  * @return clock frequency (in HZ) applies to the PWM module
23  */
24 uint32_t get_pwm_clock_freq(PWM_Type *base);
25 #endif /* CONFIG_PWM_IMX */
26 
27 #if defined(__cplusplus)
28 }
29 #endif
30 
31 /*! @brief Root control names for root clock setting. */
32 enum _ccm_root_control_extra {
33 	ccmRootPwm1   = (uint32_t)(&CCM_TARGET_ROOT106),
34 	ccmRootPwm2   = (uint32_t)(&CCM_TARGET_ROOT107),
35 	ccmRootPwm3   = (uint32_t)(&CCM_TARGET_ROOT108),
36 	ccmRootPwm4   = (uint32_t)(&CCM_TARGET_ROOT109),
37 };
38 
39 /*! @brief Clock source enumeration for PWM peripheral. */
40 enum _ccm_rootmux_pwm {
41 	ccmRootmuxPwmOsc24m	  = 0U,
42 	ccmRootmuxPwmEnetPllDiv10 = 1U,
43 	ccmRootmuxPwmSysPllDiv4   = 2U,
44 	ccmRootmuxPwmEnetPllDiv25 = 3U,
45 	ccmRootmuxPwmAudioPll	  = 4U,
46 	ccmRootmuxPwmExtClk2	  = 5U,
47 	ccmRootmuxPwmRef1m	  = 6U,
48 	ccmRootmuxPwmVideoPll	  = 7U,
49 };
50 
51 /*! @brief CCM CCGR gate control. */
52 enum _ccm_ccgr_gate_extra {
53 	ccmCcgrGatePwm1      = (uint32_t)(&CCM_CCGR132),
54 	ccmCcgrGatePwm2      = (uint32_t)(&CCM_CCGR133),
55 	ccmCcgrGatePwm3      = (uint32_t)(&CCM_CCGR134),
56 	ccmCcgrGatePwm4      = (uint32_t)(&CCM_CCGR135),
57 };
58 #endif /* __SOC_CLOCK_FREQ_H__ */
59