1 /*
2 * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
3 * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
4 * Copyright 2016-2021, 2023 NXP. Not a Contribution.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 *
8 * Licensed under the Apache License, Version 2.0 (the License); you may
9 * not use this file except in compliance with the License.
10 * You may obtain a copy of the License at
11 *
12 * http://www.apache.org/licenses/LICENSE-2.0
13 *
14 * Unless required by applicable law or agreed to in writing, software
15 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
16 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
17 * See the License for the specific language governing permissions and
18 * limitations under the License.
19 */
20
21 #include "fsl_enet_cmsis.h"
22
23 /* Component ID definition, used by tools. */
24 #ifndef FSL_COMPONENT_ID
25 #define FSL_COMPONENT_ID "platform.drivers.enet_cmsis"
26 #endif
27
28 #define ARM_ETH_MAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 3)
29
30 /* Define the alignment macro. */
31 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
32 #if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) && \
33 ((!defined(FSL_SDK_DISBLE_L2CACHE_PRESENT)) || (FSL_SDK_DISBLE_L2CACHE_PRESENT == 0))
34 #define CMSIS_CACHE_LINESIZE_MAX MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
35 #define CMSIS_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, CMSIS_CACHE_LINESIZE_MAX)
36 #elif defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
37 #define CMSIS_ENET_BUFF_ALIGNMENT MAX(ENET_BUFF_ALIGNMENT, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
38 #endif
39 #else
40 #define CMSIS_ENET_BUFF_ALIGNMENT ENET_BUFF_ALIGNMENT
41 #endif
42 /* Define the ENET buffer information. */
43 #define ENET_RXBD_NUM (4)
44 #define ENET_TXBD_NUM (4)
45 #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
46 #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
47 /* Define the timeout macro. */
48 #define ENET_SMI_TIMEOUT_COUNT 0xffff
49
50 typedef struct _cmsis_enet_mac_driver_state
51 {
52 cmsis_enet_mac_resource_t *resource; /*!< Basic enet resource. */
53 enet_handle_t *handle; /*!< ENET handler. */
54 enet_buffer_config_t *buffers; /*!< Buffers res*/
55 ARM_ETH_MAC_SignalEvent_t cb_event; /*!< Callback function. */
56 volatile enet_tx_bd_struct_t *txBdTs; /*!< Tx timestamp index. */
57 uint8_t flags; /*!< Control and state flags. */
58 } cmsis_enet_mac_driver_state_t;
59
60 static const ARM_DRIVER_VERSION s_enetDriverVersion = {ARM_ETH_MAC_API_VERSION, ARM_ETH_MAC_DRV_VERSION};
61
62 /* Driver Capabilities */
63 static const ARM_ETH_MAC_CAPABILITIES s_enetDriverCapabilities = {
64 0, /* checksum_offload_rx_ip4 */
65 0, /* checksum_offload_rx_ip6 */
66 0, /* checksum_offload_rx_udp */
67 0, /* checksum_offload_rx_tcp */
68 0, /* checksum_offload_rx_icmp */
69 0, /* checksum_offload_tx_ip4 */
70 0, /* checksum_offload_tx_ip6 */
71 0, /* checksum_offload_tx_udp */
72 0, /* checksum_offload_tx_tcp */
73 0, /* checksum_offload_tx_icmp */
74 (RTE_ENET_RMII) ? ARM_ETH_INTERFACE_RMII : ARM_ETH_INTERFACE_MII, /* media_interface */
75 0, /* mac_address */
76 1, /* event_rx_frame */
77 1, /* event_tx_frame */
78 1, /* event_wakeup */
79 0 /* precision_timer */
80 };
81
ENETx_GetVersion(void)82 static ARM_DRIVER_VERSION ENETx_GetVersion(void)
83 {
84 return s_enetDriverVersion;
85 }
86
ENETx_GetCapabilities(void)87 static ARM_ETH_MAC_CAPABILITIES ENETx_GetCapabilities(void)
88 {
89 return s_enetDriverCapabilities;
90 }
91
ENET_CommonInitialize(ARM_ETH_MAC_SignalEvent_t cb_event,cmsis_enet_mac_driver_state_t * enet)92 static int32_t ENET_CommonInitialize(ARM_ETH_MAC_SignalEvent_t cb_event, cmsis_enet_mac_driver_state_t *enet)
93 {
94 if ((enet->flags & ENET_FLAG_INIT) == 0U)
95 {
96 enet->cb_event = cb_event;
97 enet->flags = ENET_FLAG_INIT;
98 }
99
100 return ARM_DRIVER_OK;
101 }
102
ENET_SetInterruptCallback(ENET_Type * base,enet_handle_t * handle,uint32_t ringId,enet_event_t event,enet_frame_info_t * frameInfo,void * userData)103 static void ENET_SetInterruptCallback(ENET_Type *base,
104 enet_handle_t *handle,
105 #if FSL_FEATURE_ENET_QUEUE > 1
106 uint32_t ringId,
107 #endif
108 enet_event_t event,
109 enet_frame_info_t *frameInfo,
110 void *userData)
111 {
112 uint32_t newEvent;
113
114 switch (event)
115 {
116 case kENET_RxEvent:
117 newEvent = ARM_ETH_MAC_EVENT_RX_FRAME;
118 break;
119 case kENET_TxEvent:
120 newEvent = ARM_ETH_MAC_EVENT_TX_FRAME;
121 break;
122 case kENET_WakeUpEvent:
123 newEvent = ARM_ETH_MAC_EVENT_WAKEUP;
124 break;
125 case kENET_TimeStampEvent:
126 newEvent = ARM_ETH_MAC_EVENT_TIMER_ALARM;
127 break;
128 default:
129 newEvent = ETH_MAC_EVENT_OTHERS;
130 break;
131 }
132
133 /* User data is actually CMSIS driver callback. */
134 if (userData != NULL)
135 {
136 ((ARM_ETH_MAC_SignalEvent_t)userData)(newEvent);
137 }
138 }
139
ENET_CommonUninitialize(cmsis_enet_mac_driver_state_t * enet)140 static int32_t ENET_CommonUninitialize(cmsis_enet_mac_driver_state_t *enet)
141 {
142 enet->flags = ENET_FLAG_UNINIT;
143 return ARM_DRIVER_OK;
144 }
145
ENET_CommonControl(uint32_t control,uint32_t arg,cmsis_enet_mac_driver_state_t * enet)146 static int32_t ENET_CommonControl(uint32_t control, uint32_t arg, cmsis_enet_mac_driver_state_t *enet)
147 {
148 int32_t result = ARM_DRIVER_OK;
149
150 if (enet->flags == ENET_FLAG_UNINIT)
151 {
152 return ARM_DRIVER_ERROR;
153 }
154
155 switch (control)
156 {
157 case (uint32_t)ARM_ETH_MAC_CONFIGURE:
158 {
159 uint32_t rcr = enet->resource->base->RCR;
160 uint32_t tcr = enet->resource->base->TCR;
161 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
162 uint32_t ecr = enet->resource->base->ECR;
163 if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
164 {
165 ecr &= ~ENET_ECR_SPEED_MASK;
166 }
167 #endif /* FSL_FEATURE_ENET_HAS_AVB */
168
169 switch (arg & (uint32_t)ARM_ETH_MAC_SPEED_Msk)
170 {
171 case (uint32_t)ARM_ETH_MAC_SPEED_10M:
172 rcr |= ENET_RCR_RMII_10T_MASK;
173 break;
174 case (uint32_t)ARM_ETH_MAC_SPEED_100M:
175 rcr &= ~ENET_RCR_RMII_10T_MASK;
176 break;
177 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
178 case (uint32_t)ARM_ETH_MAC_SPEED_1G:
179 /* If the selected enet doesn't support 1G, return unsupported status */
180 if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
181 {
182 ecr |= ENET_ECR_SPEED_MASK;
183 rcr &= ~ENET_RCR_RMII_10T_MASK;
184 }
185 else
186 {
187 result = ARM_DRIVER_ERROR_UNSUPPORTED;
188 }
189 break;
190 #endif /* FSL_FEATURE_ENET_HAS_AVB */
191 default:
192 result = ARM_DRIVER_ERROR_UNSUPPORTED;
193 break;
194 }
195 if (result != ARM_DRIVER_OK)
196 {
197 return result;
198 }
199 switch (arg & ARM_ETH_MAC_DUPLEX_Msk)
200 {
201 case (uint32_t)ARM_ETH_MAC_DUPLEX_HALF:
202 rcr |= ENET_RCR_DRT_MASK;
203 tcr &= ~ENET_TCR_FDEN_MASK;
204 break;
205 case (uint32_t)ARM_ETH_MAC_DUPLEX_FULL:
206 rcr &= ~ENET_RCR_DRT_MASK;
207 tcr |= ENET_TCR_FDEN_MASK;
208 break;
209 default:
210 result = ARM_DRIVER_ERROR_UNSUPPORTED;
211 break;
212 }
213 if (result != ARM_DRIVER_OK)
214 {
215 return result;
216 }
217
218 if ((arg & (ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX | ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX)) != 0U)
219 {
220 return ARM_DRIVER_ERROR_UNSUPPORTED;
221 }
222
223 if ((arg & ARM_ETH_MAC_ADDRESS_BROADCAST) != 0U)
224 {
225 rcr &= ~ENET_RCR_BC_REJ_MASK;
226 }
227 else
228 {
229 rcr |= ENET_RCR_BC_REJ_MASK;
230 }
231
232 if ((arg & ARM_ETH_MAC_ADDRESS_MULTICAST) != 0U)
233 {
234 return ARM_DRIVER_ERROR_UNSUPPORTED;
235 }
236
237 if ((arg & ARM_ETH_MAC_ADDRESS_ALL) != 0U)
238 {
239 rcr |= ENET_RCR_PROM_MASK;
240 }
241
242 if ((arg & ARM_ETH_MAC_LOOPBACK) != 0U)
243 {
244 /* Loop back only supported on MII mode. */
245 if ((rcr & ENET_RCR_RMII_MODE_MASK) == 0U)
246 {
247 rcr |= ENET_RCR_LOOP_MASK;
248 rcr &= ~ENET_RCR_DRT_MASK;
249 }
250 }
251
252 enet->resource->base->RCR = rcr;
253 enet->resource->base->TCR = tcr;
254 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
255 if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
256 {
257 enet->resource->base->ECR = ecr;
258 }
259 #endif /* FSL_FEATURE_ENET_HAS_AVB */
260 }
261 break;
262 case (uint32_t)ARM_ETH_MAC_CONTROL_TX:
263 if (arg != 0U)
264 {
265 enet->resource->base->TDAR = ENET_TDAR_TDAR_MASK;
266 }
267 else
268 {
269 enet->resource->base->TDAR &= ~ENET_TDAR_TDAR_MASK;
270 }
271 break;
272 case (uint32_t)ARM_ETH_MAC_CONTROL_RX:
273 if (arg != 0U)
274 {
275 ENET_ActiveRead(enet->resource->base);
276 }
277 else
278 {
279 enet->resource->base->RDAR &= ~ENET_RDAR_RDAR_MASK;
280 }
281 break;
282 case (uint32_t)ARM_ETH_MAC_SLEEP:
283 ENET_EnableSleepMode(enet->resource->base, (bool)arg);
284 break;
285 default:
286 result = ARM_DRIVER_ERROR_UNSUPPORTED;
287 break;
288 }
289 return result;
290 }
291
ENET_CommonPowerControl(ARM_POWER_STATE state,cmsis_enet_mac_driver_state_t * enet)292 static int32_t ENET_CommonPowerControl(ARM_POWER_STATE state, cmsis_enet_mac_driver_state_t *enet)
293 {
294 int32_t result = ARM_DRIVER_OK;
295 ARM_ETH_MAC_CAPABILITIES capabilities;
296
297 switch (state)
298 {
299 case ARM_POWER_OFF:
300 if ((enet->flags & ENET_FLAG_POWER) != 0U)
301 {
302 (void)ENET_CommonControl(ARM_ETH_MAC_CONTROL_TX, 0, enet);
303 (void)ENET_CommonControl(ARM_ETH_MAC_CONTROL_RX, 0, enet);
304 ENET_Reset(enet->resource->base);
305 ENET_Deinit(enet->resource->base);
306
307 enet->flags = ENET_FLAG_INIT;
308 }
309 break;
310 case ARM_POWER_LOW:
311 result = ARM_DRIVER_ERROR_UNSUPPORTED;
312 break;
313 case ARM_POWER_FULL:
314 {
315 if (enet->flags == ENET_FLAG_UNINIT)
316 {
317 return ARM_DRIVER_ERROR;
318 }
319
320 if ((enet->flags & ENET_FLAG_POWER) != 0U)
321 {
322 /* Driver already powered */
323 break;
324 }
325
326 enet_config_t config;
327 uint8_t macAddr[6] = {0};
328 uint32_t freq;
329
330 /* Get default configuration. */
331 ENET_GetDefaultConfig(&config);
332 /* Change the MII interface mode according to the MII interface macro. */
333 capabilities = ENETx_GetCapabilities();
334 if (capabilities.media_interface == (uint32_t)ARM_ETH_INTERFACE_MII)
335 {
336 config.miiMode = kENET_MiiMode;
337 }
338 else if (capabilities.media_interface == (uint32_t)ARM_ETH_INTERFACE_RMII)
339 {
340 #if defined(RTE_ENET_RGMII) && RTE_ENET_RGMII
341 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
342 if (FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(enet->resource->base) > 0)
343 {
344 config.miiMode = kENET_RgmiiMode;
345 }
346 else
347 {
348 result = ARM_DRIVER_ERROR_UNSUPPORTED;
349 break;
350 }
351 #endif /* FSL_FEATURE_ENET_HAS_AVB */
352 #else
353 config.miiMode = kENET_RmiiMode;
354 #endif /* RTE_ENET_RGMII */
355 }
356 else
357 {
358 /* Intentional empty */
359 }
360
361 /* Enable the tx/rx interrupt mode. */
362 config.interrupt = (uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt |
363 (uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt;
364 /* Enable tx accelerate function. */
365 config.txAccelerConfig = (uint8_t)kENET_TxAccelIpCheckEnabled | (uint8_t)kENET_TxAccelProtoCheckEnabled;
366 /* Callback setup */
367 config.callback = ENET_SetInterruptCallback;
368 config.userData = (void *)enet->cb_event;
369 /* Initialize Ethernet Mac. */
370 freq = enet->resource->GetFreq();
371 (void)ENET_Init(enet->resource->base, enet->handle, &config, enet->buffers, &macAddr[0], freq);
372 enet->flags |= ENET_FLAG_POWER;
373 break;
374 }
375 default:
376 result = ARM_DRIVER_ERROR_UNSUPPORTED;
377 break;
378 }
379 return result;
380 }
381
ENET_Phy_Write(cmsis_enet_mac_resource_t * enet,uint8_t phy_addr,uint8_t reg_addr,uint16_t data)382 static int32_t ENET_Phy_Write(cmsis_enet_mac_resource_t *enet, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
383 {
384 uint32_t counter;
385
386 /* Clear the SMI interrupt event. */
387 ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
388
389 /* Starts a SMI write command. */
390 ENET_StartSMIWrite(enet->base, phy_addr, reg_addr, kENET_MiiWriteValidFrame, data);
391
392 /* Wait for SMI complete. */
393 for (counter = ENET_SMI_TIMEOUT_COUNT; counter > 0U; counter--)
394 {
395 if ((ENET_GetInterruptStatus(enet->base) & ENET_EIR_MII_MASK) != 0U)
396 {
397 break;
398 }
399 }
400
401 /* Check for timeout. */
402 if (counter == 0U)
403 {
404 return ARM_DRIVER_ERROR;
405 }
406
407 /* Clear MII interrupt event. */
408 ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
409
410 return ARM_DRIVER_OK;
411 }
412
ENET_Phy_Read(cmsis_enet_mac_resource_t * enet,uint8_t phy_addr,uint8_t reg_addr,uint16_t * data)413 static int32_t ENET_Phy_Read(cmsis_enet_mac_resource_t *enet, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
414 {
415 assert(data);
416
417 uint32_t counter;
418
419 /* Clear the MII interrupt event. */
420 ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
421
422 /* Starts a SMI read command operation. */
423 ENET_StartSMIRead(enet->base, phy_addr, reg_addr, kENET_MiiReadValidFrame);
424
425 /* Wait for MII complete. */
426 for (counter = ENET_SMI_TIMEOUT_COUNT; counter > 0U; counter--)
427 {
428 if ((ENET_GetInterruptStatus(enet->base) & ENET_EIR_MII_MASK) != 0U)
429 {
430 break;
431 }
432 }
433
434 /* Check for timeout. */
435 if (counter == 0U)
436 {
437 return ARM_DRIVER_ERROR;
438 }
439
440 /* Get data from MII register. */
441 *data = (uint16_t)ENET_ReadSMIData(enet->base);
442
443 /* Clear MII interrupt event. */
444 ENET_ClearInterruptStatus(enet->base, ENET_EIR_MII_MASK);
445
446 return ARM_DRIVER_OK;
447 }
448
ENET_CommonSendFrame(cmsis_enet_mac_driver_state_t * enet,const uint8_t * frame,uint32_t len,uint32_t flags)449 static int32_t ENET_CommonSendFrame(cmsis_enet_mac_driver_state_t *enet,
450 const uint8_t *frame,
451 uint32_t len,
452 uint32_t flags)
453 {
454 status_t status;
455
456 /* The SDK send frame driver is send with a whole frame and
457 * the timestamp will be enabled automatically when it is a PTP frame
458 * by parse the frame.
459 */
460 if ((flags & (ARM_ETH_MAC_TX_FRAME_FRAGMENT | ARM_ETH_MAC_TX_FRAME_TIMESTAMP)) != 0U)
461 {
462 return ARM_DRIVER_ERROR;
463 }
464
465 status = ENET_SendFrame(enet->resource->base, enet->handle, frame, len, 0, false, NULL);
466 if (status == kStatus_ENET_TxFrameOverLen)
467 {
468 return ARM_DRIVER_ERROR_PARAMETER;
469 }
470 else if (status == kStatus_ENET_TxFrameBusy)
471 {
472 return ARM_DRIVER_ERROR_BUSY;
473 }
474 else if (status == kStatus_ENET_TxFrameFail)
475 {
476 return ARM_DRIVER_ERROR;
477 }
478 else
479 {
480 return ARM_DRIVER_OK;
481 }
482 }
483
ENET_CommonGetFrameSize(cmsis_enet_mac_driver_state_t * enet)484 static uint32_t ENET_CommonGetFrameSize(cmsis_enet_mac_driver_state_t *enet)
485 {
486 status_t status;
487 uint32_t length = 0;
488
489 status = ENET_GetRxFrameSize(enet->handle, &length, 0);
490 if (status == kStatus_ENET_RxFrameError)
491 {
492 /* Should update the buffers. */
493 (void)ENET_ReadFrame(enet->resource->base, enet->handle, NULL, 0, 0, NULL);
494 }
495 return length;
496 }
497
ENET_CommonReadFrame(cmsis_enet_mac_driver_state_t * enet,uint8_t * frame,uint32_t len)498 static int32_t ENET_CommonReadFrame(cmsis_enet_mac_driver_state_t *enet, uint8_t *frame, uint32_t len)
499 {
500 status_t status;
501
502 status = ENET_ReadFrame(enet->resource->base, enet->handle, frame, len, 0, NULL);
503 if (status != kStatus_Success)
504 {
505 return ARM_DRIVER_ERROR;
506 }
507
508 return (int32_t)len;
509 }
510
511 #if RTE_ENET
512
513 /*! @brief Buffer descriptors should be in non-cacheable region and should be align to "ENET_BUFF_ALIGNMENT". */
514 AT_NONCACHEABLE_SECTION_ALIGN(static enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM], ENET_BUFF_ALIGNMENT);
515 AT_NONCACHEABLE_SECTION_ALIGN(static enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM], ENET_BUFF_ALIGNMENT);
516 /*! @brief The data buffers can be in cacheable region or in non-cacheable region.
517 * If use cacheable region, the alignment size should be the maximum size of "CACHE LINE SIZE" and "ENET_BUFF_ALIGNMENT"
518 * If use non-cache region, the alignment size is the "ENET_BUFF_ALIGNMENT".
519 */
520 SDK_ALIGN(static uint8_t g_rxDataBuff[ENET_RXBD_NUM][SDK_SIZEALIGN(ENET_RXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT)],
521 CMSIS_ENET_BUFF_ALIGNMENT);
522 SDK_ALIGN(static uint8_t g_txDataBuff[ENET_TXBD_NUM][SDK_SIZEALIGN(ENET_TXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT)],
523 CMSIS_ENET_BUFF_ALIGNMENT);
524
525 extern cmsis_enet_mac_resource_t ENET0_Resource;
526
527 extern void ENET0_InitPins(void);
528 extern void ENET0_DeinitPins(void);
529
530 static enet_handle_t ENET0_Handle;
531 static enet_buffer_config_t ENET0_BuffConfig = {ENET_RXBD_NUM,
532 ENET_TXBD_NUM,
533 SDK_SIZEALIGN(ENET_RXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT),
534 SDK_SIZEALIGN(ENET_TXBUFF_SIZE, CMSIS_ENET_BUFF_ALIGNMENT),
535 &g_rxBuffDescrip[0],
536 &g_txBuffDescrip[0],
537 &g_rxDataBuff[0][0],
538 &g_txDataBuff[0][0],
539 (bool)true,
540 (bool)true,
541 NULL};
542
543 static cmsis_enet_mac_driver_state_t ENET0_DriverState = {&ENET0_Resource, &ENET0_Handle, &ENET0_BuffConfig};
544
ENET0_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)545 static int32_t ENET0_Initialize(ARM_ETH_MAC_SignalEvent_t cb_event)
546 {
547 ENET0_InitPins();
548 return ENET_CommonInitialize(cb_event, &ENET0_DriverState);
549 }
550
ENET0_Uninitialize(void)551 static int32_t ENET0_Uninitialize(void)
552 {
553 ENET0_DeinitPins();
554 return ENET_CommonUninitialize(&ENET0_DriverState);
555 }
556
ENET0_PowerControl(ARM_POWER_STATE state)557 static int32_t ENET0_PowerControl(ARM_POWER_STATE state)
558 {
559 return ENET_CommonPowerControl(state, &ENET0_DriverState);
560 }
561
ENET0_GetMacAddress(ARM_ETH_MAC_ADDR * ptr_addr)562 static int32_t ENET0_GetMacAddress(ARM_ETH_MAC_ADDR *ptr_addr)
563 {
564 ENET_GetMacAddr(ENET0_Resource.base, &ptr_addr->b[0]);
565
566 return ARM_DRIVER_OK;
567 }
568
ENET0_SetMacAddress(const ARM_ETH_MAC_ADDR * ptr_addr)569 static int32_t ENET0_SetMacAddress(const ARM_ETH_MAC_ADDR *ptr_addr)
570 {
571 uint8_t mac[6];
572 (void)memcpy((void *)&mac[0], (const void *)ptr_addr, 6);
573 ENET_SetMacAddr(ENET0_Resource.base, &mac[0]);
574
575 return ARM_DRIVER_OK;
576 }
577
ENET0_TransmitFrame(const uint8_t * frame,uint32_t len,uint32_t flags)578 static int32_t ENET0_TransmitFrame(const uint8_t *frame, uint32_t len, uint32_t flags)
579 {
580 return ENET_CommonSendFrame(&ENET0_DriverState, frame, len, flags);
581 }
582
ENET0_GetReceiveFrameSize(void)583 static uint32_t ENET0_GetReceiveFrameSize(void)
584 {
585 return ENET_CommonGetFrameSize(&ENET0_DriverState);
586 }
587
ENET0_ReceiveFrame(uint8_t * frame,uint32_t len)588 static int32_t ENET0_ReceiveFrame(uint8_t *frame, uint32_t len)
589 {
590 return ENET_CommonReadFrame(&ENET0_DriverState, frame, len);
591 }
592
ENET0_Control(uint32_t control,uint32_t arg)593 static int32_t ENET0_Control(uint32_t control, uint32_t arg)
594 {
595 return ENET_CommonControl(control, arg, &ENET0_DriverState);
596 }
597
ENET0_PhyWrite(uint8_t phy_addr,uint8_t reg_addr,uint16_t data)598 static int32_t ENET0_PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
599 {
600 return ENET_Phy_Write(&ENET0_Resource, phy_addr, reg_addr, data);
601 }
602
ENET0_PhyRead(uint8_t phy_addr,uint8_t reg_addr,uint16_t * data)603 static int32_t ENET0_PhyRead(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
604 {
605 return ENET_Phy_Read(&ENET0_Resource, phy_addr, reg_addr, data);
606 }
607
ENET0_SetAddressFilter(const ARM_ETH_MAC_ADDR * ptr_addr,uint32_t num_addr)608 static int32_t ENET0_SetAddressFilter(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr)
609 {
610 return ARM_DRIVER_ERROR_UNSUPPORTED;
611 }
612
ENET0_GetRxFrameTime(ARM_ETH_MAC_TIME * time)613 static int32_t ENET0_GetRxFrameTime(ARM_ETH_MAC_TIME *time)
614 {
615 return ARM_DRIVER_ERROR_UNSUPPORTED;
616 }
617
ENET0_GetTxFrameTime(ARM_ETH_MAC_TIME * time)618 static int32_t ENET0_GetTxFrameTime(ARM_ETH_MAC_TIME *time)
619 {
620 return ARM_DRIVER_ERROR_UNSUPPORTED;
621 }
622
ENET0_ControlTimer(uint32_t control,ARM_ETH_MAC_TIME * time)623 static int32_t ENET0_ControlTimer(uint32_t control, ARM_ETH_MAC_TIME *time)
624 {
625 return ARM_DRIVER_ERROR_UNSUPPORTED;
626 }
627
628 ARM_DRIVER_ETH_MAC Driver_ETH_MAC0 = {ENETx_GetVersion,
629 ENETx_GetCapabilities,
630 ENET0_Initialize,
631 ENET0_Uninitialize,
632 ENET0_PowerControl,
633 ENET0_GetMacAddress,
634 ENET0_SetMacAddress,
635 ENET0_SetAddressFilter,
636 ENET0_TransmitFrame,
637 ENET0_ReceiveFrame,
638 ENET0_GetReceiveFrameSize,
639 ENET0_GetRxFrameTime,
640 ENET0_GetTxFrameTime,
641 ENET0_ControlTimer,
642 ENET0_Control,
643 ENET0_PhyRead,
644 ENET0_PhyWrite};
645 #endif
646
