1 /*
2  * Copyright (c) 2023 Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_DRIVERS_PCIE_HOST_VC_H_
8 #define ZEPHYR_DRIVERS_PCIE_HOST_VC_H_
9 
10 #define PCIE_VC_CAP_REG_1_OFFSET	0x04U
11 #define PCIE_VC_CAP_REG_2_OFFSET	0x08U
12 #define PCIE_VC_CTRL_STATUS_REG_OFFSET	0x0CU
13 
14 /** Virtual Channel capability and control Registers */
15 struct pcie_vc_regs {
16 	union {
17 		struct {
18 			/** Virtual Channel Count */
19 			uint32_t vc_count              : 3;
20 			uint32_t _reserved1            : 1;
21 			/** Low Priority Virtual Channel Count */
22 			uint32_t lpvc_count            : 3;
23 			uint32_t _reserved2            : 1;
24 			/** Reference Clock */
25 			uint32_t reference_clock       : 2;
26 			/** Port Arbitration Table Entry Size */
27 			uint32_t pat_entry_size        : 3;
28 			uint32_t _reserved3            : 19;
29 		};
30 		uint32_t raw;
31 	} cap_reg_1;
32 
33 	union {
34 		struct {
35 			/** Virtual Channel Arbitration Capability */
36 			uint32_t vca_cap               : 8;
37 			uint32_t _reserved1            : 16;
38 			/** Virtual Channel Arbitration Table Offset */
39 			uint32_t vca_table_offset      : 8;
40 		};
41 		uint32_t raw;
42 	} cap_reg_2;
43 
44 	union {
45 		struct {
46 			/** Load Virtual Channel Arbitration Table */
47 			uint32_t load_vca_table        : 1;
48 			/** Virtual Channel Arbitration Select */
49 			uint32_t vca_select            : 3;
50 			uint32_t _reserved1            : 12;
51 			/** Virtual Channel Arbitration Table Status */
52 			uint32_t vca_table_status      : 1;
53 			uint32_t _reserved2            : 15;
54 		};
55 		uint32_t raw;
56 	} ctrl_reg;
57 };
58 
59 #define PCIE_VC_RES_CAP_REG_OFFSET(_vc)		(0x10U + _vc * 0X0CU)
60 #define PCIE_VC_RES_CTRL_REG_OFFSET(_vc)	(0x14U + _vc * 0X0CU)
61 #define PCIE_VC_RES_STATUS_REG_OFFSET(_vc)	(0x18U + _vc * 0X0CU)
62 
63 #define PCIE_VC_PA_RR		BIT(0)
64 #define PCIE_VC_PA_WRR		BIT(1)
65 #define PCIE_VC_PA_WRR64	BIT(2)
66 #define PCIE_VC_PA_WRR128	BIT(3)
67 #define PCIE_VC_PA_TMWRR128	BIT(4)
68 #define PCIE_VC_PA_WRR256	BIT(5)
69 
70 /** Virtual Channel Resource Registers */
71 struct pcie_vc_resource_regs {
72 	union {
73 		struct {
74 			/** Port Arbitration Capability */
75 			uint32_t pa_cap                : 8;
76 			uint32_t _reserved1            : 6;
77 			uint32_t undefined             : 1;
78 			/** Reject Snoop Transactions */
79 			uint32_t rst                   : 1;
80 			/** Maximum Time Slots */
81 			uint32_t max_time_slots        : 7;
82 			uint32_t _reserved2            : 1;
83 			/** Port Arbitration Table Offset */
84 			uint32_t pa_table_offset       : 8;
85 		};
86 		uint32_t raw;
87 	} cap_reg;
88 
89 	union {
90 		struct {
91 			/** Traffic Class to Virtual Channel Map */
92 			uint32_t tc_vc_map             : 8;
93 			uint32_t _reserved1            : 8;
94 			/** Load Port Arbitration Table */
95 			uint32_t load_pa_table         : 1;
96 			/** Port Arbitration Select */
97 			uint32_t pa_select             : 3;
98 			uint32_t _reserved2            : 4;
99 			/** Virtual Channel ID */
100 			uint32_t vc_id                 : 3;
101 			uint32_t _reserved3            : 4;
102 			/** Virtual Channel Enable */
103 			uint32_t vc_enable             : 1;
104 		};
105 		uint32_t raw;
106 	} ctrl_reg;
107 
108 	union {
109 		struct {
110 			uint32_t _reserved1            : 16;
111 			/** Port Arbitration Table Status */
112 			uint32_t pa_table_status       : 1;
113 			/** Virtual Channel Negociation Pending */
114 			uint32_t vc_negocation_pending : 1;
115 			uint32_t _reserved2            : 14;
116 		};
117 		uint32_t raw;
118 	} status_reg;
119 };
120 
121 uint32_t pcie_vc_cap_lookup(pcie_bdf_t bdf, struct pcie_vc_regs *regs);
122 
123 void pcie_vc_load_resources_regs(pcie_bdf_t bdf,
124 				 uint32_t base,
125 				 struct pcie_vc_resource_regs *regs,
126 				 int nb_regs);
127 
128 #endif /* ZEPHYR_DRIVERS_PCIE_HOST_VC_H_ */
129