1 /*
2 * Copyright (c) 2022-2023 Vestas Wind Systems A/S
3 * Copyright (c) 2020 Alexander Wachter
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/can/transceiver.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/sys_io.h>
14 #include <zephyr/sys/util.h>
15
16 LOG_MODULE_REGISTER(can_mcan, CONFIG_CAN_LOG_LEVEL);
17
18 #define CAN_INIT_TIMEOUT_MS 100
19
can_mcan_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)20 int can_mcan_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
21 {
22 const struct can_mcan_config *config = dev->config;
23 int err;
24
25 err = config->ops->read_reg(dev, reg, val);
26 if (err != 0) {
27 LOG_ERR("failed to read reg 0x%03x (err %d)", reg, err);
28 }
29
30 return err;
31 }
32
can_mcan_write_reg(const struct device * dev,uint16_t reg,uint32_t val)33 int can_mcan_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
34 {
35 const struct can_mcan_config *config = dev->config;
36 int err;
37
38 err = config->ops->write_reg(dev, reg, val);
39 if (err != 0) {
40 LOG_ERR("failed to write reg 0x%03x (err %d)", reg, err);
41 }
42
43 return err;
44 }
45
can_mcan_exit_sleep_mode(const struct device * dev)46 static int can_mcan_exit_sleep_mode(const struct device *dev)
47 {
48 struct can_mcan_data *data = dev->data;
49 uint32_t start_time;
50 uint32_t cccr;
51 int err;
52
53 k_mutex_lock(&data->lock, K_FOREVER);
54
55 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
56 if (err != 0) {
57 goto unlock;
58 }
59
60 cccr &= ~CAN_MCAN_CCCR_CSR;
61
62 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
63 if (err != 0) {
64 goto unlock;
65 }
66
67 start_time = k_cycle_get_32();
68
69 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
70 if (err != 0) {
71 goto unlock;
72 }
73
74 while ((cccr & CAN_MCAN_CCCR_CSA) == CAN_MCAN_CCCR_CSA) {
75 if (k_cycle_get_32() - start_time > k_ms_to_cyc_ceil32(CAN_INIT_TIMEOUT_MS)) {
76 cccr |= CAN_MCAN_CCCR_CSR;
77 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
78 if (err != 0) {
79 goto unlock;
80 }
81
82 err = -EAGAIN;
83 goto unlock;
84 }
85
86 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
87 if (err != 0) {
88 goto unlock;
89 }
90 }
91
92
93 unlock:
94 k_mutex_unlock(&data->lock);
95
96 return err;
97 }
98
can_mcan_enter_init_mode(const struct device * dev,k_timeout_t timeout)99 static int can_mcan_enter_init_mode(const struct device *dev, k_timeout_t timeout)
100 {
101 struct can_mcan_data *data = dev->data;
102 int64_t start_time;
103 uint32_t cccr;
104 int err;
105
106 k_mutex_lock(&data->lock, K_FOREVER);
107
108 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
109 if (err != 0) {
110 goto unlock;
111 }
112
113 cccr |= CAN_MCAN_CCCR_INIT;
114
115 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
116 if (err != 0) {
117 goto unlock;
118 }
119
120 start_time = k_uptime_ticks();
121
122 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
123 if (err != 0) {
124 goto unlock;
125 }
126
127 while ((cccr & CAN_MCAN_CCCR_INIT) == 0U) {
128 if (k_uptime_ticks() - start_time > timeout.ticks) {
129 cccr &= ~CAN_MCAN_CCCR_INIT;
130 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
131 if (err != 0) {
132 goto unlock;
133 }
134
135 err = -EAGAIN;
136 goto unlock;
137 }
138
139 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
140 if (err != 0) {
141 goto unlock;
142 }
143 }
144
145 unlock:
146 k_mutex_unlock(&data->lock);
147
148 return err;
149 }
150
can_mcan_leave_init_mode(const struct device * dev,k_timeout_t timeout)151 static int can_mcan_leave_init_mode(const struct device *dev, k_timeout_t timeout)
152 {
153 struct can_mcan_data *data = dev->data;
154 int64_t start_time;
155 uint32_t cccr;
156 int err;
157
158 k_mutex_lock(&data->lock, K_FOREVER);
159
160 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
161 if (err != 0) {
162 goto unlock;
163 }
164
165 cccr &= ~CAN_MCAN_CCCR_INIT;
166
167 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
168 if (err != 0) {
169 goto unlock;
170 }
171
172 start_time = k_uptime_ticks();
173
174 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
175 if (err != 0) {
176 goto unlock;
177 }
178
179 while ((cccr & CAN_MCAN_CCCR_INIT) != 0U) {
180 if (k_uptime_ticks() - start_time > timeout.ticks) {
181 err = -EAGAIN;
182 goto unlock;
183 }
184
185 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
186 if (err != 0) {
187 goto unlock;
188 }
189 }
190
191 unlock:
192 k_mutex_unlock(&data->lock);
193
194 return err;
195 }
196
can_mcan_set_timing(const struct device * dev,const struct can_timing * timing)197 int can_mcan_set_timing(const struct device *dev, const struct can_timing *timing)
198 {
199 struct can_mcan_data *data = dev->data;
200 uint32_t nbtp = 0U;
201 int err;
202
203 if (data->common.started) {
204 return -EBUSY;
205 }
206
207 k_mutex_lock(&data->lock, K_FOREVER);
208
209 nbtp |= FIELD_PREP(CAN_MCAN_NBTP_NSJW, timing->sjw - 1UL) |
210 FIELD_PREP(CAN_MCAN_NBTP_NTSEG1, timing->phase_seg1 - 1UL) |
211 FIELD_PREP(CAN_MCAN_NBTP_NTSEG2, timing->phase_seg2 - 1UL) |
212 FIELD_PREP(CAN_MCAN_NBTP_NBRP, timing->prescaler - 1UL);
213
214 err = can_mcan_write_reg(dev, CAN_MCAN_NBTP, nbtp);
215 if (err != 0) {
216 goto unlock;
217 }
218
219 unlock:
220 k_mutex_unlock(&data->lock);
221
222 return err;
223 }
224
225 #ifdef CONFIG_CAN_FD_MODE
can_mcan_set_timing_data(const struct device * dev,const struct can_timing * timing_data)226 int can_mcan_set_timing_data(const struct device *dev, const struct can_timing *timing_data)
227 {
228 const uint8_t tdco_max = FIELD_GET(CAN_MCAN_TDCR_TDCO, CAN_MCAN_TDCR_TDCO);
229 struct can_mcan_data *data = dev->data;
230 uint32_t dbtp = 0U;
231 uint8_t tdco;
232 int err;
233
234 if (data->common.started) {
235 return -EBUSY;
236 }
237
238 k_mutex_lock(&data->lock, K_FOREVER);
239
240 dbtp |= FIELD_PREP(CAN_MCAN_DBTP_DSJW, timing_data->sjw - 1UL) |
241 FIELD_PREP(CAN_MCAN_DBTP_DTSEG1, timing_data->phase_seg1 - 1UL) |
242 FIELD_PREP(CAN_MCAN_DBTP_DTSEG2, timing_data->phase_seg2 - 1UL) |
243 FIELD_PREP(CAN_MCAN_DBTP_DBRP, timing_data->prescaler - 1UL);
244
245 if (timing_data->prescaler == 1U || timing_data->prescaler == 2U) {
246 /* TDC can only be enabled if DBRP = { 0, 1 } */
247 dbtp |= CAN_MCAN_DBTP_TDC;
248
249 /* Set TDC offset for correct location of the Secondary Sample Point (SSP) */
250 tdco = CAN_CALC_TDCO(timing_data, 0U, tdco_max);
251 LOG_DBG("TDC enabled, using TDCO %u", tdco);
252
253 err = can_mcan_write_reg(dev, CAN_MCAN_TDCR, FIELD_PREP(CAN_MCAN_TDCR_TDCO, tdco));
254 if (err != 0) {
255 goto unlock;
256 }
257 } else {
258 LOG_DBG("TDC cannot be enabled, prescaler value %u too high",
259 timing_data->prescaler);
260 }
261
262 err = can_mcan_write_reg(dev, CAN_MCAN_DBTP, dbtp);
263 if (err != 0) {
264 goto unlock;
265 }
266
267 unlock:
268 k_mutex_unlock(&data->lock);
269
270 return err;
271 }
272 #endif /* CONFIG_CAN_FD_MODE */
273
can_mcan_get_capabilities(const struct device * dev,can_mode_t * cap)274 int can_mcan_get_capabilities(const struct device *dev, can_mode_t *cap)
275 {
276 ARG_UNUSED(dev);
277
278 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
279
280 if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
281 *cap |= CAN_MODE_MANUAL_RECOVERY;
282 }
283
284 if (IS_ENABLED(CONFIG_CAN_FD_MODE)) {
285 *cap |= CAN_MODE_FD;
286 }
287
288 return 0;
289 }
290
can_mcan_start(const struct device * dev)291 int can_mcan_start(const struct device *dev)
292 {
293 const struct can_mcan_config *config = dev->config;
294 struct can_mcan_data *data = dev->data;
295 int err;
296
297 if (data->common.started) {
298 return -EALREADY;
299 }
300
301 if (config->common.phy != NULL) {
302 err = can_transceiver_enable(config->common.phy, data->common.mode);
303 if (err != 0) {
304 LOG_ERR("failed to enable CAN transceiver (err %d)", err);
305 return err;
306 }
307 }
308
309 /* Reset statistics */
310 CAN_STATS_RESET(dev);
311
312 err = can_mcan_leave_init_mode(dev, K_MSEC(CAN_INIT_TIMEOUT_MS));
313 if (err != 0) {
314 LOG_ERR("failed to leave init mode");
315
316 if (config->common.phy != NULL) {
317 /* Attempt to disable the CAN transceiver in case of error */
318 (void)can_transceiver_disable(config->common.phy);
319 }
320
321 return -EIO;
322 }
323
324 data->common.started = true;
325
326 return 0;
327 }
328
can_mcan_stop(const struct device * dev)329 int can_mcan_stop(const struct device *dev)
330 {
331 const struct can_mcan_config *config = dev->config;
332 const struct can_mcan_callbacks *cbs = config->callbacks;
333 struct can_mcan_data *data = dev->data;
334 can_tx_callback_t tx_cb;
335 uint32_t tx_idx;
336 int err;
337
338 if (!data->common.started) {
339 return -EALREADY;
340 }
341
342 /* CAN transmissions are automatically stopped when entering init mode */
343 err = can_mcan_enter_init_mode(dev, K_MSEC(CAN_INIT_TIMEOUT_MS));
344 if (err != 0) {
345 LOG_ERR("Failed to enter init mode");
346 return -EIO;
347 }
348
349 if (config->common.phy != NULL) {
350 err = can_transceiver_disable(config->common.phy);
351 if (err != 0) {
352 LOG_ERR("failed to disable CAN transceiver (err %d)", err);
353 return err;
354 }
355 }
356
357 can_mcan_enable_configuration_change(dev);
358
359 data->common.started = false;
360
361 for (tx_idx = 0U; tx_idx < cbs->num_tx; tx_idx++) {
362 tx_cb = cbs->tx[tx_idx].function;
363
364 if (tx_cb != NULL) {
365 cbs->tx[tx_idx].function = NULL;
366 tx_cb(dev, -ENETDOWN, cbs->tx[tx_idx].user_data);
367 k_sem_give(&data->tx_sem);
368 }
369 }
370
371 return 0;
372 }
373
can_mcan_set_mode(const struct device * dev,can_mode_t mode)374 int can_mcan_set_mode(const struct device *dev, can_mode_t mode)
375 {
376 can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
377 struct can_mcan_data *data = dev->data;
378 uint32_t cccr;
379 uint32_t test;
380 int err;
381
382 if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
383 supported |= CAN_MODE_MANUAL_RECOVERY;
384 }
385
386 if (IS_ENABLED(CONFIG_CAN_FD_MODE)) {
387 supported |= CAN_MODE_FD;
388 }
389
390 if ((mode & ~(supported)) != 0U) {
391 LOG_ERR("unsupported mode: 0x%08x", mode);
392 return -ENOTSUP;
393 }
394
395 if (data->common.started) {
396 return -EBUSY;
397 }
398
399 k_mutex_lock(&data->lock, K_FOREVER);
400
401 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
402 if (err != 0) {
403 goto unlock;
404 }
405
406 err = can_mcan_read_reg(dev, CAN_MCAN_TEST, &test);
407 if (err != 0) {
408 goto unlock;
409 }
410
411 if ((mode & CAN_MODE_LOOPBACK) != 0) {
412 /* Loopback mode */
413 cccr |= CAN_MCAN_CCCR_TEST;
414 test |= CAN_MCAN_TEST_LBCK;
415 } else {
416 cccr &= ~CAN_MCAN_CCCR_TEST;
417 }
418
419 if ((mode & CAN_MODE_LISTENONLY) != 0) {
420 /* Bus monitoring mode */
421 cccr |= CAN_MCAN_CCCR_MON;
422 } else {
423 cccr &= ~CAN_MCAN_CCCR_MON;
424 }
425
426 #ifdef CONFIG_CAN_FD_MODE
427 if ((mode & CAN_MODE_FD) != 0) {
428 cccr |= CAN_MCAN_CCCR_FDOE | CAN_MCAN_CCCR_BRSE;
429 } else {
430 cccr &= ~(CAN_MCAN_CCCR_FDOE | CAN_MCAN_CCCR_BRSE);
431 }
432 #endif /* CONFIG_CAN_FD_MODE */
433
434 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
435 if (err != 0) {
436 goto unlock;
437 }
438
439 err = can_mcan_write_reg(dev, CAN_MCAN_TEST, test);
440 if (err != 0) {
441 goto unlock;
442 }
443
444 data->common.mode = mode;
445
446 unlock:
447 k_mutex_unlock(&data->lock);
448
449 return err;
450 }
451
can_mcan_state_change_handler(const struct device * dev)452 static void can_mcan_state_change_handler(const struct device *dev)
453 {
454 const struct can_mcan_config *config = dev->config;
455 struct can_mcan_data *data = dev->data;
456 const can_state_change_callback_t state_cb = data->common.state_change_cb;
457 void *state_cb_data = data->common.state_change_cb_user_data;
458 const struct can_mcan_callbacks *cbs = config->callbacks;
459 can_tx_callback_t tx_cb;
460 uint32_t tx_idx;
461 struct can_bus_err_cnt err_cnt;
462 enum can_state state;
463 uint32_t cccr;
464 int err;
465
466 err = can_mcan_get_state(dev, &state, &err_cnt);
467 if (err != 0) {
468 return;
469 }
470
471 if (state_cb != NULL) {
472 state_cb(dev, state, err_cnt, state_cb_data);
473 }
474
475 if (state == CAN_STATE_BUS_OFF) {
476 /* Request all TX buffers to be cancelled */
477 err = can_mcan_write_reg(dev, CAN_MCAN_TXBCR, CAN_MCAN_TXBCR_CR);
478 if (err != 0) {
479 return;
480 }
481
482 /* Call all TX queue callbacks with -ENETUNREACH */
483 for (tx_idx = 0U; tx_idx < cbs->num_tx; tx_idx++) {
484 tx_cb = cbs->tx[tx_idx].function;
485
486 if (tx_cb != NULL) {
487 cbs->tx[tx_idx].function = NULL;
488 tx_cb(dev, -ENETUNREACH, cbs->tx[tx_idx].user_data);
489 k_sem_give(&data->tx_sem);
490 }
491 }
492
493 if (!IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE) ||
494 (data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) {
495 /*
496 * Request leaving init mode, but do not take the lock (as we are in ISR
497 * context), nor wait for the result.
498 */
499 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
500 if (err != 0) {
501 return;
502 }
503
504 cccr &= ~CAN_MCAN_CCCR_INIT;
505
506 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
507 if (err != 0) {
508 return;
509 }
510 }
511 }
512 }
513
can_mcan_tx_event_handler(const struct device * dev)514 static void can_mcan_tx_event_handler(const struct device *dev)
515 {
516 const struct can_mcan_config *config = dev->config;
517 const struct can_mcan_callbacks *cbs = config->callbacks;
518 struct can_mcan_data *data = dev->data;
519 struct can_mcan_tx_event_fifo tx_event;
520 can_tx_callback_t tx_cb;
521 void *user_data;
522 uint32_t event_idx;
523 uint32_t tx_idx;
524 uint32_t txefs;
525 int err;
526
527 err = can_mcan_read_reg(dev, CAN_MCAN_TXEFS, &txefs);
528 if (err != 0) {
529 return;
530 }
531
532 while ((txefs & CAN_MCAN_TXEFS_EFFL) != 0U) {
533 event_idx = FIELD_GET(CAN_MCAN_TXEFS_EFGI, txefs);
534 err = can_mcan_read_mram(dev,
535 config->mram_offsets[CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO] +
536 event_idx * sizeof(struct can_mcan_tx_event_fifo),
537 &tx_event,
538 sizeof(struct can_mcan_tx_event_fifo));
539 if (err != 0) {
540 LOG_ERR("failed to read tx event fifo (err %d)", err);
541 return;
542 }
543
544 tx_idx = tx_event.mm;
545
546 /* Acknowledge TX event */
547 err = can_mcan_write_reg(dev, CAN_MCAN_TXEFA, event_idx);
548 if (err != 0) {
549 return;
550 }
551
552 __ASSERT_NO_MSG(tx_idx < cbs->num_tx);
553 tx_cb = cbs->tx[tx_idx].function;
554 user_data = cbs->tx[tx_idx].user_data;
555 cbs->tx[tx_idx].function = NULL;
556
557 k_sem_give(&data->tx_sem);
558
559 tx_cb(dev, 0, user_data);
560
561 err = can_mcan_read_reg(dev, CAN_MCAN_TXEFS, &txefs);
562 if (err != 0) {
563 return;
564 }
565 }
566 }
567
568 #ifdef CONFIG_CAN_STATS
can_mcan_lec_update_stats(const struct device * dev,enum can_mcan_psr_lec lec)569 static void can_mcan_lec_update_stats(const struct device *dev, enum can_mcan_psr_lec lec)
570 {
571 switch (lec) {
572 case CAN_MCAN_PSR_LEC_STUFF_ERROR:
573 CAN_STATS_STUFF_ERROR_INC(dev);
574 break;
575 case CAN_MCAN_PSR_LEC_FORM_ERROR:
576 CAN_STATS_FORM_ERROR_INC(dev);
577 break;
578 case CAN_MCAN_PSR_LEC_ACK_ERROR:
579 CAN_STATS_ACK_ERROR_INC(dev);
580 break;
581 case CAN_MCAN_PSR_LEC_BIT1_ERROR:
582 CAN_STATS_BIT1_ERROR_INC(dev);
583 break;
584 case CAN_MCAN_PSR_LEC_BIT0_ERROR:
585 CAN_STATS_BIT0_ERROR_INC(dev);
586 break;
587 case CAN_MCAN_PSR_LEC_CRC_ERROR:
588 CAN_STATS_CRC_ERROR_INC(dev);
589 break;
590 case CAN_MCAN_PSR_LEC_NO_ERROR:
591 case CAN_MCAN_PSR_LEC_NO_CHANGE:
592 default:
593 break;
594 }
595 }
596 #endif /* CONFIG_CAN_STATS */
597
can_mcan_read_psr(const struct device * dev,uint32_t * val)598 static int can_mcan_read_psr(const struct device *dev, uint32_t *val)
599 {
600 /* Reading the lower byte of the PSR register clears the protocol last
601 * error codes (LEC). To avoid missing errors, this function should be
602 * used whenever the PSR register is read.
603 */
604 int err = can_mcan_read_reg(dev, CAN_MCAN_PSR, val);
605
606 if (err != 0) {
607 return err;
608 }
609
610 #ifdef CONFIG_CAN_STATS
611 enum can_mcan_psr_lec lec;
612
613 lec = FIELD_GET(CAN_MCAN_PSR_LEC, *val);
614 can_mcan_lec_update_stats(dev, lec);
615 #ifdef CONFIG_CAN_FD_MODE
616 lec = FIELD_GET(CAN_MCAN_PSR_DLEC, *val);
617 can_mcan_lec_update_stats(dev, lec);
618 #endif
619 #endif /* CONFIG_CAN_STATS */
620
621 return 0;
622 }
623
can_mcan_line_0_isr(const struct device * dev)624 void can_mcan_line_0_isr(const struct device *dev)
625 {
626 const uint32_t events = CAN_MCAN_IR_BO | CAN_MCAN_IR_EP | CAN_MCAN_IR_EW |
627 CAN_MCAN_IR_TEFN | CAN_MCAN_IR_TEFL | CAN_MCAN_IR_ARA |
628 CAN_MCAN_IR_MRAF | CAN_MCAN_IR_PEA | CAN_MCAN_IR_PED;
629 struct can_mcan_data *data = dev->data;
630 uint32_t ir;
631 int err;
632
633 err = can_mcan_read_reg(dev, CAN_MCAN_IR, &ir);
634 if (err != 0) {
635 return;
636 }
637
638 while ((ir & events) != 0U) {
639 err = can_mcan_write_reg(dev, CAN_MCAN_IR, ir & events);
640 if (err != 0) {
641 return;
642 }
643
644 if ((ir & (CAN_MCAN_IR_BO | CAN_MCAN_IR_EP | CAN_MCAN_IR_EW)) != 0U) {
645 can_mcan_state_change_handler(dev);
646 }
647
648 /* TX event FIFO new entry */
649 if ((ir & CAN_MCAN_IR_TEFN) != 0U) {
650 can_mcan_tx_event_handler(dev);
651 }
652
653 if ((ir & CAN_MCAN_IR_TEFL) != 0U) {
654 LOG_ERR("TX FIFO element lost");
655 k_sem_give(&data->tx_sem);
656 }
657
658 if ((ir & CAN_MCAN_IR_ARA) != 0U) {
659 LOG_ERR("Access to reserved address");
660 }
661
662 if ((ir & CAN_MCAN_IR_MRAF) != 0U) {
663 LOG_ERR("Message RAM access failure");
664 }
665
666 #ifdef CONFIG_CAN_STATS
667 if ((ir & (CAN_MCAN_IR_PEA | CAN_MCAN_IR_PED)) != 0U) {
668 uint32_t reg;
669 /* This function automatically updates protocol error stats */
670 can_mcan_read_psr(dev, ®);
671 }
672 #endif
673
674 err = can_mcan_read_reg(dev, CAN_MCAN_IR, &ir);
675 if (err != 0) {
676 return;
677 }
678 }
679 }
680
can_mcan_get_message(const struct device * dev,uint16_t fifo_offset,uint16_t fifo_status_reg,uint16_t fifo_ack_reg)681 static void can_mcan_get_message(const struct device *dev, uint16_t fifo_offset,
682 uint16_t fifo_status_reg, uint16_t fifo_ack_reg)
683 {
684 const struct can_mcan_config *config = dev->config;
685 const struct can_mcan_callbacks *cbs = config->callbacks;
686 struct can_mcan_rx_fifo_hdr hdr;
687 struct can_frame frame = {0};
688 can_rx_callback_t cb;
689 void *user_data;
690 uint32_t get_idx;
691 uint32_t filt_idx;
692 int data_length;
693 uint32_t fifo_status;
694 int err;
695
696 err = can_mcan_read_reg(dev, fifo_status_reg, &fifo_status);
697 if (err != 0) {
698 return;
699 }
700
701 while (FIELD_GET(CAN_MCAN_RXF0S_F0FL, fifo_status) != 0U) {
702 get_idx = FIELD_GET(CAN_MCAN_RXF0S_F0GI, fifo_status);
703
704 err = can_mcan_read_mram(dev, fifo_offset + get_idx *
705 sizeof(struct can_mcan_rx_fifo) +
706 offsetof(struct can_mcan_rx_fifo, hdr),
707 &hdr, sizeof(struct can_mcan_rx_fifo_hdr));
708 if (err != 0) {
709 LOG_ERR("failed to read Rx FIFO header (err %d)", err);
710 return;
711 }
712
713 frame.dlc = hdr.dlc;
714
715 if (hdr.rtr != 0) {
716 frame.flags |= CAN_FRAME_RTR;
717 }
718
719 if (hdr.fdf != 0) {
720 frame.flags |= CAN_FRAME_FDF;
721 }
722
723 if (hdr.brs != 0) {
724 frame.flags |= CAN_FRAME_BRS;
725 }
726
727 if (hdr.esi != 0) {
728 frame.flags |= CAN_FRAME_ESI;
729 }
730
731 #ifdef CONFIG_CAN_RX_TIMESTAMP
732 frame.timestamp = hdr.rxts;
733 #endif /* CONFIG_CAN_RX_TIMESTAMP */
734
735 filt_idx = hdr.fidx;
736
737 if (hdr.xtd != 0) {
738 frame.id = hdr.ext_id;
739 frame.flags |= CAN_FRAME_IDE;
740 } else {
741 frame.id = hdr.std_id;
742 }
743
744 data_length = can_dlc_to_bytes(frame.dlc);
745 if (data_length <= sizeof(frame.data)) {
746 if ((frame.flags & CAN_FRAME_RTR) == 0U && data_length != 0U) {
747 err = can_mcan_read_mram(dev, fifo_offset + get_idx *
748 sizeof(struct can_mcan_rx_fifo) +
749 offsetof(struct can_mcan_rx_fifo, data_32),
750 &frame.data_32,
751 ROUND_UP(data_length, sizeof(uint32_t)));
752 if (err != 0) {
753 LOG_ERR("failed to read Rx FIFO data (err %d)", err);
754 return;
755 }
756 }
757
758 if ((frame.flags & CAN_FRAME_IDE) != 0) {
759 LOG_DBG("Frame on filter %d, ID: 0x%x",
760 filt_idx + cbs->num_std, frame.id);
761 __ASSERT_NO_MSG(filt_idx < cbs->num_ext);
762 cb = cbs->ext[filt_idx].function;
763 user_data = cbs->ext[filt_idx].user_data;
764 } else {
765 LOG_DBG("Frame on filter %d, ID: 0x%x", filt_idx, frame.id);
766 __ASSERT_NO_MSG(filt_idx < cbs->num_std);
767 cb = cbs->std[filt_idx].function;
768 user_data = cbs->std[filt_idx].user_data;
769 }
770
771 if (cb) {
772 cb(dev, &frame, user_data);
773 } else {
774 LOG_DBG("cb missing");
775 }
776 } else {
777 LOG_ERR("Frame is too big");
778 }
779
780 err = can_mcan_write_reg(dev, fifo_ack_reg, get_idx);
781 if (err != 0) {
782 return;
783 }
784
785 err = can_mcan_read_reg(dev, fifo_status_reg, &fifo_status);
786 if (err != 0) {
787 return;
788 }
789 }
790 }
791
can_mcan_line_1_isr(const struct device * dev)792 void can_mcan_line_1_isr(const struct device *dev)
793 {
794 const struct can_mcan_config *config = dev->config;
795 const uint32_t events =
796 CAN_MCAN_IR_RF0N | CAN_MCAN_IR_RF1N | CAN_MCAN_IR_RF0L | CAN_MCAN_IR_RF1L;
797 uint32_t ir;
798 int err;
799
800 err = can_mcan_read_reg(dev, CAN_MCAN_IR, &ir);
801 if (err != 0) {
802 return;
803 }
804
805 if ((ir & CAN_MCAN_IR_PEA) != 0U) {
806 LOG_DBG("Protocol error in arbitration phase: ir: 0x%x", ir);
807 }
808
809 if ((ir & CAN_MCAN_IR_PED) != 0U) {
810 LOG_DBG("Protocol error in data phase: ir: 0x%x", ir);
811 }
812
813 while ((ir & events) != 0U) {
814 err = can_mcan_write_reg(dev, CAN_MCAN_IR, events & ir);
815 if (err != 0) {
816 return;
817 }
818
819 if ((ir & CAN_MCAN_IR_RF0N) != 0U) {
820 LOG_DBG("RX FIFO0 INT");
821 can_mcan_get_message(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_RX_FIFO0],
822 CAN_MCAN_RXF0S, CAN_MCAN_RXF0A);
823 }
824
825 if ((ir & CAN_MCAN_IR_RF1N) != 0U) {
826 LOG_DBG("RX FIFO1 INT");
827 can_mcan_get_message(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_RX_FIFO1],
828 CAN_MCAN_RXF1S, CAN_MCAN_RXF1A);
829 }
830
831 if ((ir & CAN_MCAN_IR_RF0L) != 0U) {
832 LOG_ERR("Message lost on FIFO0");
833 CAN_STATS_RX_OVERRUN_INC(dev);
834 }
835
836 if ((ir & CAN_MCAN_IR_RF1L) != 0U) {
837 LOG_ERR("Message lost on FIFO1");
838 CAN_STATS_RX_OVERRUN_INC(dev);
839 }
840
841 err = can_mcan_read_reg(dev, CAN_MCAN_IR, &ir);
842 if (err != 0) {
843 return;
844 }
845 }
846 }
847
can_mcan_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)848 int can_mcan_get_state(const struct device *dev, enum can_state *state,
849 struct can_bus_err_cnt *err_cnt)
850 {
851 struct can_mcan_data *data = dev->data;
852 uint32_t reg;
853 int err;
854
855 if (state != NULL) {
856 err = can_mcan_read_psr(dev, ®);
857 if (err != 0) {
858 return err;
859 }
860
861 if (!data->common.started) {
862 *state = CAN_STATE_STOPPED;
863 } else if ((reg & CAN_MCAN_PSR_BO) != 0U) {
864 *state = CAN_STATE_BUS_OFF;
865 } else if ((reg & CAN_MCAN_PSR_EP) != 0U) {
866 *state = CAN_STATE_ERROR_PASSIVE;
867 } else if ((reg & CAN_MCAN_PSR_EW) != 0U) {
868 *state = CAN_STATE_ERROR_WARNING;
869 } else {
870 *state = CAN_STATE_ERROR_ACTIVE;
871 }
872 }
873
874 if (err_cnt != NULL) {
875 err = can_mcan_read_reg(dev, CAN_MCAN_ECR, ®);
876 if (err != 0) {
877 return err;
878 }
879
880 err_cnt->tx_err_cnt = FIELD_GET(CAN_MCAN_ECR_TEC, reg);
881 err_cnt->rx_err_cnt = FIELD_GET(CAN_MCAN_ECR_REC, reg);
882 }
883
884 return 0;
885 }
886
887 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
can_mcan_recover(const struct device * dev,k_timeout_t timeout)888 int can_mcan_recover(const struct device *dev, k_timeout_t timeout)
889 {
890 struct can_mcan_data *data = dev->data;
891
892 if (!data->common.started) {
893 return -ENETDOWN;
894 }
895
896 if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) {
897 return -ENOTSUP;
898 }
899
900 return can_mcan_leave_init_mode(dev, timeout);
901 }
902 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
903
can_mcan_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)904 int can_mcan_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout,
905 can_tx_callback_t callback, void *user_data)
906 {
907 const struct can_mcan_config *config = dev->config;
908 const struct can_mcan_callbacks *cbs = config->callbacks;
909 struct can_mcan_data *data = dev->data;
910 size_t data_length = can_dlc_to_bytes(frame->dlc);
911 struct can_mcan_tx_buffer_hdr tx_hdr = {
912 .rtr = (frame->flags & CAN_FRAME_RTR) != 0U ? 1U : 0U,
913 .xtd = (frame->flags & CAN_FRAME_IDE) != 0U ? 1U : 0U,
914 .esi = 0U,
915 .dlc = frame->dlc,
916 #ifdef CONFIG_CAN_FD_MODE
917 .fdf = (frame->flags & CAN_FRAME_FDF) != 0U ? 1U : 0U,
918 .brs = (frame->flags & CAN_FRAME_BRS) != 0U ? 1U : 0U,
919 #else /* CONFIG_CAN_FD_MODE */
920 .fdf = 0U,
921 .brs = 0U,
922 #endif /* !CONFIG_CAN_FD_MODE */
923 .efc = 1U,
924 };
925 uint32_t put_idx = -1;
926 uint32_t reg;
927 int err;
928
929 LOG_DBG("Sending %zu bytes. Id: 0x%x, ID type: %s %s %s %s", data_length, frame->id,
930 (frame->flags & CAN_FRAME_IDE) != 0U ? "extended" : "standard",
931 (frame->flags & CAN_FRAME_RTR) != 0U ? "RTR" : "",
932 (frame->flags & CAN_FRAME_FDF) != 0U ? "FD frame" : "",
933 (frame->flags & CAN_FRAME_BRS) != 0U ? "BRS" : "");
934
935 #ifdef CONFIG_CAN_FD_MODE
936 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR | CAN_FRAME_FDF | CAN_FRAME_BRS)) !=
937 0) {
938 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
939 return -ENOTSUP;
940 }
941
942 if ((data->common.mode & CAN_MODE_FD) == 0U &&
943 ((frame->flags & (CAN_FRAME_FDF | CAN_FRAME_BRS)) != 0U)) {
944 LOG_ERR("CAN FD format not supported in non-FD mode");
945 return -ENOTSUP;
946 }
947 #else /* CONFIG_CAN_FD_MODE */
948 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0U) {
949 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
950 return -ENOTSUP;
951 }
952 #endif /* !CONFIG_CAN_FD_MODE */
953
954 if (data_length > sizeof(frame->data)) {
955 LOG_ERR("data length (%zu) > max frame data length (%zu)", data_length,
956 sizeof(frame->data));
957 return -EINVAL;
958 }
959
960 if ((frame->flags & CAN_FRAME_FDF) != 0U) {
961 if (frame->dlc > CANFD_MAX_DLC) {
962 LOG_ERR("DLC of %d for CAN FD format frame", frame->dlc);
963 return -EINVAL;
964 }
965 } else {
966 if (frame->dlc > CAN_MAX_DLC) {
967 LOG_ERR("DLC of %d for non-FD format frame", frame->dlc);
968 return -EINVAL;
969 }
970 }
971
972 if (!data->common.started) {
973 return -ENETDOWN;
974 }
975
976 err = can_mcan_read_psr(dev, ®);
977 if (err != 0) {
978 return err;
979 }
980
981 if ((reg & CAN_MCAN_PSR_BO) != 0U) {
982 return -ENETUNREACH;
983 }
984
985 err = k_sem_take(&data->tx_sem, timeout);
986 if (err != 0) {
987 return -EAGAIN;
988 }
989
990 k_mutex_lock(&data->tx_mtx, K_FOREVER);
991
992 /* Acquire a free TX buffer */
993 for (int i = 0; i < cbs->num_tx; i++) {
994 if (cbs->tx[i].function == NULL) {
995 put_idx = i;
996 break;
997 }
998 }
999
1000 tx_hdr.mm = put_idx;
1001
1002 if ((frame->flags & CAN_FRAME_IDE) != 0U) {
1003 tx_hdr.ext_id = frame->id;
1004 } else {
1005 tx_hdr.std_id = frame->id & CAN_STD_ID_MASK;
1006 }
1007
1008 err = can_mcan_write_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_TX_BUFFER] + put_idx *
1009 sizeof(struct can_mcan_tx_buffer) +
1010 offsetof(struct can_mcan_tx_buffer, hdr),
1011 &tx_hdr, sizeof(struct can_mcan_tx_buffer_hdr));
1012 if (err != 0) {
1013 LOG_ERR("failed to write Tx Buffer header (err %d)", err);
1014 goto err_unlock;
1015 }
1016
1017 if ((frame->flags & CAN_FRAME_RTR) == 0U && data_length != 0U) {
1018 err = can_mcan_write_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_TX_BUFFER] +
1019 put_idx * sizeof(struct can_mcan_tx_buffer) +
1020 offsetof(struct can_mcan_tx_buffer, data_32),
1021 &frame->data_32, ROUND_UP(data_length, sizeof(uint32_t)));
1022 if (err != 0) {
1023 LOG_ERR("failed to write Tx Buffer data (err %d)", err);
1024 goto err_unlock;
1025 }
1026 }
1027
1028 __ASSERT_NO_MSG(put_idx < cbs->num_tx);
1029 cbs->tx[put_idx].function = callback;
1030 cbs->tx[put_idx].user_data = user_data;
1031
1032 err = can_mcan_write_reg(dev, CAN_MCAN_TXBAR, BIT(put_idx));
1033 if (err != 0) {
1034 cbs->tx[put_idx].function = NULL;
1035 goto err_unlock;
1036 }
1037
1038 k_mutex_unlock(&data->tx_mtx);
1039 return 0;
1040
1041 err_unlock:
1042 k_mutex_unlock(&data->tx_mtx);
1043 k_sem_give(&data->tx_sem);
1044
1045 return err;
1046 }
1047
can_mcan_get_max_filters(const struct device * dev,bool ide)1048 int can_mcan_get_max_filters(const struct device *dev, bool ide)
1049 {
1050 const struct can_mcan_config *config = dev->config;
1051 const struct can_mcan_callbacks *cbs = config->callbacks;
1052
1053 if (ide) {
1054 return cbs->num_ext;
1055 } else {
1056 return cbs->num_std;
1057 }
1058 }
1059
1060 /* Use masked configuration only for simplicity. If someone needs more than
1061 * 28 standard filters, dual mode needs to be implemented.
1062 * Dual mode gets tricky, because we can only activate both filters.
1063 * If one of the IDs is not used anymore, we would need to mark it as unused.
1064 */
can_mcan_add_rx_filter_std(const struct device * dev,can_rx_callback_t callback,void * user_data,const struct can_filter * filter)1065 int can_mcan_add_rx_filter_std(const struct device *dev, can_rx_callback_t callback,
1066 void *user_data, const struct can_filter *filter)
1067 {
1068 const struct can_mcan_config *config = dev->config;
1069 const struct can_mcan_callbacks *cbs = config->callbacks;
1070 struct can_mcan_data *data = dev->data;
1071 struct can_mcan_std_filter filter_element = {
1072 .sfid1 = filter->id,
1073 .sfid2 = filter->mask,
1074 .sft = CAN_MCAN_SFT_CLASSIC
1075 };
1076 int filter_id = -ENOSPC;
1077 int err;
1078 int i;
1079
1080 k_mutex_lock(&data->lock, K_FOREVER);
1081
1082 for (i = 0; i < cbs->num_std; i++) {
1083 if (cbs->std[i].function == NULL) {
1084 filter_id = i;
1085 break;
1086 }
1087 }
1088
1089 if (filter_id == -ENOSPC) {
1090 LOG_WRN("No free standard id filter left");
1091 k_mutex_unlock(&data->lock);
1092 return -ENOSPC;
1093 }
1094
1095 /* TODO proper fifo balancing */
1096 filter_element.sfec = filter_id & 0x01 ? CAN_MCAN_XFEC_FIFO1 : CAN_MCAN_XFEC_FIFO0;
1097
1098 err = can_mcan_write_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_STD_FILTER] +
1099 filter_id * sizeof(struct can_mcan_std_filter),
1100 &filter_element, sizeof(filter_element));
1101 if (err != 0) {
1102 LOG_ERR("failed to write std filter element (err %d)", err);
1103 return err;
1104 }
1105
1106 k_mutex_unlock(&data->lock);
1107
1108 LOG_DBG("Attached std filter at %d", filter_id);
1109
1110 __ASSERT_NO_MSG(filter_id < cbs->num_std);
1111 cbs->std[filter_id].function = callback;
1112 cbs->std[filter_id].user_data = user_data;
1113
1114 return filter_id;
1115 }
1116
can_mcan_add_rx_filter_ext(const struct device * dev,can_rx_callback_t callback,void * user_data,const struct can_filter * filter)1117 static int can_mcan_add_rx_filter_ext(const struct device *dev, can_rx_callback_t callback,
1118 void *user_data, const struct can_filter *filter)
1119 {
1120 const struct can_mcan_config *config = dev->config;
1121 const struct can_mcan_callbacks *cbs = config->callbacks;
1122 struct can_mcan_data *data = dev->data;
1123 struct can_mcan_ext_filter filter_element = {
1124 .efid2 = filter->mask,
1125 .efid1 = filter->id,
1126 .eft = CAN_MCAN_EFT_CLASSIC
1127 };
1128 int filter_id = -ENOSPC;
1129 int err;
1130 int i;
1131
1132 k_mutex_lock(&data->lock, K_FOREVER);
1133
1134 for (i = 0; i < cbs->num_ext; i++) {
1135 if (cbs->ext[i].function == NULL) {
1136 filter_id = i;
1137 break;
1138 }
1139 }
1140
1141 if (filter_id == -ENOSPC) {
1142 LOG_WRN("No free extended id filter left");
1143 k_mutex_unlock(&data->lock);
1144 return -ENOSPC;
1145 }
1146
1147 /* TODO proper fifo balancing */
1148 filter_element.efec = filter_id & 0x01 ? CAN_MCAN_XFEC_FIFO1 : CAN_MCAN_XFEC_FIFO0;
1149
1150 err = can_mcan_write_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_EXT_FILTER] +
1151 filter_id * sizeof(struct can_mcan_ext_filter),
1152 &filter_element, sizeof(filter_element));
1153 if (err != 0) {
1154 LOG_ERR("failed to write std filter element (err %d)", err);
1155 return err;
1156 }
1157
1158 k_mutex_unlock(&data->lock);
1159
1160 LOG_DBG("Attached ext filter at %d", filter_id);
1161
1162 __ASSERT_NO_MSG(filter_id < cbs->num_ext);
1163 cbs->ext[filter_id].function = callback;
1164 cbs->ext[filter_id].user_data = user_data;
1165
1166 return filter_id;
1167 }
1168
can_mcan_add_rx_filter(const struct device * dev,can_rx_callback_t callback,void * user_data,const struct can_filter * filter)1169 int can_mcan_add_rx_filter(const struct device *dev, can_rx_callback_t callback, void *user_data,
1170 const struct can_filter *filter)
1171 {
1172 const struct can_mcan_config *config = dev->config;
1173 const struct can_mcan_callbacks *cbs = config->callbacks;
1174 int filter_id;
1175
1176 if ((filter->flags & ~(CAN_FILTER_IDE)) != 0U) {
1177 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
1178 return -ENOTSUP;
1179 }
1180
1181 if ((filter->flags & CAN_FILTER_IDE) != 0U) {
1182 filter_id = can_mcan_add_rx_filter_ext(dev, callback, user_data, filter);
1183 if (filter_id >= 0) {
1184 filter_id += cbs->num_std;
1185 }
1186 } else {
1187 filter_id = can_mcan_add_rx_filter_std(dev, callback, user_data, filter);
1188 }
1189
1190 return filter_id;
1191 }
1192
can_mcan_remove_rx_filter(const struct device * dev,int filter_id)1193 void can_mcan_remove_rx_filter(const struct device *dev, int filter_id)
1194 {
1195 const struct can_mcan_config *config = dev->config;
1196 const struct can_mcan_callbacks *cbs = config->callbacks;
1197 struct can_mcan_data *data = dev->data;
1198 int err;
1199
1200 if (filter_id < 0) {
1201 LOG_ERR("filter ID %d out of bounds", filter_id);
1202 return;
1203 }
1204
1205 k_mutex_lock(&data->lock, K_FOREVER);
1206
1207 if (filter_id >= cbs->num_std) {
1208 filter_id -= cbs->num_std;
1209 if (filter_id >= cbs->num_ext) {
1210 LOG_ERR("filter ID %d out of bounds", filter_id);
1211 k_mutex_unlock(&data->lock);
1212 return;
1213 }
1214
1215 cbs->ext[filter_id].function = NULL;
1216 cbs->ext[filter_id].user_data = NULL;
1217
1218 err = can_mcan_clear_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_EXT_FILTER] +
1219 filter_id * sizeof(struct can_mcan_ext_filter),
1220 sizeof(struct can_mcan_ext_filter));
1221 if (err != 0) {
1222 LOG_ERR("failed to clear ext filter element (err %d)", err);
1223 }
1224 } else {
1225 cbs->std[filter_id].function = NULL;
1226 cbs->std[filter_id].user_data = NULL;
1227
1228 err = can_mcan_clear_mram(dev, config->mram_offsets[CAN_MCAN_MRAM_CFG_STD_FILTER] +
1229 filter_id * sizeof(struct can_mcan_std_filter),
1230 sizeof(struct can_mcan_std_filter));
1231 if (err != 0) {
1232 LOG_ERR("failed to clear std filter element (err %d)", err);
1233 }
1234 }
1235
1236 k_mutex_unlock(&data->lock);
1237 }
1238
can_mcan_set_state_change_callback(const struct device * dev,can_state_change_callback_t callback,void * user_data)1239 void can_mcan_set_state_change_callback(const struct device *dev,
1240 can_state_change_callback_t callback, void *user_data)
1241 {
1242 struct can_mcan_data *data = dev->data;
1243
1244 data->common.state_change_cb = callback;
1245 data->common.state_change_cb_user_data = user_data;
1246 }
1247
1248 /* helper function allowing mcan drivers without access to private mcan
1249 * definitions to set CCCR_CCE, which might be needed to disable write
1250 * protection for some registers.
1251 */
can_mcan_enable_configuration_change(const struct device * dev)1252 void can_mcan_enable_configuration_change(const struct device *dev)
1253 {
1254 struct can_mcan_data *data = dev->data;
1255 uint32_t cccr;
1256 int err;
1257
1258 k_mutex_lock(&data->lock, K_FOREVER);
1259
1260 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, &cccr);
1261 if (err != 0) {
1262 goto unlock;
1263 }
1264
1265 cccr |= CAN_MCAN_CCCR_CCE;
1266
1267 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, cccr);
1268 if (err != 0) {
1269 goto unlock;
1270 }
1271
1272 unlock:
1273 k_mutex_unlock(&data->lock);
1274 }
1275
can_mcan_configure_mram(const struct device * dev,uintptr_t mrba,uintptr_t mram)1276 int can_mcan_configure_mram(const struct device *dev, uintptr_t mrba, uintptr_t mram)
1277 {
1278 const struct can_mcan_config *config = dev->config;
1279 uint32_t addr;
1280 uint32_t reg;
1281 int err;
1282
1283 err = can_mcan_exit_sleep_mode(dev);
1284 if (err != 0) {
1285 LOG_ERR("Failed to exit sleep mode");
1286 return -EIO;
1287 }
1288
1289 err = can_mcan_enter_init_mode(dev, K_MSEC(CAN_INIT_TIMEOUT_MS));
1290 if (err != 0) {
1291 LOG_ERR("Failed to enter init mode");
1292 return -EIO;
1293 }
1294
1295 can_mcan_enable_configuration_change(dev);
1296
1297 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_STD_FILTER];
1298 reg = (addr & CAN_MCAN_SIDFC_FLSSA) | FIELD_PREP(CAN_MCAN_SIDFC_LSS,
1299 config->mram_elements[CAN_MCAN_MRAM_CFG_STD_FILTER]);
1300 err = can_mcan_write_reg(dev, CAN_MCAN_SIDFC, reg);
1301 if (err != 0) {
1302 return err;
1303 }
1304
1305 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_EXT_FILTER];
1306 reg = (addr & CAN_MCAN_XIDFC_FLESA) | FIELD_PREP(CAN_MCAN_XIDFC_LSS,
1307 config->mram_elements[CAN_MCAN_MRAM_CFG_EXT_FILTER]);
1308 err = can_mcan_write_reg(dev, CAN_MCAN_XIDFC, reg);
1309 if (err != 0) {
1310 return err;
1311 }
1312
1313 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_RX_FIFO0];
1314 reg = (addr & CAN_MCAN_RXF0C_F0SA) | FIELD_PREP(CAN_MCAN_RXF0C_F0S,
1315 config->mram_elements[CAN_MCAN_MRAM_CFG_RX_FIFO0]);
1316 err = can_mcan_write_reg(dev, CAN_MCAN_RXF0C, reg);
1317 if (err != 0) {
1318 return err;
1319 }
1320
1321 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_RX_FIFO1];
1322 reg = (addr & CAN_MCAN_RXF1C_F1SA) | FIELD_PREP(CAN_MCAN_RXF1C_F1S,
1323 config->mram_elements[CAN_MCAN_MRAM_CFG_RX_FIFO1]);
1324 err = can_mcan_write_reg(dev, CAN_MCAN_RXF1C, reg);
1325 if (err != 0) {
1326 return err;
1327 }
1328
1329 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_RX_BUFFER];
1330 reg = (addr & CAN_MCAN_RXBC_RBSA);
1331 err = can_mcan_write_reg(dev, CAN_MCAN_RXBC, reg);
1332 if (err != 0) {
1333 return err;
1334 }
1335
1336 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO];
1337 reg = (addr & CAN_MCAN_TXEFC_EFSA) | FIELD_PREP(CAN_MCAN_TXEFC_EFS,
1338 config->mram_elements[CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO]);
1339 err = can_mcan_write_reg(dev, CAN_MCAN_TXEFC, reg);
1340 if (err != 0) {
1341 return err;
1342 }
1343
1344 addr = mram - mrba + config->mram_offsets[CAN_MCAN_MRAM_CFG_TX_BUFFER];
1345 reg = (addr & CAN_MCAN_TXBC_TBSA) | FIELD_PREP(CAN_MCAN_TXBC_TFQS,
1346 config->mram_elements[CAN_MCAN_MRAM_CFG_TX_BUFFER]) | CAN_MCAN_TXBC_TFQM;
1347 err = can_mcan_write_reg(dev, CAN_MCAN_TXBC, reg);
1348 if (err != 0) {
1349 return err;
1350 }
1351
1352 /* 64 byte Tx Buffer data fields size */
1353 reg = CAN_MCAN_TXESC_TBDS;
1354 err = can_mcan_write_reg(dev, CAN_MCAN_TXESC, reg);
1355 if (err != 0) {
1356 return err;
1357 }
1358
1359 /* 64 byte Rx Buffer/FIFO1/FIFO0 data fields size */
1360 reg = CAN_MCAN_RXESC_RBDS | CAN_MCAN_RXESC_F1DS | CAN_MCAN_RXESC_F0DS;
1361 err = can_mcan_write_reg(dev, CAN_MCAN_RXESC, reg);
1362 if (err != 0) {
1363 return err;
1364 }
1365
1366 return 0;
1367 }
1368
can_mcan_init(const struct device * dev)1369 int can_mcan_init(const struct device *dev)
1370 {
1371 const struct can_mcan_config *config = dev->config;
1372 const struct can_mcan_callbacks *cbs = config->callbacks;
1373 struct can_mcan_data *data = dev->data;
1374 struct can_timing timing = { 0 };
1375 #ifdef CONFIG_CAN_FD_MODE
1376 struct can_timing timing_data = { 0 };
1377 #endif /* CONFIG_CAN_FD_MODE */
1378 uint32_t reg;
1379 int err;
1380
1381 __ASSERT_NO_MSG(config->ops->read_reg != NULL);
1382 __ASSERT_NO_MSG(config->ops->write_reg != NULL);
1383 __ASSERT_NO_MSG(config->ops->read_mram != NULL);
1384 __ASSERT_NO_MSG(config->ops->write_mram != NULL);
1385 __ASSERT_NO_MSG(config->ops->clear_mram != NULL);
1386 __ASSERT_NO_MSG(config->callbacks != NULL);
1387
1388 __ASSERT_NO_MSG(cbs->num_tx <= config->mram_elements[CAN_MCAN_MRAM_CFG_TX_BUFFER]);
1389 __ASSERT_NO_MSG(cbs->num_std <= config->mram_elements[CAN_MCAN_MRAM_CFG_STD_FILTER]);
1390 __ASSERT_NO_MSG(cbs->num_ext <= config->mram_elements[CAN_MCAN_MRAM_CFG_EXT_FILTER]);
1391
1392 k_mutex_init(&data->lock);
1393 k_mutex_init(&data->tx_mtx);
1394 k_sem_init(&data->tx_sem, cbs->num_tx, cbs->num_tx);
1395
1396 if (config->common.phy != NULL) {
1397 if (!device_is_ready(config->common.phy)) {
1398 LOG_ERR("CAN transceiver not ready");
1399 return -ENODEV;
1400 }
1401 }
1402
1403 err = can_mcan_exit_sleep_mode(dev);
1404 if (err != 0) {
1405 LOG_ERR("Failed to exit sleep mode");
1406 return -EIO;
1407 }
1408
1409 err = can_mcan_enter_init_mode(dev, K_MSEC(CAN_INIT_TIMEOUT_MS));
1410 if (err != 0) {
1411 LOG_ERR("Failed to enter init mode");
1412 return -EIO;
1413 }
1414
1415 can_mcan_enable_configuration_change(dev);
1416
1417 #if CONFIG_CAN_LOG_LEVEL >= LOG_LEVEL_DBG
1418 err = can_mcan_read_reg(dev, CAN_MCAN_CREL, ®);
1419 if (err != 0) {
1420 return -EIO;
1421 }
1422
1423 LOG_DBG("IP rel: %lu.%lu.%lu %02lu.%lu.%lu", FIELD_GET(CAN_MCAN_CREL_REL, reg),
1424 FIELD_GET(CAN_MCAN_CREL_STEP, reg), FIELD_GET(CAN_MCAN_CREL_SUBSTEP, reg),
1425 FIELD_GET(CAN_MCAN_CREL_YEAR, reg), FIELD_GET(CAN_MCAN_CREL_MON, reg),
1426 FIELD_GET(CAN_MCAN_CREL_DAY, reg));
1427 #endif /* CONFIG_CAN_LOG_LEVEL >= LOG_LEVEL_DBG */
1428
1429 err = can_mcan_read_reg(dev, CAN_MCAN_CCCR, ®);
1430 if (err != 0) {
1431 return err;
1432 }
1433
1434 reg &= ~(CAN_MCAN_CCCR_FDOE | CAN_MCAN_CCCR_BRSE | CAN_MCAN_CCCR_TEST | CAN_MCAN_CCCR_MON |
1435 CAN_MCAN_CCCR_ASM);
1436
1437 err = can_mcan_write_reg(dev, CAN_MCAN_CCCR, reg);
1438 if (err != 0) {
1439 return err;
1440 }
1441
1442 err = can_mcan_read_reg(dev, CAN_MCAN_TEST, ®);
1443 if (err != 0) {
1444 return err;
1445 }
1446
1447 reg &= ~(CAN_MCAN_TEST_LBCK);
1448
1449 err = can_mcan_write_reg(dev, CAN_MCAN_TEST, reg);
1450 if (err != 0) {
1451 return err;
1452 }
1453
1454 err = can_mcan_read_reg(dev, CAN_MCAN_GFC, ®);
1455 if (err != 0) {
1456 return err;
1457 }
1458
1459 reg |= FIELD_PREP(CAN_MCAN_GFC_ANFE, 0x2) | FIELD_PREP(CAN_MCAN_GFC_ANFS, 0x2);
1460 if (!IS_ENABLED(CONFIG_CAN_ACCEPT_RTR)) {
1461 reg |= CAN_MCAN_GFC_RRFS | CAN_MCAN_GFC_RRFE;
1462 }
1463
1464 err = can_mcan_write_reg(dev, CAN_MCAN_GFC, reg);
1465 if (err != 0) {
1466 return err;
1467 }
1468
1469 err = can_calc_timing(dev, &timing, config->common.bitrate,
1470 config->common.sample_point);
1471 if (err == -EINVAL) {
1472 LOG_ERR("Can't find timing for given param");
1473 return -EIO;
1474 }
1475
1476 LOG_DBG("Presc: %d, TS1: %d, TS2: %d", timing.prescaler, timing.phase_seg1,
1477 timing.phase_seg2);
1478 LOG_DBG("Sample-point err : %d", err);
1479 #ifdef CONFIG_CAN_FD_MODE
1480 err = can_calc_timing_data(dev, &timing_data, config->common.bitrate_data,
1481 config->common.sample_point_data);
1482 if (err == -EINVAL) {
1483 LOG_ERR("Can't find timing for given dataphase param");
1484 return -EIO;
1485 }
1486
1487 LOG_DBG("Sample-point err data phase: %d", err);
1488 #endif /* CONFIG_CAN_FD_MODE */
1489
1490 err = can_set_timing(dev, &timing);
1491 if (err != 0) {
1492 LOG_ERR("failed to set timing (err %d)", err);
1493 return -ENODEV;
1494 }
1495
1496 #ifdef CONFIG_CAN_FD_MODE
1497 err = can_set_timing_data(dev, &timing_data);
1498 if (err != 0) {
1499 LOG_ERR("failed to set data phase timing (err %d)", err);
1500 return -ENODEV;
1501 }
1502 #endif /* CONFIG_CAN_FD_MODE */
1503
1504 reg = CAN_MCAN_IE_BOE | CAN_MCAN_IE_EWE | CAN_MCAN_IE_EPE | CAN_MCAN_IE_MRAFE |
1505 CAN_MCAN_IE_TEFLE | CAN_MCAN_IE_TEFNE | CAN_MCAN_IE_RF0NE | CAN_MCAN_IE_RF1NE |
1506 CAN_MCAN_IE_RF0LE | CAN_MCAN_IE_RF1LE;
1507 #ifdef CONFIG_CAN_STATS
1508 /* These ISRs are only enabled/used for statistics, they are otherwise
1509 * disabled as they may produce a significant amount of frequent ISRs.
1510 */
1511 reg |= CAN_MCAN_IE_PEAE | CAN_MCAN_IE_PEDE;
1512 #endif
1513
1514 err = can_mcan_write_reg(dev, CAN_MCAN_IE, reg);
1515 if (err != 0) {
1516 return err;
1517 }
1518
1519 reg = CAN_MCAN_ILS_RF0NL | CAN_MCAN_ILS_RF1NL | CAN_MCAN_ILS_RF0LL | CAN_MCAN_ILS_RF1LL;
1520 err = can_mcan_write_reg(dev, CAN_MCAN_ILS, reg);
1521 if (err != 0) {
1522 return err;
1523 }
1524
1525 reg = CAN_MCAN_ILE_EINT0 | CAN_MCAN_ILE_EINT1;
1526 err = can_mcan_write_reg(dev, CAN_MCAN_ILE, reg);
1527 if (err != 0) {
1528 return err;
1529 }
1530
1531 /* Interrupt on every TX buffer transmission event */
1532 reg = CAN_MCAN_TXBTIE_TIE;
1533 err = can_mcan_write_reg(dev, CAN_MCAN_TXBTIE, reg);
1534 if (err != 0) {
1535 return err;
1536 }
1537
1538 return can_mcan_clear_mram(dev, 0, config->mram_size);
1539 }
1540
