1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #ifndef _ROM_CACHE_H_
16 #define _ROM_CACHE_H_
17
18 #include "soc/dport_access.h"
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 /** \defgroup uart_apis, uart configuration and communication related apis
25 * @brief uart apis
26 */
27
28 /** @addtogroup uart_apis
29 * @{
30 */
31
32 /**
33 * @brief Initialise cache mmu, mark all entries as invalid.
34 * Please do not call this function in your SDK application.
35 *
36 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
37 *
38 * @return None
39 */
40 void mmu_init(int cpu_no);
41
42 /**
43 * @brief Set Flash-Cache mmu mapping.
44 * Please do not call this function in your SDK application.
45 *
46 * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
47 *
48 * @param int pod : process identifier. Range 0~7.
49 *
50 * @param unsigned int vaddr : virtual address in CPU address space.
51 * Can be IRam0, IRam1, IRom0 and DRom0 memory address.
52 * Should be aligned by psize.
53 *
54 * @param unsigned int paddr : physical address in Flash.
55 * Should be aligned by psize.
56 *
57 * @param int psize : page size of flash, in kilobytes. Should be 64 here.
58 *
59 * @param int num : pages to be set.
60 *
61 * @return unsigned int: error status
62 * 0 : mmu set success
63 * 1 : vaddr or paddr is not aligned
64 * 2 : pid error
65 * 3 : psize error
66 * 4 : mmu table to be written is out of range
67 * 5 : vaddr is out of range
68 */
cache_flash_mmu_set(int cpu_no,int pid,unsigned int vaddr,unsigned int paddr,int psize,int num)69 static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
70 {
71 extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
72
73 unsigned int ret;
74
75 DPORT_STALL_OTHER_CPU_START();
76 ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
77 DPORT_STALL_OTHER_CPU_END();
78
79 return ret;
80 }
81
82 /**
83 * @brief Set Ext-SRAM-Cache mmu mapping.
84 * Please do not call this function in your SDK application.
85 *
86 * Note that this code lives in IRAM and has a bugfix in respect to the ROM version
87 * of this function (which erroneously refused a vaddr > 2MiB
88 *
89 * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
90 *
91 * @param int pod : process identifier. Range 0~7.
92 *
93 * @param unsigned int vaddr : virtual address in CPU address space.
94 * Can be IRam0, IRam1, IRom0 and DRom0 memory address.
95 * Should be aligned by psize.
96 *
97 * @param unsigned int paddr : physical address in Ext-SRAM.
98 * Should be aligned by psize.
99 *
100 * @param int psize : page size of flash, in kilobytes. Should be 32 here.
101 *
102 * @param int num : pages to be set.
103 *
104 * @return unsigned int: error status
105 * 0 : mmu set success
106 * 1 : vaddr or paddr is not aligned
107 * 2 : pid error
108 * 3 : psize error
109 * 4 : mmu table to be written is out of range
110 * 5 : vaddr is out of range
111 */
112 unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
113
114 /**
115 * @brief Initialise cache access for the cpu.
116 * Please do not call this function in your SDK application.
117 *
118 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
119 *
120 * @return None
121 */
Cache_Read_Init(int cpu_no)122 static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
123 {
124 extern void Cache_Read_Init_rom(int cpu_no);
125 DPORT_STALL_OTHER_CPU_START();
126 Cache_Read_Init_rom(cpu_no);
127 DPORT_STALL_OTHER_CPU_END();
128 }
129
130 /**
131 * @brief Flush the cache value for the cpu.
132 * Please do not call this function in your SDK application.
133 *
134 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
135 *
136 * @return None
137 */
Cache_Flush(int cpu_no)138 static inline void IRAM_ATTR Cache_Flush(int cpu_no)
139 {
140 extern void Cache_Flush_rom(int cpu_no);
141 DPORT_STALL_OTHER_CPU_START();
142 Cache_Flush_rom(cpu_no);
143 DPORT_STALL_OTHER_CPU_END();
144 }
145
146 /**
147 * @brief Disable Cache access for the cpu.
148 * Please do not call this function in your SDK application.
149 *
150 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
151 *
152 * @return None
153 */
Cache_Read_Disable(int cpu_no)154 static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
155 {
156 extern void Cache_Read_Disable_rom(int cpu_no);
157 DPORT_STALL_OTHER_CPU_START();
158 Cache_Read_Disable_rom(cpu_no);
159 DPORT_STALL_OTHER_CPU_END();
160 }
161
162 /**
163 * @brief Enable Cache access for the cpu.
164 * Please do not call this function in your SDK application.
165 *
166 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
167 *
168 * @return None
169 */
Cache_Read_Enable(int cpu_no)170 static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
171 {
172 extern void Cache_Read_Enable_rom(int cpu_no);
173 DPORT_STALL_OTHER_CPU_START();
174 Cache_Read_Enable_rom(cpu_no);
175 DPORT_STALL_OTHER_CPU_END();
176 }
177
178 /**
179 * @}
180 */
181
182 #ifdef __cplusplus
183 }
184 #endif
185
186 #endif /* _ROM_CACHE_H_ */
187
