1 /* coherence.c - Cache coherence opt-in / opt-out functions */
2
3 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/hal/coherence.c#1 $ */
4
5 /*
6 * Copyright (c) 2008 Tensilica Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sublicense, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included
17 * in all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
23 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28 #include <xtensa/config/core.h>
29
30
31 /*
32 * Opt-out of cache coherence.
33 *
34 * Caveat: on a core with full MMU, cache attribute handling done here only
35 * works well with the default (reset) TLB mapping of eight 512MB regions.
36 * It likely won't work correctly when other page sizes are in use (it may
37 * appear to work but be open to race conditions, depending on situation).
38 */
xthal_cache_coherence_optout(void)39 void xthal_cache_coherence_optout( void )
40 {
41 #if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT
42 unsigned ca = xthal_get_cacheattr();
43 /* Writeback all dirty entries. Writethru mode avoids new dirty entries. */
44 xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_WRITETHRU, XTHAL_CAFLAG_EXPAND);
45 xthal_dcache_all_writeback();
46 /* Invalidate all cache entries. Cache-bypass mode avoids new entries. */
47 xthal_set_region_attribute(0,0xFFFFFFFF, XCHAL_CA_BYPASS, XTHAL_CAFLAG_EXPAND);
48 xthal_dcache_all_writeback_inv();
49 /* Wait for everything to settle. */
50 asm("memw");
51 xthal_dcache_sync();
52 xthal_icache_sync();
53 /* Opt-out of cache coherency protocol. */
54 xthal_cache_coherence_off();
55 /* Restore cache attributes, as of entry to this function. */
56 xthal_set_cacheattr(ca);
57 #endif
58 }
59
60
