1 /***************************************************************************//**
2 * \file cy_mcwdt.h
3 * \version 1.80
4 *
5 * Provides an API declaration of the Cypress PDL 3.0 MCWDT driver
6 *
7 ********************************************************************************
8 * \copyright
9 * Copyright (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 /**
27 * \addtogroup group_mcwdt
28 * \{
29 * A MCWDT has two 16-bit counters and one 32-bit counter.
30 *
31 * The functions and other declarations used in this driver are in cy_mcwdt.h.
32 * You can include cy_pdl.h to get access to all functions
33 * and declarations in the PDL.
34 *
35 * You can use this driver to create a free-running
36 * timer or generate periodic interrupts. The driver also
37 * includes support for the watchdog function to recover from CPU or
38 * firmware failures.
39 *
40 * There are two primary use cases for MCWDT: generating periodic CPU interrupts;
41 * and implementing a free-running timer. Both have many applications in
42 * embedded systems:
43 * * Measuring time between events
44 * * Generating periodic events
45 * * Synchronizing actions
46 * * Real-time clocking
47 * * Polling
48 *
49 * An additional use case is to implement a watchdog used for recovering from a CPU or
50 * firmware failure.
51 *
52 * \section group_mcwdt_configuration Configuration Considerations
53 *
54 * Each MCWDT may be configured for a particular product.
55 * One MCWDT block can be associated with only one CPU during runtime.
56 * A single MCWDT is not intended to be used by multiple CPUs simultaneously.
57 * Each block contains three sub-counters, each of which can be configured for
58 * various system utility functions - free running counter, periodic interrupts,
59 * watchdog reset, or three interrupts followed by a watchdog reset.
60 * All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
61 * counter.
62 * A simplified diagram of the MCWDT hardware is shown below:
63 * \image html mcwdt.png
64 * The frequency of the periodic interrupts can be configured using the Match
65 * value with combining Clear on match option, which can be set individually
66 * for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
67 * is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
68 * after 65535 counts and the match value defines the shift between interrupts
69 * (see the figure below). The enabled Clear on match option
70 * resets the counter when the interrupt occurs.
71 * \image html mcwdt_counters.png
72 * 32-bit sub-counter C2 does not have Clear on match option.
73 * The interrupt of counter C2 occurs when the counts equal
74 * 2<sup>Toggle bit</sup> value.
75 * \image html mcwdt_subcounters.png
76 * To set up an MCWDT, provide the configuration parameters in the
77 * cy_stc_mcwdt_config_t structure. Then call
78 * Cy_MCWDT_Init() to initialize the driver.
79 * Call Cy_MCWDT_Enable() to enable all specified counters.
80 *
81 * You can also set the mode of operation for any counter. If you choose
82 * interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
83 * parameter for the masks described in Macro Section. All counter interrupts
84 * are OR'd together to from a single combined MCWDT interrupt.
85 * Additionally, enable the Global interrupts and initialize the referenced
86 * interrupt by setting the priority and the interrupt vector using
87 * \ref Cy_SysInt_Init() of the sysint driver.
88 *
89 * The values of the MCWDT counters can be monitored using
90 * Cy_MCWDT_GetCount().
91 *
92 * CAT1C and TVIIBE devices support MCWDT_B type of counters, which are slightly different
93 * from MCWDT, which is explained above
94 *
95 * A simplified diagram of the MCWDT_B hardware is shown below:
96 * \image html mcwdt_b.png
97 *
98 * \note Please refer to TRM for more information on CAT1C and TVIIBE supported MCWDT_B counters.
99 *
100 * \note In addition to the MCWDTs, each device has a separate watchdog timer
101 * (WDT) that can also be used to generate a watchdog reset or periodic
102 * interrupts. For more information on the WDT, see the appropriate section
103 * of the PDL.
104 *
105 * \section group_mcwdt_more_information More Information
106 *
107 * For more information on the MCWDT peripheral, refer to
108 * the technical reference manual (TRM).
109 *
110 * \section group_mcwdt_changelog Changelog
111 * <table class="doxtable">
112 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
113 * <tr>
114 * <td>1.80</td>
115 * <td>Added support for TRAVEO™ II Body Entry devices.<br>
116 * Pre-processor check for MXS40SRSS version now groups ver. 2 with ver. 3. Previously ver. 2 was grouped with ver. 1.</td>
117 * <td>Code enhancement and support for new devices.</td>
118 * </tr>
119 * <tr>
120 * <td>1.70</td>
121 * <td>Added MCWDT_B type support required for CAT1C devices.<br>Newly added APIs:
122 * \n Cy_MCWDT_SetLowerAction(),
123 * \n Cy_MCWDT_SetUpperAction(),
124 * \n Cy_MCWDT_SetWarnAction(),
125 * \n Cy_MCWDT_SetSubCounter2Action(),
126 * \n Cy_MCWDT_GetLowerAction(),
127 * \n Cy_MCWDT_GetUpperAction(),
128 * \n Cy_MCWDT_GetWarnAction(),
129 * \n Cy_MCWDT_GetSubCounter2Action(),
130 * \n Cy_MCWDT_SetAutoService(),
131 * \n Cy_MCWDT_GetAutoService(),
132 * \n Cy_MCWDT_SetSleepDeepPause(),
133 * \n Cy_MCWDT_GetSleepDeepPause(),
134 * \n Cy_MCWDT_SetDebugRun(),
135 * \n Cy_MCWDT_GetDebugRun(),
136 * \n Cy_MCWDT_SetLowerLimit(),
137 * \n Cy_MCWDT_SetUpperLimit(),
138 * \n Cy_MCWDT_SetWarnLimit(),
139 * \n Cy_MCWDT_GetLowerLimit(),
140 * \n Cy_MCWDT_GetUpperLimit(),
141 * \n Cy_MCWDT_GetWarnLimit(),
142 * \n Cy_MCWDT_WaitForCounterReset(),
143 * \n Cy_MCWDT_CpuSelectForDpSlpPauseAction(),
144 * \n Cy_MCWDT_GetCascadeMatchCombined().</td>
145 * <td>Support for new devices.</td>
146 * </tr>
147 * <tr>
148 * <td>1.60</td>
149 * <td>CAT1B, CAT1C devices support.<br>Newly added APIs:
150 * \n Cy_MCWDT_GetLowerLimit() to get the lower limit value of the specified counter,
151 * \n Cy_MCWDT_SetLowerLimit() to set the the lower limit value of the specified counter,
152 * \n Cy_MCWDT_GetLowerLimitMode() to get the lower limit mode of the specified counter,
153 * \n Cy_MCWDT_SetLowerLimitMode() to set the lower limit mode of the specified counter,
154 * \n Cy_MCWDT_GetLowerLimitCascaded() to get the lower limit registers cascaded value,
155 * \n Cy_MCWDT_SetCascadeCarryOutRollOver() to enable the Rollover mode for carryout,
156 * \n Cy_MCWDT_GetCascadeCarryOutRollOver() to check if Rollover mode enabled for carryout or not,
157 * \n Cy_MCWDT_SetCascadeMatchCombined() to set the match to combined cascade counters,
158 * \n Cy_MCWDT_GetCascadeMatchCombined() to report if match is enabled with combined cascade counters or not.</td>
159 * <td>Support for new devices.</td>
160 * </tr>
161 * <tr>
162 * <td>1.50.1</td>
163 * <td>Minor documentation updates.</td>
164 * <td>Documentation enhancement.</td>
165 * </tr>
166 * <tr>
167 * <td>1.50</td>
168 * <td>Added support for new family of devices.</td>
169 * <td>New device support.</td>
170 * </tr>
171 * <tr>
172 * <td>1.40</td>
173 * <td>Fixed/documented MISRA 2012 violations.</td>
174 * <td>MISRA 2012 compliance.</td>
175 * </tr>
176 * <tr>
177 * <td>1.30.1</td>
178 * <td>Minor documentation updates.</td>
179 * <td>Documentation enhancement.</td>
180 * </tr>
181 * <tr>
182 * <td>1.30</td>
183 * <td>In version 1.20 the Cy_MCWDT_GetCountCascaded() function
184 * returned the wrong value when counter#1 overflowed.
185 * This bug is corrected in version 1.30.
186 * </td>
187 * <td>Defect fixes.
188 * </td>
189 * </tr>
190 * <tr>
191 * <td rowspan="2">1.20</td>
192 * <td>Flattened the organization of the driver source code into the single
193 * source directory and the single include directory.
194 * </td>
195 * <td>Driver library directory-structure simplification.</td>
196 * </tr>
197 * <tr>
198 * <td>Added register access layer. Use register access macros instead
199 * of direct register access using dereferenced pointers.</td>
200 * <td>Makes register access device-independent, so that the PDL does
201 * not need to be recompiled for each supported part number.</td>
202 * </tr>
203 * <tr>
204 * <td>1.10.1</td>
205 * <td>Updated description of the \ref cy_stc_mcwdt_config_t structure type</td>
206 * <td>Documentation update and clarification</td>
207 * </tr>
208 * <tr>
209 * <td>1.10</td>
210 * <td>Added input parameter validation to the API functions.<br>
211 * Added API function GetCountCascaded()</td>
212 * <td></td>
213 * </tr>
214 * <tr>
215 * <td>1.0</td>
216 * <td>Initial version</td>
217 * <td></td>
218 * </tr>
219 * </table>
220 *
221 * \defgroup group_mcwdt_macros Macros
222 * \defgroup group_mcwdt_functions Functions
223 * \defgroup group_mcwdt_data_structures Data Structures
224 * \defgroup group_mcwdt_enums Enumerated Types
225 */
226
227 #ifndef CY_MCWDT_H
228 #define CY_MCWDT_H
229
230 #if defined(__cplusplus)
231 extern "C" {
232 #endif
233
234 #include "cy_device.h"
235
236 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) || defined (CY_IP_MXS22SRSS)
237
238 #include <stdbool.h>
239 #include <stddef.h>
240 #include "cy_syslib.h"
241
242
243 /**
244 * \addtogroup group_mcwdt_macros
245 * \{
246 */
247
248 /** Driver major version */
249 #define CY_MCWDT_DRV_VERSION_MAJOR 1
250
251 /** Driver minor version */
252 #define CY_MCWDT_DRV_VERSION_MINOR 80
253
254 /** \cond INTERNAL_MACROS */
255
256 /***************************************
257 * Registers Constants
258 ***************************************/
259
260 #define CY_MCWDT_LOCK_CLR0 (1u)
261 #define CY_MCWDT_LOCK_CLR1 (2u)
262 #define CY_MCWDT_LOCK_SET01 (3u)
263
264 #define CY_MCWDT_BYTE_SHIFT (8u)
265 #define CY_MCWDT_C0C1_MODE_MASK (3u)
266 #define CY_MCWDT_C2_MODE_MASK (1u)
267
268
269 /***************************************
270 * API Constants
271 ***************************************/
272
273 #define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
274 MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
275
276 #define CY_MCWDT_CTR0_Pos (0u)
277 #define CY_MCWDT_CTR1_Pos (1u)
278 #define CY_MCWDT_CTR2_Pos (2u)
279 #define CY_MCWDT_CTR_Pos (0UL)
280
281 /** \endcond */
282
283 #define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
284
285 #define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
286 that handle multiple counters, including Cy_MCWDT_Enable(),
287 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
288 #define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
289 that handle multiple counters, including Cy_MCWDT_Enable(),
290 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
291 #define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
292 that handle multiple counters, including Cy_MCWDT_Enable(),
293 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
294 #define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
295 that handle multiple counters, including Cy_MCWDT_Enable(),
296 Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
297
298 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
299 /** For compatibility with CAT1C and TVIIBE MCWDT driver */
300 #define MCWDT_STRUCT_Type MCWDT_Type
301 #endif
302
303 /** \} group_mcwdt_macros */
304
305
306 /**
307 * \addtogroup group_mcwdt_enums
308 * \{
309 */
310
311 /** The mcwdt sub-counter identifiers. */
312 typedef enum
313 {
314 CY_MCWDT_COUNTER0, /**< Sub-counter#0 identifier. */
315 CY_MCWDT_COUNTER1, /**< Sub-counter#1 identifier. */
316 CY_MCWDT_COUNTER2 /**< Sub-counter#2 identifier. */
317 } cy_en_mcwdtctr_t;
318
319 /** The mcwdt modes. */
320 typedef enum
321 {
322 CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
323 CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
324 CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
325 CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
326 Set/GetMode functions. */
327 } cy_en_mcwdtmode_t;
328
329 /** The mcwdt cascading. */
330 typedef enum
331 {
332 CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
333 CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
334 It is used for Set/GetCascade functions. */
335 CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
336 It is used for Set/GetCascade functions. */
337 CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
338 and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
339 It is used for Set/GetCascade functions. */
340 } cy_en_mcwdtcascade_t;
341
342 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
343 /** The mcwdt lower limit identifiers. */
344 /**
345 * \note
346 * This enum is available for CAT1B and CAT1D devices.
347 **/
348 typedef enum
349 {
350 CY_MCWDT_LOWER_LIMIT0, /**< Lower limit for Sub-counter#0 identifier. */
351 CY_MCWDT_LOWER_LIMIT1, /**< Lower limit for Sub-counter#1 identifier. */
352 } cy_en_mcwdtlowerlimit_t;
353
354 /** The mcwdt lower limit mode identifiers. */
355 /**
356 * \note
357 * This enum is available for CAT1B devices.
358 **/
359 typedef enum
360 {
361 CY_MCWDT_LOWER_LIMIT_MODE_NOTHING, /**< Do nothing. */
362 CY_MCWDT_LOWER_LIMIT_MODE_INT, /**< Assert WDT_INTx. */
363 CY_MCWDT_LOWER_LIMIT_MODE_RESET, /**< Assert WDT Reset. */
364 } cy_en_mcwdtlowerlimitmode_t;
365 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS*/
366
367 /** The MCWDT error codes. */
368 typedef enum
369 {
370 CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
371 CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
372 } cy_en_mcwdt_status_t;
373
374 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
375 /** The MCWDT Enable/Disable identifiers. */
376 /**
377 * \note
378 * Below enum is available for CAT1C and TVIIBE devices only.
379 **/
380 typedef enum
381 {
382 CY_MCWDT_DISABLE = 0u,
383 CY_MCWDT_ENABLE,
384 } cy_en_mcwdt_enable_t;
385
386 /** The MCWDT Deep Sleep Cores identifiers. */
387 /**
388 * \note
389 * Below enum is available for CAT1C and TVIIBE devices only.
390 **/
391 typedef enum
392 {
393 CY_MCWDT_PAUSED_BY_DPSLP_CM0 = 0u,
394 CY_MCWDT_PAUSED_BY_DPSLP_CM4 = 1u,
395 CY_MCWDT_PAUSED_BY_DPSLP_CM7_0 = 1u,
396 CY_MCWDT_PAUSED_BY_DPSLP_CM7_1 = 2u,
397 CY_MCWDT_PAUSED_BY_NO_CORE = 3u,
398 } cy_en_mcwdt_select_core_t;
399
400 /** The MCWDT subcounter 2 actions. */
401 /**
402 * \note
403 * Below enum is available for CAT1C and TVIIBE devices only.
404 **/
405 typedef enum
406 {
407 CY_MCWDT_CNT2_ACTION_NONE,
408 CY_MCWDT_CNT2_ACTION_INT,
409 } cy_en_mcwdt_cnt2_action_t;
410
411 /** The MCWDT lower and upper actions. */
412 /**
413 * \note
414 * Below enum is available for CAT1C and TVIIBE devices only.
415 **/
416 typedef enum
417 {
418 CY_MCWDT_ACTION_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
419 CY_MCWDT_ACTION_FAULT, /**< The Fault mode. It is used for Set/GetMode functions. */
420 CY_MCWDT_ACTION_FAULT_THEN_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
421 } cy_en_mcwdt_lower_upper_action_t;
422
423 /** The MCWDT warn actions. */
424 /**
425 * \note
426 * Below enum is available for CAT1C and TVIIBE devices only.
427 */
428 typedef enum
429 {
430 CY_MCWDT_WARN_ACTION_NONE,
431 CY_MCWDT_WARN_ACTION_INT,
432 } cy_en_mcwdt_warn_action_t;
433
434 #endif /* (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2)) */
435
436 /** \} group_mcwdt_enums */
437
438 /**
439 * \addtogroup group_mcwdt_data_structures
440 * \{
441 */
442
443 /** The MCWDT component configuration structure. */
444 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
445 typedef struct
446 {
447 uint16_t c0LowerLimit; /**< The sub-counter#0 lower limit value, for reset or fault.
448 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
449 Only for CAT1C and TVIIBE devices*/
450 uint16_t c0UpperLimit; /**< The sub-counter#0 upper limit value, for reset or fault.
451 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
452 Only for CAT1C and TVIIBE devices*/
453 uint16_t c0WarnLimit; /**< The sub-counter#0 warn limit value, for interrupt.
454 Range: 0 - 65535 for c0AutoService = 0 and 1 - 65535 for c0AutoService = 1.
455 Only for CAT1C and TVIIBE devices*/
456 cy_en_mcwdt_lower_upper_action_t c0LowerAction; /**< The sub-counter#0 action. It can have the following values:
457 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C and TVIIBE devices*/
458 cy_en_mcwdt_lower_upper_action_t c0UpperAction; /**< The sub-counter#0 action. It can have the following values:
459 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C and TVIIBE devices*/
460 cy_en_mcwdt_warn_action_t c0WarnAction; /**< The sub-counter#0 warn action. It can have the following values:
461 \ref cy_en_mcwdt_warn_action_t. Only for CAT1C and TVIIBE devices*/
462 cy_en_mcwdt_enable_t c0AutoService; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
463 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
464 cy_en_mcwdt_enable_t c0SleepDeepPause; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
465 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
466 cy_en_mcwdt_enable_t c0DebugRun; /**< The sub-counter#0 Auto Service parameter enabled/disabled.
467 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
468 uint16_t c1LowerLimit; /**< The sub-counter#0 lower limit value, for reset or fault.
469 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
470 Only for CAT1C and TVIIBE devices*/
471 uint16_t c1UpperLimit; /**< The sub-counter#0 upper limit value, for reset or fault.
472 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
473 Only for CAT1C and TVIIBE devices*/
474 uint16_t c1WarnLimit; /**< The sub-counter#0 warn limit value, for interrupt.
475 Range: 0 - 65535 for c1AutoService = 0 and 1 - 65535 for c1AutoService = 1.
476 Only for CAT1C and TVIIBE devices*/
477 cy_en_mcwdt_lower_upper_action_t c1LowerAction; /**< The sub-counter#1 action. It can have the following values:
478 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C and TVIIBE devices*/
479 cy_en_mcwdt_lower_upper_action_t c1UpperAction; /**< The sub-counter#1 action. It can have the following values:
480 \ref cy_en_mcwdt_lower_upper_action_t. Only for CAT1C and TVIIBE devices*/
481 cy_en_mcwdt_warn_action_t c1WarnAction; /**< The sub-counter#1 warn action. It can have the following values:
482 \ref cy_en_mcwdt_warn_action_t. Only for CAT1C and TVIIBE devices*/
483 cy_en_mcwdt_enable_t c1AutoService; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
484 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
485 cy_en_mcwdt_enable_t c1SleepDeepPause; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
486 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
487 cy_en_mcwdt_enable_t c1DebugRun; /**< The sub-counter#1 Auto Service parameter enabled/disabled.
488 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
489 uint32_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value. Only for CAT1C and TVIIBE devices*/
490 cy_en_mcwdt_cnt2_action_t c2Action; /**< The sub-counter#2 mode. It can have the following values:
491 \ref cy_en_mcwdt_cnt2_action_t. Only for CAT1C and TVIIBE devices*/
492 cy_en_mcwdt_enable_t c2SleepDeepPause; /**< The sub-counter#2 Auto Service parameter enabled/disabled.
493 Range: FALSE - TRUE. Only for CAT1C and TVIIBE devices*/
494 cy_en_mcwdt_enable_t c2DebugRun; /**< The sub-counter#2 Auto Service parameter enabled/disabled. Only for CAT1C and TVIIBE devices **/
495
496 cy_en_mcwdt_select_core_t coreSelect; /**< Selecting the the core. The DeepSleep of the core pauses this MCWDT counter only for CAT1C and TVIIBE devices **/
497 } cy_stc_mcwdt_config_t;
498 #endif
499
500
501 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_IP_MXS22SRSS)
502 /**
503 * \note
504 * Below structure variables are available for CAT1A (except TVIIBE), CAT1B and CAT1D devices.
505 **/
506 typedef struct
507 {
508 uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
509 Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
510 c0ClearOnMatch = 1. For CAT1A, CAT1B and CAT1D devices */
511 uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
512 Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
513 c1ClearOnMatch = 1. For CAT1A, CAT1B and CAT1D devices */
514 uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
515 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET.
516 For CAT1A, CAT1B and CAT1D devices */
517 uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
518 \ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET.
519 For CAT1A, CAT1B and CAT1D devices */
520 uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
521 Range: 0 - 31. For CAT1A, CAT1B and CAT1D devices */
522 uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
523 and \ref CY_MCWDT_MODE_INT. For CAT1A, CAT1B and CAT1D devices */
524 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
525 uint16_t c0LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
526 Range: 0 - 65535. Only for CAT1B devices */
527 uint16_t c1LowerLimit; /**< Lower limit for sub-counter 0 of this MCWDT.
528 Range: 0 - 65535. Only for CAT1B devices */
529 uint16_t c0LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
530 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset.
531 Only for CAT1B devices */
532 uint16_t c1LowerLimitMode; /**< Watchdog Counter Action on service before lower limit.
533 Range: 0 - 2., 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset.
534 Only for CAT1B devices */
535 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
536
537 /**
538 * \note
539 * This parameter is available for devices having MXS40SSRSS IP.
540 **/
541
542 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
543 bool c0c1carryoutconfig; /**< Carryout behaviour that applies when counter 0 and 1 are cascaded
544 false: carry out on counter 0 match, true: carry out on counter 0 roll-over.
545 Only for CAT1B devices */
546 bool c0c1matchconfig; /**< Matching behaviour that applies when counter 0 and 1 are cascaded
547 false: Match based on counter 1 alone, true: Match based on counter 1 and 0 simultaneously.
548 Only for CAT1B devices */
549 bool c1c2carryoutconfig; /**< Carryout behaviour that applies when counter 1 and 2 are cascaded
550 false: carry out on counter 1 match, true: carry out on counter 1 roll-over.
551 Only for CAT1B devices */
552 bool c1c2matchconfig; /**< Matching behaviour that applies when counter 1 and 2 are cascaded
553 false: Match based on counter 1 alone, true: Match based on counter 2 and 1 simultaneously.
554 Only for CAT1B devices */
555 #endif /* CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
556
557 bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. For CAT1A, CAT1B and CAT1D devices */
558 bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. For CAT1A, CAT1B and CAT1D devices */
559 bool c0c1Cascade; /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade. For CAT1A, CAT1B and CAT1D devices */
560 bool c1c2Cascade; /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade. For CAT1A, CAT1B and CAT1D devices */
561 } cy_stc_mcwdt_config_t;
562 #endif
563 /** \} group_mcwdt_data_structures */
564
565
566 /** \cond PARAM_CHECK_MACROS */
567
568 /** Parameter check macros */
569 #define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
570
571 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
572 #define CY_MCWDT_IS_LOWER_LIMIT_VALID(counter) ((CY_MCWDT_LOWER_LIMIT0 == (counter)) || \
573 (CY_MCWDT_LOWER_LIMIT1 == (counter)))
574
575 #define CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode) ((CY_MCWDT_LOWER_LIMIT_MODE_NOTHING == (mode)) || \
576 (CY_MCWDT_LOWER_LIMIT_MODE_INT == (mode)) || \
577 (CY_MCWDT_LOWER_LIMIT_MODE_RESET == (mode)))
578 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
579
580 #define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
581 (CY_MCWDT_COUNTER1 == (counter)) || \
582 (CY_MCWDT_COUNTER2 == (counter)))
583
584 #define CY_MCWDT_IS_MODE_VALID(mode) ((CY_MCWDT_MODE_NONE == (mode)) || \
585 (CY_MCWDT_MODE_INT == (mode)) || \
586 (CY_MCWDT_MODE_RESET == (mode)) || \
587 (CY_MCWDT_MODE_INT_RESET == (mode)))
588
589 #define CY_MCWDT_IS_ENABLE_VALID(enable) (1UL >= (enable))
590
591
592 #define CY_MCWDT_IS_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_NONE == (cascade)) || \
593 (CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
594 (CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
595 (CY_MCWDT_CASCADE_BOTH == (cascade)))
596
597 #define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
598
599 #define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
600
601 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
602 #define CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(cascade) ((CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
603 (CY_MCWDT_CASCADE_C1C2 == (cascade)))
604 #endif
605
606 /** \endcond */
607
608
609 /*******************************************************************************
610 * Function Prototypes
611 *******************************************************************************/
612
613 /**
614 * \addtogroup group_mcwdt_functions
615 * \{
616 */
617 cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_t const *config);
618 void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base);
619 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
620 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
621 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
622 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base);
623 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base);
624 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base);
625 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_IP_MXS22SRSS)
626 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode);
627 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
628 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
629 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
630 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade);
631 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base);
632 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs);
633 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
634 uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
635 #endif
636 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit);
637 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base);
638 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter);
639 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs);
640 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base);
641 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
642 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters);
643 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base);
644 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters);
645 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base);
646 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
647 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
648 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs);
649 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter);
650 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode);
651 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base);
652 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
653
654 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
655 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool carryoutconfig);
656 __STATIC_INLINE bool Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
657
658 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool matchconfig);
659 __STATIC_INLINE bool Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter);
660 #endif /* CY_IP_MXS40SSRSS,CY_IP_MXS22SRSS */
661
662 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
663 void Cy_MCWDT_CpuSelectForDpSlpPauseAction(MCWDT_Type *base, cy_en_mcwdt_select_core_t core);
664 void Cy_MCWDT_SetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action);
665 void Cy_MCWDT_SetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_lower_upper_action_t action);
666 void Cy_MCWDT_SetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdt_warn_action_t action);
667 void Cy_MCWDT_SetSubCounter2Action(MCWDT_Type *base, cy_en_mcwdt_cnt2_action_t action);
668 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetLowerAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
669 cy_en_mcwdt_lower_upper_action_t Cy_MCWDT_GetUpperAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
670 cy_en_mcwdt_warn_action_t Cy_MCWDT_GetWarnAction(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
671 cy_en_mcwdt_cnt2_action_t Cy_MCWDT_GetSubCounter2Action(MCWDT_Type *base);
672 void Cy_MCWDT_SetAutoService(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
673 uint32_t Cy_MCWDT_GetAutoService(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
674 uint32_t Cy_MCWDT_GetSleepDeepPause(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
675 void Cy_MCWDT_SetSleepDeepPause(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
676 void Cy_MCWDT_SetDebugRun(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable);
677 uint32_t Cy_MCWDT_GetDebugRun(MCWDT_Type const *base, cy_en_mcwdtctr_t counter);
678 void Cy_MCWDT_SetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
679 void Cy_MCWDT_SetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
680 void Cy_MCWDT_SetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter, uint16_t limit, uint16_t waitUs);
681 uint16_t Cy_MCWDT_GetUpperLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
682 uint16_t Cy_MCWDT_GetWarnLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
683 void Cy_MCWDT_WaitForCounterReset(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
684 void Cy_MCWDT_ClearWatchdog(MCWDT_Type *base, uint32_t counters);
685 uint16_t Cy_MCWDT_GetLowerLimit(MCWDT_Type *base, cy_en_mcwdtctr_t counter);
686
687 #endif
688
689
690 /*******************************************************************************
691 * Function Name: Cy_MCWDT_Enable
692 ****************************************************************************//**
693 *
694 * Enables all specified counters.
695 *
696 * \param base
697 * The base pointer to a structure that describes registers.
698 *
699 * \param counters
700 * OR of all counters to enable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
701 * CY_MCWDT_CTR2 macros.
702 *
703 * \param waitUs
704 * The function waits for some delay in microseconds before returning,
705 * because the counter begins counting after two lf_clk cycles pass.
706 * The recommended value is 93 us.
707 * \note
708 * Setting this parameter to a zero means No wait. In this case, it is
709 * the user's responsibility to check whether the selected counters were enabled
710 * immediately after the function call. This can be done by the
711 * Cy_MCWDT_GetEnabledStatus() API.
712 *
713 *******************************************************************************/
Cy_MCWDT_Enable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)714 __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
715 {
716 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
717
718 if (0UL != (counters & CY_MCWDT_CTR0))
719 {
720 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0) |= MCWDT_CTR_CTL_ENABLE_Msk;
721 }
722 if (0UL != (counters & CY_MCWDT_CTR1))
723 {
724 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1) |= MCWDT_CTR_CTL_ENABLE_Msk;
725 }
726 if (0UL != (counters & CY_MCWDT_CTR2))
727 {
728 MCWDT_CTR2_CTL(base) |= MCWDT_CTR2_CTL_ENABLE_Msk;
729 }
730
731 #else
732 uint32_t enableCounters;
733
734 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
735
736 /* Extract particular counters for enable */
737 enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
738 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
739 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
740
741 MCWDT_CTL(base) |= enableCounters;
742 #endif
743
744 Cy_SysLib_DelayUs(waitUs);
745 }
746
747
748 /*******************************************************************************
749 * Function Name: Cy_MCWDT_Disable
750 ****************************************************************************//**
751 *
752 * Disables all specified counters.
753 *
754 * \param base
755 * The base pointer to a structure describing registers.
756 *
757 * \param counters
758 * OR of all counters to disable. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
759 * CY_MCWDT_CTR2 macros.
760 *
761 * \param waitUs
762 * The function waits for some delay in microseconds before returning,
763 * because the counter stops counting after two lf_clk cycles pass.
764 * The recommended value is 93 us.
765 * \note
766 * Setting this parameter to a zero means No wait. In this case, it is
767 * the user's responsibility to check whether the selected counters were disabled
768 * immediately after the function call. This can be done by the
769 * Cy_MCWDT_GetEnabledStatus() API.
770 *
771 *******************************************************************************/
Cy_MCWDT_Disable(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)772 __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
773 {
774 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
775
776 if (0UL != (counters & CY_MCWDT_CTR0))
777 {
778 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0) &= (uint32_t) ~MCWDT_CTR_CTL_ENABLE_Msk;
779 }
780 if (0UL != (counters & CY_MCWDT_CTR1))
781 {
782 MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1) &= (uint32_t) ~MCWDT_CTR_CTL_ENABLE_Msk;
783 }
784 if (0UL != (counters & CY_MCWDT_CTR2))
785 {
786 MCWDT_CTR2_CTL(base) &= (uint32_t) ~MCWDT_CTR2_CTL_ENABLE_Msk;
787 }
788 #else
789 uint32_t disableCounters;
790
791 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
792
793 /* Extract particular counters for disable */
794 disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
795 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
796 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk : 0UL);
797
798 MCWDT_CTL(base) &= ~disableCounters;
799 #endif
800
801 Cy_SysLib_DelayUs(waitUs);
802 }
803
804
805 /*******************************************************************************
806 * Function Name: Cy_MCWDT_GetEnabledStatus
807 ****************************************************************************//**
808 *
809 * Reports the enabled status of the specified counter.
810 *
811 * \param base
812 * The base pointer to a structure that describes registers.
813 *
814 * \param counter
815 * The number of the MCWDT counter. The valid range is [0-2].
816 *
817 * \return
818 * The status of the MCWDT counter: 0 = disabled, 1 = enabled.
819 *
820 *******************************************************************************/
Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)821 __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
822 {
823 uint32_t status = 0u;
824
825 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
826
827 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
828 switch (counter)
829 {
830 case CY_MCWDT_COUNTER0:
831 status = _FLD2VAL(MCWDT_CTR_CTL_ENABLE, MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER0));
832 break;
833 case CY_MCWDT_COUNTER1:
834 status = _FLD2VAL(MCWDT_CTR_CTL_ENABLE, MCWDT_CTR_CTL(base, CY_MCWDT_COUNTER1));
835 break;
836 case CY_MCWDT_COUNTER2:
837 status = _FLD2VAL(MCWDT_CTR2_CTL_ENABLE, MCWDT_CTR2_CTL(base));
838 break;
839 default:
840 CY_ASSERT(0u != 0u);
841 break;
842 }
843 #else
844 switch (counter)
845 {
846 case CY_MCWDT_COUNTER0:
847 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0, MCWDT_CTL(base));
848 break;
849 case CY_MCWDT_COUNTER1:
850 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1, MCWDT_CTL(base));
851 break;
852 case CY_MCWDT_COUNTER2:
853 status = _FLD2VAL(MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2, MCWDT_CTL(base));
854 break;
855
856 default:
857 CY_ASSERT(0u != 0u);
858 break;
859 }
860 #endif
861
862 return (status);
863 }
864
865
866 /*******************************************************************************
867 * Function Name: Cy_MCWDT_Lock
868 ****************************************************************************//**
869 *
870 * Locks out configuration changes to all MCWDT registers.
871 *
872 * \param base
873 * The base pointer to a structure that describes registers.
874 *
875 *******************************************************************************/
Cy_MCWDT_Lock(MCWDT_STRUCT_Type * base)876 __STATIC_INLINE void Cy_MCWDT_Lock(MCWDT_STRUCT_Type *base)
877 {
878 uint32_t interruptState;
879
880 interruptState = Cy_SysLib_EnterCriticalSection();
881 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
882 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, CY_MCWDT_LOCK_SET01);
883 #else
884 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_SET01);
885 #endif
886
887 Cy_SysLib_ExitCriticalSection(interruptState);
888 }
889
890
891 /*******************************************************************************
892 * Function Name: Cy_MCWDT_Unlock
893 ****************************************************************************//**
894 *
895 * Unlocks the MCWDT configuration registers.
896 *
897 * \param base
898 * The base pointer to a structure that describes registers.
899 *
900 *******************************************************************************/
Cy_MCWDT_Unlock(MCWDT_STRUCT_Type * base)901 __STATIC_INLINE void Cy_MCWDT_Unlock(MCWDT_STRUCT_Type *base)
902 {
903 uint32_t interruptState;
904
905 interruptState = Cy_SysLib_EnterCriticalSection();
906 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
907 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
908 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
909 #else
910 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR0);
911 MCWDT_LOCK(base) = _CLR_SET_FLD32U(MCWDT_LOCK(base), MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK, (uint32_t)CY_MCWDT_LOCK_CLR1);
912 #endif
913 Cy_SysLib_ExitCriticalSection(interruptState);
914 }
915
916
917 /*******************************************************************************
918 * Function Name: Cy_MCWDT_GetLockStatus
919 ****************************************************************************//**
920 *
921 * Reports the locked/unlocked state of the MCWDT.
922 *
923 * \param base
924 * The base pointer to a structure that describes registers.
925 *
926 * \return
927 * The state of the MCWDT counter: 0 = unlocked, 1 = locked.
928 *
929 *******************************************************************************/
Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const * base)930 __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
931 {
932 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
933 return ((0UL !=_FLD2VAL(MCWDT_LOCK_MCWDT_LOCK, MCWDT_LOCK(base))) ? 1UL : 0UL);
934 #else
935 return ((0UL != (MCWDT_LOCK(base) & MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk)) ? 1UL : 0UL);
936 #endif
937 }
938
939
940 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2)) || defined (CY_IP_MXS22SRSS)
941
942 /*******************************************************************************
943 * Function Name: Cy_MCWDT_SetMode
944 ****************************************************************************//**
945 *
946 * Sets the mode of the specified counter.
947 *
948 * \param base
949 * The base pointer to a structure that describes registers.
950 *
951 * \param counter
952 * The number of the WDT counter. The valid range is [0-2].
953 *
954 * \param mode
955 * The mode of operation for the counter. See enum typedef cy_en_mcwdtmode_t.
956 *
957 * \note
958 * The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
959 *
960 * \note
961 * This API must not be called while the counters are running.
962 * Prior to calling this API, the counter must be disabled.
963 *
964 * \note
965 * This API is available for CAT1A, CAT1B and CAT1D devices.
966 *
967 *******************************************************************************/
Cy_MCWDT_SetMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,cy_en_mcwdtmode_t mode)968 __STATIC_INLINE void Cy_MCWDT_SetMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, cy_en_mcwdtmode_t mode)
969 {
970 uint32_t mask, shift;
971
972 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
973 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode));
974
975 shift = CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter);
976 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
977 mask = mask << shift;
978
979 MCWDT_CONFIG(base) = (MCWDT_CONFIG(base) & ~mask) | ((uint32_t) mode << shift);
980 }
981
982
983 /*******************************************************************************
984 * Function Name: Cy_MCWDT_GetMode
985 ****************************************************************************//**
986 *
987 * Reports the mode of the specified counter.
988 *
989 * \param base
990 * The base pointer to a structure that describes registers.
991 *
992 * \param counter
993 * The number of the WDT counter. The valid range is [0-2].
994 *
995 * \return
996 * The current mode of the counter. See enum typedef cy_en_mcwdtmode_t.
997 *
998 * \note
999 * This API is available for CAT1A, CAT1B and CAT1D devices.
1000 *
1001 *******************************************************************************/
Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1002 __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1003 {
1004 uint32_t mode, mask;
1005
1006 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1007
1008 mask = (counter == CY_MCWDT_COUNTER2) ? CY_MCWDT_C2_MODE_MASK : CY_MCWDT_C0C1_MODE_MASK;
1009 mode = (MCWDT_CONFIG(base) >> (CY_MCWDT_BYTE_SHIFT * ((uint32_t)counter))) & mask;
1010
1011 return ((cy_en_mcwdtmode_t) mode);
1012 }
1013
1014
1015 /*******************************************************************************
1016 * Function Name: Cy_MCWDT_SetClearOnMatch
1017 ****************************************************************************//**
1018 *
1019 * Sets the Clear on match option for the specified counter.
1020 *
1021 * \param base
1022 * The base pointer to a structure that describes registers.
1023 *
1024 * \param counter
1025 * The number of the WDT counter. The valid range is [0-1].
1026 *
1027 * \note
1028 * The match values are not supported by Counter 2.
1029 *
1030 * \param enable
1031 * Set 0 to disable; 1 to enable.
1032 *
1033 * \note
1034 * This API must not be called while the counters are running.
1035 * Prior to calling this API, the counter must be disabled.
1036 *
1037 * \note
1038 * This API is available for CAT1A, CAT1B and CAT1D devices.
1039 *
1040 *******************************************************************************/
Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t enable)1041 __STATIC_INLINE void Cy_MCWDT_SetClearOnMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t enable)
1042 {
1043 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1044 CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable));
1045
1046 if (CY_MCWDT_COUNTER0 == counter)
1047 {
1048 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, enable);
1049 }
1050 else
1051 {
1052 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, enable);
1053 }
1054 }
1055
1056
1057 /*******************************************************************************
1058 * Function Name: Cy_MCWDT_GetClearOnMatch
1059 ****************************************************************************//**
1060 *
1061 * Reports the Clear on match setting for the specified counter.
1062 *
1063 * \param base
1064 * The base pointer to a structure that describes registers.
1065 *
1066 * \param counter
1067 * The number of the WDT counter. The valid range is [0-1].
1068 *
1069 * \return
1070 * The Clear on match status: 1 = enabled, 0 = disabled.
1071 *
1072 * \note
1073 * The match value is not supported by Counter 2.
1074 *
1075 * \note
1076 * This API is available for CAT1A, CAT1B and CAT1D devices.
1077 *
1078 *******************************************************************************/
Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1079 __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1080 {
1081 uint32_t getClear;
1082
1083 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1084
1085 if (CY_MCWDT_COUNTER0 == counter)
1086 {
1087 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, MCWDT_CONFIG(base));
1088 }
1089 else
1090 {
1091 getClear = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, MCWDT_CONFIG(base));
1092 }
1093
1094 return (getClear);
1095 }
1096
1097
1098 /*******************************************************************************
1099 * Function Name: Cy_MCWDT_SetCascade
1100 ****************************************************************************//**
1101 *
1102 * Sets all the counter cascade options.
1103 *
1104 * \param base
1105 * The base pointer to a structure that describes registers.
1106 *
1107 * \param cascade
1108 * Sets or clears each of the cascade options.
1109 *
1110 * \note
1111 * This API must not be called when the counters are running.
1112 * Prior to calling this API, the counter must be disabled.
1113 *
1114 * \note
1115 * This API is available for CAT1A, CAT1B and CAT1D devices.
1116 *
1117 *******************************************************************************/
Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t cascade)1118 __STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
1119 {
1120 CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
1121
1122 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
1123 (uint32_t) cascade);
1124 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
1125 ((uint32_t) cascade >> 1u));
1126 }
1127
1128 /*******************************************************************************
1129 * Function Name: Cy_MCWDT_GetCascade
1130 ****************************************************************************//**
1131 *
1132 * Reports all the counter cascade option settings.
1133 *
1134 * \param base
1135 * The base pointer to a structure that describes registers.
1136 *
1137 * \return
1138 * The current cascade option values.
1139 *
1140 * \note
1141 * This API is available for CAT1A, CAT1B and CAT1D devices.
1142 *
1143 *******************************************************************************/
Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const * base)1144 __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const *base)
1145 {
1146 uint32_t cascade;
1147
1148 cascade = (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2, MCWDT_CONFIG(base)) << 1u) |
1149 _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1, MCWDT_CONFIG(base));
1150
1151 return ((cy_en_mcwdtcascade_t) cascade);
1152 }
1153
1154 /*******************************************************************************
1155 * Function Name: Cy_MCWDT_SetMatch
1156 ****************************************************************************//**
1157 *
1158 * Sets the match comparison value for the specified counter (0 or 1).
1159 *
1160 * \param base
1161 * The base pointer to a structure that describes registers.
1162 *
1163 * \param counter
1164 * The number of the WDT counter. The valid range is [0-1].
1165 *
1166 * \param match
1167 * The value to match against the counter.
1168 * The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
1169 * and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
1170 *
1171 * \note
1172 * The match value is not supported by Counter 2.
1173 *
1174 * \note
1175 * Action on match is taken on the next increment after the counter value
1176 * equal to match value.
1177 *
1178 * \param waitUs
1179 * The function waits for some delay in microseconds before returning,
1180 * because the match affects after two lf_clk cycles pass. The recommended
1181 * value is 93 us.
1182 * \note
1183 * Setting this parameter to a zero means No wait. This must be taken
1184 * into account when changing the match values on the running counters.
1185 *
1186 * \note
1187 * This API is available for CAT1A, CAT1B and CAT1D devices.
1188 *
1189 *******************************************************************************/
Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type * base,cy_en_mcwdtctr_t counter,uint32_t match,uint16_t waitUs)1190 __STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
1191 {
1192 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1193 CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? \
1194 ((MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) : \
1195 ((MCWDT_CONFIG(base) & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U), \
1196 match));
1197
1198 MCWDT_MATCH(base) = (counter == CY_MCWDT_COUNTER0) ?
1199 _CLR_SET_FLD32U(MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0,
1200 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk)) :
1201 _CLR_SET_FLD32U(MCWDT_MATCH(base), MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1,
1202 (match & MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk));
1203
1204 Cy_SysLib_DelayUs(waitUs);
1205 }
1206
1207
1208 /*******************************************************************************
1209 * Function Name: Cy_MCWDT_GetMatch
1210 ****************************************************************************//**
1211 *
1212 * Reports the match comparison value for the specified counter (0 or 1).
1213 *
1214 * \param base
1215 * The base pointer to a structure that describes registers.
1216 *
1217 * \param counter
1218 * The number of the WDT counter. The valid range is [0-1].
1219 *
1220 * \note
1221 * The match values are not supported by Counter 2.
1222 *
1223 * \return
1224 * A 16-bit match value.
1225 *
1226 * \note
1227 * This API is available for CAT1A, CAT1B and CAT1D devices.
1228 *
1229 *******************************************************************************/
Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1230 __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1231 {
1232 uint32_t match;
1233
1234 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1235
1236 match = (counter == CY_MCWDT_COUNTER0) ? _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, MCWDT_MATCH(base)) :
1237 _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, MCWDT_MATCH(base));
1238
1239 return (match);
1240 }
1241 #endif /* (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION < 2) || defined (CY_IP_MXS22SRSS) */
1242
1243 /*******************************************************************************
1244 * Function Name: Cy_MCWDT_SetToggleBit
1245 ****************************************************************************//**
1246 *
1247 * Sets a bit in Counter 2 to monitor for a toggle.
1248 *
1249 * \param base
1250 * The base pointer to a structure that describes registers.
1251 *
1252 * \param bit
1253 * The Counter 2 bit is set to monitor for a toggle. The valid range [0-31].
1254 *
1255 * \note
1256 * This API must not be called when counters are running.
1257 * Prior to calling this API, the counter must be disabled.
1258 *
1259 *******************************************************************************/
Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type * base,uint32_t bit)1260 __STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
1261 {
1262 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
1263 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
1264 MCWDT_CTR2_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CTR2_CONFIG(base), MCWDT_CTR2_CONFIG_BITS, bit);
1265 #else
1266 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
1267 #endif
1268 }
1269
1270
1271 /*******************************************************************************
1272 * Function Name: Cy_MCWDT_GetToggleBit
1273 ****************************************************************************//**
1274 *
1275 * Reports which bit in Counter 2 is monitored for a toggle.
1276 *
1277 * \param base
1278 * The base pointer to a structure that describes registers.
1279 *
1280 * \return
1281 * The bit that is monitored (range 0 to 31).
1282 *
1283 *******************************************************************************/
Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const * base)1284 __STATIC_INLINE uint32_t Cy_MCWDT_GetToggleBit(MCWDT_STRUCT_Type const *base)
1285 {
1286 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
1287 return (uint32_t)(_FLD2VAL(MCWDT_CTR2_CONFIG_BITS, MCWDT_CTR2_CONFIG(base)));
1288 #else
1289 return (_FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, MCWDT_CONFIG(base)));
1290 #endif
1291 }
1292
1293
1294 /*******************************************************************************
1295 * Function Name: Cy_MCWDT_GetCount
1296 ****************************************************************************//**
1297 *
1298 * Reports the current counter value of the specified counter.
1299 *
1300 * \param base
1301 * The base pointer to a structure that describes registers.
1302 *
1303 * \param counter
1304 * The number of the WDT counter. The valid range is [0-2].
1305 *
1306 * \return
1307 * A live counter value. Counters 0 and 1 are 16-bit counters and Counter 2 is
1308 * a 32-bit counter.
1309 *
1310 *******************************************************************************/
Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const * base,cy_en_mcwdtctr_t counter)1311 __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_mcwdtctr_t counter)
1312 {
1313 uint32_t countVal = 0u;
1314
1315 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
1316
1317 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
1318 switch (counter)
1319 {
1320 case CY_MCWDT_COUNTER0:
1321 countVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_CNT_CNT, MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER0)));
1322 break;
1323 case CY_MCWDT_COUNTER1:
1324 countVal = (uint16_t)(_FLD2VAL(MCWDT_CTR_CNT_CNT, MCWDT_CTR_CNT(base, CY_MCWDT_COUNTER1)));
1325 break;
1326 case CY_MCWDT_COUNTER2:
1327 countVal = (_FLD2VAL(MCWDT_CTR2_CNT_CNT2, MCWDT_CTR2_CNT(base)));
1328 break;
1329 default:
1330 CY_ASSERT(0u != 0u);
1331 break;
1332 }
1333
1334 #else
1335
1336 switch (counter)
1337 {
1338 case CY_MCWDT_COUNTER0:
1339 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0, MCWDT_CNTLOW(base));
1340 break;
1341 case CY_MCWDT_COUNTER1:
1342 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1, MCWDT_CNTLOW(base));
1343 break;
1344 case CY_MCWDT_COUNTER2:
1345 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2, MCWDT_CNTHIGH(base));
1346 break;
1347 default:
1348 CY_ASSERT(0u != 0u);
1349 break;
1350 }
1351 #endif
1352
1353 return (countVal);
1354 }
1355
1356
1357 /*******************************************************************************
1358 * Function Name: Cy_MCWDT_ResetCounters
1359 ****************************************************************************//**
1360 *
1361 * Resets all specified counters.
1362 *
1363 * \param base
1364 * The base pointer to a structure that describes registers.
1365 *
1366 * \param counters
1367 * OR of all counters to reset. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1368 * CY_MCWDT_CTR2 macros.
1369 *
1370 * \param waitUs
1371 * The function waits for some delay in microseconds before returning, because
1372 * a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
1373 * \note This function resets the counters two times to prevent the case when
1374 * the Counter 1 is not reset when the counters are cascaded. The delay waitUs
1375 * must be greater than 100 us when the counters are cascaded.
1376 * The total delay is greater than 2*waitUs because the function has
1377 * the delay after the first reset.
1378 * \note
1379 * Setting this parameter to a zero means No wait. In this case, it is the
1380 * user's responsibility to check whether the selected counters were reset
1381 * immediately after the function call. This can be done by the
1382 * Cy_MCWDT_GetCount() API.
1383 *
1384 * \note
1385 * For CAT1C and TVIIBE devices, only CY_MCWDT_CTR0 and CY_MCWDT_CTR1 can be Reset.
1386 *
1387 *******************************************************************************/
Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type * base,uint32_t counters,uint16_t waitUs)1388 __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t counters, uint16_t waitUs)
1389 {
1390 #if (defined (CY_IP_MXS40SRSS) && (CY_IP_MXS40SRSS_VERSION >= 2))
1391 if (0UL != (counters & CY_MCWDT_CTR0))
1392 {
1393 MCWDT_SERVICE(base) |= MCWDT_SERVICE_CTR0_SERVICE_Msk;
1394 }
1395 if (0UL != (counters & CY_MCWDT_CTR1))
1396 {
1397 MCWDT_SERVICE(base) |= MCWDT_SERVICE_CTR1_SERVICE_Msk;
1398 }
1399
1400 #else
1401
1402 uint32_t resetCounters;
1403
1404 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1405
1406 /* Extract particular counters for reset */
1407 resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
1408 ((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
1409 ((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
1410
1411 MCWDT_CTL(base) |= resetCounters;
1412
1413 Cy_SysLib_DelayUs(waitUs);
1414
1415 MCWDT_CTL(base) |= resetCounters;
1416 #endif
1417
1418 Cy_SysLib_DelayUs(waitUs);
1419 }
1420
1421
1422 /*******************************************************************************
1423 * Function Name: Cy_MCWDT_GetInterruptStatus
1424 ****************************************************************************//**
1425 *
1426 * Reports the state of all MCWDT interrupts.
1427 *
1428 * \param base
1429 * The base pointer to a structure that describes registers.
1430 *
1431 * \return
1432 * The OR'd state of the interrupts. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1433 * CY_MCWDT_CTR2 macros.
1434 *
1435 *******************************************************************************/
Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const * base)1436 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *base)
1437 {
1438 return (MCWDT_INTR(base));
1439 }
1440
1441
1442 /*******************************************************************************
1443 * Function Name: Cy_MCWDT_ClearInterrupt
1444 ****************************************************************************//**
1445 *
1446 * Clears all specified MCWDT interrupts.
1447 *
1448 * All the WDT interrupts must be cleared by the firmware; otherwise
1449 * interrupts are generated continuously.
1450 *
1451 * \param base
1452 * The base pointer to a structure describes registers.
1453 *
1454 * \param counters
1455 * OR of all interrupt sources to clear. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1456 * CY_MCWDT_CTR2 macros.
1457 *
1458 *******************************************************************************/
Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1459 __STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1460 {
1461 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1462
1463 MCWDT_INTR(base) = counters;
1464 /* This dummy reading is necessary here. It provides a guarantee that interrupt is cleared at returning from this function. */
1465 (void) MCWDT_INTR(base);
1466 }
1467
1468
1469 /*******************************************************************************
1470 * Function Name: Cy_MCWDT_SetInterrupt
1471 ****************************************************************************//**
1472 *
1473 * Sets MCWDT interrupt sources in the interrupt request register.
1474 *
1475 * \param base
1476 * The base pointer to a structure that describes registers.
1477 *
1478 * \param counters
1479 * OR of all interrupt sources to set. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1480 * CY_MCWDT_CTR2 macros.
1481 *
1482 *******************************************************************************/
Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type * base,uint32_t counters)1483 __STATIC_INLINE void Cy_MCWDT_SetInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
1484 {
1485 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1486
1487 MCWDT_INTR_SET(base) = counters;
1488 }
1489
1490
1491 /*******************************************************************************
1492 * Function Name: Cy_MCWDT_GetInterruptMask
1493 ****************************************************************************//**
1494 *
1495 * Returns the CWDT interrupt mask register. This register specifies which bits
1496 * from the MCWDT interrupt request register will trigger an interrupt event.
1497 *
1498 * \param base
1499 * The base pointer to a structure that describes registers.
1500 *
1501 * \return
1502 * The OR'd state of the interrupt masks. See the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1503 * CY_MCWDT_CTR2 macros.
1504 *
1505 *******************************************************************************/
Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const * base)1506 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base)
1507 {
1508 return (MCWDT_INTR_MASK(base));
1509 }
1510
1511
1512 /*******************************************************************************
1513 * Function Name: Cy_MCWDT_SetInterruptMask
1514 ****************************************************************************//**
1515 *
1516 * Writes MCWDT interrupt mask register. This register configures which bits
1517 * from MCWDT interrupt request register will trigger an interrupt event.
1518 *
1519 * \param base
1520 * The base pointer to a structure that describes registers.
1521 *
1522 * \param counters
1523 * OR of all interrupt masks to set. See \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and
1524 * CY_MCWDT_CTR2 macros.
1525 *
1526 *******************************************************************************/
Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type * base,uint32_t counters)1527 __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
1528 {
1529 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
1530
1531 MCWDT_INTR_MASK(base) = counters;
1532 }
1533
1534
1535 /*******************************************************************************
1536 * Function Name: Cy_MCWDT_GetInterruptStatusMasked
1537 ****************************************************************************//**
1538 *
1539 * Returns the MCWDT interrupt masked request register. This register contains
1540 * the logical AND of corresponding bits from the MCWDT interrupt request and
1541 * mask registers.
1542 * In the interrupt service routine, this function identifies which of the
1543 * enabled MCWDT interrupt sources caused an interrupt event.
1544 *
1545 * \param base
1546 * The base pointer to a structure that describes registers.
1547 *
1548 * \return
1549 * The current status of enabled MCWDT interrupt sources. See
1550 * the \ref CY_MCWDT_CTR0, CY_MCWDT_CTR1, and CY_MCWDT_CTR2 macros.
1551 *
1552 *******************************************************************************/
Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const * base)1553 __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatusMasked(MCWDT_STRUCT_Type const *base)
1554 {
1555 return (MCWDT_INTR_MASKED(base));
1556 }
1557
1558 #if defined (CY_IP_MXS28SRSS) || defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS)
1559 /*******************************************************************************
1560 * Function Name: Cy_MCWDT_SetLowerLimit
1561 ****************************************************************************//**
1562 *
1563 * Sets the lower limit value for the specified counter (0 or 1).
1564 *
1565 * \param base
1566 * The base pointer to a structure that describes registers.
1567 *
1568 * \param counter
1569 * The number of the WDT counter. The valid range is [0-1].
1570 *
1571 * \param lowerLimit
1572 * The value to be written in the lower limit register
1573 * The valid range is [0-65535] for c0
1574 * and [1-65535] for c1.
1575 *
1576 * \note
1577 * The lower limit mode is not supported by Counter 2.
1578 *
1579 * \param waitUs
1580 * The function waits for some delay in microseconds before returning,
1581 * because the lower limit register write affects after two lf_clk cycles pass.
1582 * The recommended value is 93 us.
1583 * \note
1584 * Setting this parameter to a zero means No wait. This must be taken
1585 * into account when changing the lower limit register values.
1586 *
1587 * \note
1588 * This API is available for CAT1B and CAT1D devices.
1589 *
1590 *******************************************************************************/
Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,uint32_t lowerLimit,uint16_t waitUs)1591 __STATIC_INLINE void Cy_MCWDT_SetLowerLimit(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, uint32_t lowerLimit, uint16_t waitUs)
1592 {
1593 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1594
1595 MCWDT_LOWER_LIMIT(base) = (counter == CY_MCWDT_LOWER_LIMIT0) ?
1596 _CLR_SET_FLD32U(MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0,
1597 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk)) :
1598 _CLR_SET_FLD32U(MCWDT_LOWER_LIMIT(base), MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1,
1599 (lowerLimit & MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0_Msk));
1600
1601 Cy_SysLib_DelayUs(waitUs);
1602 }
1603
1604 /*******************************************************************************
1605 * Function Name: Cy_MCWDT_GetLowerLimit
1606 ****************************************************************************//**
1607 *
1608 * Reports the Lower Limit value of the specified counter.
1609 *
1610 * \param base
1611 * The base pointer to a structure that describes registers.
1612 *
1613 * \param counter
1614 * The number of the WDT counter. The valid range is [0-1].
1615 *
1616 * \return
1617 * A Lower Limit value. Counters 0 and 1 are 16-bit counters.
1618 *
1619 * \note
1620 * This API is available for CAT1B and CAT1D devices.
1621 *
1622 *******************************************************************************/
Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1623 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimit(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1624 {
1625 uint32_t countVal = 0u;
1626
1627 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1628
1629 switch (counter)
1630 {
1631 case CY_MCWDT_LOWER_LIMIT0:
1632 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT0, MCWDT_LOWER_LIMIT(base));
1633 break;
1634 case CY_MCWDT_LOWER_LIMIT1:
1635 countVal = _FLD2VAL(MCWDT_STRUCT_MCWDT_LOWER_LIMIT_WDT_LOWER_LIMIT1, MCWDT_LOWER_LIMIT(base));
1636 break;
1637 default:
1638 CY_ASSERT(0u != 0u);
1639 break;
1640 }
1641
1642 return (countVal);
1643 }
1644
1645 /*******************************************************************************
1646 * Function Name: Cy_MCWDT_SetLowerLimitMode
1647 ****************************************************************************//**
1648 *
1649 * Sets the lower limit mode option for the specified counter.
1650 *
1651 * \param base
1652 * The base pointer to a structure that describes registers.
1653 *
1654 * \param counter
1655 * The number of the WDT counter. The valid range is [0-1].
1656 *
1657 * \note
1658 * The lower limit mode is not supported by Counter 2.
1659 *
1660 * \param mode
1661 * Set 0 - Do nothing, 1 - Assert WDT_INTx, 2 - Assert WDT Reset
1662 *
1663 * \note
1664 * This API must not be called while the counters are running.
1665 * Prior to calling this API, the counter must be disabled.
1666 * This API is available for CAT1B and CAT1D devices.
1667 *
1668 *******************************************************************************/
Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type * base,cy_en_mcwdtlowerlimit_t counter,cy_en_mcwdtlowerlimitmode_t mode)1669 __STATIC_INLINE void Cy_MCWDT_SetLowerLimitMode(MCWDT_STRUCT_Type *base, cy_en_mcwdtlowerlimit_t counter, cy_en_mcwdtlowerlimitmode_t mode)
1670 {
1671 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1672 CY_ASSERT_L2(CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode));
1673
1674 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1675 {
1676 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, mode);
1677 }
1678 else
1679 {
1680 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, mode);
1681 }
1682 }
1683
1684 /*******************************************************************************
1685 * Function Name: Cy_MCWDT_GetLowerLimitMode
1686 ****************************************************************************//**
1687 *
1688 * Reports the lower limit mode of the specified counter.
1689 *
1690 * \param base
1691 * The base pointer to a structure that describes registers.
1692 *
1693 * \param counter
1694 * The number of the WDT counter. The valid range is [0-1].
1695 *
1696 * \return
1697 * The current lower limit mode of the counter. See enum typedef cy_en_mcwdtlowerlimitmode_t.
1698 *
1699 * \note
1700 * This API is available for CAT1B and CAT1D devices.
1701 *
1702 *******************************************************************************/
Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const * base,cy_en_mcwdtlowerlimit_t counter)1703 __STATIC_INLINE cy_en_mcwdtlowerlimitmode_t Cy_MCWDT_GetLowerLimitMode(MCWDT_STRUCT_Type const *base, cy_en_mcwdtlowerlimit_t counter)
1704 {
1705 uint32_t getLowerLimitMode;
1706
1707 CY_ASSERT_L3(CY_MCWDT_IS_LOWER_LIMIT_VALID(counter));
1708
1709 if (CY_MCWDT_LOWER_LIMIT0 == counter)
1710 {
1711 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE0, MCWDT_CONFIG(base));
1712 }
1713 else
1714 {
1715 getLowerLimitMode = _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_LOWER_MODE1, MCWDT_CONFIG(base));
1716 }
1717
1718 return (cy_en_mcwdtlowerlimitmode_t)getLowerLimitMode;
1719
1720 }
1721
1722 /*******************************************************************************
1723 * Function Name: Cy_MCWDT_GetLowerLimitCascaded
1724 ****************************************************************************//**
1725 *
1726 * Gets lower limit registers cascaded value.
1727 *
1728 * \param base
1729 * The base pointer to a structure that describes registers.
1730 *
1731 * \note
1732 * The lower limit mode is not supported by Counter 2.
1733 *
1734 * \return
1735 * A 32-bit lower limit register value.
1736 *
1737 * \note
1738 * This API is available for CAT1B and CAT1D devices.
1739 *
1740 *******************************************************************************/
Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const * base)1741 __STATIC_INLINE uint32_t Cy_MCWDT_GetLowerLimitCascaded(MCWDT_STRUCT_Type const *base)
1742 {
1743 return (uint32_t)(MCWDT_LOWER_LIMIT(base));
1744 }
1745 #endif /* CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS ,CY_IP_MXS22SRSS*/
1746
1747 #if defined (CY_IP_MXS40SSRSS) || defined (CY_IP_MXS22SRSS) || defined (CY_DOXYGEN)
1748
1749 /*******************************************************************************
1750 * Function Name: Cy_MCWDT_SetCascadeCarryOutRollOver
1751 ****************************************************************************//**
1752 *
1753 * Enables the Rollover mode for carryout.
1754 *
1755 * \param base
1756 * The base pointer to a structure that describes registers.
1757 *
1758 * \param counter
1759 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1760 *
1761 * \param carryoutconfig
1762 * For CY_MCWDT_CASCADE_C0C1:
1763 * FALSE: carry out on counter 0 match
1764 * TRUE: carry out on counter 0 rollover.
1765 * For CY_MCWDT_CASCADE_C1C2:
1766 * FALSE: carry out on counter 1 match
1767 * TRUE: carry out on counter 1 rollover.
1768 *
1769 * \note
1770 * This API is available for CAT1B and CAT1D devices.
1771 *
1772 *******************************************************************************/
Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,bool carryoutconfig)1773 __STATIC_INLINE void Cy_MCWDT_SetCascadeCarryOutRollOver(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool carryoutconfig)
1774 {
1775 CY_ASSERT_L3(CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(counter));
1776
1777 if (CY_MCWDT_CASCADE_C0C1 == counter)
1778 {
1779 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, carryoutconfig);
1780 }
1781 else
1782 {
1783 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, carryoutconfig);
1784 }
1785 }
1786
1787 /*******************************************************************************
1788 * Function Name: Cy_MCWDT_GetCascadeCarryOutModeRollOver
1789 ****************************************************************************//**
1790 *
1791 * Checks if Rollover mode enabled for carryout or not.
1792 *
1793 * \param base
1794 * The base pointer to a structure that describes registers.
1795 *
1796 * \param counter
1797 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1798 *
1799 * \return
1800 * True : Rollover Enabled
1801 * False : Rollover Disabled
1802 *
1803 * \note
1804 * This API is available for CAT1B and CAT1D devices.
1805 *
1806 *******************************************************************************/
Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1807 __STATIC_INLINE bool Cy_MCWDT_GetCascadeCarryOutRollOver(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1808 {
1809 bool countVal = false;
1810
1811 CY_ASSERT_L3(CY_MCWDT_IS_CARRYMODE_CASCADE_VALID(counter));
1812
1813 switch (counter)
1814 {
1815 case CY_MCWDT_CASCADE_C0C1:
1816 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY0_1, MCWDT_CONFIG(base));
1817 break;
1818 case CY_MCWDT_CASCADE_C1C2:
1819 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CARRY1_2, MCWDT_CONFIG(base));
1820 break;
1821 default:
1822 CY_ASSERT(0u != 0u);
1823 break;
1824 }
1825
1826 return (countVal);
1827 }
1828
1829 /*******************************************************************************
1830 * Function Name: Cy_MCWDT_SetCascadeMatchCombined
1831 ****************************************************************************//**
1832 *
1833 * Sets the match to combined cascade counters.
1834 *
1835 * \param base
1836 * The base pointer to a structure that describes registers.
1837 *
1838 * \param counter
1839 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1840 *
1841 * \param matchconfig
1842 * For CY_MCWDT_CASCADE_C0C1:
1843 * FALSE: Match based on counter 1 alone
1844 * TRUE: Match based on counter 1 and counter 0 matching simultaneously
1845 * For CY_MCWDT_CASCADE_C1C2:
1846 * FALSE: Match based on counter 2 alone
1847 * TRUE: Match based on counter 2 and counter 1 matching simultaneously
1848 *
1849 * \note
1850 * This API is available for CAT1B and CAT1D devices.
1851 *
1852 *******************************************************************************/
Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type * base,cy_en_mcwdtcascade_t counter,bool matchconfig)1853 __STATIC_INLINE void Cy_MCWDT_SetCascadeMatchCombined(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t counter, bool matchconfig)
1854 {
1855 if (CY_MCWDT_CASCADE_C0C1 == counter)
1856 {
1857 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, matchconfig);
1858 }
1859 else
1860 {
1861 MCWDT_CONFIG(base) = _CLR_SET_FLD32U(MCWDT_CONFIG(base), MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, matchconfig);
1862 }
1863 }
1864
1865 /*******************************************************************************
1866 * Function Name: Cy_MCWDT_GetCascadeMatchModeCombined
1867 ****************************************************************************//**
1868 *
1869 * Reports if match is enabled with combined cascade counters or not.
1870 *
1871 * \param base
1872 * The base pointer to a structure that describes registers.
1873 *
1874 * \param counter
1875 * The cascaded counter type. The valid cascaded type is either C0C1 or C1C2.
1876 *
1877 * \return
1878 * True : Combined match is enabled
1879 * False : Combined match is disabled.
1880 *
1881 * \note
1882 * This API is available for CAT1B and CAT1D devices.
1883 *
1884 *******************************************************************************/
Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const * base,cy_en_mcwdtcascade_t counter)1885 __STATIC_INLINE bool Cy_MCWDT_GetCascadeMatchCombined(MCWDT_STRUCT_Type const *base, cy_en_mcwdtcascade_t counter)
1886 {
1887 bool countVal = false;
1888
1889 switch (counter)
1890 {
1891 case CY_MCWDT_CASCADE_C0C1:
1892 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH0_1, MCWDT_CONFIG(base));
1893 break;
1894 case CY_MCWDT_CASCADE_C1C2:
1895 countVal = _FLD2BOOL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MATCH1_2, MCWDT_CONFIG(base));
1896 break;
1897 default:
1898 CY_ASSERT(0u != 0u);
1899 break;
1900 }
1901
1902 return (countVal);
1903 }
1904
1905 #endif /* CY_IP_MXS40SSRSS,CY_IP_MXS22SRSS */
1906
1907
1908 /** \} group_mcwdt_functions */
1909
1910 #endif /* CY_IP_MXS40SRSS_MCWDT, CY_IP_MXS28SRSS, CY_IP_MXS40SSRSS, CY_IP_MXS22SRSS */
1911
1912 #if defined(__cplusplus)
1913 }
1914 #endif
1915
1916 #endif /* CY_MCWDT_H */
1917
1918 /** \} group_mcwdt */
1919
1920 /* [] END OF FILE */
1921
