1 /*
2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /***********************************************************************************************************************
8 * Includes <System Includes> , "Project Includes"
9 **********************************************************************************************************************/
10 #include "bsp_clocks.h"
11
12 #if BSP_TZ_NONSECURE_BUILD
13 #include "bsp_guard.h"
14 #endif
15
16 /***********************************************************************************************************************
17 * Macro definitions
18 **********************************************************************************************************************/
19
20 /* The number of clocks is used to size the g_clock_freq array. */
21 #define BSP_PRV_NUM_CLOCKS (FSP_PRIV_CLOCK_NUM)
22
23 /***********************************************************************************************************************
24 * Typedef definitions
25 **********************************************************************************************************************/
26
27 /***********************************************************************************************************************
28 * Exported global variables (to be accessed by other files)
29 **********************************************************************************************************************/
30
31 /***********************************************************************************************************************
32 * Private global variables and functions
33 **********************************************************************************************************************/
34 static void bsp_prv_clock_pre_setting(fsp_priv_clock_t clock);
35 static void bsp_prv_clock_post_setting(fsp_priv_clock_t clock);
36 void bsp_prv_clock_selector_set(fsp_priv_clock_t clock, uint32_t clock_sel);
37 void bsp_prv_clock_divider_set(fsp_priv_clock_t clock, uint32_t clock_div);
38
39 /*******************************************************************************************************************//**
40 * @internal
41 * @addtogroup BSP_MCU_PRV Internal BSP Documentation
42 * @ingroup RENESAS_INTERNAL
43 * @{
44 **********************************************************************************************************************/
45
46 /* This array stores the clock frequency of each bus clock. This section of RAM should not be initialized by the C
47 * runtime environment. This is initialized and used in bsp_clock_init, which is called before the C runtime
48 * environment is initialized. */
49 static uint32_t g_clock_freq[BSP_PRV_NUM_CLOCKS] BSP_PLACE_IN_SECTION(BSP_SECTION_NOINIT);
50
51 /*******************************************************************************************************************//**
52 * Update SystemCoreClock variable based on current clock settings.
53 **********************************************************************************************************************/
SystemCoreClockUpdate(void)54 void SystemCoreClockUpdate (void)
55 {
56 SystemCoreClock = g_clock_freq[FSP_PRIV_CLOCK_I2CLK];
57 }
58
59 /*******************************************************************************************************************//**
60 * Initializes variable to store system clock frequencies.
61 **********************************************************************************************************************/
62 #if BSP_TZ_CFG_INIT_SECURE_ONLY
bsp_clock_freq_var_init(void)63 void bsp_clock_freq_var_init (void)
64 #else
65 static void bsp_clock_freq_var_init (void)
66 #endif
67 {
68 #if defined(BSP_CFG_CLOCK_ICLK_HZ)
69 g_clock_freq[FSP_PRIV_CLOCK_ICLK] = BSP_CFG_CLOCK_ICLK_HZ;
70 #endif
71 #if defined(BSP_CFG_CLOCK_I2CLK_HZ)
72 g_clock_freq[FSP_PRIV_CLOCK_I2CLK] = BSP_CFG_CLOCK_I2CLK_HZ;
73 #endif
74 #if defined(BSP_CFG_CLOCK_GCLK_HZ)
75 g_clock_freq[FSP_PRIV_CLOCK_GCLK] = BSP_CFG_CLOCK_GCLK_HZ;
76 #endif
77 #if defined(BSP_CFG_CLOCK_S0CLK_HZ)
78 g_clock_freq[FSP_PRIV_CLOCK_S0CLK] = BSP_CFG_CLOCK_S0CLK_HZ;
79 #endif
80 #if defined(BSP_CFG_CLOCK_SPI0CLK_HZ)
81 g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = BSP_CFG_CLOCK_SPI0CLK_HZ;
82 #endif
83 #if defined(BSP_CFG_CLOCK_SPI1CLK_HZ)
84 g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = BSP_CFG_CLOCK_SPI1CLK_HZ;
85 #endif
86 #if defined(BSP_CFG_CLOCK_SD0CLK_HZ)
87 g_clock_freq[FSP_PRIV_CLOCK_SD0CLK] = BSP_CFG_CLOCK_SD0CLK_HZ;
88 #endif
89 #if defined(BSP_CFG_CLOCK_SD1CLK_HZ)
90 g_clock_freq[FSP_PRIV_CLOCK_SD1CLK] = BSP_CFG_CLOCK_SD1CLK_HZ;
91 #endif
92 #if defined(BSP_CFG_CLOCK_M0CLK_HZ)
93 g_clock_freq[FSP_PRIV_CLOCK_M0CLK] = BSP_CFG_CLOCK_M0CLK_HZ;
94 #endif
95 #if defined(BSP_CFG_CLOCK_M1CLK_HZ)
96 g_clock_freq[FSP_PRIV_CLOCK_M1CLK] = BSP_CFG_CLOCK_M1CLK_HZ;
97 #endif
98 #if defined(BSP_CFG_CLOCK_M2CLK_HZ)
99 g_clock_freq[FSP_PRIV_CLOCK_M2CLK] = BSP_CFG_CLOCK_M2CLK_HZ;
100 #endif
101 #if defined(BSP_CFG_CLOCK_M3CLK_HZ)
102 g_clock_freq[FSP_PRIV_CLOCK_M3CLK] = BSP_CFG_CLOCK_M3CLK_HZ;
103 #endif
104 #if defined(BSP_CFG_CLOCK_M4CLK_HZ)
105 g_clock_freq[FSP_PRIV_CLOCK_M4CLK] = BSP_CFG_CLOCK_M4CLK_HZ;
106 #endif
107 #if defined(BSP_CFG_CLOCK_HPCLK_HZ)
108 g_clock_freq[FSP_PRIV_CLOCK_HPCLK] = BSP_CFG_CLOCK_HPCLK_HZ;
109 #endif
110 #if defined(BSP_CFG_CLOCK_TSUCLK_HZ)
111 g_clock_freq[FSP_PRIV_CLOCK_TSUCLK] = BSP_CFG_CLOCK_TSUCLK_HZ;
112 #endif
113 #if defined(BSP_CFG_CLOCK_ZTCLK_HZ)
114 g_clock_freq[FSP_PRIV_CLOCK_ZTCLK] = BSP_CFG_CLOCK_ZTCLK_HZ;
115 #endif
116 #if defined(BSP_CFG_CLOCK_P0CLK_HZ)
117 g_clock_freq[FSP_PRIV_CLOCK_P0CLK] = BSP_CFG_CLOCK_P0CLK_HZ;
118 #endif
119 #if defined(BSP_CFG_CLOCK_P1CLK_HZ)
120 g_clock_freq[FSP_PRIV_CLOCK_P1CLK] = BSP_CFG_CLOCK_P1CLK_HZ;
121 #endif
122 #if defined(BSP_CFG_CLOCK_P2CLK_HZ)
123 g_clock_freq[FSP_PRIV_CLOCK_P2CLK] = BSP_CFG_CLOCK_P2CLK_HZ;
124 #endif
125 #if defined(BSP_CFG_CLOCK_ATCLK_HZ)
126 g_clock_freq[FSP_PRIV_CLOCK_ATCLK] = BSP_CFG_CLOCK_ATCLK_HZ;
127 #endif
128 #if defined(BSP_CFG_CLOCK_OSCCLK_HZ)
129 g_clock_freq[FSP_PRIV_CLOCK_OSCCLK] = BSP_CFG_CLOCK_OSCCLK_HZ;
130 #endif
131 #if defined(BSP_CFG_CLOCK_I3CLK_HZ)
132 g_clock_freq[FSP_PRIV_CLOCK_I3CLK] = BSP_CFG_CLOCK_I3CLK_HZ;
133 #endif
134 #if defined(BSP_CFG_CLOCK_P3CLK_HZ)
135 g_clock_freq[FSP_PRIV_CLOCK_P3CLK] = BSP_CFG_CLOCK_P3CLK_HZ;
136 #endif
137 #if defined(BSP_CFG_CLOCK_P4CLK_HZ)
138 g_clock_freq[FSP_PRIV_CLOCK_P4CLK] = BSP_CFG_CLOCK_P4CLK_HZ;
139 #endif
140 #if defined(BSP_CFG_CLOCK_P5CLK_HZ)
141 g_clock_freq[FSP_PRIV_CLOCK_P5CLK] = BSP_CFG_CLOCK_P5CLK_HZ;
142 #endif
143 #if defined(BSP_CFG_CLOCK_SD2CLK_HZ)
144 g_clock_freq[FSP_PRIV_CLOCK_SD2CLK] = BSP_CFG_CLOCK_SD2CLK_HZ;
145 #endif
146 #if defined(BSP_CFG_CLOCK_OC0CLK_HZ)
147 g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = BSP_CFG_CLOCK_OC0CLK_HZ;
148 #endif
149 #if defined(BSP_CFG_CLOCK_OC1CLK_HZ)
150 g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = BSP_CFG_CLOCK_OC1CLK_HZ;
151 #endif
152 #if defined(BSP_CFG_CLOCK_OSCCLK2_HZ)
153 g_clock_freq[FSP_PRIV_CLOCK_OSCCLK2] = BSP_CFG_CLOCK_OSCCLK2_HZ;
154 #endif
155
156 /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */
157 SystemCoreClockUpdate();
158 }
159
160 /*******************************************************************************************************************//**
161 * Initializes system clocks. Makes no assumptions about current register settings.
162 **********************************************************************************************************************/
bsp_clock_init(void)163 void bsp_clock_init (void)
164 {
165 bsp_clock_freq_var_init();
166 }
167
168 /*******************************************************************************************************************//**
169 * Clock frequency configuration. According to the information specified in the Clocks tab, the divider and clock selector are initialized.
170 **********************************************************************************************************************/
bsp_clock_freq_init_cfg(void)171 void bsp_clock_freq_init_cfg (void)
172 {
173 #if BSP_FEATURE_BSP_CLOCK_FREQ_INIT_CFG_SUPPORT
174 uint32_t setting_value = 0;
175
176 /* Set CPG_PL1_DDIV to configure the frequency of ICLK. */
177 setting_value = (uint32_t) (BSP_CFG_DIVPL1_SET_DIV << R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Pos);
178 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U);
179 R_CPG->CPG_PL1_DDIV =
180 (uint32_t) (R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk | (R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Msk & setting_value));
181 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U);
182
183 /* Set CPG_PL2_DDIV to configure the frequency of P0CLK. */
184 setting_value = (uint32_t) (BSP_CFG_DIVPL2B_SET_DIV << R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Pos);
185 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U);
186 R_CPG->CPG_PL2_DDIV =
187 (uint32_t) (R_CPG_CPG_PL2_DDIV_DIV_PLL2_B_WEN_Msk | (R_CPG_CPG_PL2_DDIV_DIVPL2B_SET_Msk & setting_value));
188 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL2B_STS_Msk & R_CPG->CPG_CLKDIVSTATUS), 0U);
189
190 /* Set CPG_PL3_DDIV to configure the frequency of P1CLK, P2CLK and P3CLK. */
191 setting_value = (uint32_t) ((BSP_CFG_DIVPL3A_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Pos) |
192 (BSP_CFG_DIVPL3B_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Pos) |
193 (BSP_CFG_DIVPL3C_SET_DIV << R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Pos));
194 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Msk |
195 R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Msk) &
196 R_CPG->CPG_CLKDIVSTATUS),
197 0U);
198 R_CPG->CPG_PL3_DDIV =
199 (uint32_t) ((R_CPG_CPG_PL3_DDIV_DIV_PLL3_A_WEN_Msk | R_CPG_CPG_PL3_DDIV_DIV_PLL3_B_WEN_Msk |
200 R_CPG_CPG_PL3_DDIV_DIV_PLL3_C_WEN_Msk) |
201 ((R_CPG_CPG_PL3_DDIV_DIVPL3A_SET_Msk | R_CPG_CPG_PL3_DDIV_DIVPL3B_SET_Msk |
202 R_CPG_CPG_PL3_DDIV_DIVPL3C_SET_Msk) &
203 setting_value));
204 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL3A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL3B_STS_Msk |
205 R_CPG_CPG_CLKDIVSTATUS_DIVPL3C_STS_Msk) &
206 R_CPG->CPG_CLKDIVSTATUS),
207 0U);
208
209 /* Set CPG_PL6_DDIV to configure the frequency of I2CLK and I3CLK. */
210 setting_value = (uint32_t) ((BSP_CFG_DIVPL6A_SET_DIV << R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Pos) |
211 (BSP_CFG_DIVPL6B_SET_DIV << R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Pos));
212 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Msk) &
213 R_CPG->CPG_CLKDIVSTATUS),
214 0U);
215 R_CPG->CPG_PL6_DDIV =
216 (uint32_t) ((R_CPG_CPG_PL6_DDIV_DIV_PLL6_A_WEN_Msk | R_CPG_CPG_PL6_DDIV_DIV_PLL6_B_WEN_Msk) |
217 ((R_CPG_CPG_PL6_DDIV_DIVPL6A_SET_Msk | R_CPG_CPG_PL6_DDIV_DIVPL6B_SET_Msk) &
218 setting_value));
219 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVPL6A_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVPL6B_STS_Msk) &
220 R_CPG->CPG_CLKDIVSTATUS),
221 0U);
222
223 /* Set CPG_SDHI_DDIV and CPG_SDHI_DSEL to configure the frequency of SD0CLK, SD1CLK and SD2CLK. */
224 setting_value = (uint32_t) ((BSP_CFG_DIVSDHI0_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Pos) |
225 (BSP_CFG_DIVSDHI1_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Pos) |
226 (BSP_CFG_DIVSDHI2_SET_DIV << R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Pos));
227 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Msk |
228 R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Msk) &
229 R_CPG->CPG_CLKDIVSTATUS),
230 0U);
231 R_CPG->CPG_SDHI_DDIV =
232 (uint32_t) ((R_CPG_CPG_SDHI_DDIV_DIVSDHI0_WEN_Msk | R_CPG_CPG_SDHI_DDIV_DIVSDHI1_WEN_Msk |
233 R_CPG_CPG_SDHI_DDIV_DIVSDHI2_WEN_Msk) |
234 ((R_CPG_CPG_SDHI_DDIV_DIVSDHI0_SET_Msk | R_CPG_CPG_SDHI_DDIV_DIVSDHI1_SET_Msk |
235 R_CPG_CPG_SDHI_DDIV_DIVSDHI2_SET_Msk) &
236 setting_value));
237 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKDIVSTATUS_DIVSDHI0_STS_Msk | R_CPG_CPG_CLKDIVSTATUS_DIVSDHI1_STS_Msk |
238 R_CPG_CPG_CLKDIVSTATUS_DIVSDHI2_STS_Msk) &
239 R_CPG->CPG_CLKDIVSTATUS),
240 0U);
241
242 setting_value = (uint32_t) ((BSP_CFG_SEL_SDHI0_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Pos) |
243 (BSP_CFG_SEL_SDHI1_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Pos) |
244 (BSP_CFG_SEL_SDHI2_SET_SOURCE << R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Pos));
245 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk | R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk |
246 R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk) &
247 R_CPG->CPG_CLKSELSTATUS),
248 0U);
249 R_CPG->CPG_SDHI_DSEL =
250 (uint32_t) ((R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Msk | R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Msk |
251 R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Msk) |
252 ((R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Msk | R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Msk |
253 R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Msk) &
254 setting_value));
255 FSP_HARDWARE_REGISTER_WAIT(((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk | R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk |
256 R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk) &
257 R_CPG->CPG_CLKSELSTATUS),
258 0U);
259
260 /* Set CPG_PLL_DSEL to configure the frequency of S0CLK. */
261 setting_value = (uint32_t) (BSP_CFG_SELPL4_SET_SOURCE << R_CPG_CPG_PLL_DSEL_SELPL4_SET_Pos);
262 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Msk & R_CPG->CPG_CLKSELSTATUS), 0U);
263 R_CPG->CPG_PLL_DSEL =
264 (uint32_t) (R_CPG_CPG_PLL_DSEL_SELPL4_WEN_Msk | (R_CPG_CPG_PLL_DSEL_SELPL4_SET_Msk & setting_value));
265 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELPL4_STS_Msk & R_CPG->CPG_CLKSELSTATUS), 0U);
266 #endif
267 }
268
269 /*******************************************************************************************************************//**
270 * Perform any necessary processing before changing the frequency.
271 *
272 * @param[in] clock Desired clock
273 **********************************************************************************************************************/
bsp_prv_clock_pre_setting(fsp_priv_clock_t clock)274 static void bsp_prv_clock_pre_setting (fsp_priv_clock_t clock)
275 {
276 FSP_PARAMETER_NOT_USED(clock);
277 }
278
279 /*******************************************************************************************************************//**
280 * Perform any necessary processing after changing the frequency.
281 *
282 * @param[in] clock Desired clock
283 **********************************************************************************************************************/
bsp_prv_clock_post_setting(fsp_priv_clock_t clock)284 static void bsp_prv_clock_post_setting (fsp_priv_clock_t clock)
285 {
286 FSP_PARAMETER_NOT_USED(clock);
287 }
288
289 /*******************************************************************************************************************//**
290 * Set the Source Clock Setting register to change the frequency.
291 *
292 * @param[in] clock Element number of the array that defines the frequency of each clock.
293 * @param[in] clock_sel Value to set in Source Clock Setting register.
294 **********************************************************************************************************************/
bsp_prv_clock_selector_set(fsp_priv_clock_t clock,uint32_t clock_sel)295 void bsp_prv_clock_selector_set (fsp_priv_clock_t clock, uint32_t clock_sel)
296 {
297 uint32_t clock_freq = g_clock_freq[clock];
298
299 switch (clock)
300 {
301 #if defined(BSP_CFG_SEL_SDHI0_SET_SOURCE)
302
303 /* Source Clock setting for SDHI0. */
304 case FSP_PRIV_CLOCK_SD0CLK:
305 {
306 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
307 R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Pos,
308 0U);
309
310 R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_WEN_Msk |
311 (R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Msk &
312 (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI0_SET_Pos)));
313
314 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
315 R_CPG_CPG_CLKSELSTATUS_SELSDHI0_STS_Pos,
316 0U);
317
318 if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel)
319 {
320 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1;
321 }
322 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel)
323 {
324 clock_freq = BSP_CFG_CLOCK_PLL6_HZ;
325 }
326 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel)
327 {
328 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6;
329 }
330 else
331 {
332 /* If this condition is met, prohibited value was set in the register. */
333 ;
334 }
335
336 break;
337 }
338 #endif /* BSP_CFG_SEL_SDHI0_SET_SOURCE */
339
340 #if defined(BSP_CFG_SEL_SDHI1_SET_SOURCE)
341
342 /* Source Clock setting for SDHI1. */
343 case FSP_PRIV_CLOCK_SD1CLK:
344 {
345 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
346 R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Pos,
347 0U);
348
349 R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_WEN_Msk |
350 (R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Msk &
351 (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI1_SET_Pos)));
352
353 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
354 R_CPG_CPG_CLKSELSTATUS_SELSDHI1_STS_Pos,
355 0U);
356
357 if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel)
358 {
359 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1;
360 }
361 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel)
362 {
363 clock_freq = BSP_CFG_CLOCK_PLL6_HZ;
364 }
365 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel)
366 {
367 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6;
368 }
369 else
370 {
371 /* If this condition is met, prohibited value was set in the register. */
372 ;
373 }
374
375 break;
376 }
377 #endif /* BSP_CFG_SEL_SDHI1_SET_SOURCE */
378
379 #if defined(BSP_CFG_SEL_SDHI2_SET_SOURCE)
380
381 /* Source Clock setting for SDHI2. */
382 case FSP_PRIV_CLOCK_SD2CLK:
383 {
384 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
385 R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Pos,
386 0U);
387
388 R_CPG->CPG_SDHI_DSEL = (uint32_t) (R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_WEN_Msk |
389 (R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Msk &
390 (clock_sel << R_CPG_CPG_SDHI_DSEL_SEL_SDHI2_SET_Pos)));
391
392 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Msk & R_CPG->CPG_CLKSELSTATUS) >>
393 R_CPG_CPG_CLKSELSTATUS_SELSDHI2_STS_Pos,
394 0U);
395
396 if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_800 == clock_sel)
397 {
398 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ >> 1;
399 }
400 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_500 == clock_sel)
401 {
402 clock_freq = BSP_CFG_CLOCK_PLL6_HZ;
403 }
404 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL2_266 == clock_sel)
405 {
406 clock_freq = BSP_CFG_CLOCK_PLL2_1600_HZ / 6;
407 }
408 else
409 {
410 /* If this condition is met, prohibited value was set in the register. */
411 ;
412 }
413
414 break;
415 }
416 #endif /* BSP_CFG_SEL_SDHI2_SET_SOURCE */
417
418 #if defined(BSP_CFG_SELSPI_SET_SOURCE)
419
420 /* Source Clock setting for SPI0. */
421 case FSP_PRIV_CLOCK_SPI0CLK:
422 {
423 uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
424 R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos);
425
426 /* If SPI_CLKX2 is supplied, the clock stops before setting the Source Clock Setting Register. */
427 if (clock_mon)
428 {
429 R_CPG->CPG_CLKON_SPI = R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Msk;
430 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
431 R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos,
432 0U);
433 }
434
435 R_CPG->CPG_SPI_SSEL = (uint32_t) (R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Msk |
436 (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk &
437 (clock_sel << R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos)));
438
439 /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */
440 if (clock_mon)
441 {
442 R_CPG->CPG_CLKON_SPI = (uint32_t) (R_CPG_CPG_CLKON_SPI_CLK3_ONWEN_Msk |
443 R_CPG_CPG_CLKON_SPI_CLK3_ON_Msk);
444 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK3_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
445 R_CPG_CPG_CLKMON_SPI_CLK3_MON_Pos,
446 1U);
447 }
448
449 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel)
450 {
451 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
452 }
453 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel)
454 {
455 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
456 }
457 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel)
458 {
459 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
460 }
461 else
462 {
463 /* If this condition is met, clock_sel is an invalid value. */
464 ;
465 }
466
467 uint32_t clock_div = (uint32_t) ((R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & R_CPG->CPG_SPI_DDIV) >>
468 R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos);
469 if (BSP_CLOCKS_SPI_DIV_32 == clock_div)
470 {
471 clock_div++;
472 }
473
474 clock_freq = clock_freq >> (clock_div + 1);
475
476 /* Changing settings for the SPI0 clock related register, SPI1 clock frequency changes at the same time.
477 * So it is updated the variable that stored SPI1 clock frequency. */
478 g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = clock_freq >> 1;
479 break;
480 }
481
482 /* Source Clock setting for SPI1. */
483 case FSP_PRIV_CLOCK_SPI1CLK:
484 {
485 uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
486 R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos);
487
488 /* If SPI_CLK is supplied, the clock stops before setting the Source Clock Setting Register. */
489 if (clock_mon)
490 {
491 R_CPG->CPG_CLKON_SPI = R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Msk;
492 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
493 R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos,
494 0U);
495 }
496
497 R_CPG->CPG_SPI_SSEL = (uint32_t) (R_CPG_CPG_SPI_SSEL_SELSPI_WEN_Msk |
498 (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk &
499 (clock_sel << R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos)));
500
501 /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */
502 if (clock_mon)
503 {
504 R_CPG->CPG_CLKON_SPI = (uint32_t) (R_CPG_CPG_CLKON_SPI_CLK2_ONWEN_Msk |
505 R_CPG_CPG_CLKON_SPI_CLK2_ON_Msk);
506 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_SPI_CLK2_MON_Msk & R_CPG->CPG_CLKMON_SPI) >>
507 R_CPG_CPG_CLKMON_SPI_CLK2_MON_Pos,
508 1U);
509 }
510
511 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel)
512 {
513 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
514 }
515 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel)
516 {
517 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
518 }
519 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel)
520 {
521 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
522 }
523 else
524 {
525 /* If this condition is met, clock_sel is an invalid value. */
526 ;
527 }
528
529 uint32_t clock_div = (uint32_t) ((R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk & R_CPG->CPG_SPI_DDIV) >>
530 R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos);
531 if (BSP_CLOCKS_SPI_DIV_32 == clock_div)
532 {
533 clock_div++;
534 }
535
536 clock_freq = clock_freq >> (clock_div + 2);
537
538 /* Changing settings for the SPI1 clock related register, SPI0 clock frequency changes at the same time.
539 * So it is updated the variable that stored SPI0 clock frequency. */
540 g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = clock_freq << 1;
541 break;
542 }
543 #endif /* BSP_CFG_SELSPI_SET_SOURCE */
544
545 #if defined(BSP_CFG_SELOCTA_SET_SOURCE)
546
547 /* Source Clock setting for OC0. */
548 case FSP_PRIV_CLOCK_OC0CLK:
549 {
550 uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
551 R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos);
552
553 /* If OCTA_MCLK is supplied, the clock stops before setting the Source Clock Setting Register. */
554 if (clock_mon)
555 {
556 R_CPG->CPG_CLKON_OCTA = R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Msk;
557 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
558 R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos,
559 0U);
560 }
561
562 R_CPG->CPG_OCTA_SSEL = (uint32_t) (R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Msk |
563 (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk &
564 (clock_sel << R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos)));
565
566 /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */
567 if (clock_mon)
568 {
569 R_CPG->CPG_CLKON_OCTA = (uint32_t) (R_CPG_CPG_CLKON_OCTA_CLK1_ONWEN_Msk |
570 R_CPG_CPG_CLKON_OCTA_CLK1_ON_Msk);
571 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
572 R_CPG_CPG_CLKMON_OCTA_CLK1_MON_Pos,
573 1U);
574 }
575
576 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel)
577 {
578 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
579 }
580 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel)
581 {
582 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
583 }
584 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel)
585 {
586 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
587 }
588 else
589 {
590 /* If this condition is met, clock_sel is an invalid value. */
591 ;
592 }
593
594 uint32_t clock_div = (uint32_t) ((R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & R_CPG->CPG_OCTA_DDIV) >>
595 R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos);
596 if (BSP_CLOCKS_OCTA_DIV_32 == clock_div)
597 {
598 clock_div++;
599 }
600
601 clock_freq = clock_freq >> (clock_div + 1);
602
603 /* Changing settings for the OC0 clock related register, OC1 clock frequency changes at the same time.
604 * So it is updated the variable that stored OC1 clock frequency. */
605 g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = clock_freq >> 1;
606 break;
607 }
608
609 /* Source Clock setting for OC1. */
610 case FSP_PRIV_CLOCK_OC1CLK:
611 {
612 uint32_t clock_mon = (uint32_t) ((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
613 R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos);
614
615 /* If OCTA_ACLK is supplied, the clock stops before setting the Source Clock Setting Register. */
616 if (clock_mon)
617 {
618 R_CPG->CPG_CLKON_OCTA = R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Msk;
619 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
620 R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos,
621 0U);
622 }
623
624 R_CPG->CPG_OCTA_SSEL = (uint32_t) (R_CPG_CPG_OCTA_SSEL_SELOCTA_WEN_Msk |
625 (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk &
626 (clock_sel << R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos)));
627
628 /* If the clock was stopped before setting the Source Clock Setting Register, the clock supply resumes. */
629 if (clock_mon)
630 {
631 R_CPG->CPG_CLKON_OCTA = (uint32_t) (R_CPG_CPG_CLKON_OCTA_CLK0_ONWEN_Msk |
632 R_CPG_CPG_CLKON_OCTA_CLK0_ON_Msk);
633 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Msk & R_CPG->CPG_CLKMON_OCTA) >>
634 R_CPG_CPG_CLKMON_OCTA_CLK0_MON_Pos,
635 1U);
636 }
637
638 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_sel)
639 {
640 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
641 }
642 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_sel)
643 {
644 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
645 }
646 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_sel)
647 {
648 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
649 }
650 else
651 {
652 /* If this condition is met, clock_sel is an invalid value. */
653 ;
654 }
655
656 uint32_t clock_div = (uint32_t) ((R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk & R_CPG->CPG_OCTA_DDIV) >>
657 R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos);
658 if (BSP_CLOCKS_OCTA_DIV_32 == clock_div)
659 {
660 clock_div++;
661 }
662
663 clock_freq = clock_freq >> (clock_div + 2);
664
665 /* Changing settings for the OC1 clock related register, OC0 clock frequency changes at the same time.
666 * So it is updated the variable that stored OC0 clock frequency. */
667 g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = clock_freq << 1;
668 break;
669 }
670 #endif /* BSP_CFG_SELOCTA_SET_SOURCE */
671
672 default:
673 {
674 FSP_PARAMETER_NOT_USED(clock_sel);
675 break;
676 }
677 }
678
679 g_clock_freq[clock] = clock_freq;
680 }
681
682 /*******************************************************************************************************************//**
683 * Set the Division Ratio Setting register to change the frequency.
684 *
685 * @param[in] clock Element number of the array that defines the frequency of each clock.
686 * @param[in] clock_div Value to set in Division Ratio Setting register.
687 **********************************************************************************************************************/
bsp_prv_clock_divider_set(fsp_priv_clock_t clock,uint32_t clock_div)688 void bsp_prv_clock_divider_set (fsp_priv_clock_t clock, uint32_t clock_div)
689 {
690 uint32_t clock_freq = g_clock_freq[clock];
691
692 switch (clock)
693 {
694 #if defined(BSP_CFG_DIVPL1_SET_DIV)
695
696 /* ICLK division ratio setting. */
697 case FSP_PRIV_CLOCK_ICLK:
698 {
699 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
700 R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Pos,
701 0U);
702 R_CPG->CPG_PL1_DDIV = (uint32_t) (R_CPG_CPG_PL1_DDIV_DIV_PLL1SET_WEN_Msk |
703 (R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Msk &
704 (clock_div << R_CPG_CPG_PL1_DDIV_DIVPL1_SET_Pos)));
705 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
706 R_CPG_CPG_CLKDIVSTATUS_DIVPL1_STS_Pos,
707 0U);
708 clock_freq = BSP_CFG_CLOCK_PLL1_HZ >> clock_div;
709 break;
710 }
711 #endif
712
713 #if defined(BSP_CFG_DIVSPI_SET_DIV)
714
715 /* SPI0CLK division ratio setting. */
716 case FSP_PRIV_CLOCK_SPI0CLK:
717 {
718 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
719 R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos,
720 0U);
721 R_CPG->CPG_SPI_DDIV = (uint32_t) (R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Msk |
722 (R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk &
723 (clock_div << R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos)));
724 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
725 R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos,
726 0U);
727
728 uint32_t clock_source = (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & R_CPG->CPG_SPI_SSEL) >>
729 R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos;
730
731 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source)
732 {
733 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
734 }
735 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source)
736 {
737 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
738 }
739 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source)
740 {
741 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
742 }
743 else
744 {
745 /* If this condition is met, prohibited value was set in the register. */
746 ;
747 }
748
749 if (BSP_CLOCKS_SPI_DIV_32 == clock_div)
750 {
751 clock_div++;
752 }
753
754 clock_freq = clock_freq >> clock_div;
755
756 /* Changing settings for the SPI0 clock related register, SPI1 clock frequency changes at the same time.
757 * So it is updated the variable that stored SPI1 clock frequency. */
758 g_clock_freq[FSP_PRIV_CLOCK_SPI1CLK] = clock_freq >> 1;
759 break;
760 }
761 #endif
762
763 #if defined(BSP_CFG_DIVSPI_SET_DIV)
764
765 /* SPI1CLK division ratio setting. */
766 case FSP_PRIV_CLOCK_SPI1CLK:
767 {
768 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
769 R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos,
770 0U);
771 R_CPG->CPG_SPI_DDIV = (uint32_t) (R_CPG_CPG_SPI_DDIV_DIVSPI_WEN_Msk |
772 (R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Msk &
773 (clock_div << R_CPG_CPG_SPI_DDIV_DIVSPI_SET_Pos)));
774 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
775 R_CPG_CPG_CLKDIVSTATUS_DIVSPI_STS_Pos,
776 0U);
777
778 uint32_t clock_source = (R_CPG_CPG_SPI_SSEL_SELSPI_SET_Msk & R_CPG->CPG_SPI_SSEL) >>
779 R_CPG_CPG_SPI_SSEL_SELSPI_SET_Pos;
780
781 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source)
782 {
783 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
784 }
785 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source)
786 {
787 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
788 }
789 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source)
790 {
791 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
792 }
793 else
794 {
795 /* If this condition is met, prohibited value was set in the register. */
796 ;
797 }
798
799 if (BSP_CLOCKS_SPI_DIV_32 == clock_div)
800 {
801 clock_div++;
802 }
803
804 clock_freq = clock_freq >> (clock_div + 1);
805
806 /* Changing settings for the SPI1 clock related register, SPI0 clock frequency changes at the same time.
807 * So it is updated the variable that stored SPI0 clock frequency. */
808 g_clock_freq[FSP_PRIV_CLOCK_SPI0CLK] = clock_freq << 1;
809 break;
810 }
811 #endif
812
813 #if defined(BSP_CFG_DIVOCTA_SET_DIV)
814
815 /* OC0CLK division ratio setting. */
816 case FSP_PRIV_CLOCK_OC0CLK:
817 {
818 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
819 R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos,
820 0U);
821 R_CPG->CPG_OCTA_DDIV = (uint32_t) (R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Msk |
822 (R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk &
823 (clock_div << R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos)));
824 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
825 R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos,
826 0U);
827
828 uint32_t clock_source = (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & R_CPG->CPG_OCTA_SSEL) >>
829 R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos;
830
831 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source)
832 {
833 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
834 }
835 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source)
836 {
837 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
838 }
839 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source)
840 {
841 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
842 }
843 else
844 {
845 /* If this condition is met, prohibited value was set in the register. */
846 ;
847 }
848
849 if (BSP_CLOCKS_OCTA_DIV_32 == clock_div)
850 {
851 clock_div++;
852 }
853
854 clock_freq = clock_freq >> clock_div;
855
856 /* Changing settings for the OC0 clock related register, OC1 clock frequency changes at the same time.
857 * So it is updated the variable that stored OC1 clock frequency. */
858 g_clock_freq[FSP_PRIV_CLOCK_OC1CLK] = clock_freq >> 1;
859 break;
860 }
861 #endif
862
863 #if defined(BSP_CFG_DIVOCTA_SET_DIV)
864
865 /* OC1CLK division ratio setting. */
866 case FSP_PRIV_CLOCK_OC1CLK:
867 {
868 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
869 R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos,
870 0U);
871 R_CPG->CPG_OCTA_DDIV = (uint32_t) (R_CPG_CPG_OCTA_DDIV_DIVOCTA_WEN_Msk |
872 (R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Msk &
873 (clock_div << R_CPG_CPG_OCTA_DDIV_DIVOCTA_SET_Pos)));
874 FSP_HARDWARE_REGISTER_WAIT((R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Msk & R_CPG->CPG_CLKDIVSTATUS) >>
875 R_CPG_CPG_CLKDIVSTATUS_DIVOCTA_STS_Pos,
876 0U);
877
878 uint32_t clock_source = (R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Msk & R_CPG->CPG_OCTA_SSEL) >>
879 R_CPG_CPG_OCTA_SSEL_SELOCTA_SET_Pos;
880
881 if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_400 == clock_source)
882 {
883 clock_freq = BSP_CFG_CLOCK_PLL3_HZ >> 2;
884 }
885 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL3_266 == clock_source)
886 {
887 clock_freq = BSP_CFG_CLOCK_PLL3_HZ / 6;
888 }
889 else if (BSP_CLOCKS_SOURCE_CLOCK_PLL6_250 == clock_source)
890 {
891 clock_freq = BSP_CFG_CLOCK_PLL6_HZ >> 1;
892 }
893 else
894 {
895 /* If this condition is met, prohibited value was set in the register. */
896 ;
897 }
898
899 if (BSP_CLOCKS_OCTA_DIV_32 == clock_div)
900 {
901 clock_div++;
902 }
903
904 clock_freq = clock_freq >> (clock_div + 1);
905
906 /* Changing settings for the OC1 clock related register, OC0 clock frequency changes at the same time.
907 * So it is updated the variable that stored OC0 clock frequency. */
908 g_clock_freq[FSP_PRIV_CLOCK_OC0CLK] = clock_freq << 1;
909 break;
910 }
911 #endif
912
913 default:
914 {
915 FSP_PARAMETER_NOT_USED(clock_div);
916 break;
917 }
918 }
919
920 g_clock_freq[clock] = clock_freq;
921 }
922
923 /** @} (end addtogroup BSP_MCU_PRV) */
924
925 /*******************************************************************************************************************//**
926 * @addtogroup BSP_MCU
927 * @{
928 **********************************************************************************************************************/
929
930 /*******************************************************************************************************************//**
931 * Get the system clock frequency.
932 *
933 * @param[in] clock Element number of the array that defines the frequency of the bus clock.
934 *
935 * @retval g_clock_freq[clock] System clock frequency.
936 **********************************************************************************************************************/
R_FSP_SystemClockHzGet(fsp_priv_clock_t clock)937 uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
938 {
939 return g_clock_freq[clock];
940 }
941
942 /*******************************************************************************************************************//**
943 * Set a clock frequency.
944 *
945 * @param[in] clock Element number of the array that defines the frequency of each clock.
946 * @param[in] clock_sel Value to set in Source Clock Setting register.
947 * @param[in] clock_div Value to set in Division Ratio Setting register.
948 **********************************************************************************************************************/
R_FSP_SystemClockHzSet(fsp_priv_clock_t clock,uint32_t clock_sel,uint32_t clock_div)949 void R_FSP_SystemClockHzSet (fsp_priv_clock_t clock, uint32_t clock_sel, uint32_t clock_div)
950 {
951 bsp_prv_clock_pre_setting(clock);
952 bsp_prv_clock_selector_set(clock, clock_sel);
953 bsp_prv_clock_divider_set(clock, clock_div);
954 bsp_prv_clock_post_setting(clock);
955 }
956
957 /** @} (end addtogroup BSP_MCU) */
958
