1 /*
2  * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <stddef.h>
7 #include <stdint.h>
8 #include "bootloader_flash_config.h"
9 #include "flash_qio_mode.h"
10 #include "sdkconfig.h"
11 #include "bootloader_flash_priv.h"
12 #include "esp_log.h"
13 #include "esp_err.h"
14 #include "esp_attr.h"
15 #include "esp_rom_spiflash.h"
16 #include "esp_rom_efuse.h"
17 #include "flash_qio_mode.h"
18 #include "soc/efuse_periph.h"
19 #include "soc/io_mux_reg.h"
20 #include "esp_private/spi_flash_os.h"
21 
22 
23 static const char *TAG = "qio_mode";
24 
25 /* Array of known flash chips and data to enable Quad I/O mode
26 
27    Manufacturer & flash ID can be tested by running "esptool.py
28    flash_id"
29 
30    If manufacturer ID matches, and flash ID ORed with flash ID mask
31    matches, enable_qio_mode() will execute "Read Cmd", test if bit
32    number "QIE Bit" is set, and if not set it will call "Write Cmd"
33    with this bit set.
34 
35    Searching of this table stops when the first match is found.
36  */
37 const bootloader_qio_info_t __attribute__((weak)) bootloader_flash_qe_support_list[] = {
38     /*   Manufacturer,   mfg_id, flash_id, id mask, Read Status,                Write Status,               QIE Bit */
39     { "MXIC",        0xC2,   0x2000, 0xFF00,    bootloader_read_status_8b_rdsr,        bootloader_write_status_8b_wrsr,       6 },
40     { "ISSI",        0x9D,   0x4000, 0xCF00,    bootloader_read_status_8b_rdsr,        bootloader_write_status_8b_wrsr,       6 }, /* IDs 0x40xx, 0x70xx */
41     { "WinBond",     0xEF,   0x4000, 0xFF00,    bootloader_read_status_16b_rdsr_rdsr2, bootloader_write_status_16b_wrsr,      9 },
42     { "GD",          0xC8,   0x6000, 0xFF00,    bootloader_read_status_16b_rdsr_rdsr2, bootloader_write_status_16b_wrsr,      9 },
43     { "XM25QU64A",   0x20,   0x3817, 0xFFFF,    bootloader_read_status_8b_xmc25qu64a,  bootloader_write_status_8b_xmc25qu64a, 6 },
44     { "TH",          0xcd,   0x6000, 0xFF00,    bootloader_read_status_16b_rdsr_rdsr2, bootloader_write_status_16b_wrsr,      9 },
45 
46     /* Final entry is default entry, if no other IDs have matched.
47 
48        This approach works for chips including:
49        GigaDevice (mfg ID 0xC8, flash IDs including 4016),
50        FM25Q32 (QOUT mode only, mfg ID 0xA1, flash IDs including 4016)
51        BY25Q32 (mfg ID 0x68, flash IDs including 4016)
52     */
53     { NULL,          0xFF,    0xFFFF, 0xFFFF,   bootloader_read_status_8b_rdsr2,       bootloader_write_status_8b_wrsr2,      1 },
54 };
55 
56 #define NUM_CHIPS (sizeof(bootloader_flash_qe_support_list) / sizeof(bootloader_qio_info_t))
57 
58 static esp_err_t enable_qio_mode(bootloader_flash_read_status_fn_t read_status_fn,
59                                  bootloader_flash_write_status_fn_t write_status_fn,
60                                  uint8_t status_qio_bit);
61 
62 /* Generic function to use the "user command" SPI controller functionality
63    to send commands to the SPI flash and read the respopnse.
64 
65    The command passed here is always the on-the-wire command given to the SPI flash unit.
66 */
67 
bootloader_enable_qio_mode(void)68 void bootloader_enable_qio_mode(void)
69 {
70     uint32_t raw_flash_id;
71     uint8_t mfg_id;
72     uint16_t flash_id;
73     size_t i;
74 
75     ESP_LOGD(TAG, "Probing for QIO mode enable...");
76     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
77 
78     raw_flash_id = g_rom_flashchip.device_id;
79     ESP_LOGD(TAG, "Raw SPI flash chip id 0x%"PRIx32, raw_flash_id);
80 
81     mfg_id = (raw_flash_id >> 16) & 0xFF;
82     flash_id = raw_flash_id & 0xFFFF;
83     ESP_LOGD(TAG, "Manufacturer ID 0x%02x chip ID 0x%04x", mfg_id, flash_id);
84 
85     for (i = 0; i < NUM_CHIPS - 1; i++) {
86         const bootloader_qio_info_t *chip = &bootloader_flash_qe_support_list[i];
87         if (mfg_id == chip->mfg_id && (flash_id & chip->id_mask) == (chip->flash_id & chip->id_mask)) {
88             ESP_LOGI(TAG, "Enabling QIO for flash chip %s", bootloader_flash_qe_support_list[i].manufacturer);
89             break;
90         }
91     }
92 
93     if (i == NUM_CHIPS - 1) {
94         ESP_LOGI(TAG, "Enabling default flash chip QIO");
95     }
96     enable_qio_mode(bootloader_flash_qe_support_list[i].read_status_fn,
97                     bootloader_flash_qe_support_list[i].write_status_fn,
98                     bootloader_flash_qe_support_list[i].status_qio_bit);
99 #if SOC_CACHE_SUPPORT_WRAP
100     spi_flash_wrap_probe();
101     spi_flash_wrap_disable();
102 #endif
103 }
104 
s_flash_set_qio_pins(void)105 static void s_flash_set_qio_pins(void)
106 {
107 #if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
108 
109 #if CONFIG_IDF_TARGET_ESP32
110     esp_rom_spiflash_select_qio_pins(bootloader_flash_get_wp_pin(), esp_rom_efuse_get_flash_gpio_info());
111 #else
112     esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), esp_rom_efuse_get_flash_gpio_info());
113 #endif // CONFIG_IDF_TARGET_ESP32
114 
115 #else
116     // ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second
117     // parameter is set to 0, means that chip uses default SPI pins
118     // and wp_gpio_num parameter(the first parameter) is ignored.
119     esp_rom_spiflash_select_qio_pins(0, 0);
120 #endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
121 }
122 
123 
enable_qio_mode(bootloader_flash_read_status_fn_t read_status_fn,bootloader_flash_write_status_fn_t write_status_fn,uint8_t status_qio_bit)124 static esp_err_t enable_qio_mode(bootloader_flash_read_status_fn_t read_status_fn,
125                                  bootloader_flash_write_status_fn_t write_status_fn,
126                                  uint8_t status_qio_bit)
127 {
128     uint32_t status;
129 
130     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
131 
132     status = read_status_fn();
133     ESP_LOGD(TAG, "Initial flash chip status 0x%"PRIx32, status);
134 
135     if ((status & (1 << status_qio_bit)) == 0) {
136         bootloader_execute_flash_command(CMD_WREN, 0, 0, 0);
137         write_status_fn(status | (1 << status_qio_bit));
138 
139         esp_rom_spiflash_wait_idle(&g_rom_flashchip);
140 
141         status = read_status_fn();
142         ESP_LOGD(TAG, "Updated flash chip status 0x%"PRIx32, status);
143         if ((status & (1 << status_qio_bit)) == 0) {
144             ESP_LOGE(TAG, "Failed to set QIE bit, not enabling QIO mode");
145             return ESP_FAIL;
146         }
147 
148     } else {
149         ESP_LOGD(TAG, "QIO mode already enabled in flash");
150     }
151 
152     ESP_LOGD(TAG, "Enabling QIO mode...");
153 
154     esp_rom_spiflash_read_mode_t mode;
155 #if CONFIG_ESPTOOLPY_FLASHMODE_QOUT
156     mode = ESP_ROM_SPIFLASH_QOUT_MODE;
157 #else
158     mode = ESP_ROM_SPIFLASH_QIO_MODE;
159 #endif
160 
161     esp_rom_spiflash_config_readmode(mode);
162 
163     s_flash_set_qio_pins();
164     return ESP_OK;
165 }
166 
bootloader_read_status_8b_rdsr(void)167 IRAM_ATTR unsigned bootloader_read_status_8b_rdsr(void)
168 {
169     return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8);
170 }
171 
bootloader_read_status_8b_rdsr2(void)172 IRAM_ATTR unsigned bootloader_read_status_8b_rdsr2(void)
173 {
174     return bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8);
175 }
176 
bootloader_read_status_8b_rdsr3(void)177 IRAM_ATTR unsigned bootloader_read_status_8b_rdsr3(void)
178 {
179     return bootloader_execute_flash_command(CMD_RDSR3, 0, 0, 8);
180 }
181 
bootloader_read_status_16b_rdsr_rdsr2(void)182 IRAM_ATTR unsigned bootloader_read_status_16b_rdsr_rdsr2(void)
183 {
184     return bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8) | (bootloader_execute_flash_command(CMD_RDSR2, 0, 0, 8) << 8);
185 }
186 
bootloader_write_status_8b_wrsr(unsigned new_status)187 IRAM_ATTR void bootloader_write_status_8b_wrsr(unsigned new_status)
188 {
189     bootloader_execute_flash_command(CMD_WRSR, new_status, 8, 0);
190 }
191 
bootloader_write_status_8b_wrsr2(unsigned new_status)192 IRAM_ATTR void bootloader_write_status_8b_wrsr2(unsigned new_status)
193 {
194     bootloader_execute_flash_command(CMD_WRSR2, new_status, 8, 0);
195 }
196 
bootloader_write_status_8b_wrsr3(unsigned new_status)197 IRAM_ATTR void bootloader_write_status_8b_wrsr3(unsigned new_status)
198 {
199     bootloader_execute_flash_command(CMD_WRSR3, new_status, 8, 0);
200 }
201 
bootloader_write_status_16b_wrsr(unsigned new_status)202 IRAM_ATTR void bootloader_write_status_16b_wrsr(unsigned new_status)
203 {
204     bootloader_execute_flash_command(CMD_WRSR, new_status, 16, 0);
205 }
206 
bootloader_read_status_8b_xmc25qu64a(void)207 IRAM_ATTR unsigned bootloader_read_status_8b_xmc25qu64a(void)
208 {
209     bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0);  /* Enter OTP mode */
210     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
211     uint32_t read_status = bootloader_execute_flash_command(CMD_RDSR, 0, 0, 8);
212     bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0);   /* Exit OTP mode */
213     return read_status;
214 }
215 
bootloader_write_status_8b_xmc25qu64a(unsigned new_status)216 IRAM_ATTR void bootloader_write_status_8b_xmc25qu64a(unsigned new_status)
217 {
218     bootloader_execute_flash_command(CMD_OTPEN, 0, 0, 0);  /* Enter OTP mode */
219     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
220     bootloader_execute_flash_command(CMD_WRSR, new_status, 8, 0);
221     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
222     bootloader_execute_flash_command(CMD_WRDI, 0, 0, 0);   /* Exit OTP mode */
223 }
224