1 /*
2 * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdbool.h>
7 #include <assert.h>
8 #include "string.h"
9 #include "sdkconfig.h"
10 #include "esp_err.h"
11 #include "esp_log.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp32/rom/spi_flash.h"
15 #include "esp32/rom/cache.h"
16 #include "soc/gpio_periph.h"
17 #include "soc/efuse_reg.h"
18 #include "soc/spi_reg.h"
19 #include "soc/soc_caps.h"
20 #include "soc/soc_pins.h"
21 #include "soc/chip_revision.h"
22 #include "hal/efuse_hal.h"
23 #include "hal/gpio_hal.h"
24 #include "flash_qio_mode.h"
25 #include "bootloader_common.h"
26 #include "bootloader_flash_config.h"
27 #include "bootloader_flash_priv.h"
28 #include "bootloader_init.h"
29
30 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
31 #define FLASH_CS_IO SPI_CS0_GPIO_NUM
32 #define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
33 #define FLASH_SPID_IO SPI_D_GPIO_NUM
34 #define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
35 #define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
36
bootloader_flash_update_id(void)37 void bootloader_flash_update_id(void)
38 {
39 g_rom_flashchip.device_id = bootloader_read_flash_id();
40 }
41
bootloader_flash_update_size(uint32_t size)42 void bootloader_flash_update_size(uint32_t size)
43 {
44 g_rom_flashchip.chip_size = size;
45 }
46
bootloader_flash_cs_timing_config(void)47 void IRAM_ATTR bootloader_flash_cs_timing_config(void)
48 {
49 SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
50 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
51 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
52 SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
53 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
54 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
55 }
56
bootloader_flash_clock_config(const esp_image_header_t * pfhdr)57 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
58 {
59 uint32_t spi_clk_div = 0;
60 switch (pfhdr->spi_speed) {
61 case ESP_IMAGE_SPI_SPEED_DIV_1:
62 spi_clk_div = 1;
63 break;
64 case ESP_IMAGE_SPI_SPEED_DIV_2:
65 spi_clk_div = 2;
66 break;
67 case ESP_IMAGE_SPI_SPEED_DIV_3:
68 spi_clk_div = 3;
69 break;
70 case ESP_IMAGE_SPI_SPEED_DIV_4:
71 spi_clk_div = 4;
72 break;
73 default:
74 break;
75 }
76 esp_rom_spiflash_config_clk(spi_clk_div, 0);
77 esp_rom_spiflash_config_clk(spi_clk_div, 1);
78 }
79
bootloader_flash_gpio_config(const esp_image_header_t * pfhdr)80 void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
81 {
82 uint32_t drv = 2;
83 if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_DIV_1) {
84 drv = 3;
85 }
86
87 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
88
89 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
90 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
91 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
92 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
93 // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
94 // flash clock signal should come from IO MUX.
95 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
96 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
97 } else {
98 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
99 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
100 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
101 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
102 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
103 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
104 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
105 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
106 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
107 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
108 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
109 //select pin function gpio
110 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
111 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
112 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
113 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
114 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
115 // flash clock signal should come from IO MUX.
116 // set drive ability for clock
117 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
118 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
119
120 uint32_t flash_id = g_rom_flashchip.device_id;
121 if (flash_id == FLASH_ID_GD25LQ32C) {
122 // Set drive ability for 1.8v flash in 80Mhz.
123 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
124 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
125 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
126 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
127 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
128 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
129 }
130 }
131 }
132 }
133
bootloader_flash_dummy_config(const esp_image_header_t * pfhdr)134 void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
135 {
136 int spi_cache_dummy = 0;
137 uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
138 if (modebit & SPI_FASTRD_MODE) {
139 if (modebit & SPI_FREAD_QIO) { //SPI mode is QIO
140 spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
141 } else if (modebit & SPI_FREAD_DIO) { //SPI mode is DIO
142 spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
143 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
144 } else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
145 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
146 }
147 }
148
149 switch (pfhdr->spi_speed) {
150 case ESP_IMAGE_SPI_SPEED_DIV_1:
151 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
152 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
153 break;
154 case ESP_IMAGE_SPI_SPEED_DIV_2:
155 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
156 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
157 break;
158 case ESP_IMAGE_SPI_SPEED_DIV_3:
159 case ESP_IMAGE_SPI_SPEED_DIV_4:
160 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
161 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
162 break;
163 default:
164 break;
165 }
166
167 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
168 SPI_USR_DUMMY_CYCLELEN_S);
169 }
170
171 #define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD & ESP32-PICO-D4 has this GPIO wired to WP pin of flash */
172 #define ESP32_PICO_V3_GPIO 18 /* ESP32-PICO-V3* use this GPIO for WP pin of flash */
173
bootloader_flash_get_wp_pin(void)174 int bootloader_flash_get_wp_pin(void)
175 {
176 #if CONFIG_BOOTLOADER_SPI_CUSTOM_WP_PIN
177 return CONFIG_BOOTLOADER_SPI_WP_PIN; // can be set for bootloader when QIO or QOUT config in use
178 #elif CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN
179 return CONFIG_SPIRAM_SPIWP_SD3_PIN; // can be set for app when DIO or DOUT config used for PSRAM only
180 #else
181 // no custom value, find it based on the package eFuse value
182 switch(bootloader_common_get_chip_ver_pkg()) {
183 case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
184 case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
185 return ESP32_D2WD_WP_GPIO;
186 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
187 /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
188 return !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
189 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
190 return ESP32_PICO_V3_GPIO;
191 default:
192 return SPI_WP_GPIO_NUM;
193 }
194 #endif
195 }
196
197 static const char *TAG = "boot.esp32";
198
bootloader_configure_spi_pins(int drv)199 void bootloader_configure_spi_pins(int drv)
200 {
201 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
202
203 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
204 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
205 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
206 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
207 // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
208 // flash clock signal should come from IO MUX.
209 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
210 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
211 } else {
212 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
213 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
214 esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
215 esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
216 esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
217 esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
218 esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
219 esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
220 esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
221 esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
222 esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
223 //select pin function gpio
224 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
225 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
226 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
227 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
228 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
229 // flash clock signal should come from IO MUX.
230 // set drive ability for clock
231 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
232 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
233
234 #if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64
235 uint32_t flash_id = g_rom_flashchip.device_id;
236 if (flash_id == FLASH_ID_GD25LQ32C) {
237 // Set drive ability for 1.8v flash in 80Mhz.
238 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
239 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
240 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
241 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
242 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
243 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
244 }
245 #endif
246 }
247 }
248 }
249
update_flash_config(const esp_image_header_t * bootloader_hdr)250 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
251 {
252 uint32_t size;
253 switch (bootloader_hdr->spi_size) {
254 case ESP_IMAGE_FLASH_SIZE_1MB:
255 size = 1;
256 break;
257 case ESP_IMAGE_FLASH_SIZE_2MB:
258 size = 2;
259 break;
260 case ESP_IMAGE_FLASH_SIZE_4MB:
261 size = 4;
262 break;
263 case ESP_IMAGE_FLASH_SIZE_8MB:
264 size = 8;
265 break;
266 case ESP_IMAGE_FLASH_SIZE_16MB:
267 size = 16;
268 break;
269 default:
270 size = 2;
271 }
272 Cache_Read_Disable(0);
273 // Set flash chip size
274 esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
275 // TODO: set mode
276 // TODO: set frequency
277 Cache_Flush(0);
278 Cache_Read_Enable(0);
279 }
280
print_flash_info(const esp_image_header_t * bootloader_hdr)281 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
282 {
283 ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
284 ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
285 ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
286 ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
287 ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
288
289 const char *str;
290 switch (bootloader_hdr->spi_speed) {
291 case ESP_IMAGE_SPI_SPEED_DIV_2:
292 str = "40MHz";
293 break;
294 case ESP_IMAGE_SPI_SPEED_DIV_3:
295 str = "26.7MHz";
296 break;
297 case ESP_IMAGE_SPI_SPEED_DIV_4:
298 str = "20MHz";
299 break;
300 case ESP_IMAGE_SPI_SPEED_DIV_1:
301 str = "80MHz";
302 break;
303 default:
304 str = "20MHz";
305 break;
306 }
307 ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
308
309 /* SPI mode could have been set to QIO during boot already,
310 so test the SPI registers not the flash header */
311 uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
312 if (spi_ctrl & SPI_FREAD_QIO) {
313 str = "QIO";
314 } else if (spi_ctrl & SPI_FREAD_QUAD) {
315 str = "QOUT";
316 } else if (spi_ctrl & SPI_FREAD_DIO) {
317 str = "DIO";
318 } else if (spi_ctrl & SPI_FREAD_DUAL) {
319 str = "DOUT";
320 } else if (spi_ctrl & SPI_FASTRD_MODE) {
321 str = "FAST READ";
322 } else {
323 str = "SLOW READ";
324 }
325 ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
326
327 switch (bootloader_hdr->spi_size) {
328 case ESP_IMAGE_FLASH_SIZE_1MB:
329 str = "1MB";
330 break;
331 case ESP_IMAGE_FLASH_SIZE_2MB:
332 str = "2MB";
333 break;
334 case ESP_IMAGE_FLASH_SIZE_4MB:
335 str = "4MB";
336 break;
337 case ESP_IMAGE_FLASH_SIZE_8MB:
338 str = "8MB";
339 break;
340 case ESP_IMAGE_FLASH_SIZE_16MB:
341 str = "16MB";
342 break;
343 default:
344 str = "2MB";
345 break;
346 }
347 ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
348 }
349
bootloader_init_flash_configure(void)350 static void IRAM_ATTR bootloader_init_flash_configure(void)
351 {
352 bootloader_flash_gpio_config(&bootloader_image_hdr);
353 bootloader_flash_dummy_config(&bootloader_image_hdr);
354 bootloader_flash_cs_timing_config();
355 }
356
bootloader_init_spi_flash(void)357 esp_err_t bootloader_init_spi_flash(void)
358 {
359 bootloader_init_flash_configure();
360 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
361 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
362 if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
363 ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
364 return ESP_FAIL;
365 }
366 #endif
367
368 bootloader_flash_unlock();
369
370 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
371 bootloader_enable_qio_mode();
372 #endif
373
374 print_flash_info(&bootloader_image_hdr);
375 update_flash_config(&bootloader_image_hdr);
376 //ensure the flash is write-protected
377 bootloader_enable_wp();
378 return ESP_OK;
379 }
380
