1 /*
2 * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdbool.h>
7 #include <assert.h>
8 #include "string.h"
9 #include "sdkconfig.h"
10 #include "esp_err.h"
11 #include "esp_log.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp32/rom/spi_flash.h"
15 #include "soc/gpio_periph.h"
16 #include "soc/efuse_reg.h"
17 #include "soc/spi_reg.h"
18 #include "soc/soc_caps.h"
19 #include "soc/soc_pins.h"
20 #include "hal/gpio_hal.h"
21 #include "flash_qio_mode.h"
22 #include "bootloader_common.h"
23 #include "bootloader_flash_config.h"
24
bootloader_flash_update_id(void)25 void bootloader_flash_update_id(void)
26 {
27 g_rom_flashchip.device_id = bootloader_read_flash_id();
28 }
29
bootloader_flash_update_size(uint32_t size)30 void bootloader_flash_update_size(uint32_t size)
31 {
32 g_rom_flashchip.chip_size = size;
33 }
34
bootloader_flash_cs_timing_config(void)35 void IRAM_ATTR bootloader_flash_cs_timing_config(void)
36 {
37 SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
38 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
39 SET_PERI_REG_BITS(SPI_CTRL2_REG(0), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
40 SET_PERI_REG_MASK(SPI_USER_REG(1), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
41 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
42 SET_PERI_REG_BITS(SPI_CTRL2_REG(1), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
43 }
44
bootloader_flash_clock_config(const esp_image_header_t * pfhdr)45 void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t* pfhdr)
46 {
47 uint32_t spi_clk_div = 0;
48 switch (pfhdr->spi_speed) {
49 case ESP_IMAGE_SPI_SPEED_80M:
50 spi_clk_div = 1;
51 break;
52 case ESP_IMAGE_SPI_SPEED_40M:
53 spi_clk_div = 2;
54 break;
55 case ESP_IMAGE_SPI_SPEED_26M:
56 spi_clk_div = 3;
57 break;
58 case ESP_IMAGE_SPI_SPEED_20M:
59 spi_clk_div = 4;
60 break;
61 default:
62 break;
63 }
64 esp_rom_spiflash_config_clk(spi_clk_div, 0);
65 esp_rom_spiflash_config_clk(spi_clk_div, 1);
66 }
67
bootloader_flash_gpio_config(const esp_image_header_t * pfhdr)68 void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
69 {
70 uint32_t drv = 2;
71 if (pfhdr->spi_speed == ESP_IMAGE_SPI_SPEED_80M) {
72 drv = 3;
73 }
74
75 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
76
77 if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 ||
78 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 ||
79 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 ||
80 pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
81 // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured
82 // flash clock signal should come from IO MUX.
83 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
84 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
85 } else {
86 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
87 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
88 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
89 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
90 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
91 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
92 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
93 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
94 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
95 esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
96 esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
97 //select pin function gpio
98 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
99 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
100 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
101 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
102 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
103 // flash clock signal should come from IO MUX.
104 // set drive ability for clock
105 gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
106 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
107
108 uint32_t flash_id = g_rom_flashchip.device_id;
109 if (flash_id == FLASH_ID_GD25LQ32C) {
110 // Set drive ability for 1.8v flash in 80Mhz.
111 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S);
112 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S);
113 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S);
114 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S);
115 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
116 SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
117 }
118 }
119 }
120 }
121
bootloader_flash_dummy_config(const esp_image_header_t * pfhdr)122 void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
123 {
124 int spi_cache_dummy = 0;
125 uint32_t modebit = READ_PERI_REG(SPI_CTRL_REG(0));
126 if (modebit & SPI_FASTRD_MODE) {
127 if (modebit & SPI_FREAD_QIO) { //SPI mode is QIO
128 spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
129 } else if (modebit & SPI_FREAD_DIO) { //SPI mode is DIO
130 spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
131 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
132 } else if(modebit & (SPI_FREAD_QUAD | SPI_FREAD_DUAL)) { //SPI mode is QOUT or DIO
133 spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
134 }
135 }
136
137 extern uint8_t g_rom_spiflash_dummy_len_plus[];
138 switch (pfhdr->spi_speed) {
139 case ESP_IMAGE_SPI_SPEED_80M:
140 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
141 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
142 break;
143 case ESP_IMAGE_SPI_SPEED_40M:
144 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
145 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
146 break;
147 case ESP_IMAGE_SPI_SPEED_26M:
148 case ESP_IMAGE_SPI_SPEED_20M:
149 g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
150 g_rom_spiflash_dummy_len_plus[1] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
151 break;
152 default:
153 break;
154 }
155
156 SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + g_rom_spiflash_dummy_len_plus[0],
157 SPI_USR_DUMMY_CYCLELEN_S);
158 }
159
160 #define ESP32_D2WD_WP_GPIO 7 /* ESP32-D2WD & ESP32-PICO-D4 has this GPIO wired to WP pin of flash */
161 #define ESP32_PICO_V3_GPIO 18 /* ESP32-PICO-V3* use this GPIO for WP pin of flash */
162
bootloader_flash_get_wp_pin(void)163 int bootloader_flash_get_wp_pin(void)
164 {
165 #if CONFIG_BOOTLOADER_SPI_CUSTOM_WP_PIN
166 return CONFIG_BOOTLOADER_SPI_WP_PIN; // can be set for bootloader when QIO or QOUT config in use
167 #elif CONFIG_SPIRAM_CUSTOM_SPIWP_SD3_PIN
168 return CONFIG_SPIRAM_SPIWP_SD3_PIN; // can be set for app when DIO or DOUT config used for PSRAM only
169 #else
170 // no custom value, find it based on the package eFuse value
171 uint8_t chip_ver;
172 uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
173 switch(pkg_ver) {
174 case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
175 case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
176 return ESP32_D2WD_WP_GPIO;
177 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
178 /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
179 chip_ver = bootloader_common_get_chip_revision();
180 return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
181 case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
182 return ESP32_PICO_V3_GPIO;
183 default:
184 return SPI_WP_GPIO_NUM;
185 }
186 #endif
187 }
188
