1 /*
2 * Copyright 2016-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_SDMA_H_
10 #define FSL_SDMA_H_
11
12 #include "fsl_common.h"
13 #include "fsl_sdma_script.h"
14
15 /*!
16 * @addtogroup sdma
17 * @{
18 */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*! @{ */
26 /*! @brief SDMA driver version */
27 #define FSL_SDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2. */
28 /*! @} */
29
30 #ifndef SDMA_DRIVER_LOAD_RAM_SCRIPT
31 #define SDMA_DRIVER_LOAD_RAM_SCRIPT (1)
32 #endif
33
34 #ifndef SDMA_DRIVER_LOAD_RAM_SCRIPT
35 #define SDMA_DRIVER_LOAD_RAM_SCRIPT (1)
36 #endif
37
38 /*! @brief SDMA transfer configuration */
39 typedef enum _sdma_transfer_size
40 {
41 kSDMA_TransferSize1Bytes = 0x1U, /*!< Source/Destination data transfer size is 1 byte every time */
42 kSDMA_TransferSize2Bytes = 0x2U, /*!< Source/Destination data transfer size is 2 bytes every time */
43 kSDMA_TransferSize3Bytes = 0x3U, /*!< Source/Destination data transfer size is 3 bytes every time */
44 kSDMA_TransferSize4Bytes = 0x0U, /*!< Source/Destination data transfer size is 4 bytes every time */
45 } sdma_transfer_size_t;
46
47 /*! @brief SDMA buffer descriptor status */
48 typedef enum _sdma_bd_status
49 {
50 kSDMA_BDStatusDone = 0x1U, /*!< BD ownership, 0 means ARM core owns the BD, while 1 means SDMA owns BD. */
51 kSDMA_BDStatusWrap = 0x2U, /*!< While this BD is last one, the next BD will be the first one */
52 kSDMA_BDStatusContinuous = 0x4U, /*!< Buffer is allowed to transfer/receive to/from multiple buffers */
53 kSDMA_BDStatusInterrupt = 0x8U, /*!< While this BD finished, send an interrupt. */
54 kSDMA_BDStatusError = 0x10U, /*!< Error occurred on buffer descriptor command. */
55 kSDMA_BDStatusLast =
56 0x20U, /*!< This BD is the last BD in this array. It means the transfer ended after this buffer */
57 kSDMA_BDStatusExtend = 0x80U, /*!< Buffer descriptor extend status for SDMA scripts */
58 } sdma_bd_status_t;
59
60 /*! @brief SDMA buffer descriptor command */
61 typedef enum _sdma_bd_command
62 {
63 kSDMA_BDCommandSETDM = 0x1U, /*!< Load SDMA data memory from ARM core memory buffer. */
64 kSDMA_BDCommandGETDM = 0x2U, /*!< Copy SDMA data memory to ARM core memory buffer. */
65 kSDMA_BDCommandSETPM = 0x4U, /*!< Load SDMA program memory from ARM core memory buffer. */
66 kSDMA_BDCommandGETPM = 0x6U, /*!< Copy SDMA program memory to ARM core memory buffer. */
67 kSDMA_BDCommandSETCTX = 0x7U, /*!< Load context for one channel into SDMA RAM from ARM platform memory buffer. */
68 kSDMA_BDCommandGETCTX = 0x3U, /*!< Copy context for one channel from SDMA RAM to ARM platform memory buffer. */
69 } sdma_bd_command_t;
70
71 /*! @brief SDMA context switch mode */
72 typedef enum _sdma_context_switch_mode
73 {
74 kSDMA_ContextSwitchModeStatic = 0x0U, /*!< SDMA context switch mode static */
75 kSDMA_ContextSwitchModeDynamicLowPower, /*!< SDMA context switch mode dynamic with low power */
76 kSDMA_ContextSwitchModeDynamicWithNoLoop, /*!< SDMA context switch mode dynamic with no loop */
77 kSDMA_ContextSwitchModeDynamic, /*!< SDMA context switch mode dynamic */
78 } sdma_context_switch_mode_t;
79
80 /*! @brief SDMA core clock frequency ratio to the ARM DMA interface. */
81 typedef enum _sdma_clock_ratio
82 {
83 kSDMA_HalfARMClockFreq = 0x0U, /*!< SDMA core clock frequency half of ARM platform */
84 kSDMA_ARMClockFreq, /*!< SDMA core clock frequency equals to ARM platform */
85 } sdma_clock_ratio_t;
86
87 /*! @brief SDMA transfer type */
88 typedef enum _sdma_transfer_type
89 {
90 kSDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */
91 kSDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */
92 kSDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */
93 kSDMA_PeripheralToPeripheral, /*!< Transfer from peripheral to peripheral */
94 } sdma_transfer_type_t;
95
96 /*! @brief Peripheral type use SDMA */
97 typedef enum sdma_peripheral
98 {
99 kSDMA_PeripheralTypeMemory = 0x0, /*!< Peripheral DDR memory */
100 kSDMA_PeripheralTypeUART, /*!< UART use SDMA */
101 kSDMA_PeripheralTypeUART_SP, /*!< UART instance in SPBA use SDMA */
102 kSDMA_PeripheralTypeSPDIF, /*!< SPDIF use SDMA */
103 kSDMA_PeripheralNormal, /*!< Normal peripheral use SDMA */
104 kSDMA_PeripheralNormal_SP, /*!< Normal peripheral in SPBA use SDMA */
105 kSDMA_PeripheralMultiFifoPDM, /*!< multi fifo PDM */
106 kSDMA_PeripheralMultiFifoSaiRX, /*!< multi fifo sai rx use SDMA */
107 kSDMA_PeripheralMultiFifoSaiTX, /*!< multi fifo sai tx use SDMA */
108 kSDMA_PeripheralASRCM2P, /*!< asrc m2p */
109 kSDMA_PeripheralASRCP2M, /*!< asrc p2m */
110 kSDMA_PeripheralASRCP2P, /*!< asrc p2p */
111 } sdma_peripheral_t;
112
113 /*! @brief _sdma_transfer_status SDMA transfer status */
114 enum
115 {
116 kStatus_SDMA_ERROR = MAKE_STATUS(kStatusGroup_SDMA, 0), /*!< SDMA context error. */
117 kStatus_SDMA_Busy = MAKE_STATUS(kStatusGroup_SDMA, 1), /*!< Channel is busy and can't handle the
118 transfer request. */
119 };
120
121 /*! @brief _sdma_multi_fifo_mask SDMA multi fifo mask */
122 enum
123 {
124 kSDMA_MultiFifoWatermarkLevelMask = 0xFFFU, /*!< multi fifo watermark level mask */
125 kSDMA_MultiFifoNumsMask = 0xFU, /*!< multi fifo nums mask */
126 kSDMA_MultiFifoOffsetMask = 0xFU, /*!< multi fifo offset mask */
127 kSDMA_MultiFifoSwDoneMask = 0x1U, /*!< multi fifo sw done mask */
128 kSDMA_MultiFifoSwDoneSelectorMask = 0xFU, /*!< multi fifo sw done selector mask */
129 };
130
131 /*! @brief _sdma_multi_fifo_shift SDMA multi fifo shift */
132 enum
133 {
134 kSDMA_MultiFifoWatermarkLevelShift = 0U, /*!< multi fifo watermark level shift */
135 kSDMA_MultiFifoNumsShift = 12U, /*!< multi fifo nums shift */
136 kSDMA_MultiFifoOffsetShift = 16U, /*!< multi fifo offset shift */
137 kSDMA_MultiFifoSwDoneShift = 23U, /*!< multi fifo sw done shift */
138 kSDMA_MultiFifoSwDoneSelectorShift = 24U, /*!< multi fifo sw done selector shift */
139 };
140
141 /*! @brief _sdma_done_channel SDMA done channel */
142 enum
143 {
144 kSDMA_DoneChannel0 = 0U, /*!< SDMA done channel 0 */
145 kSDMA_DoneChannel1 = 1U, /*!< SDMA done channel 1 */
146 kSDMA_DoneChannel2 = 2U, /*!< SDMA done channel 2 */
147 kSDMA_DoneChannel3 = 3U, /*!< SDMA done channel 3 */
148 kSDMA_DoneChannel4 = 4U, /*!< SDMA done channel 4 */
149 kSDMA_DoneChannel5 = 5U, /*!< SDMA done channel 5 */
150 kSDMA_DoneChannel6 = 6U, /*!< SDMA done channel 6 */
151 kSDMA_DoneChannel7 = 7U, /*!< SDMA done channel 7 */
152 };
153
154 /*! @brief SDMA done source */
155 typedef enum _sdma_done_src
156 {
157 kSDMA_DoneSrcSW = 0U, /*!< software done */
158 kSDMA_DoneSrcHwEvent0U = 1U, /*!< HW event 0 is used for DONE event */
159 kSDMA_DoneSrcHwEvent1U = 2U, /*!< HW event 1 is used for DONE event */
160 kSDMA_DoneSrcHwEvent2U = 3U, /*!< HW event 2 is used for DONE event */
161 kSDMA_DoneSrcHwEvent3U = 4U, /*!< HW event 3 is used for DONE event */
162 kSDMA_DoneSrcHwEvent4U = 5U, /*!< HW event 4 is used for DONE event */
163 kSDMA_DoneSrcHwEvent5U = 6U, /*!< HW event 5 is used for DONE event */
164 kSDMA_DoneSrCHwEvent6U = 7U, /*!< HW event 6 is used for DONE event */
165 kSDMA_DoneSrcHwEvent7U = 8U, /*!< HW event 7 is used for DONE event */
166 kSDMA_DoneSrcHwEvent8U = 9U, /*!< HW event 8 is used for DONE event */
167 kSDMA_DoneSrcHwEvent9U = 10U, /*!< HW event 9 is used for DONE event */
168 kSDMA_DoneSrcHwEvent10U = 11U, /*!< HW event 10 is used for DONE event */
169 kSDMA_DoneSrcHwEvent11U = 12U, /*!< HW event 11 is used for DONE event */
170 kSDMA_DoneSrcHwEvent12U = 13U, /*!< HW event 12 is used for DONE event */
171 kSDMA_DoneSrcHwEvent13U = 14U, /*!< HW event 13 is used for DONE event */
172 kSDMA_DoneSrcHwEvent14U = 15U, /*!< HW event 14 is used for DONE event */
173 kSDMA_DoneSrcHwEvent15U = 16U, /*!< HW event 15 is used for DONE event */
174 kSDMA_DoneSrcHwEvent16U = 17U, /*!< HW event 16 is used for DONE event */
175 kSDMA_DoneSrcHwEvent17U = 18U, /*!< HW event 17 is used for DONE event */
176 kSDMA_DoneSrcHwEvent18U = 19U, /*!< HW event 18 is used for DONE event */
177 kSDMA_DoneSrcHwEvent19U = 20U, /*!< HW event 19 is used for DONE event */
178 kSDMA_DoneSrcHwEvent20U = 21U, /*!< HW event 20 is used for DONE event */
179 kSDMA_DoneSrcHwEvent21U = 22U, /*!< HW event 21 is used for DONE event */
180 kSDMA_DoneSrcHwEvent22U = 23U, /*!< HW event 22 is used for DONE event */
181 kSDMA_DoneSrcHwEvent23U = 24U, /*!< HW event 23 is used for DONE event */
182 kSDMA_DoneSrcHwEvent24U = 25U, /*!< HW event 24 is used for DONE event */
183 kSDMA_DoneSrcHwEvent25U = 26U, /*!< HW event 25 is used for DONE event */
184 kSDMA_DoneSrcHwEvent26U = 27U, /*!< HW event 26 is used for DONE event */
185 kSDMA_DoneSrcHwEvent27U = 28U, /*!< HW event 27 is used for DONE event */
186 kSDMA_DoneSrcHwEvent28U = 29U, /*!< HW event 28 is used for DONE event */
187 kSDMA_DoneSrcHwEvent29U = 30U, /*!< HW event 29 is used for DONE event */
188 kSDMA_DoneSrcHwEvent30U = 31U, /*!< HW event 30 is used for DONE event */
189 kSDMA_DoneSrcHwEvent31U = 32U, /*!< HW event 31 is used for DONE event */
190 } sdma_done_src_t;
191
192 /*! @brief SDMA global configuration structure.*/
193 typedef struct _sdma_config
194 {
195 bool enableRealTimeDebugPin; /*!< If enable real-time debug pin, default is closed to reduce power consumption.*/
196 bool isSoftwareResetClearLock; /*!< If software reset clears the LOCK bit which prevent writing SDMA scripts into
197 SDMA.*/
198 sdma_clock_ratio_t ratio; /*!< SDMA core clock ratio to ARM platform DMA interface */
199 } sdma_config_t;
200
201 /*! @brief SDMA multi fifo configurations.*/
202 typedef struct _sdma_multi_fifo_config
203 {
204 uint8_t fifoNums; /*!< fifo numbers */
205 uint8_t fifoOffset; /*!< offset between multi fifo data register address */
206 } sdma_multi_fifo_config_t;
207
208 /*! @brief SDMA sw done configurations.*/
209 typedef struct _sdma_sw_done_config
210 {
211 bool enableSwDone; /*!< true is enable sw done, false is disable */
212 uint8_t swDoneSel; /*!< sw done channel number per peripheral type */
213 } sdma_sw_done_config_t;
214
215 /*! @brief SDMA peripheral to peripheral R7 config*/
216 typedef struct _sdma_p2p_config
217 {
218 uint8_t sourceWatermark; /*!< lower watermark value */
219 uint8_t destWatermark; /*!< higher water makr value */
220 bool continuousTransfer; /*!< 0: the amount of samples to be transferred is equal to the cont field of mode word
221 1: the amount of samples to be transferred is unknown and script will keep on
222 transferring as long as both events are detected and script must be stopped by
223 application.*/
224 } sdma_p2p_config_t;
225
226 /*!
227 * @brief SDMA transfer configuration
228 *
229 * This structure configures the source/destination transfer attribute.
230 */
231 typedef struct _sdma_transfer_config
232 {
233 uint32_t srcAddr; /*!< Source address of the transfer */
234 uint32_t destAddr; /*!< Destination address of the transfer */
235 sdma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */
236 sdma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
237 uint32_t bytesPerRequest; /*!< Bytes to transfer in a minor loop*/
238 uint32_t transferSzie; /*!< Bytes to transfer for this descriptor */
239 uint32_t scriptAddr; /*!< SDMA script address located in SDMA ROM. */
240 uint32_t eventSource; /*!< Event source number for the channel. 0 means no event, use software trigger */
241 uint32_t eventSource1; /*!< event source 1 */
242 bool isEventIgnore; /*!< True means software trigger, false means hardware trigger */
243 bool
244 isSoftTriggerIgnore; /*!< If ignore the HE bit, 1 means use hardware events trigger, 0 means software trigger */
245 sdma_transfer_type_t type; /*!< Transfer type, transfer type used to decide the SDMA script. */
246 sdma_multi_fifo_config_t multiFifo; /*!< multi fifo configurations */
247 sdma_sw_done_config_t swDone; /*!< sw done selector */
248 uint32_t watermarkLevel; /*!< watermark level */
249 uint32_t eventMask0; /*!< event mask 0 */
250 uint32_t eventMask1; /*!< event mask 1 */
251
252 } sdma_transfer_config_t;
253
254 /*!
255 * @brief SDMA buffer descriptor structure.
256 *
257 * This structure is a buffer descriptor, this structure describes the buffer start address and other options
258 */
259 typedef struct _sdma_buffer_descriptor
260 {
261 uint32_t count : 16; /*!< Bytes of the buffer length for this buffer descriptor. */
262 uint32_t status : 8; /*!< E,R,I,C,W,D status bits stored here */
263 uint32_t command : 8; /*!< command mostlky used for channel 0 */
264 uint32_t bufferAddr; /*!< Buffer start address for this descriptor. */
265 uint32_t extendBufferAddr; /*!< External buffer start address, this is an optional for a transfer. */
266 } sdma_buffer_descriptor_t;
267
268 /*!
269 * @brief SDMA channel control descriptor structure.
270 */
271 typedef struct _sdma_channel_control
272 {
273 uint32_t currentBDAddr; /*!< Address of current buffer descriptor processed */
274 uint32_t baseBDAddr; /*!< The start address of the buffer descriptor array */
275 uint32_t channelDesc; /*!< Optional for transfer */
276 uint32_t status; /*!< Channel status */
277 } sdma_channel_control_t;
278
279 /*!
280 * @brief SDMA context structure for each channel. This structure can be load into SDMA core, with this structure, SDMA
281 * scripts can start work.
282 */
283 typedef struct _sdma_context_data
284 {
285 uint32_t PC : 14;
286 uint32_t unused1 : 1;
287 uint32_t T : 1;
288 uint32_t RPC : 14;
289 uint32_t unused0 : 1;
290 uint32_t SF : 1;
291 uint32_t SPC : 14;
292 uint32_t unused2 : 1;
293 uint32_t DF : 1;
294 uint32_t EPC : 14;
295 uint32_t LM : 2;
296 uint32_t GeneralReg[8]; /*!< 8 general regsiters used for SDMA RISC core */
297 uint32_t MDA;
298 uint32_t MSA;
299 uint32_t MS;
300 uint32_t MD;
301 uint32_t PDA;
302 uint32_t PSA;
303 uint32_t PS;
304 uint32_t PD;
305 uint32_t CA;
306 uint32_t CS;
307 uint32_t DDA;
308 uint32_t DSA;
309 uint32_t DS;
310 uint32_t DD;
311 uint32_t Scratch0;
312 uint32_t Scratch1;
313 uint32_t Scratch2;
314 uint32_t Scratch3;
315 uint32_t Scratch4;
316 uint32_t Scratch5;
317 uint32_t Scratch6;
318 uint32_t Scratch7;
319 } sdma_context_data_t;
320
321 /*! @brief Callback for SDMA */
322 struct _sdma_handle;
323
324 /*! @brief Define callback function for SDMA. */
325 typedef void (*sdma_callback)(struct _sdma_handle *handle, void *userData, bool transferDone, uint32_t bdIndex);
326
327 /*! @brief SDMA transfer handle structure */
328 typedef struct _sdma_handle
329 {
330 sdma_callback callback; /*!< Callback function for major count exhausted. */
331 void *userData; /*!< Callback function parameter. */
332 SDMAARM_Type *base; /*!< SDMA peripheral base address. */
333 sdma_buffer_descriptor_t *BDPool; /*!< Pointer to memory stored BD arrays. */
334 uint32_t bdCount; /*!< How many buffer descriptor */
335 uint32_t bdIndex; /*!< How many buffer descriptor */
336 uint32_t eventSource; /*!< Event source count for the channel */
337 uint32_t eventSource1; /*!< Event source 1 count for the channel */
338 sdma_context_data_t *context; /*!< Channel context to exectute in SDMA */
339 uint8_t channel; /*!< SDMA channel number. */
340 uint8_t priority; /*!< SDMA channel priority */
341 uint8_t flags; /*!< The status of the current channel. */
342 } sdma_handle_t;
343
344 /*******************************************************************************
345 * APIs
346 ******************************************************************************/
347 #if defined(__cplusplus)
348 extern "C" {
349 #endif /* __cplusplus */
350
351 /*!
352 * @name SDMA initialization and de-initialization
353 * @{
354 */
355
356 /*!
357 * @brief Initializes the SDMA peripheral.
358 *
359 * This function ungates the SDMA clock and configures the SDMA peripheral according
360 * to the configuration structure.
361 *
362 * @param base SDMA peripheral base address.
363 * @param config A pointer to the configuration structure, see "sdma_config_t".
364 * @note This function enables the minor loop map feature.
365 */
366 void SDMA_Init(SDMAARM_Type *base, const sdma_config_t *config);
367
368 /*!
369 * @brief Deinitializes the SDMA peripheral.
370 *
371 * This function gates the SDMA clock.
372 *
373 * @param base SDMA peripheral base address.
374 */
375 void SDMA_Deinit(SDMAARM_Type *base);
376
377 /*!
378 * @brief Gets the SDMA default configuration structure.
379 *
380 * This function sets the configuration structure to default values.
381 * The default configuration is set to the following values.
382 * @code
383 * config.enableRealTimeDebugPin = false;
384 * config.isSoftwareResetClearLock = true;
385 * config.ratio = kSDMA_HalfARMClockFreq;
386 * @endcode
387 *
388 * @param config A pointer to the SDMA configuration structure.
389 */
390 void SDMA_GetDefaultConfig(sdma_config_t *config);
391
392 /*!
393 * @brief Sets all SDMA core register to reset status.
394 *
395 * If only reset ARM core, SDMA register cannot return to reset value, shall call this function to reset all SDMA
396 * register to reset value. But the internal status cannot be reset.
397 *
398 * @param base SDMA peripheral base address.
399 */
400 void SDMA_ResetModule(SDMAARM_Type *base);
401
402 /*! @} */
403 /*!
404 * @name SDMA Channel Operation
405 * @{
406 */
407 /*!
408 * @brief Enables the interrupt source for the SDMA error.
409 *
410 * Enable this will trigger an interrupt while SDMA occurs error while executing scripts.
411 *
412 * @param base SDMA peripheral base address.
413 * @param channel SDMA channel number.
414 */
SDMA_EnableChannelErrorInterrupts(SDMAARM_Type * base,uint32_t channel)415 static inline void SDMA_EnableChannelErrorInterrupts(SDMAARM_Type *base, uint32_t channel)
416 {
417 base->INTRMASK |= (1UL << channel);
418 }
419
420 /*!
421 * @brief Disables the interrupt source for the SDMA error.
422 *
423 * @param base SDMA peripheral base address.
424 * @param channel SDMA channel number.
425 */
SDMA_DisableChannelErrorInterrupts(SDMAARM_Type * base,uint32_t channel)426 static inline void SDMA_DisableChannelErrorInterrupts(SDMAARM_Type *base, uint32_t channel)
427 {
428 base->INTRMASK &= ~(1UL << channel);
429 }
430
431 /*! @} */
432 /*!
433 * @name SDMA Buffer Descriptor Operation
434 * @{
435 */
436
437 /*!
438 * @brief Sets buffer descriptor contents.
439 *
440 * This function sets the descriptor contents such as source, dest address and status bits.
441 *
442 * @param bd Pointer to the buffer descriptor structure.
443 * @param srcAddr Source address for the buffer descriptor.
444 * @param destAddr Destination address for the buffer descriptor.
445 * @param busWidth The transfer width, it only can be a member of sdma_transfer_size_t.
446 * @param bufferSize Buffer size for this descriptor, this number shall less than 0xFFFF. If need to transfer a big
447 * size,
448 * shall divide into several buffer descriptors.
449 * @param isLast Is the buffer descriptor the last one for the channel to transfer. If only one descriptor used for
450 * the channel, this bit shall set to TRUE.
451 * @param enableInterrupt If trigger an interrupt while this buffer descriptor transfer finished.
452 * @param isWrap Is the buffer descriptor need to be wrapped. While this bit set to true, it will automatically wrap
453 * to the first buffer descrtiptor to do transfer.
454 * @param type Transfer type, memory to memory, peripheral to memory or memory to peripheral.
455 */
456 void SDMA_ConfigBufferDescriptor(sdma_buffer_descriptor_t *bd,
457 uint32_t srcAddr,
458 uint32_t destAddr,
459 sdma_transfer_size_t busWidth,
460 size_t bufferSize,
461 bool isLast,
462 bool enableInterrupt,
463 bool isWrap,
464 sdma_transfer_type_t type);
465
466 /*! @} */
467 /*!
468 * @name SDMA Channel Transfer Operation
469 * @{
470 */
471
472 /*!
473 * @brief Set SDMA channel priority.
474 *
475 * This function sets the channel priority. The default value is 0 for all channels, priority 0 will prevents
476 * channel from starting, so the priority must be set before start a channel.
477 *
478 * @param base SDMA peripheral base address.
479 * @param channel SDMA channel number.
480 * @param priority SDMA channel priority.
481 */
SDMA_SetChannelPriority(SDMAARM_Type * base,uint32_t channel,uint8_t priority)482 static inline void SDMA_SetChannelPriority(SDMAARM_Type *base, uint32_t channel, uint8_t priority)
483 {
484 base->SDMA_CHNPRI[channel] = priority;
485 }
486
487 /*!
488 * @brief Set SDMA request source mapping channel.
489 *
490 * This function sets which channel will be triggered by the dma request source.
491 *
492 * @param base SDMA peripheral base address.
493 * @param source SDMA dma request source number.
494 * @param channelMask SDMA channel mask. 1 means channel 0, 2 means channel 1, 4 means channel 3. SDMA supports
495 * an event trigger multi-channel. A channel can also be triggered by several source events.
496 */
SDMA_SetSourceChannel(SDMAARM_Type * base,uint32_t source,uint32_t channelMask)497 static inline void SDMA_SetSourceChannel(SDMAARM_Type *base, uint32_t source, uint32_t channelMask)
498 {
499 base->CHNENBL[source] = channelMask;
500 }
501
502 /*!
503 * @brief Start a SDMA channel by software trigger.
504 *
505 * This function start a channel.
506 *
507 * @param base SDMA peripheral base address.
508 * @param channel SDMA channel number.
509 */
SDMA_StartChannelSoftware(SDMAARM_Type * base,uint32_t channel)510 static inline void SDMA_StartChannelSoftware(SDMAARM_Type *base, uint32_t channel)
511 {
512 base->HSTART = (1UL << channel);
513 }
514
515 /*!
516 * @brief Start a SDMA channel by hardware events.
517 *
518 * This function start a channel.
519 *
520 * @param base SDMA peripheral base address.
521 * @param channel SDMA channel number.
522 */
SDMA_StartChannelEvents(SDMAARM_Type * base,uint32_t channel)523 static inline void SDMA_StartChannelEvents(SDMAARM_Type *base, uint32_t channel)
524 {
525 base->EVTPEND = (1UL << channel);
526 }
527
528 /*!
529 * @brief Stop a SDMA channel.
530 *
531 * This function stops a channel.
532 *
533 * @param base SDMA peripheral base address.
534 * @param channel SDMA channel number.
535 */
SDMA_StopChannel(SDMAARM_Type * base,uint32_t channel)536 static inline void SDMA_StopChannel(SDMAARM_Type *base, uint32_t channel)
537 {
538 base->STOP_STAT = (1UL << channel);
539 }
540
541 /*!
542 * @brief Set the SDMA context switch mode.
543 *
544 * @param base SDMA peripheral base address.
545 * @param mode SDMA context switch mode.
546 */
547 void SDMA_SetContextSwitchMode(SDMAARM_Type *base, sdma_context_switch_mode_t mode);
548
549 /*! @} */
550
551 /*!
552 * @name SDMA Channel Status Operation
553 * @{
554 */
555
556 /*!
557 * @brief Gets the SDMA interrupt status of all channels.
558 *
559 * @param base SDMA peripheral base address.
560 * @return The interrupt status for all channels. Check the relevant bits for specific channel.
561 */
SDMA_GetChannelInterruptStatus(SDMAARM_Type * base)562 static inline uint32_t SDMA_GetChannelInterruptStatus(SDMAARM_Type *base)
563 {
564 return base->INTR;
565 }
566
567 /*!
568 * @brief Clear the SDMA channel interrupt status of specific channels.
569 *
570 * @param base SDMA peripheral base address.
571 * @param mask The interrupt status need to be cleared.
572 */
SDMA_ClearChannelInterruptStatus(SDMAARM_Type * base,uint32_t mask)573 static inline void SDMA_ClearChannelInterruptStatus(SDMAARM_Type *base, uint32_t mask)
574 {
575 base->INTR = mask;
576 }
577
578 /*!
579 * @brief Gets the SDMA stop status of all channels.
580 *
581 * @param base SDMA peripheral base address.
582 * @return The stop status for all channels. Check the relevant bits for specific channel.
583 */
SDMA_GetChannelStopStatus(SDMAARM_Type * base)584 static inline uint32_t SDMA_GetChannelStopStatus(SDMAARM_Type *base)
585 {
586 return base->STOP_STAT;
587 }
588
589 /*!
590 * @brief Clear the SDMA channel stop status of specific channels.
591 *
592 * @param base SDMA peripheral base address.
593 * @param mask The stop status need to be cleared.
594 */
SDMA_ClearChannelStopStatus(SDMAARM_Type * base,uint32_t mask)595 static inline void SDMA_ClearChannelStopStatus(SDMAARM_Type *base, uint32_t mask)
596 {
597 base->STOP_STAT = mask;
598 }
599
600 /*!
601 * @brief Gets the SDMA channel pending status of all channels.
602 *
603 * @param base SDMA peripheral base address.
604 * @return The pending status for all channels. Check the relevant bits for specific channel.
605 */
SDMA_GetChannelPendStatus(SDMAARM_Type * base)606 static inline uint32_t SDMA_GetChannelPendStatus(SDMAARM_Type *base)
607 {
608 return base->EVTPEND;
609 }
610
611 /*!
612 * @brief Clear the SDMA channel pending status of specific channels.
613 *
614 * @param base SDMA peripheral base address.
615 * @param mask The pending status need to be cleared.
616 */
SDMA_ClearChannelPendStatus(SDMAARM_Type * base,uint32_t mask)617 static inline void SDMA_ClearChannelPendStatus(SDMAARM_Type *base, uint32_t mask)
618 {
619 base->EVTPEND = mask;
620 }
621
622 /*!
623 * @brief Gets the SDMA channel error status.
624 *
625 * SDMA channel error flag is asserted while an incoming DMA request was detected and it triggers a channel
626 * that is already pending or being serviced. This probably means there is an overflow of data for that channel.
627 *
628 * @param base SDMA peripheral base address.
629 * @return The error status for all channels. Check the relevant bits for specific channel.
630 */
SDMA_GetErrorStatus(SDMAARM_Type * base)631 static inline uint32_t SDMA_GetErrorStatus(SDMAARM_Type *base)
632 {
633 return base->EVTERR;
634 }
635
636 /*!
637 * @brief Gets the SDMA request source pending status.
638 *
639 * @param base SDMA peripheral base address.
640 * @param source DMA request source number.
641 * @return True means the request source is pending, otherwise not pending.
642 */
643 bool SDMA_GetRequestSourceStatus(SDMAARM_Type *base, uint32_t source);
644
645 /*! @} */
646 /*!
647 * @name SDMA Transactional Operation
648 */
649
650 /*!
651 * @brief Creates the SDMA handle.
652 *
653 * This function is called if using the transactional API for SDMA. This function
654 * initializes the internal state of the SDMA handle.
655 *
656 * @param handle SDMA handle pointer. The SDMA handle stores callback function and parameters.
657 * @param base SDMA peripheral base address.
658 * @param channel SDMA channel number.
659 * @param context Context structure for the channel to download into SDMA. Users shall make sure the context located
660 * in a non-cacheable memory, or it will cause SDMA run fail. Users shall not touch the context contents, it only be
661 * filled by SDMA driver in SDMA_SubmitTransfer function.
662 */
663 void SDMA_CreateHandle(sdma_handle_t *handle, SDMAARM_Type *base, uint32_t channel, sdma_context_data_t *context);
664
665 /*!
666 * @brief Installs the BDs memory pool into the SDMA handle.
667 *
668 * This function is called after the SDMA_CreateHandle to use multi-buffer feature.
669 *
670 * @param handle SDMA handle pointer.
671 * @param BDPool A memory pool to store BDs. It must be located in non-cacheable address.
672 * @param BDCount The number of BD slots.
673 */
674 void SDMA_InstallBDMemory(sdma_handle_t *handle, sdma_buffer_descriptor_t *BDPool, uint32_t BDCount);
675
676 /*!
677 * @brief Installs a callback function for the SDMA transfer.
678 *
679 * This callback is called in the SDMA IRQ handler. Use the callback to do something after
680 * the current major loop transfer completes.
681 *
682 * @param handle SDMA handle pointer.
683 * @param callback SDMA callback function pointer.
684 * @param userData A parameter for the callback function.
685 */
686 void SDMA_SetCallback(sdma_handle_t *handle, sdma_callback callback, void *userData);
687
688 /*!
689 * @brief multi fifo configurations.
690 *
691 * This api is used to support multi fifo for SDMA, if user want to get multi fifo data, then this api
692 * shoule be called before submit transfer.
693 *
694 * @param config transfer configurations.
695 * @param fifoNums fifo numbers that multi fifo operation perform, support up to 15 fifo numbers.
696 * @param fifoOffset fifoOffset = fifo address offset / sizeof(uint32_t) - 1.
697 */
698 void SDMA_SetMultiFifoConfig(sdma_transfer_config_t *config, uint32_t fifoNums, uint32_t fifoOffset);
699
700 /*!
701 * @brief enable sdma sw done feature.
702 *
703 * @deprecated Do not use this function. It has been superceded by @ref SDMA_SetDoneConfig.
704 *
705 * @param base SDMA base.
706 * @param config transfer configurations.
707 * @param sel sw done selector.
708 * @param type peripheral type is used to determine the corresponding peripheral sw done selector bit.
709 */
710 void SDMA_EnableSwDone(SDMAARM_Type *base, sdma_transfer_config_t *config, uint8_t sel, sdma_peripheral_t type);
711
712 /*!
713 * @brief sdma channel done configurations.
714 *
715 * @param base SDMA base.
716 * @param config transfer configurations.
717 * @param type peripheral type.
718 * @param doneSrc reference sdma_done_src_t.
719 */
720 void SDMA_SetDoneConfig(SDMAARM_Type *base,
721 sdma_transfer_config_t *config,
722 sdma_peripheral_t type,
723 sdma_done_src_t doneSrc);
724
725 /*!
726 * @brief load script to sdma program memory.
727 *
728 * @param base SDMA base.
729 * @param destAddr dest script address, should be SDMA program memory address.
730 * @param srcAddr source address of target script.
731 * @param bufferSizeBytes bytes size of script.
732 */
733 void SDMA_LoadScript(SDMAARM_Type *base, uint32_t destAddr, void *srcAddr, size_t bufferSizeBytes);
734
735 /*!
736 * @brief dump script from sdma program memory.
737 *
738 * @param base SDMA base.
739 * @param srcAddr should be SDMA program memory address.
740 * @param destAddr address to store scripts.
741 * @param bufferSizeBytes bytes size of script.
742 */
743 void SDMA_DumpScript(SDMAARM_Type *base, uint32_t srcAddr, void *destAddr, size_t bufferSizeBytes);
744
745 /*!
746 * @brief Get RAM script version.
747 *
748 * @param base SDMA base.
749 * @return The script version of RAM.
750 */
SDMA_GetRamScriptVersion(SDMAARM_Type * base)751 static inline const char * SDMA_GetRamScriptVersion(SDMAARM_Type *base)
752 {
753 return FSL_SDMA_SCRIPT_VERSION;
754 }
755
756 /*!
757 * @brief Prepares the SDMA transfer structure.
758 *
759 * This function prepares the transfer configuration structure according to the user input.
760 *
761 * @param config The user configuration structure of type sdma_transfer_t.
762 * @param srcAddr SDMA transfer source address.
763 * @param destAddr SDMA transfer destination address.
764 * @param srcWidth SDMA transfer source address width(bytes).
765 * @param destWidth SDMA transfer destination address width(bytes).
766 * @param bytesEachRequest SDMA transfer bytes per channel request.
767 * @param transferSize SDMA transfer bytes to be transferred.
768 * @param eventSource Event source number for the transfer, if use software trigger, just write 0.
769 * @param peripheral Peripheral type, used to decide if need to use some special scripts.
770 * @param type SDMA transfer type. Used to decide the correct SDMA script address in SDMA ROM.
771 * @note The data address and the data width must be consistent. For example, if the SRC
772 * is 4 bytes, the source address must be 4 bytes aligned, or it results in
773 * source address error.
774 */
775 void SDMA_PrepareTransfer(sdma_transfer_config_t *config,
776 uint32_t srcAddr,
777 uint32_t destAddr,
778 uint32_t srcWidth,
779 uint32_t destWidth,
780 uint32_t bytesEachRequest,
781 uint32_t transferSize,
782 uint32_t eventSource,
783 sdma_peripheral_t peripheral,
784 sdma_transfer_type_t type);
785
786 /*!
787 * @brief Prepares the SDMA P2P transfer structure.
788 *
789 * This function prepares the transfer configuration structure according to the user input.
790 *
791 * @param config The user configuration structure of type sdma_transfer_t.
792 * @param srcAddr SDMA transfer source address.
793 * @param destAddr SDMA transfer destination address.
794 * @param srcWidth SDMA transfer source address width(bytes).
795 * @param destWidth SDMA transfer destination address width(bytes).
796 * @param bytesEachRequest SDMA transfer bytes per channel request.
797 * @param transferSize SDMA transfer bytes to be transferred.
798 * @param eventSource Event source number for the transfer.
799 * @param eventSource1 Event source1 number for the transfer.
800 * @param peripheral Peripheral type, used to decide if need to use some special scripts.
801 * @param p2p sdma p2p configuration pointer.
802 * @note The data address and the data width must be consistent. For example, if the SRC
803 * is 4 bytes, the source address must be 4 bytes aligned, or it results in
804 * source address error.
805 */
806 void SDMA_PrepareP2PTransfer(sdma_transfer_config_t *config,
807 uint32_t srcAddr,
808 uint32_t destAddr,
809 uint32_t srcWidth,
810 uint32_t destWidth,
811 uint32_t bytesEachRequest,
812 uint32_t transferSize,
813 uint32_t eventSource,
814 uint32_t eventSource1,
815 sdma_peripheral_t peripheral,
816 sdma_p2p_config_t *p2p);
817
818 /*!
819 * @brief Submits the SDMA transfer request.
820 *
821 * This function submits the SDMA transfer request according to the transfer configuration structure.
822 *
823 * @param handle SDMA handle pointer.
824 * @param config Pointer to SDMA transfer configuration structure.
825 */
826 void SDMA_SubmitTransfer(sdma_handle_t *handle, const sdma_transfer_config_t *config);
827
828 /*!
829 * @brief SDMA starts transfer.
830 *
831 * This function enables the channel request. Users can call this function after submitting the transfer request
832 * or before submitting the transfer request.
833 *
834 * @param handle SDMA handle pointer.
835 */
836 void SDMA_StartTransfer(sdma_handle_t *handle);
837
838 /*!
839 * @brief SDMA stops transfer.
840 *
841 * This function disables the channel request to pause the transfer. Users can call SDMA_StartTransfer()
842 * again to resume the transfer.
843 *
844 * @param handle SDMA handle pointer.
845 */
846 void SDMA_StopTransfer(sdma_handle_t *handle);
847
848 /*!
849 * @brief SDMA aborts transfer.
850 *
851 * This function disables the channel request and clear transfer status bits.
852 * Users can submit another transfer after calling this API.
853 *
854 * @param handle DMA handle pointer.
855 */
856 void SDMA_AbortTransfer(sdma_handle_t *handle);
857
858 /*!
859 * @brief Get transferred bytes while not using BD pools.
860 *
861 * This function returns the buffer descriptor count value if not using buffer descriptor.
862 * While do a simple transfer, which only uses one descriptor, the SDMA driver inside handle the
863 * buffer descriptor. In uart receive case, it can tell users how many data already received, also
864 * it can tells users how many data transfferd while error occurred.
865 * Notice, the count would not change while transfer is on-going using default SDMA script.
866 *
867 * @param handle DMA handle pointer.
868 * @return Transferred bytes.
869 */
870 uint32_t SDMA_GetTransferredBytes(sdma_handle_t *handle);
871
872 #if defined FSL_FEATURE_SOC_SPBA_COUNT && (FSL_FEATURE_SOC_SPBA_COUNT > 0)
873 /*!
874 * @brief Judge if address located in SPBA.
875 *
876 * @param addr Address which need to judge.
877 * @retval True means located in SPBA, false means not.
878 */
879 bool SDMA_IsPeripheralInSPBA(uint32_t addr);
880 #endif /* FSL_FEATURE_SOC_SPBA_COUNT */
881
882 /*!
883 * @brief SDMA IRQ handler for complete a buffer descriptor transfer.
884 *
885 * This function clears the interrupt flags and also handle the CCB for the channel.
886 *
887 * @param handle SDMA handle pointer.
888 */
889 void SDMA_HandleIRQ(sdma_handle_t *handle);
890
891 /*! @} */
892
893 #if defined(__cplusplus)
894 }
895 #endif /* __cplusplus */
896
897 /*! @} */
898
899 #endif /*FSL_SDMA_H_*/
900
