1 /*
2 ******************************************************************************
3 * @file asm330lhhxg1_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ASM330LHHXG1 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "asm330lhhxg1_reg.h"
21
22 /**
23 * @defgroup ASM330LHHXG1
24 * @brief This file provides a set of functions needed to drive the
25 * asm330lhhxg1 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ASM330LHHXG1_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
asm330lhhxg1_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak asm330lhhxg1_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL) return -1;
55
56 ret = ctx->read_reg(ctx->handle, reg, data, len);
57
58 return ret;
59 }
60
61 /**
62 * @brief Write generic device register
63 *
64 * @param ctx read / write interface definitions(ptr)
65 * @param reg register to write
66 * @param data pointer to data to write in register reg(ptr)
67 * @param len number of consecutive register to write
68 * @retval interface status (MANDATORY: return 0 -> no Error)
69 *
70 */
asm330lhhxg1_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)71 int32_t __weak asm330lhhxg1_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 if (ctx == NULL) return -1;
77
78 ret = ctx->write_reg(ctx->handle, reg, data, len);
79
80 return ret;
81 }
82
83 /**
84 * @}
85 *
86 */
87
88 /**
89 * @defgroup ASM330LHHXG1_Sensitivity
90 * @brief These functions convert raw-data into engineering units.
91 * @{
92 *
93 */
94
asm330lhhxg1_from_fs2g_to_mg(int16_t lsb)95 float_t asm330lhhxg1_from_fs2g_to_mg(int16_t lsb)
96 {
97 return ((float_t)lsb * 0.061f);
98 }
99
asm330lhhxg1_from_fs4g_to_mg(int16_t lsb)100 float_t asm330lhhxg1_from_fs4g_to_mg(int16_t lsb)
101 {
102 return ((float_t)lsb * 0.122f);
103 }
104
asm330lhhxg1_from_fs8g_to_mg(int16_t lsb)105 float_t asm330lhhxg1_from_fs8g_to_mg(int16_t lsb)
106 {
107 return ((float_t)lsb * 0.244f);
108 }
109
asm330lhhxg1_from_fs16g_to_mg(int16_t lsb)110 float_t asm330lhhxg1_from_fs16g_to_mg(int16_t lsb)
111 {
112 return ((float_t)lsb * 0.488f);
113 }
114
asm330lhhxg1_from_fs125dps_to_mdps(int16_t lsb)115 float_t asm330lhhxg1_from_fs125dps_to_mdps(int16_t lsb)
116 {
117 return ((float_t)lsb * 4.375f);
118 }
119
asm330lhhxg1_from_fs250dps_to_mdps(int16_t lsb)120 float_t asm330lhhxg1_from_fs250dps_to_mdps(int16_t lsb)
121 {
122 return ((float_t)lsb * 8.75f);
123 }
124
asm330lhhxg1_from_fs500dps_to_mdps(int16_t lsb)125 float_t asm330lhhxg1_from_fs500dps_to_mdps(int16_t lsb)
126 {
127 return ((float_t)lsb * 17.50f);
128 }
129
asm330lhhxg1_from_fs1000dps_to_mdps(int16_t lsb)130 float_t asm330lhhxg1_from_fs1000dps_to_mdps(int16_t lsb)
131 {
132 return ((float_t)lsb * 35.0f);
133 }
134
asm330lhhxg1_from_fs2000dps_to_mdps(int16_t lsb)135 float_t asm330lhhxg1_from_fs2000dps_to_mdps(int16_t lsb)
136 {
137 return ((float_t)lsb * 70.0f);
138 }
139
asm330lhhxg1_from_fs4000dps_to_mdps(int16_t lsb)140 float_t asm330lhhxg1_from_fs4000dps_to_mdps(int16_t lsb)
141 {
142 return ((float_t)lsb * 140.0f);
143 }
144
asm330lhhxg1_from_lsb_to_celsius(int16_t lsb)145 float_t asm330lhhxg1_from_lsb_to_celsius(int16_t lsb)
146 {
147 return (((float_t)lsb / 256.0f) + 25.0f);
148 }
149
asm330lhhxg1_from_lsb_to_nsec(int32_t lsb)150 float_t asm330lhhxg1_from_lsb_to_nsec(int32_t lsb)
151 {
152 return ((float_t)lsb * 25000.0f);
153 }
154
155 /**
156 * @}
157 *
158 */
159
160 /**
161 * @defgroup LSM9DS1_Data_generation
162 * @brief This section groups all the functions concerning data
163 * generation
164 * @{
165 *
166 */
167
168 /**
169 * @brief Accelerometer full-scale selection[set]
170 *
171 * @param ctx Read / write interface definitions.(ptr)
172 * @param val Change the values of fs_xl in reg CTRL1_XL
173 * @retval Interface status (MANDATORY: return 0 -> no Error).
174 *
175 */
asm330lhhxg1_xl_full_scale_set(const stmdev_ctx_t * ctx,asm330lhhxg1_fs_xl_t val)176 int32_t asm330lhhxg1_xl_full_scale_set(const stmdev_ctx_t *ctx,
177 asm330lhhxg1_fs_xl_t val)
178 {
179 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
180 int32_t ret;
181
182 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
183 if (ret == 0)
184 {
185 ctrl1_xl.fs_xl = (uint8_t)val;
186 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL,
187 (uint8_t *)&ctrl1_xl, 1);
188 }
189 return ret;
190 }
191
192 /**
193 * @brief Accelerometer full-scale selection.[get]
194 *
195 * @param ctx Read / write interface definitions.(ptr)
196 * @param val Get the values of fs_xl in reg CTRL1_XL
197 * @retval Interface status (MANDATORY: return 0 -> no Error).
198 *
199 */
asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fs_xl_t * val)200 int32_t asm330lhhxg1_xl_full_scale_get(const stmdev_ctx_t *ctx,
201 asm330lhhxg1_fs_xl_t *val)
202 {
203 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
204 int32_t ret;
205
206 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
207 switch (ctrl1_xl.fs_xl)
208 {
209 case ASM330LHHXG1_2g:
210 *val = ASM330LHHXG1_2g;
211 break;
212 case ASM330LHHXG1_16g:
213 *val = ASM330LHHXG1_16g;
214 break;
215 case ASM330LHHXG1_4g:
216 *val = ASM330LHHXG1_4g;
217 break;
218 case ASM330LHHXG1_8g:
219 *val = ASM330LHHXG1_8g;
220 break;
221 default:
222 *val = ASM330LHHXG1_2g;
223 break;
224 }
225 return ret;
226 }
227
228 /**
229 * @brief Accelerometer UI data rate selection.[set]
230 *
231 * @param ctx Read / write interface definitions.(ptr)
232 * @param val Change the values of odr_xl in reg CTRL1_XL
233 * @retval Interface status (MANDATORY: return 0 -> no Error).
234 *
235 */
asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_xl_t val)236 int32_t asm330lhhxg1_xl_data_rate_set(const stmdev_ctx_t *ctx,
237 asm330lhhxg1_odr_xl_t val)
238 {
239 asm330lhhxg1_odr_xl_t odr_xl = val;
240 asm330lhhxg1_emb_fsm_enable_t fsm_enable;
241 asm330lhhxg1_fsm_odr_t fsm_odr;
242 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
243 asm330lhhxg1_mlc_odr_t mlc_odr;
244 uint8_t mlc_enable;
245 int32_t ret;
246
247 /* Check the Finite State Machine data rate constraints */
248 ret = asm330lhhxg1_fsm_enable_get(ctx, &fsm_enable);
249 if (ret == 0)
250 {
251 if ((fsm_enable.fsm_enable_a.fsm1_en |
252 fsm_enable.fsm_enable_a.fsm2_en |
253 fsm_enable.fsm_enable_a.fsm3_en |
254 fsm_enable.fsm_enable_a.fsm4_en |
255 fsm_enable.fsm_enable_a.fsm5_en |
256 fsm_enable.fsm_enable_a.fsm6_en |
257 fsm_enable.fsm_enable_a.fsm7_en |
258 fsm_enable.fsm_enable_a.fsm8_en |
259 fsm_enable.fsm_enable_b.fsm9_en |
260 fsm_enable.fsm_enable_b.fsm10_en |
261 fsm_enable.fsm_enable_b.fsm11_en |
262 fsm_enable.fsm_enable_b.fsm12_en |
263 fsm_enable.fsm_enable_b.fsm13_en |
264 fsm_enable.fsm_enable_b.fsm14_en |
265 fsm_enable.fsm_enable_b.fsm15_en |
266 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
267 {
268
269 ret = asm330lhhxg1_fsm_data_rate_get(ctx, &fsm_odr);
270 if (ret == 0)
271 {
272 switch (fsm_odr)
273 {
274 case ASM330LHHXG1_ODR_FSM_12Hz5:
275
276 if (val == ASM330LHHXG1_XL_ODR_OFF)
277 {
278 odr_xl = ASM330LHHXG1_XL_ODR_12Hz5;
279
280 }
281 else
282 {
283 odr_xl = val;
284 }
285 break;
286 case ASM330LHHXG1_ODR_FSM_26Hz:
287
288 if (val == ASM330LHHXG1_XL_ODR_OFF)
289 {
290 odr_xl = ASM330LHHXG1_XL_ODR_26Hz;
291
292 }
293 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
294 {
295 odr_xl = ASM330LHHXG1_XL_ODR_26Hz;
296
297 }
298 else
299 {
300 odr_xl = val;
301 }
302 break;
303 case ASM330LHHXG1_ODR_FSM_52Hz:
304
305 if (val == ASM330LHHXG1_XL_ODR_OFF)
306 {
307 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
308
309 }
310 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
311 {
312 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
313
314 }
315 else if (val == ASM330LHHXG1_XL_ODR_26Hz)
316 {
317 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
318
319 }
320 else
321 {
322 odr_xl = val;
323 }
324 break;
325 case ASM330LHHXG1_ODR_FSM_104Hz:
326
327 if (val == ASM330LHHXG1_XL_ODR_OFF)
328 {
329 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
330
331 }
332 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
333 {
334 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
335
336 }
337 else if (val == ASM330LHHXG1_XL_ODR_26Hz)
338 {
339 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
340
341 }
342 else if (val == ASM330LHHXG1_XL_ODR_52Hz)
343 {
344 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
345
346 }
347 else
348 {
349 odr_xl = val;
350 }
351 break;
352 default:
353 odr_xl = val;
354 break;
355 }
356 }
357 }
358 }
359
360 /* Check the Machine Learning Core data rate constraints */
361 mlc_enable = PROPERTY_DISABLE;
362 if (ret == 0)
363 {
364 ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable);
365 if (mlc_enable == PROPERTY_ENABLE)
366 {
367
368 ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr);
369 if (ret == 0)
370 {
371 switch (mlc_odr)
372 {
373 case ASM330LHHXG1_ODR_PRGS_12Hz5:
374
375 if (val == ASM330LHHXG1_XL_ODR_OFF)
376 {
377 odr_xl = ASM330LHHXG1_XL_ODR_12Hz5;
378
379 }
380 else
381 {
382 odr_xl = val;
383 }
384 break;
385 case ASM330LHHXG1_ODR_PRGS_26Hz:
386 if (val == ASM330LHHXG1_XL_ODR_OFF)
387 {
388 odr_xl = ASM330LHHXG1_XL_ODR_26Hz;
389
390 }
391 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
392 {
393 odr_xl = ASM330LHHXG1_XL_ODR_26Hz;
394
395 }
396 else
397 {
398 odr_xl = val;
399 }
400 break;
401 case ASM330LHHXG1_ODR_PRGS_52Hz:
402
403 if (val == ASM330LHHXG1_XL_ODR_OFF)
404 {
405 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
406
407 }
408 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
409 {
410 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
411
412 }
413 else if (val == ASM330LHHXG1_XL_ODR_26Hz)
414 {
415 odr_xl = ASM330LHHXG1_XL_ODR_52Hz;
416
417 }
418 else
419 {
420 odr_xl = val;
421 }
422 break;
423 case ASM330LHHXG1_ODR_PRGS_104Hz:
424 if (val == ASM330LHHXG1_XL_ODR_OFF)
425 {
426 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
427
428 }
429 else if (val == ASM330LHHXG1_XL_ODR_12Hz5)
430 {
431 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
432
433 }
434 else if (val == ASM330LHHXG1_XL_ODR_26Hz)
435 {
436 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
437
438 }
439 else if (val == ASM330LHHXG1_XL_ODR_52Hz)
440 {
441 odr_xl = ASM330LHHXG1_XL_ODR_104Hz;
442
443 }
444 else
445 {
446 odr_xl = val;
447 }
448 break;
449 default:
450 odr_xl = val;
451 break;
452 }
453 }
454 }
455 }
456
457 if (ret == 0)
458 {
459 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
460 }
461 if (ret == 0)
462 {
463 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
464 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL,
465 (uint8_t *)&ctrl1_xl, 1);
466 }
467 return ret;
468 }
469
470 /**
471 * @brief Accelerometer UI data rate selection.[get]
472 *
473 * @param ctx Read / write interface definitions.(ptr)
474 * @param val Get the values of odr_xl in reg CTRL1_XL
475 * @retval Interface status (MANDATORY: return 0 -> no Error).
476 *
477 */
asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_xl_t * val)478 int32_t asm330lhhxg1_xl_data_rate_get(const stmdev_ctx_t *ctx,
479 asm330lhhxg1_odr_xl_t *val)
480 {
481 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
482 int32_t ret;
483
484 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
485 switch (ctrl1_xl.odr_xl)
486 {
487 case ASM330LHHXG1_XL_ODR_OFF:
488 *val = ASM330LHHXG1_XL_ODR_OFF;
489 break;
490 case ASM330LHHXG1_XL_ODR_12Hz5:
491 *val = ASM330LHHXG1_XL_ODR_12Hz5;
492 break;
493 case ASM330LHHXG1_XL_ODR_26Hz:
494 *val = ASM330LHHXG1_XL_ODR_26Hz;
495 break;
496 case ASM330LHHXG1_XL_ODR_52Hz:
497 *val = ASM330LHHXG1_XL_ODR_52Hz;
498 break;
499 case ASM330LHHXG1_XL_ODR_104Hz:
500 *val = ASM330LHHXG1_XL_ODR_104Hz;
501 break;
502 case ASM330LHHXG1_XL_ODR_208Hz:
503 *val = ASM330LHHXG1_XL_ODR_208Hz;
504 break;
505 case ASM330LHHXG1_XL_ODR_417Hz:
506 *val = ASM330LHHXG1_XL_ODR_417Hz;
507 break;
508 case ASM330LHHXG1_XL_ODR_833Hz:
509 *val = ASM330LHHXG1_XL_ODR_833Hz;
510 break;
511 case ASM330LHHXG1_XL_ODR_1667Hz:
512 *val = ASM330LHHXG1_XL_ODR_1667Hz;
513 break;
514 case ASM330LHHXG1_XL_ODR_3333Hz:
515 *val = ASM330LHHXG1_XL_ODR_3333Hz;
516 break;
517 case ASM330LHHXG1_XL_ODR_6667Hz:
518 *val = ASM330LHHXG1_XL_ODR_6667Hz;
519 break;
520 case ASM330LHHXG1_XL_ODR_1Hz6:
521 *val = ASM330LHHXG1_XL_ODR_1Hz6;
522 break;
523 default:
524 *val = ASM330LHHXG1_XL_ODR_OFF;
525 break;
526 }
527 return ret;
528 }
529
530 /**
531 * @brief Gyroscope UI chain full-scale selection.[set]
532 *
533 * @param ctx Read / write interface definitions.(ptr)
534 * @param val Change the values of fs_g in reg CTRL2_G
535 * @retval Interface status (MANDATORY: return 0 -> no Error).
536 *
537 */
asm330lhhxg1_gy_full_scale_set(const stmdev_ctx_t * ctx,asm330lhhxg1_fs_g_t val)538 int32_t asm330lhhxg1_gy_full_scale_set(const stmdev_ctx_t *ctx,
539 asm330lhhxg1_fs_g_t val)
540 {
541 asm330lhhxg1_ctrl2_g_t ctrl2_g;
542 int32_t ret;
543
544 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
545 if (ret == 0)
546 {
547 ctrl2_g.fs_g = (uint8_t)val;
548 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
549 }
550 return ret;
551 }
552
553 /**
554 * @brief Gyroscope UI chain full-scale selection.[get]
555 *
556 * @param ctx Read / write interface definitions.(ptr)
557 * @param val Get the values of fs_g in reg CTRL2_G
558 * @retval Interface status (MANDATORY: return 0 -> no Error).
559 *
560 */
asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fs_g_t * val)561 int32_t asm330lhhxg1_gy_full_scale_get(const stmdev_ctx_t *ctx,
562 asm330lhhxg1_fs_g_t *val)
563 {
564 asm330lhhxg1_ctrl2_g_t ctrl2_g;
565 int32_t ret;
566
567 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
568 switch (ctrl2_g.fs_g)
569 {
570 case ASM330LHHXG1_125dps:
571 *val = ASM330LHHXG1_125dps;
572 break;
573 case ASM330LHHXG1_250dps:
574 *val = ASM330LHHXG1_250dps;
575 break;
576 case ASM330LHHXG1_500dps:
577 *val = ASM330LHHXG1_500dps;
578 break;
579 case ASM330LHHXG1_1000dps:
580 *val = ASM330LHHXG1_1000dps;
581 break;
582 case ASM330LHHXG1_2000dps:
583 *val = ASM330LHHXG1_2000dps;
584 break;
585 case ASM330LHHXG1_4000dps:
586 *val = ASM330LHHXG1_4000dps;
587 break;
588 default:
589 *val = ASM330LHHXG1_125dps;
590 break;
591 }
592 return ret;
593 }
594
595 /**
596 * @brief Gyroscope data rate.[set]
597 *
598 * @param ctx Read / write interface definitions.(ptr)
599 * @param val Change the values of odr_g in reg CTRL2_G
600 * @retval Interface status (MANDATORY: return 0 -> no Error).
601 *
602 */
asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_g_t val)603 int32_t asm330lhhxg1_gy_data_rate_set(const stmdev_ctx_t *ctx,
604 asm330lhhxg1_odr_g_t val)
605 {
606 asm330lhhxg1_odr_g_t odr_gy = val;
607 asm330lhhxg1_emb_fsm_enable_t fsm_enable;
608 asm330lhhxg1_fsm_odr_t fsm_odr;
609 asm330lhhxg1_ctrl2_g_t ctrl2_g;
610 asm330lhhxg1_mlc_odr_t mlc_odr;
611 uint8_t mlc_enable;
612 int32_t ret;
613
614 /* Check the Finite State Machine data rate constraints */
615 ret = asm330lhhxg1_fsm_enable_get(ctx, &fsm_enable);
616 if (ret == 0)
617 {
618 if ((fsm_enable.fsm_enable_a.fsm1_en |
619 fsm_enable.fsm_enable_a.fsm2_en |
620 fsm_enable.fsm_enable_a.fsm3_en |
621 fsm_enable.fsm_enable_a.fsm4_en |
622 fsm_enable.fsm_enable_a.fsm5_en |
623 fsm_enable.fsm_enable_a.fsm6_en |
624 fsm_enable.fsm_enable_a.fsm7_en |
625 fsm_enable.fsm_enable_a.fsm8_en |
626 fsm_enable.fsm_enable_b.fsm9_en |
627 fsm_enable.fsm_enable_b.fsm10_en |
628 fsm_enable.fsm_enable_b.fsm11_en |
629 fsm_enable.fsm_enable_b.fsm12_en |
630 fsm_enable.fsm_enable_b.fsm13_en |
631 fsm_enable.fsm_enable_b.fsm14_en |
632 fsm_enable.fsm_enable_b.fsm15_en |
633 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
634 {
635
636 ret = asm330lhhxg1_fsm_data_rate_get(ctx, &fsm_odr);
637 if (ret == 0)
638 {
639 switch (fsm_odr)
640 {
641 case ASM330LHHXG1_ODR_FSM_12Hz5:
642
643 if (val == ASM330LHHXG1_GY_ODR_OFF)
644 {
645 odr_gy = ASM330LHHXG1_GY_ODR_12Hz5;
646
647 }
648 else
649 {
650 odr_gy = val;
651 }
652 break;
653 case ASM330LHHXG1_ODR_FSM_26Hz:
654
655 if (val == ASM330LHHXG1_GY_ODR_OFF)
656 {
657 odr_gy = ASM330LHHXG1_GY_ODR_26Hz;
658
659 }
660 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
661 {
662 odr_gy = ASM330LHHXG1_GY_ODR_26Hz;
663
664 }
665 else
666 {
667 odr_gy = val;
668 }
669 break;
670 case ASM330LHHXG1_ODR_FSM_52Hz:
671
672 if (val == ASM330LHHXG1_GY_ODR_OFF)
673 {
674 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
675
676 }
677 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
678 {
679 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
680
681 }
682 else if (val == ASM330LHHXG1_GY_ODR_26Hz)
683 {
684 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
685
686 }
687 else
688 {
689 odr_gy = val;
690 }
691 break;
692 case ASM330LHHXG1_ODR_FSM_104Hz:
693
694 if (val == ASM330LHHXG1_GY_ODR_OFF)
695 {
696 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
697
698 }
699 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
700 {
701 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
702
703 }
704 else if (val == ASM330LHHXG1_GY_ODR_26Hz)
705 {
706 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
707
708 }
709 else if (val == ASM330LHHXG1_GY_ODR_52Hz)
710 {
711 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
712
713 }
714 else
715 {
716 odr_gy = val;
717 }
718 break;
719 default:
720 odr_gy = val;
721 break;
722 }
723 }
724 }
725 }
726
727 /* Check the Machine Learning Core data rate constraints */
728 mlc_enable = PROPERTY_DISABLE;
729 if (ret == 0)
730 {
731 ret = asm330lhhxg1_mlc_get(ctx, &mlc_enable);
732 if (mlc_enable == PROPERTY_ENABLE)
733 {
734
735 ret = asm330lhhxg1_mlc_data_rate_get(ctx, &mlc_odr);
736 if (ret == 0)
737 {
738 switch (mlc_odr)
739 {
740 case ASM330LHHXG1_ODR_PRGS_12Hz5:
741
742 if (val == ASM330LHHXG1_GY_ODR_OFF)
743 {
744 odr_gy = ASM330LHHXG1_GY_ODR_12Hz5;
745
746 }
747 else
748 {
749 odr_gy = val;
750 }
751 break;
752 case ASM330LHHXG1_ODR_PRGS_26Hz:
753
754 if (val == ASM330LHHXG1_GY_ODR_OFF)
755 {
756 odr_gy = ASM330LHHXG1_GY_ODR_26Hz;
757
758 }
759 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
760 {
761 odr_gy = ASM330LHHXG1_GY_ODR_26Hz;
762
763 }
764 else
765 {
766 odr_gy = val;
767 }
768 break;
769 case ASM330LHHXG1_ODR_PRGS_52Hz:
770
771 if (val == ASM330LHHXG1_GY_ODR_OFF)
772 {
773 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
774
775 }
776 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
777 {
778 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
779
780 }
781 else if (val == ASM330LHHXG1_GY_ODR_26Hz)
782 {
783 odr_gy = ASM330LHHXG1_GY_ODR_52Hz;
784
785 }
786 else
787 {
788 odr_gy = val;
789 }
790 break;
791 case ASM330LHHXG1_ODR_PRGS_104Hz:
792
793 if (val == ASM330LHHXG1_GY_ODR_OFF)
794 {
795 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
796
797 }
798 else if (val == ASM330LHHXG1_GY_ODR_12Hz5)
799 {
800 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
801
802 }
803 else if (val == ASM330LHHXG1_GY_ODR_26Hz)
804 {
805 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
806
807 }
808 else if (val == ASM330LHHXG1_GY_ODR_52Hz)
809 {
810 odr_gy = ASM330LHHXG1_GY_ODR_104Hz;
811
812 }
813 else
814 {
815 odr_gy = val;
816 }
817 break;
818 default:
819 odr_gy = val;
820 break;
821 }
822 }
823 }
824 }
825
826 if (ret == 0)
827 {
828 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
829 }
830 if (ret == 0)
831 {
832 ctrl2_g.odr_g = (uint8_t)odr_gy;
833 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
834 }
835 return ret;
836 }
837
838 /**
839 * @brief Gyroscope data rate.[get]
840 *
841 * @param ctx Read / write interface definitions.(ptr)
842 * @param val Get the values of odr_g in reg CTRL2_G
843 * @retval Interface status (MANDATORY: return 0 -> no Error).
844 *
845 */
asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_g_t * val)846 int32_t asm330lhhxg1_gy_data_rate_get(const stmdev_ctx_t *ctx,
847 asm330lhhxg1_odr_g_t *val)
848 {
849 asm330lhhxg1_ctrl2_g_t ctrl2_g;
850 int32_t ret;
851
852 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
853 switch (ctrl2_g.odr_g)
854 {
855 case ASM330LHHXG1_GY_ODR_OFF:
856 *val = ASM330LHHXG1_GY_ODR_OFF;
857 break;
858 case ASM330LHHXG1_GY_ODR_12Hz5:
859 *val = ASM330LHHXG1_GY_ODR_12Hz5;
860 break;
861 case ASM330LHHXG1_GY_ODR_26Hz:
862 *val = ASM330LHHXG1_GY_ODR_26Hz;
863 break;
864 case ASM330LHHXG1_GY_ODR_52Hz:
865 *val = ASM330LHHXG1_GY_ODR_52Hz;
866 break;
867 case ASM330LHHXG1_GY_ODR_104Hz:
868 *val = ASM330LHHXG1_GY_ODR_104Hz;
869 break;
870 case ASM330LHHXG1_GY_ODR_208Hz:
871 *val = ASM330LHHXG1_GY_ODR_208Hz;
872 break;
873 case ASM330LHHXG1_GY_ODR_417Hz:
874 *val = ASM330LHHXG1_GY_ODR_417Hz;
875 break;
876 case ASM330LHHXG1_GY_ODR_833Hz:
877 *val = ASM330LHHXG1_GY_ODR_833Hz;
878 break;
879 case ASM330LHHXG1_GY_ODR_1667Hz:
880 *val = ASM330LHHXG1_GY_ODR_1667Hz;
881 break;
882 case ASM330LHHXG1_GY_ODR_3333Hz:
883 *val = ASM330LHHXG1_GY_ODR_3333Hz;
884 break;
885 case ASM330LHHXG1_GY_ODR_6667Hz:
886 *val = ASM330LHHXG1_GY_ODR_6667Hz;
887 break;
888 default:
889 *val = ASM330LHHXG1_GY_ODR_OFF;
890 break;
891 }
892 return ret;
893 }
894
895 /**
896 * @brief Block data update.[set]
897 *
898 * @param ctx Read / write interface definitions.(ptr)
899 * @param val Change the values of bdu in reg CTRL3_C
900 * @retval Interface status (MANDATORY: return 0 -> no Error).
901 *
902 */
asm330lhhxg1_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)903 int32_t asm330lhhxg1_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
904 {
905 asm330lhhxg1_ctrl3_c_t ctrl3_c;
906 int32_t ret;
907
908 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
909 if (ret == 0)
910 {
911 ctrl3_c.bdu = (uint8_t)val;
912 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
913 }
914 return ret;
915 }
916
917 /**
918 * @brief Block data update.[get]
919 *
920 * @param ctx Read / write interface definitions.(ptr)
921 * @param val Change the values of bdu in reg CTRL3_C
922 * @retval Interface status (MANDATORY: return 0 -> no Error).
923 *
924 */
asm330lhhxg1_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)925 int32_t asm330lhhxg1_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
926 {
927 asm330lhhxg1_ctrl3_c_t ctrl3_c;
928 int32_t ret;
929
930 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
931 *val = ctrl3_c.bdu;
932
933 return ret;
934 }
935
936 /**
937 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
938 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
939 *
940 * @param ctx Read / write interface definitions.(ptr)
941 * @param val Change the values of usr_off_w in reg CTRL6_C
942 * @retval Interface status (MANDATORY: return 0 -> no Error).
943 *
944 */
asm330lhhxg1_xl_offset_weight_set(const stmdev_ctx_t * ctx,asm330lhhxg1_usr_off_w_t val)945 int32_t asm330lhhxg1_xl_offset_weight_set(const stmdev_ctx_t *ctx,
946 asm330lhhxg1_usr_off_w_t val)
947 {
948 asm330lhhxg1_ctrl6_c_t ctrl6_c;
949 int32_t ret;
950
951 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
952 if (ret == 0)
953 {
954 ctrl6_c.usr_off_w = (uint8_t)val;
955 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
956 }
957 return ret;
958 }
959
960 /**
961 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
962 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
963 *
964 * @param ctx Read / write interface definitions.(ptr)
965 * @param val Get the values of usr_off_w in reg CTRL6_C
966 * @retval Interface status (MANDATORY: return 0 -> no Error).
967 *
968 */
asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t * ctx,asm330lhhxg1_usr_off_w_t * val)969 int32_t asm330lhhxg1_xl_offset_weight_get(const stmdev_ctx_t *ctx,
970 asm330lhhxg1_usr_off_w_t *val)
971 {
972 asm330lhhxg1_ctrl6_c_t ctrl6_c;
973 int32_t ret;
974
975 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
976
977 switch (ctrl6_c.usr_off_w)
978 {
979 case ASM330LHHXG1_LSb_1mg:
980 *val = ASM330LHHXG1_LSb_1mg;
981 break;
982 case ASM330LHHXG1_LSb_16mg:
983 *val = ASM330LHHXG1_LSb_16mg;
984 break;
985 default:
986 *val = ASM330LHHXG1_LSb_1mg;
987 break;
988 }
989 return ret;
990 }
991
992 /**
993 * @brief Accelerometer power mode.[set]
994 *
995 * @param ctx Read / write interface definitions.(ptr)
996 * @param val Change the values of xl_hm_mode in reg CTRL6_C
997 * @retval Interface status (MANDATORY: return 0 -> no Error).
998 *
999 */
asm330lhhxg1_xl_power_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_xl_hm_mode_t val)1000 int32_t asm330lhhxg1_xl_power_mode_set(const stmdev_ctx_t *ctx,
1001 asm330lhhxg1_xl_hm_mode_t val)
1002 {
1003 asm330lhhxg1_ctrl6_c_t ctrl6_c;
1004 int32_t ret;
1005
1006 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1007 if (ret == 0)
1008 {
1009 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1010 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1011 }
1012 return ret;
1013 }
1014
1015 /**
1016 * @brief Accelerometer power mode[get]
1017 *
1018 * @param ctx Read / write interface definitions.(ptr)
1019 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1020 * @retval Interface status (MANDATORY: return 0 -> no Error).
1021 *
1022 */
asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_xl_hm_mode_t * val)1023 int32_t asm330lhhxg1_xl_power_mode_get(const stmdev_ctx_t *ctx,
1024 asm330lhhxg1_xl_hm_mode_t *val)
1025 {
1026 asm330lhhxg1_ctrl6_c_t ctrl6_c;
1027 int32_t ret;
1028
1029 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1030 switch (ctrl6_c.xl_hm_mode)
1031 {
1032 case ASM330LHHXG1_HIGH_PERFORMANCE_MD:
1033 *val = ASM330LHHXG1_HIGH_PERFORMANCE_MD;
1034 break;
1035 case ASM330LHHXG1_LOW_NORMAL_POWER_MD:
1036 *val = ASM330LHHXG1_LOW_NORMAL_POWER_MD;
1037 break;
1038 default:
1039 *val = ASM330LHHXG1_HIGH_PERFORMANCE_MD;
1040 break;
1041 }
1042 return ret;
1043 }
1044
1045 /**
1046 * @brief Operating mode for gyroscope.[set]
1047 *
1048 * @param ctx Read / write interface definitions.(ptr)
1049 * @param val Change the values of g_hm_mode in reg CTRL7_G
1050 * @retval Interface status (MANDATORY: return 0 -> no Error).
1051 *
1052 */
asm330lhhxg1_gy_power_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_g_hm_mode_t val)1053 int32_t asm330lhhxg1_gy_power_mode_set(const stmdev_ctx_t *ctx,
1054 asm330lhhxg1_g_hm_mode_t val)
1055 {
1056 asm330lhhxg1_ctrl7_g_t ctrl7_g;
1057 int32_t ret;
1058
1059 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1060 if (ret == 0)
1061 {
1062 ctrl7_g.g_hm_mode = (uint8_t)val;
1063 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1064 }
1065 return ret;
1066 }
1067
1068 /**
1069 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1070 *
1071 * @param ctx Read / write interface definitions.(ptr)
1072 * @param val Get the values of g_hm_mode in reg CTRL7_G
1073 * @retval Interface status (MANDATORY: return 0 -> no Error).
1074 *
1075 */
asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_g_hm_mode_t * val)1076 int32_t asm330lhhxg1_gy_power_mode_get(const stmdev_ctx_t *ctx,
1077 asm330lhhxg1_g_hm_mode_t *val)
1078 {
1079 asm330lhhxg1_ctrl7_g_t ctrl7_g;
1080 int32_t ret;
1081
1082 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1083 switch (ctrl7_g.g_hm_mode)
1084 {
1085 case ASM330LHHXG1_GY_HIGH_PERFORMANCE:
1086 *val = ASM330LHHXG1_GY_HIGH_PERFORMANCE;
1087 break;
1088 case ASM330LHHXG1_GY_NORMAL:
1089 *val = ASM330LHHXG1_GY_NORMAL;
1090 break;
1091 default:
1092 *val = ASM330LHHXG1_GY_HIGH_PERFORMANCE;
1093 break;
1094 }
1095 return ret;
1096 }
1097
1098 /**
1099 * @brief Read all the interrupt flag of the device.
1100 *[get]
1101 * @param ctx Read / write interface definitions.(ptr)
1102 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1103 * TAP_SRC; D6D_SRC; STATUS_REG;
1104 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1105 * @retval Interface status (MANDATORY: return 0 -> no Error).
1106 *
1107 */
asm330lhhxg1_all_sources_get(const stmdev_ctx_t * ctx,asm330lhhxg1_all_sources_t * val)1108 int32_t asm330lhhxg1_all_sources_get(const stmdev_ctx_t *ctx,
1109 asm330lhhxg1_all_sources_t *val)
1110 {
1111 int32_t ret;
1112
1113 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_ALL_INT_SRC,
1114 (uint8_t *)&val->all_int_src, 1);
1115 if (ret == 0)
1116 {
1117 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_SRC,
1118 (uint8_t *)&val->wake_up_src, 1);
1119 }
1120 if (ret == 0)
1121 {
1122 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_D6D_SRC,
1123 (uint8_t *)&val->d6d_src, 1);
1124 }
1125 if (ret == 0)
1126 {
1127 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG,
1128 (uint8_t *)&val->status_reg, 1);
1129 }
1130 if (ret == 0)
1131 {
1132 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
1133 }
1134 if (ret == 0)
1135 {
1136 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_STATUS,
1137 (uint8_t *)&val->emb_func_status, 1);
1138 }
1139 if (ret == 0)
1140 {
1141 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_A,
1142 (uint8_t *)&val->fsm_status_a, 1);
1143 }
1144 if (ret == 0)
1145 {
1146 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B,
1147 (uint8_t *)&val->fsm_status_b, 1);
1148 }
1149 if (ret == 0)
1150 {
1151 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_STATUS,
1152 (uint8_t *)&val->mlc_status, 1);
1153 }
1154 if (ret == 0)
1155 {
1156 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
1157 }
1158
1159 return ret;
1160 }
1161
1162 /**
1163 * @brief The STATUS_REG register is read by the primary interface.[get]
1164 *
1165 * @param ctx Read / write interface definitions.(ptr)
1166 * @param val Get register STATUS_REG
1167 * @retval Interface status (MANDATORY: return 0 -> no Error).
1168 *
1169 */
asm330lhhxg1_status_reg_get(const stmdev_ctx_t * ctx,asm330lhhxg1_status_reg_t * val)1170 int32_t asm330lhhxg1_status_reg_get(const stmdev_ctx_t *ctx,
1171 asm330lhhxg1_status_reg_t *val)
1172 {
1173 int32_t ret;
1174 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG, (uint8_t *) val, 1);
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Accelerometer new data available.[get]
1180 *
1181 * @param ctx Read / write interface definitions.(ptr)
1182 * @param val Get the values of xlda in reg STATUS_REG
1183 * @retval Interface status (MANDATORY: return 0 -> no Error).
1184 *
1185 */
asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1186 int32_t asm330lhhxg1_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1187 {
1188 asm330lhhxg1_status_reg_t status_reg;
1189 int32_t ret;
1190
1191 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG,
1192 (uint8_t *)&status_reg, 1);
1193 *val = status_reg.xlda;
1194
1195 return ret;
1196 }
1197
1198 /**
1199 * @brief Gyroscope new data available.[get]
1200 *
1201 * @param ctx Read / write interface definitions.(ptr)
1202 * @param val Get the values of gda in reg STATUS_REG
1203 * @retval Interface status (MANDATORY: return 0 -> no Error).
1204 *
1205 */
asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1206 int32_t asm330lhhxg1_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1207 {
1208 asm330lhhxg1_status_reg_t status_reg;
1209 int32_t ret;
1210
1211 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG,
1212 (uint8_t *)&status_reg, 1);
1213 *val = status_reg.gda;
1214
1215 return ret;
1216 }
1217
1218 /**
1219 * @brief Temperature new data available.[get]
1220 *
1221 * @param ctx Read / write interface definitions.(ptr)
1222 * @param val Get the values of tda in reg STATUS_REG
1223 * @retval Interface status (MANDATORY: return 0 -> no Error).
1224 *
1225 */
asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1226 int32_t asm330lhhxg1_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1227 {
1228 asm330lhhxg1_status_reg_t status_reg;
1229 int32_t ret;
1230
1231 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_REG,
1232 (uint8_t *)&status_reg, 1);
1233 *val = status_reg.tda;
1234
1235 return ret;
1236 }
1237
1238 /**
1239 * @brief Accelerometer X-axis user offset correction expressed in two’s
1240 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1241 * The value must be in the range [-127 127].[set]
1242 *
1243 * @param ctx Read / write interface definitions.(ptr)
1244 * @param buff Buffer that contains data to write
1245 * @retval Interface status (MANDATORY: return 0 -> no Error).
1246 *
1247 */
asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1248 int32_t asm330lhhxg1_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1249 {
1250 int32_t ret;
1251 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_X_OFS_USR, buff, 1);
1252 return ret;
1253 }
1254
1255 /**
1256 * @brief Accelerometer X-axis user offset correction expressed in two’s
1257 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1258 * The value must be in the range [-127 127].[get]
1259 *
1260 * @param ctx Read / write interface definitions.(ptr)
1261 * @param buff Buffer that stores data read
1262 * @retval Interface status (MANDATORY: return 0 -> no Error).
1263 *
1264 */
asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1265 int32_t asm330lhhxg1_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1266 {
1267 int32_t ret;
1268 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_X_OFS_USR, buff, 1);
1269 return ret;
1270 }
1271
1272 /**
1273 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1274 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1275 * The value must be in the range [-127 127].[set]
1276 *
1277 * @param ctx Read / write interface definitions.(ptr)
1278 * @param buff Buffer that contains data to write
1279 * @retval Interface status (MANDATORY: return 0 -> no Error).
1280 *
1281 */
asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1282 int32_t asm330lhhxg1_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1283 {
1284 int32_t ret;
1285 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_Y_OFS_USR, buff, 1);
1286 return ret;
1287 }
1288
1289 /**
1290 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1291 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1292 * The value must be in the range [-127 127].[get]
1293 *
1294 * @param ctx Read / write interface definitions.(ptr)
1295 * @param buff Buffer that stores data read
1296 * @retval Interface status (MANDATORY: return 0 -> no Error).
1297 *
1298 */
asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1299 int32_t asm330lhhxg1_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1300 {
1301 int32_t ret;
1302 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_Y_OFS_USR, buff, 1);
1303 return ret;
1304 }
1305
1306 /**
1307 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1308 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1309 * The value must be in the range [-127 127].[set]
1310 *
1311 * @param ctx Read / write interface definitions.(ptr)
1312 * @param buff Buffer that contains data to write
1313 * @retval Interface status (MANDATORY: return 0 -> no Error).
1314 *
1315 */
asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1316 int32_t asm330lhhxg1_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1317 {
1318 int32_t ret;
1319 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_Z_OFS_USR, buff, 1);
1320 return ret;
1321 }
1322
1323 /**
1324 * @brief Accelerometer X-axis user offset correction expressed in two’s
1325 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1326 * The value must be in the range [-127 127].[get]
1327 *
1328 * @param ctx Read / write interface definitions.(ptr)
1329 * @param buff Buffer that stores data read
1330 * @retval Interface status (MANDATORY: return 0 -> no Error).
1331 *
1332 */
asm330lhhxg1_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1333 int32_t asm330lhhxg1_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1334 {
1335 int32_t ret;
1336 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_Z_OFS_USR, buff, 1);
1337 return ret;
1338 }
1339
1340 /**
1341 * @brief Enables user offset on out.[set]
1342 *
1343 * @param ctx Read / write interface definitions.(ptr)
1344 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1345 * @retval Interface status (MANDATORY: return 0 -> no Error).
1346 *
1347 */
asm330lhhxg1_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1348 int32_t asm330lhhxg1_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1349 {
1350 asm330lhhxg1_ctrl7_g_t ctrl7_g;
1351 int32_t ret;
1352
1353 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1354 if (ret == 0)
1355 {
1356 ctrl7_g.usr_off_on_out = (uint8_t)val;
1357 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1358 }
1359 return ret;
1360 }
1361
1362 /**
1363 * @brief Get user offset on out flag.[get]
1364 *
1365 * @param ctx Read / write interface definitions.(ptr)
1366 * @param val Get values of usr_off_on_out in reg CTRL7_G
1367 * @retval Interface status (MANDATORY: return 0 -> no Error).
1368 *
1369 */
asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1370 int32_t asm330lhhxg1_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1371 {
1372 asm330lhhxg1_ctrl7_g_t ctrl7_g;
1373 int32_t ret;
1374
1375 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1376 *val = ctrl7_g.usr_off_on_out;
1377
1378 return ret;
1379 }
1380
1381 /**
1382 * @}
1383 *
1384 */
1385
1386 /**
1387 * @defgroup ASM330LHHXG1_Timestamp
1388 * @brief This section groups all the functions that manage the
1389 * timestamp generation.
1390 * @{
1391 *
1392 */
1393
1394 /**
1395 * @brief Reset timestamp counter.[set]
1396 *
1397 * @param ctx Read / write interface definitions.(ptr)
1398 * @retval Interface status (MANDATORY: return 0 -> no Error).
1399 *
1400 */
asm330lhhxg1_timestamp_rst(const stmdev_ctx_t * ctx)1401 int32_t asm330lhhxg1_timestamp_rst(const stmdev_ctx_t *ctx)
1402 {
1403 uint8_t rst_val = 0xAA;
1404
1405 return asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_TIMESTAMP2, &rst_val, 1);
1406 }
1407
1408 /**
1409 * @brief Enables timestamp counter.[set]
1410 *
1411 * @param ctx Read / write interface definitions.(ptr)
1412 * @param val Change the values of timestamp_en in reg CTRL10_C
1413 * @retval Interface status (MANDATORY: return 0 -> no Error).
1414 *
1415 */
asm330lhhxg1_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1416 int32_t asm330lhhxg1_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1417 {
1418 asm330lhhxg1_ctrl10_c_t ctrl10_c;
1419 int32_t ret;
1420
1421 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1422 if (ret == 0)
1423 {
1424 ctrl10_c.timestamp_en = (uint8_t)val;
1425 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL10_C,
1426 (uint8_t *)&ctrl10_c, 1);
1427 }
1428 return ret;
1429 }
1430
1431 /**
1432 * @brief Enables timestamp counter.[get]
1433 *
1434 * @param ctx Read / write interface definitions.(ptr)
1435 * @param val Change the values of timestamp_en in reg CTRL10_C
1436 * @retval Interface status (MANDATORY: return 0 -> no Error).
1437 *
1438 */
asm330lhhxg1_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1439 int32_t asm330lhhxg1_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1440 {
1441 asm330lhhxg1_ctrl10_c_t ctrl10_c;
1442 int32_t ret;
1443
1444 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1445 *val = ctrl10_c.timestamp_en;
1446
1447 return ret;
1448 }
1449
1450 /**
1451 * @brief Timestamp first data output register (r).
1452 * The value is expressed as a 32-bit word and the bit resolution
1453 * is 25 μs.[get]
1454 *
1455 * @param ctx Read / write interface definitions.(ptr)
1456 * @param buff Buffer that stores data read
1457 * @retval Interface status (MANDATORY: return 0 -> no Error).
1458 *
1459 */
asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1460 int32_t asm330lhhxg1_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1461 {
1462 uint8_t buff[4];
1463 int32_t ret;
1464
1465 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_TIMESTAMP0, buff, 4);
1466 *val = buff[3];
1467 *val = (*val * 256U) + buff[2];
1468 *val = (*val * 256U) + buff[1];
1469 *val = (*val * 256U) + buff[0];
1470
1471 return ret;
1472 }
1473
1474 /**
1475 * @}
1476 *
1477 */
1478
1479 /**
1480 * @defgroup ASM330LHHXG1_Data output
1481 * @brief This section groups all the data output functions.
1482 * @{
1483 *
1484 */
1485
1486 /**
1487 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1488 *
1489 * @param ctx Read / write interface definitions.(ptr)
1490 * @param val Change the values of rounding in reg CTRL5_C
1491 * @retval Interface status (MANDATORY: return 0 -> no Error).
1492 *
1493 */
asm330lhhxg1_rounding_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_rounding_t val)1494 int32_t asm330lhhxg1_rounding_mode_set(const stmdev_ctx_t *ctx,
1495 asm330lhhxg1_rounding_t val)
1496 {
1497 asm330lhhxg1_ctrl5_c_t ctrl5_c;
1498 int32_t ret;
1499
1500 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1501 if (ret == 0)
1502 {
1503 ctrl5_c.rounding = (uint8_t)val;
1504 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1505 }
1506 return ret;
1507 }
1508
1509 /**
1510 * @brief Gyroscope UI chain full-scale selection.[get]
1511 *
1512 * @param ctx Read / write interface definitions.(ptr)
1513 * @param val Get the values of rounding in reg CTRL5_C
1514 * @retval Interface status (MANDATORY: return 0 -> no Error).
1515 *
1516 */
asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_rounding_t * val)1517 int32_t asm330lhhxg1_rounding_mode_get(const stmdev_ctx_t *ctx,
1518 asm330lhhxg1_rounding_t *val)
1519 {
1520 asm330lhhxg1_ctrl5_c_t ctrl5_c;
1521 int32_t ret;
1522
1523 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1524 switch (ctrl5_c.rounding)
1525 {
1526 case ASM330LHHXG1_NO_ROUND:
1527 *val = ASM330LHHXG1_NO_ROUND;
1528 break;
1529 case ASM330LHHXG1_ROUND_XL:
1530 *val = ASM330LHHXG1_ROUND_XL;
1531 break;
1532 case ASM330LHHXG1_ROUND_GY:
1533 *val = ASM330LHHXG1_ROUND_GY;
1534 break;
1535 case ASM330LHHXG1_ROUND_GY_XL:
1536 *val = ASM330LHHXG1_ROUND_GY_XL;
1537 break;
1538 default:
1539 *val = ASM330LHHXG1_NO_ROUND;
1540 break;
1541 }
1542 return ret;
1543 }
1544
1545 /**
1546 * @brief Temperature data output register (r).
1547 * L and H registers together express a 16-bit word in two’s
1548 * complement.[get]
1549 *
1550 * @param ctx Read / write interface definitions.(ptr)
1551 * @param buff Buffer that stores data read
1552 * @retval Interface status (MANDATORY: return 0 -> no Error).
1553 *
1554 */
asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1555 int32_t asm330lhhxg1_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1556 {
1557 uint8_t buff[2];
1558 int32_t ret;
1559
1560 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUT_TEMP_L, buff, 2);
1561 *val = (int16_t)buff[1];
1562 *val = (*val * 256) + (int16_t)buff[0];
1563
1564 return ret;
1565 }
1566
1567 /**
1568 * @brief Angular rate sensor. The value is expressed as a 16-bit
1569 * word in two’s complement.[get]
1570 *
1571 * @param ctx Read / write interface definitions.(ptr)
1572 * @param buff Buffer that stores data read
1573 * @retval Interface status (MANDATORY: return 0 -> no Error).
1574 *
1575 */
asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1576 int32_t asm330lhhxg1_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1577 {
1578 uint8_t buff[6];
1579 int32_t ret;
1580 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_G, buff, 6);
1581
1582 val[0] = (int16_t)buff[1];
1583 val[0] = (val[0] * 256) + (int16_t)buff[0];
1584 val[1] = (int16_t)buff[3];
1585 val[1] = (val[1] * 256) + (int16_t)buff[2];
1586 val[2] = (int16_t)buff[5];
1587 val[2] = (val[2] * 256) + (int16_t)buff[4];
1588
1589 return ret;
1590 }
1591
1592 /**
1593 * @brief Linear acceleration output register. The value is expressed as a
1594 * 16-bit word in two’s complement.[get]
1595 *
1596 * @param ctx Read / write interface definitions.(ptr)
1597 * @param buff Buffer that stores data read
1598 * @retval Interface status (MANDATORY: return 0 -> no Error).
1599 *
1600 */
asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1601 int32_t asm330lhhxg1_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1602 {
1603 uint8_t buff[6];
1604 int32_t ret;
1605 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_OUTX_L_A, buff, 6);
1606
1607 val[0] = (int16_t)buff[1];
1608 val[0] = (val[0] * 256) + (int16_t)buff[0];
1609 val[1] = (int16_t)buff[3];
1610 val[1] = (val[1] * 256) + (int16_t)buff[2];
1611 val[2] = (int16_t)buff[5];
1612 val[2] = (val[2] * 256) + (int16_t)buff[4];
1613
1614 return ret;
1615 }
1616
1617 /**
1618 * @brief FIFO data output.[get]
1619 *
1620 * @param ctx Read / write interface definitions.(ptr)
1621 * @param buff Buffer that stores data read
1622 * @retval Interface status (MANDATORY: return 0 -> no Error).
1623 *
1624 */
asm330lhhxg1_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * val)1625 int32_t asm330lhhxg1_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val)
1626 {
1627 int32_t ret;
1628 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_DATA_OUT_X_L, val, 6);
1629 return ret;
1630 }
1631
1632 /**
1633 * @}
1634 *
1635 */
1636
1637 /**
1638 * @defgroup ASM330LHHXG1_common
1639 * @brief This section groups common useful functions.
1640 * @{
1641 *
1642 */
1643
1644 /**
1645 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1646 * with respect to the typical.[set]
1647 * Step: 0.15%. 8-bit format, 2's complement.
1648 *
1649 * @param ctx Read / write interface definitions.(ptr)
1650 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1651 * @retval Interface status (MANDATORY: return 0 -> no Error).
1652 *
1653 */
asm330lhhxg1_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1654 int32_t asm330lhhxg1_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1655 {
1656 asm330lhhxg1_internal_freq_fine_t internal_freq_fine;
1657 int32_t ret;
1658
1659 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE,
1660 (uint8_t *)&internal_freq_fine, 1);
1661 if (ret == 0)
1662 {
1663 internal_freq_fine.freq_fine = (uint8_t)val;
1664 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE,
1665 (uint8_t *)&internal_freq_fine, 1);
1666 }
1667 return ret;
1668 }
1669
1670 /**
1671 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1672 * with respect to the typical.[get]
1673 * Step: 0.15%. 8-bit format, 2's complement.
1674 *
1675 * @param ctx Read / write interface definitions.(ptr)
1676 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1677 * @retval Interface status (MANDATORY: return 0 -> no Error).
1678 *
1679 */
asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1680 int32_t asm330lhhxg1_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1681 {
1682 asm330lhhxg1_internal_freq_fine_t internal_freq_fine;
1683 int32_t ret;
1684
1685 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INTERNAL_FREQ_FINE,
1686 (uint8_t *)&internal_freq_fine, 1);
1687 *val = internal_freq_fine.freq_fine;
1688
1689 return ret;
1690 }
1691
1692 /**
1693 * @brief Enable access to the embedded functions/sensor hub configuration
1694 * registers.[set]
1695 *
1696 * @param ctx Read / write interface definitions.(ptr)
1697 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1698 * @retval Interface status (MANDATORY: return 0 -> no Error).
1699 *
1700 */
asm330lhhxg1_mem_bank_set(const stmdev_ctx_t * ctx,asm330lhhxg1_reg_access_t val)1701 int32_t asm330lhhxg1_mem_bank_set(const stmdev_ctx_t *ctx,
1702 asm330lhhxg1_reg_access_t val)
1703 {
1704 asm330lhhxg1_func_cfg_access_t func_cfg_access;
1705 int32_t ret;
1706
1707 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS,
1708 (uint8_t *)&func_cfg_access, 1);
1709 if (ret == 0)
1710 {
1711 func_cfg_access.reg_access = (uint8_t)val;
1712 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS,
1713 (uint8_t *)&func_cfg_access, 1);
1714 }
1715 return ret;
1716 }
1717
1718 /**
1719 * @brief Enable access to the embedded functions/sensor hub configuration
1720 * registers.[get]
1721 *
1722 * @param ctx Read / write interface definitions.(ptr)
1723 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1724 * @retval Interface status (MANDATORY: return 0 -> no Error).
1725 *
1726 */
asm330lhhxg1_mem_bank_get(const stmdev_ctx_t * ctx,asm330lhhxg1_reg_access_t * val)1727 int32_t asm330lhhxg1_mem_bank_get(const stmdev_ctx_t *ctx,
1728 asm330lhhxg1_reg_access_t *val)
1729 {
1730 asm330lhhxg1_func_cfg_access_t func_cfg_access;
1731 int32_t ret;
1732
1733 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FUNC_CFG_ACCESS,
1734 (uint8_t *)&func_cfg_access, 1);
1735 switch (func_cfg_access.reg_access)
1736 {
1737 case ASM330LHHXG1_USER_BANK:
1738 *val = ASM330LHHXG1_USER_BANK;
1739 break;
1740 case ASM330LHHXG1_SENSOR_HUB_BANK:
1741 *val = ASM330LHHXG1_SENSOR_HUB_BANK;
1742 break;
1743 case ASM330LHHXG1_EMBEDDED_FUNC_BANK:
1744 *val = ASM330LHHXG1_EMBEDDED_FUNC_BANK;
1745 break;
1746 default:
1747 *val = ASM330LHHXG1_USER_BANK;
1748 break;
1749 }
1750 return ret;
1751 }
1752
1753 /**
1754 * @brief Write a line(byte) in a page.[set]
1755 *
1756 * @param ctx Read / write interface definitions.(ptr)
1757 * @param add Page line address
1758 * @param val Value to write
1759 * @retval Interface status (MANDATORY: return 0 -> no Error).
1760 *
1761 */
asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1762 int32_t asm330lhhxg1_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
1763 uint8_t *val)
1764 {
1765 asm330lhhxg1_page_rw_t page_rw;
1766 asm330lhhxg1_page_sel_t page_sel;
1767 asm330lhhxg1_page_address_t page_address;
1768 int32_t ret;
1769
1770 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
1771 if (ret == 0)
1772 {
1773 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1774 }
1775 if (ret == 0)
1776 {
1777 page_rw.page_rw = 0x02U; /* page_write enable */
1778 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1779 }
1780 if (ret == 0)
1781 {
1782 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1);
1783 }
1784 if (ret == 0)
1785 {
1786 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1787 page_sel.not_used_01 = 1;
1788 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1789 (uint8_t *)&page_sel, 1);
1790 }
1791 if (ret == 0)
1792 {
1793 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1794 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS,
1795 (uint8_t *)&page_address, 1);
1796 }
1797 if (ret == 0)
1798 {
1799 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 1);
1800 }
1801 if (ret == 0)
1802 {
1803 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1804 }
1805 if (ret == 0)
1806 {
1807 page_rw.page_rw = 0x00; /* page_write disable */
1808 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1809 }
1810 if (ret == 0)
1811 {
1812 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
1813 }
1814 return ret;
1815 }
1816
1817 /**
1818 * @brief Write buffer in a page.[set]
1819 *
1820 * @param ctx Read / write interface definitions.(ptr)
1821 * @param buf Page line address.(ptr)
1822 * @param val Value to write.
1823 * @param len buffer lenght.
1824 * @retval Interface status (MANDATORY: return 0 -> no Error).
1825 *
1826 */
asm330lhhxg1_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1827 int32_t asm330lhhxg1_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
1828 uint8_t *buf, uint8_t len)
1829 {
1830 asm330lhhxg1_page_rw_t page_rw;
1831 asm330lhhxg1_page_sel_t page_sel;
1832 asm330lhhxg1_page_address_t page_address;
1833 int32_t ret;
1834 uint8_t msb, lsb;
1835 uint8_t i ;
1836
1837 msb = (uint8_t)(add / 256U);
1838 lsb = (uint8_t)(add - (msb * 256U));
1839
1840 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
1841 if (ret == 0)
1842 {
1843 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1844 }
1845 if (ret == 0)
1846 {
1847 page_rw.page_rw = 0x02U; /* page_write enable*/
1848 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1849 }
1850 if (ret == 0)
1851 {
1852 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1);
1853 }
1854 if (ret == 0)
1855 {
1856 page_sel.page_sel = msb;
1857 page_sel.not_used_01 = 1;
1858 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1859 (uint8_t *)&page_sel, 1);
1860 }
1861 if (ret == 0)
1862 {
1863 page_address.page_addr = lsb;
1864 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS,
1865 (uint8_t *)&page_address, 1);
1866 }
1867 for (i = 0; i < len; i++)
1868 {
1869 if (ret == 0)
1870 {
1871 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_VALUE, &buf[i], 1);
1872 if (ret == 0)
1873 {
1874 /* Check if page wrap */
1875 if (lsb == 0x00U)
1876 {
1877 msb++;
1878 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1879 (uint8_t *)&page_sel, 1);
1880 }
1881 lsb++;
1882 }
1883 if (ret == 0)
1884 {
1885 page_sel.page_sel = msb;
1886 page_sel.not_used_01 = 1;
1887 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1888 (uint8_t *)&page_sel, 1);
1889 }
1890 }
1891 }
1892
1893 if (ret == 0)
1894 {
1895 page_sel.page_sel = 0;
1896 page_sel.not_used_01 = 1;
1897 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1898 (uint8_t *)&page_sel, 1);
1899 }
1900 if (ret == 0)
1901 {
1902 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1903 }
1904 if (ret == 0)
1905 {
1906 page_rw.page_rw = 0x00U; /* page_write disable */
1907 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1908 }
1909 if (ret == 0)
1910 {
1911 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
1912 }
1913 return ret;
1914 }
1915
1916 /**
1917 * @brief Read a line(byte) in a page.[get]
1918 *
1919 * @param ctx Read / write interface definitions.(ptr)
1920 * @param add Page line address.
1921 * @param val Read value.(ptr)
1922 * @retval Interface status (MANDATORY: return 0 -> no Error).
1923 *
1924 */
asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1925 int32_t asm330lhhxg1_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
1926 uint8_t *val)
1927 {
1928 asm330lhhxg1_page_rw_t page_rw;
1929 asm330lhhxg1_page_sel_t page_sel;
1930 asm330lhhxg1_page_address_t page_address;
1931 int32_t ret;
1932
1933 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
1934 if (ret == 0)
1935 {
1936 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1937 }
1938 if (ret == 0)
1939 {
1940 page_rw.page_rw = 0x01U; /* page_read enable*/
1941 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1942 }
1943 if (ret == 0)
1944 {
1945 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL, (uint8_t *)&page_sel, 1);
1946 }
1947 if (ret == 0)
1948 {
1949 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1950 page_sel.not_used_01 = 1;
1951 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_SEL,
1952 (uint8_t *)&page_sel, 1);
1953 }
1954 if (ret == 0)
1955 {
1956 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1957 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_ADDRESS,
1958 (uint8_t *)&page_address, 1);
1959 }
1960 if (ret == 0)
1961 {
1962 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_VALUE, val, 2);
1963 }
1964 if (ret == 0)
1965 {
1966 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1967 }
1968 if (ret == 0)
1969 {
1970 page_rw.page_rw = 0x00U; /* page_read disable */
1971 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
1972 }
1973 if (ret == 0)
1974 {
1975 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
1976 }
1977 return ret;
1978 }
1979
1980 /**
1981 * @brief Data-ready pulsed / letched mode.[set]
1982 *
1983 * @param ctx Read / write interface definitions.(ptr)
1984 * @param val Change the values of dataready_pulsed in
1985 * reg COUNTER_BDR_REG1
1986 * @retval Interface status (MANDATORY: return 0 -> no Error).
1987 *
1988 */
asm330lhhxg1_data_ready_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_dataready_pulsed_t val)1989 int32_t asm330lhhxg1_data_ready_mode_set(const stmdev_ctx_t *ctx,
1990 asm330lhhxg1_dataready_pulsed_t val)
1991 {
1992 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
1993 int32_t ret;
1994
1995 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
1996 (uint8_t *)&counter_bdr_reg1, 1);
1997 if (ret == 0)
1998 {
1999 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2000 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
2001 (uint8_t *)&counter_bdr_reg1, 1);
2002 }
2003 return ret;
2004 }
2005
2006 /**
2007 * @brief Data-ready pulsed / letched mode.[get]
2008 *
2009 * @param ctx Read / write interface definitions.(ptr)
2010 * @param val Get the values of dataready_pulsed in
2011 * reg COUNTER_BDR_REG1
2012 * @retval Interface status (MANDATORY: return 0 -> no Error).
2013 *
2014 */
asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_dataready_pulsed_t * val)2015 int32_t asm330lhhxg1_data_ready_mode_get(const stmdev_ctx_t *ctx,
2016 asm330lhhxg1_dataready_pulsed_t *val)
2017 {
2018 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
2019 int32_t ret;
2020
2021 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
2022 (uint8_t *)&counter_bdr_reg1, 1);
2023 switch (counter_bdr_reg1.dataready_pulsed)
2024 {
2025 case ASM330LHHXG1_DRDY_LATCHED:
2026 *val = ASM330LHHXG1_DRDY_LATCHED;
2027 break;
2028 case ASM330LHHXG1_DRDY_PULSED:
2029 *val = ASM330LHHXG1_DRDY_PULSED;
2030 break;
2031 default:
2032 *val = ASM330LHHXG1_DRDY_LATCHED;
2033 break;
2034 }
2035 return ret;
2036 }
2037
2038 /**
2039 * @brief Device Who am I.[get]
2040 *
2041 * @param ctx Read / write interface definitions.(ptr)
2042 * @param buff Buffer that stores data read
2043 * @retval Interface status (MANDATORY: return 0 -> no Error).
2044 *
2045 */
asm330lhhxg1_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2046 int32_t asm330lhhxg1_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2047 {
2048 int32_t ret;
2049 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WHO_AM_I, buff, 1);
2050 return ret;
2051 }
2052
2053 /**
2054 * @brief Software reset. Restore the default values in user registers.[set]
2055 *
2056 * @param ctx Read / write interface definitions.(ptr)
2057 * @param val Change the values of sw_reset in reg CTRL3_C
2058 * @retval Interface status (MANDATORY: return 0 -> no Error).
2059 *
2060 */
asm330lhhxg1_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2061 int32_t asm330lhhxg1_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2062 {
2063 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2064 int32_t ret;
2065
2066 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2067 if (ret == 0)
2068 {
2069 ctrl3_c.sw_reset = (uint8_t)val;
2070 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2071 }
2072 return ret;
2073 }
2074
2075 /**
2076 * @brief Software reset. Restore the default values in user registers.[get]
2077 *
2078 * @param ctx Read / write interface definitions.(ptr)
2079 * @param val Change the values of sw_reset in reg CTRL3_C
2080 * @retval Interface status (MANDATORY: return 0 -> no Error).
2081 *
2082 */
asm330lhhxg1_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2083 int32_t asm330lhhxg1_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2084 {
2085 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2086 int32_t ret;
2087
2088 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2089 *val = ctrl3_c.sw_reset;
2090
2091 return ret;
2092 }
2093
2094 /**
2095 * @brief Register address automatically incremented during a multiple byte
2096 * access with a serial interface.[set]
2097 *
2098 * @param ctx Read / write interface definitions.(ptr)
2099 * @param val Change the values of if_inc in reg CTRL3_C
2100 * @retval Interface status (MANDATORY: return 0 -> no Error).
2101 *
2102 */
asm330lhhxg1_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2103 int32_t asm330lhhxg1_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2104 {
2105 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2106 int32_t ret;
2107
2108 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2109 if (ret == 0)
2110 {
2111 ctrl3_c.if_inc = (uint8_t)val;
2112 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2113 }
2114 return ret;
2115 }
2116
2117 /**
2118 * @brief Register address automatically incremented during a multiple byte
2119 * access with a serial interface.[get]
2120 *
2121 * @param ctx Read / write interface definitions.(ptr)
2122 * @param val Change the values of if_inc in reg CTRL3_C
2123 * @retval Interface status (MANDATORY: return 0 -> no Error).
2124 *
2125 */
asm330lhhxg1_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2126 int32_t asm330lhhxg1_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2127 {
2128 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2129 int32_t ret;
2130
2131 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2132 *val = ctrl3_c.if_inc;
2133
2134 return ret;
2135 }
2136
2137 /**
2138 * @brief Reboot memory content. Reload the calibration parameters.[set]
2139 *
2140 * @param ctx Read / write interface definitions.(ptr)
2141 * @param val Change the values of boot in reg CTRL3_C
2142 * @retval Interface status (MANDATORY: return 0 -> no Error).
2143 *
2144 */
asm330lhhxg1_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2145 int32_t asm330lhhxg1_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2146 {
2147 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2148 int32_t ret;
2149
2150 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2151 if (ret == 0)
2152 {
2153 ctrl3_c.boot = (uint8_t)val;
2154 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2155 }
2156 return ret;
2157 }
2158
2159 /**
2160 * @brief Reboot memory content. Reload the calibration parameters.[get]
2161 *
2162 * @param ctx Read / write interface definitions.(ptr)
2163 * @param val Change the values of boot in reg CTRL3_C
2164 * @retval Interface status (MANDATORY: return 0 -> no Error).
2165 *
2166 */
asm330lhhxg1_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2167 int32_t asm330lhhxg1_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2168 {
2169 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2170 int32_t ret;
2171
2172 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2173 *val = ctrl3_c.boot;
2174
2175 return ret;
2176 }
2177
2178
2179
2180 /**
2181 * @brief Linear acceleration sensor self-test enable.[set]
2182 *
2183 * @param ctx Read / write interface definitions.(ptr)
2184 * @param val Change the values of st_xl in reg CTRL5_C
2185 * @retval Interface status (MANDATORY: return 0 -> no Error).
2186 *
2187 */
asm330lhhxg1_xl_self_test_set(const stmdev_ctx_t * ctx,asm330lhhxg1_st_xl_t val)2188 int32_t asm330lhhxg1_xl_self_test_set(const stmdev_ctx_t *ctx,
2189 asm330lhhxg1_st_xl_t val)
2190 {
2191 asm330lhhxg1_ctrl5_c_t ctrl5_c;
2192 int32_t ret;
2193
2194 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2195 if (ret == 0)
2196 {
2197 ctrl5_c.st_xl = (uint8_t)val;
2198 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2199 }
2200 return ret;
2201 }
2202
2203 /**
2204 * @brief Linear acceleration sensor self-test enable.[get]
2205 *
2206 * @param ctx Read / write interface definitions.(ptr)
2207 * @param val Get the values of st_xl in reg CTRL5_C
2208 * @retval Interface status (MANDATORY: return 0 -> no Error).
2209 *
2210 */
asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t * ctx,asm330lhhxg1_st_xl_t * val)2211 int32_t asm330lhhxg1_xl_self_test_get(const stmdev_ctx_t *ctx,
2212 asm330lhhxg1_st_xl_t *val)
2213 {
2214 asm330lhhxg1_ctrl5_c_t ctrl5_c;
2215 int32_t ret;
2216
2217 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2218
2219 switch (ctrl5_c.st_xl)
2220 {
2221 case ASM330LHHXG1_XL_ST_DISABLE:
2222 *val = ASM330LHHXG1_XL_ST_DISABLE;
2223 break;
2224 case ASM330LHHXG1_XL_ST_POSITIVE:
2225 *val = ASM330LHHXG1_XL_ST_POSITIVE;
2226 break;
2227 case ASM330LHHXG1_XL_ST_NEGATIVE:
2228 *val = ASM330LHHXG1_XL_ST_NEGATIVE;
2229 break;
2230 default:
2231 *val = ASM330LHHXG1_XL_ST_DISABLE;
2232 break;
2233 }
2234 return ret;
2235 }
2236
2237 /**
2238 * @brief Angular rate sensor self-test enable.[set]
2239 *
2240 * @param ctx Read / write interface definitions.(ptr)
2241 * @param val Change the values of st_g in reg CTRL5_C
2242 * @retval Interface status (MANDATORY: return 0 -> no Error).
2243 *
2244 */
asm330lhhxg1_gy_self_test_set(const stmdev_ctx_t * ctx,asm330lhhxg1_st_g_t val)2245 int32_t asm330lhhxg1_gy_self_test_set(const stmdev_ctx_t *ctx,
2246 asm330lhhxg1_st_g_t val)
2247 {
2248 asm330lhhxg1_ctrl5_c_t ctrl5_c;
2249 int32_t ret;
2250
2251 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2252 if (ret == 0)
2253 {
2254 ctrl5_c.st_g = (uint8_t)val;
2255 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2256 }
2257 return ret;
2258 }
2259
2260 /**
2261 * @brief Angular rate sensor self-test enable.[get]
2262 *
2263 * @param ctx Read / write interface definitions.(ptr)
2264 * @param val Get the values of st_g in reg CTRL5_C
2265 * @retval Interface status (MANDATORY: return 0 -> no Error).
2266 *
2267 */
asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t * ctx,asm330lhhxg1_st_g_t * val)2268 int32_t asm330lhhxg1_gy_self_test_get(const stmdev_ctx_t *ctx,
2269 asm330lhhxg1_st_g_t *val)
2270 {
2271 asm330lhhxg1_ctrl5_c_t ctrl5_c;
2272 int32_t ret;
2273
2274 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2275
2276 switch (ctrl5_c.st_g)
2277 {
2278 case ASM330LHHXG1_GY_ST_DISABLE:
2279 *val = ASM330LHHXG1_GY_ST_DISABLE;
2280 break;
2281 case ASM330LHHXG1_GY_ST_POSITIVE:
2282 *val = ASM330LHHXG1_GY_ST_POSITIVE;
2283 break;
2284 case ASM330LHHXG1_GY_ST_NEGATIVE:
2285 *val = ASM330LHHXG1_GY_ST_NEGATIVE;
2286 break;
2287 default:
2288 *val = ASM330LHHXG1_GY_ST_DISABLE;
2289 break;
2290 }
2291 return ret;
2292 }
2293
2294 /**
2295 * @}
2296 *
2297 */
2298
2299 /**
2300 * @defgroup ASM330LHHXG1_filters
2301 * @brief This section group all the functions concerning the
2302 * filters configuration
2303 * @{
2304 *
2305 */
2306
2307 /**
2308 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2309 *
2310 * @param ctx Read / write interface definitions.(ptr)
2311 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2312 * @retval Interface status (MANDATORY: return 0 -> no Error).
2313 *
2314 */
asm330lhhxg1_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2315 int32_t asm330lhhxg1_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2316 {
2317 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
2318 int32_t ret;
2319
2320 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2321 if (ret == 0)
2322 {
2323 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2324 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL1_XL,
2325 (uint8_t *)&ctrl1_xl, 1);
2326 }
2327 return ret;
2328 }
2329
2330 /**
2331 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2332 *
2333 * @param ctx Read / write interface definitions.(ptr)
2334 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2335 * @retval Interface status (MANDATORY: return 0 -> no Error).
2336 *
2337 */
asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2338 int32_t asm330lhhxg1_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2339 {
2340 asm330lhhxg1_ctrl1_xl_t ctrl1_xl;
2341 int32_t ret;
2342
2343 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2344 *val = ctrl1_xl.lpf2_xl_en;
2345
2346 return ret;
2347 }
2348
2349 /**
2350 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2351 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2352 *
2353 * @param ctx Read / write interface definitions.(ptr)
2354 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2355 * @retval Interface status (MANDATORY: return 0 -> no Error).
2356 *
2357 */
asm330lhhxg1_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2358 int32_t asm330lhhxg1_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2359 {
2360 asm330lhhxg1_ctrl4_c_t ctrl4_c;
2361 int32_t ret;
2362
2363 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2364 if (ret == 0)
2365 {
2366 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2367 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2368 }
2369 return ret;
2370 }
2371
2372 /**
2373 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2374 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2375 *
2376 * @param ctx Read / write interface definitions.(ptr)
2377 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2378 * @retval Interface status (MANDATORY: return 0 -> no Error).
2379 *
2380 */
asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2381 int32_t asm330lhhxg1_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2382 {
2383 asm330lhhxg1_ctrl4_c_t ctrl4_c;
2384 int32_t ret;
2385
2386 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2387 *val = ctrl4_c.lpf1_sel_g;
2388
2389 return ret;
2390 }
2391
2392 /**
2393 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2394 * (XL and Gyro independently masked).[set]
2395 *
2396 * @param ctx Read / write interface definitions.(ptr)
2397 * @param val Change the values of drdy_mask in reg CTRL4_C
2398 * @retval Interface status (MANDATORY: return 0 -> no Error).
2399 *
2400 */
asm330lhhxg1_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2401 int32_t asm330lhhxg1_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2402 {
2403 asm330lhhxg1_ctrl4_c_t ctrl4_c;
2404 int32_t ret;
2405
2406 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2407 if (ret == 0)
2408 {
2409 ctrl4_c.drdy_mask = (uint8_t)val;
2410 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2411 }
2412 return ret;
2413 }
2414
2415 /**
2416 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2417 * (XL and Gyro independently masked).[get]
2418 *
2419 * @param ctx Read / write interface definitions.(ptr)
2420 * @param val Change the values of drdy_mask in reg CTRL4_C
2421 * @retval Interface status (MANDATORY: return 0 -> no Error).
2422 *
2423 */
asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2424 int32_t asm330lhhxg1_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2425 uint8_t *val)
2426 {
2427 asm330lhhxg1_ctrl4_c_t ctrl4_c;
2428 int32_t ret;
2429
2430 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2431 *val = ctrl4_c.drdy_mask;
2432
2433 return ret;
2434 }
2435
2436 /**
2437 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2438 *
2439 * @param ctx Read / write interface definitions.(ptr)
2440 * @param val Change the values of ftype in reg CTRL6_C
2441 * @retval Interface status (MANDATORY: return 0 -> no Error).
2442 *
2443 */
asm330lhhxg1_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,asm330lhhxg1_ftype_t val)2444 int32_t asm330lhhxg1_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2445 asm330lhhxg1_ftype_t val)
2446 {
2447 asm330lhhxg1_ctrl6_c_t ctrl6_c;
2448 int32_t ret;
2449
2450 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2451 if (ret == 0)
2452 {
2453 ctrl6_c.ftype = (uint8_t)val;
2454 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2455 }
2456 return ret;
2457 }
2458
2459 /**
2460 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2461 *
2462 * @param ctx Read / write interface definitions.(ptr)
2463 * @param val Get the values of ftype in reg CTRL6_C
2464 * @retval Interface status (MANDATORY: return 0 -> no Error).
2465 *
2466 */
asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,asm330lhhxg1_ftype_t * val)2467 int32_t asm330lhhxg1_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2468 asm330lhhxg1_ftype_t *val)
2469 {
2470 asm330lhhxg1_ctrl6_c_t ctrl6_c;
2471 int32_t ret;
2472
2473 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2474
2475 switch (ctrl6_c.ftype)
2476 {
2477 case ASM330LHHXG1_ULTRA_LIGHT:
2478 *val = ASM330LHHXG1_ULTRA_LIGHT;
2479 break;
2480 case ASM330LHHXG1_VERY_LIGHT:
2481 *val = ASM330LHHXG1_VERY_LIGHT;
2482 break;
2483 case ASM330LHHXG1_LIGHT:
2484 *val = ASM330LHHXG1_LIGHT;
2485 break;
2486 case ASM330LHHXG1_MEDIUM:
2487 *val = ASM330LHHXG1_MEDIUM;
2488 break;
2489 case ASM330LHHXG1_STRONG:
2490 *val = ASM330LHHXG1_STRONG;
2491 break;
2492 case ASM330LHHXG1_VERY_STRONG:
2493 *val = ASM330LHHXG1_VERY_STRONG;
2494 break;
2495 case ASM330LHHXG1_AGGRESSIVE:
2496 *val = ASM330LHHXG1_AGGRESSIVE;
2497 break;
2498 case ASM330LHHXG1_XTREME:
2499 *val = ASM330LHHXG1_XTREME;
2500 break;
2501 default:
2502 *val = ASM330LHHXG1_ULTRA_LIGHT;
2503 break;
2504 }
2505 return ret;
2506 }
2507
2508 /**
2509 * @brief Low pass filter 2 on 6D function selection.[set]
2510 *
2511 * @param ctx Read / write interface definitions.(ptr)
2512 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2513 * @retval Interface status (MANDATORY: return 0 -> no Error).
2514 *
2515 */
asm330lhhxg1_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2516 int32_t asm330lhhxg1_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2517 {
2518 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2519 int32_t ret;
2520
2521 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2522 if (ret == 0)
2523 {
2524 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2525 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL,
2526 (uint8_t *)&ctrl8_xl, 1);
2527 }
2528 return ret;
2529 }
2530
2531 /**
2532 * @brief Low pass filter 2 on 6D function selection.[get]
2533 *
2534 * @param ctx Read / write interface definitions.(ptr)
2535 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2536 * @retval Interface status (MANDATORY: return 0 -> no Error).
2537 *
2538 */
asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2539 int32_t asm330lhhxg1_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2540 {
2541 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2542 int32_t ret;
2543
2544 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2545 *val = ctrl8_xl.low_pass_on_6d;
2546
2547 return ret;
2548 }
2549
2550 /**
2551 * @brief Accelerometer slope filter / high-pass filter selection
2552 * on output.[set]
2553 *
2554 * @param ctx Read / write interface definitions.(ptr)
2555 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2556 * @retval Interface status (MANDATORY: return 0 -> no Error).
2557 *
2558 */
asm330lhhxg1_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,asm330lhhxg1_hp_slope_xl_en_t val)2559 int32_t asm330lhhxg1_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2560 asm330lhhxg1_hp_slope_xl_en_t val)
2561 {
2562 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2563 int32_t ret;
2564
2565 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2566 if (ret == 0)
2567 {
2568 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2569 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2570 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2571 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL,
2572 (uint8_t *)&ctrl8_xl, 1);
2573 }
2574 return ret;
2575 }
2576
2577 /**
2578 * @brief Accelerometer slope filter / high-pass filter selection on
2579 * output.[get]
2580 *
2581 * @param ctx Read / write interface definitions.(ptr)
2582 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2583 * @retval Interface status (MANDATORY: return 0 -> no Error).
2584 *
2585 */
asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,asm330lhhxg1_hp_slope_xl_en_t * val)2586 int32_t asm330lhhxg1_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2587 asm330lhhxg1_hp_slope_xl_en_t *val)
2588 {
2589 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2590 int32_t ret;
2591
2592 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2593 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) +
2594 ctrl8_xl.hpcf_xl))
2595 {
2596 case ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT:
2597 *val = ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT;
2598 break;
2599 case ASM330LHHXG1_SLOPE_ODR_DIV_4:
2600 *val = ASM330LHHXG1_SLOPE_ODR_DIV_4;
2601 break;
2602 case ASM330LHHXG1_HP_ODR_DIV_10:
2603 *val = ASM330LHHXG1_HP_ODR_DIV_10;
2604 break;
2605 case ASM330LHHXG1_HP_ODR_DIV_20:
2606 *val = ASM330LHHXG1_HP_ODR_DIV_20;
2607 break;
2608 case ASM330LHHXG1_HP_ODR_DIV_45:
2609 *val = ASM330LHHXG1_HP_ODR_DIV_45;
2610 break;
2611 case ASM330LHHXG1_HP_ODR_DIV_100:
2612 *val = ASM330LHHXG1_HP_ODR_DIV_100;
2613 break;
2614 case ASM330LHHXG1_HP_ODR_DIV_200:
2615 *val = ASM330LHHXG1_HP_ODR_DIV_200;
2616 break;
2617 case ASM330LHHXG1_HP_ODR_DIV_400:
2618 *val = ASM330LHHXG1_HP_ODR_DIV_400;
2619 break;
2620 case ASM330LHHXG1_HP_ODR_DIV_800:
2621 *val = ASM330LHHXG1_HP_ODR_DIV_800;
2622 break;
2623 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_10:
2624 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_10;
2625 break;
2626 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_20:
2627 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_20;
2628 break;
2629 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_45:
2630 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_45;
2631 break;
2632 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_100:
2633 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_100;
2634 break;
2635 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_200:
2636 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_200;
2637 break;
2638 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_400:
2639 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_400;
2640 break;
2641 case ASM330LHHXG1_HP_REF_MD_ODR_DIV_800:
2642 *val = ASM330LHHXG1_HP_REF_MD_ODR_DIV_800;
2643 break;
2644 case ASM330LHHXG1_LP_ODR_DIV_10:
2645 *val = ASM330LHHXG1_LP_ODR_DIV_10;
2646 break;
2647 case ASM330LHHXG1_LP_ODR_DIV_20:
2648 *val = ASM330LHHXG1_LP_ODR_DIV_20;
2649 break;
2650 case ASM330LHHXG1_LP_ODR_DIV_45:
2651 *val = ASM330LHHXG1_LP_ODR_DIV_45;
2652 break;
2653 case ASM330LHHXG1_LP_ODR_DIV_100:
2654 *val = ASM330LHHXG1_LP_ODR_DIV_100;
2655 break;
2656 case ASM330LHHXG1_LP_ODR_DIV_200:
2657 *val = ASM330LHHXG1_LP_ODR_DIV_200;
2658 break;
2659 case ASM330LHHXG1_LP_ODR_DIV_400:
2660 *val = ASM330LHHXG1_LP_ODR_DIV_400;
2661 break;
2662 case ASM330LHHXG1_LP_ODR_DIV_800:
2663 *val = ASM330LHHXG1_LP_ODR_DIV_800;
2664 break;
2665 default:
2666 *val = ASM330LHHXG1_HP_PATH_DISABLE_ON_OUT;
2667 break;
2668 }
2669 return ret;
2670 }
2671
2672 /**
2673 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2674 * The filter sets the second samples after writing this bit.
2675 * Active only during device exit from powerdown mode.[set]
2676 *
2677 * @param ctx Read / write interface definitions.(ptr)
2678 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2679 * @retval Interface status (MANDATORY: return 0 -> no Error).
2680 *
2681 */
asm330lhhxg1_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2682 int32_t asm330lhhxg1_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2683 {
2684 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2685 int32_t ret;
2686
2687 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2688 if (ret == 0)
2689 {
2690 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2691 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL8_XL,
2692 (uint8_t *)&ctrl8_xl, 1);
2693 }
2694 return ret;
2695 }
2696
2697 /**
2698 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2699 * The filter sets the second samples after writing
2700 * this bit. Active only during device exit from powerdown mode.[get]
2701 *
2702 * @param ctx Read / write interface definitions.(ptr)
2703 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2704 * @retval Interface status (MANDATORY: return 0 -> no Error).
2705 *
2706 */
asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2707 int32_t asm330lhhxg1_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2708 {
2709 asm330lhhxg1_ctrl8_xl_t ctrl8_xl;
2710 int32_t ret;
2711
2712 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2713 *val = ctrl8_xl.fastsettl_mode_xl;
2714
2715 return ret;
2716 }
2717
2718 /**
2719 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2720 * functions.[set]
2721 *
2722 * @param ctx Read / write interface definitions.(ptr)
2723 * @param val Change the values of slope_fds in reg INT_CFG0
2724 * @retval Interface status (MANDATORY: return 0 -> no Error).
2725 *
2726 */
asm330lhhxg1_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhhxg1_slope_fds_t val)2727 int32_t asm330lhhxg1_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2728 asm330lhhxg1_slope_fds_t val)
2729 {
2730 asm330lhhxg1_int_cfg0_t int_cfg0;
2731 int32_t ret;
2732
2733 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2734 if (ret == 0)
2735 {
2736 int_cfg0.slope_fds = (uint8_t)val;
2737 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0,
2738 (uint8_t *)&int_cfg0, 1);
2739 }
2740 return ret;
2741 }
2742
2743 /**
2744 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2745 * functions.[get]
2746 *
2747 * @param ctx Read / write interface definitions.(ptr)
2748 * @param val Get the values of slope_fds in reg INT_CFG0
2749 * @retval Interface status (MANDATORY: return 0 -> no Error).
2750 *
2751 */
asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhhxg1_slope_fds_t * val)2752 int32_t asm330lhhxg1_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2753 asm330lhhxg1_slope_fds_t *val)
2754 {
2755 asm330lhhxg1_int_cfg0_t int_cfg0;
2756 int32_t ret;
2757
2758 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2759 switch (int_cfg0.slope_fds)
2760 {
2761 case ASM330LHHXG1_USE_SLOPE:
2762 *val = ASM330LHHXG1_USE_SLOPE;
2763 break;
2764 case ASM330LHHXG1_USE_HPF:
2765 *val = ASM330LHHXG1_USE_HPF;
2766 break;
2767 default:
2768 *val = ASM330LHHXG1_USE_SLOPE;
2769 break;
2770 }
2771 return ret;
2772 }
2773
2774 /**
2775 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2776 * only if the gyro is in HP mode.[set]
2777 *
2778 * @param ctx Read / write interface definitions.(ptr)
2779 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2780 * @retval Interface status (MANDATORY: return 0 -> no Error).
2781 *
2782 */
asm330lhhxg1_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhhxg1_hpm_g_t val)2783 int32_t asm330lhhxg1_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2784 asm330lhhxg1_hpm_g_t val)
2785 {
2786 asm330lhhxg1_ctrl7_g_t ctrl7_g;
2787 int32_t ret;
2788
2789 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2790 if (ret == 0)
2791 {
2792 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2793 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2794 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2795 }
2796 return ret;
2797 }
2798
2799 /**
2800 * @brief Enables gyroscope digital high-pass filter. The filter is
2801 * enabled only if the gyro is in HP mode.[get]
2802 *
2803 * @param ctx Read / write interface definitions.(ptr)
2804 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2805 * @retval Interface status (MANDATORY: return 0 -> no Error).
2806 *
2807 */
asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhhxg1_hpm_g_t * val)2808 int32_t asm330lhhxg1_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
2809 asm330lhhxg1_hpm_g_t *val)
2810 {
2811 asm330lhhxg1_ctrl7_g_t ctrl7_g;
2812 int32_t ret;
2813
2814 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2815
2816 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
2817 {
2818 case ASM330LHHXG1_HP_FILTER_NONE:
2819 *val = ASM330LHHXG1_HP_FILTER_NONE;
2820 break;
2821 case ASM330LHHXG1_HP_FILTER_16mHz:
2822 *val = ASM330LHHXG1_HP_FILTER_16mHz;
2823 break;
2824 case ASM330LHHXG1_HP_FILTER_65mHz:
2825 *val = ASM330LHHXG1_HP_FILTER_65mHz;
2826 break;
2827 case ASM330LHHXG1_HP_FILTER_260mHz:
2828 *val = ASM330LHHXG1_HP_FILTER_260mHz;
2829 break;
2830 case ASM330LHHXG1_HP_FILTER_1Hz04:
2831 *val = ASM330LHHXG1_HP_FILTER_1Hz04;
2832 break;
2833 default:
2834 *val = ASM330LHHXG1_HP_FILTER_NONE;
2835 break;
2836 }
2837 return ret;
2838 }
2839
2840 /**
2841 * @}
2842 *
2843 */
2844
2845 /**
2846 * @defgroup ASM330LHHXG1_ serial_interface
2847 * @brief This section groups all the functions concerning main
2848 * serial interface management (not auxiliary)
2849 * @{
2850 *
2851 */
2852
2853 /**
2854 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2855 *
2856 * @param ctx Read / write interface definitions.(ptr)
2857 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
2858 * @retval Interface status (MANDATORY: return 0 -> no Error).
2859 *
2860 */
asm330lhhxg1_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_sdo_pu_en_t val)2861 int32_t asm330lhhxg1_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2862 asm330lhhxg1_sdo_pu_en_t val)
2863 {
2864 asm330lhhxg1_pin_ctrl_t pin_ctrl;
2865 int32_t ret;
2866
2867 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2868 if (ret == 0)
2869 {
2870 pin_ctrl.sdo_pu_en = (uint8_t)val;
2871 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2872 }
2873 return ret;
2874 }
2875
2876 /**
2877 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2878 *
2879 * @param ctx Read / write interface definitions.(ptr)
2880 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2881 * @retval Interface status (MANDATORY: return 0 -> no Error).
2882 *
2883 */
asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_sdo_pu_en_t * val)2884 int32_t asm330lhhxg1_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2885 asm330lhhxg1_sdo_pu_en_t *val)
2886 {
2887 asm330lhhxg1_pin_ctrl_t pin_ctrl;
2888 int32_t ret;
2889
2890 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2891
2892 switch (pin_ctrl.sdo_pu_en)
2893 {
2894 case ASM330LHHXG1_PULL_UP_DISC:
2895 *val = ASM330LHHXG1_PULL_UP_DISC;
2896 break;
2897 case ASM330LHHXG1_PULL_UP_CONNECT:
2898 *val = ASM330LHHXG1_PULL_UP_CONNECT;
2899 break;
2900 default:
2901 *val = ASM330LHHXG1_PULL_UP_DISC;
2902 break;
2903 }
2904 return ret;
2905 }
2906
2907 /**
2908 * @brief Connect/Disconnect INT1 pull-down.[set]
2909 *
2910 * @param ctx Read / write interface definitions.(ptr)
2911 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
2912 * @retval Interface status (MANDATORY: return 0 -> no Error).
2913 *
2914 */
asm330lhhxg1_int1_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_pd_dis_int1_t val)2915 int32_t asm330lhhxg1_int1_mode_set(const stmdev_ctx_t *ctx,
2916 asm330lhhxg1_pd_dis_int1_t val)
2917 {
2918 asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb;
2919 int32_t ret;
2920
2921 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2922 if (ret == 0)
2923 {
2924 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
2925 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB,
2926 (uint8_t *)&i3c_bus_avb, 1);
2927 }
2928 return ret;
2929 }
2930
2931 /**
2932 * @brief Connect/Disconnect INT1 pull-down.[get]
2933 *
2934 * @param ctx Read / write interface definitions.(ptr)
2935 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
2936 * @retval Interface status (MANDATORY: return 0 -> no Error).
2937 *
2938 */
asm330lhhxg1_int1_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_pd_dis_int1_t * val)2939 int32_t asm330lhhxg1_int1_mode_get(const stmdev_ctx_t *ctx,
2940 asm330lhhxg1_pd_dis_int1_t *val)
2941 {
2942 asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb;
2943 int32_t ret;
2944
2945 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2946
2947 switch (i3c_bus_avb.pd_dis_int1)
2948 {
2949 case ASM330LHHXG1_PULL_DOWN_CONNECT:
2950 *val = ASM330LHHXG1_PULL_DOWN_CONNECT;
2951 break;
2952 case ASM330LHHXG1_PULL_DOWN_DISC:
2953 *val = ASM330LHHXG1_PULL_DOWN_DISC;
2954 break;
2955 default:
2956 *val = ASM330LHHXG1_PULL_DOWN_CONNECT;
2957 break;
2958 }
2959 return ret;
2960 }
2961
2962 /**
2963 * @brief SPI Serial Interface Mode selection.[set]
2964 *
2965 * @param ctx Read / write interface definitions.(ptr)
2966 * @param val Change the values of sim in reg CTRL3_C
2967 * @retval Interface status (MANDATORY: return 0 -> no Error).
2968 *
2969 */
asm330lhhxg1_spi_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_sim_t val)2970 int32_t asm330lhhxg1_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t val)
2971 {
2972 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2973 int32_t ret;
2974
2975 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2976 if (ret == 0)
2977 {
2978 ctrl3_c.sim = (uint8_t)val;
2979 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2980 }
2981 return ret;
2982 }
2983
2984 /**
2985 * @brief SPI Serial Interface Mode selection.[get]
2986 *
2987 * @param ctx Read / write interface definitions.(ptr)
2988 * @param val Get the values of sim in reg CTRL3_C
2989 * @retval Interface status (MANDATORY: return 0 -> no Error).
2990 *
2991 */
asm330lhhxg1_spi_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_sim_t * val)2992 int32_t asm330lhhxg1_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_sim_t *val)
2993 {
2994 asm330lhhxg1_ctrl3_c_t ctrl3_c;
2995 int32_t ret;
2996
2997 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2998
2999 switch (ctrl3_c.sim)
3000 {
3001 case ASM330LHHXG1_SPI_4_WIRE:
3002 *val = ASM330LHHXG1_SPI_4_WIRE;
3003 break;
3004 case ASM330LHHXG1_SPI_3_WIRE:
3005 *val = ASM330LHHXG1_SPI_3_WIRE;
3006 break;
3007 default:
3008 *val = ASM330LHHXG1_SPI_4_WIRE;
3009 break;
3010 }
3011 return ret;
3012 }
3013
3014 /**
3015 * @brief Disable / Enable I2C interface.[set]
3016 *
3017 * @param ctx Read / write interface definitions.(ptr)
3018 * @param val Change the values of i2c_disable in reg CTRL4_C
3019 * @retval Interface status (MANDATORY: return 0 -> no Error).
3020 *
3021 */
asm330lhhxg1_i2c_interface_set(const stmdev_ctx_t * ctx,asm330lhhxg1_i2c_disable_t val)3022 int32_t asm330lhhxg1_i2c_interface_set(const stmdev_ctx_t *ctx,
3023 asm330lhhxg1_i2c_disable_t val)
3024 {
3025 asm330lhhxg1_ctrl4_c_t ctrl4_c;
3026 int32_t ret;
3027
3028 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3029 if (ret == 0)
3030 {
3031 ctrl4_c.i2c_disable = (uint8_t)val;
3032 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3033 }
3034 return ret;
3035 }
3036
3037 /**
3038 * @brief Disable / Enable I2C interface.[get]
3039 *
3040 * @param ctx Read / write interface definitions.(ptr)
3041 * @param val Get the values of i2c reg CTRL4_C
3042 * @retval Interface status (MANDATORY: return 0 -> no Error).
3043 *
3044 */
asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t * ctx,asm330lhhxg1_i2c_disable_t * val)3045 int32_t asm330lhhxg1_i2c_interface_get(const stmdev_ctx_t *ctx,
3046 asm330lhhxg1_i2c_disable_t *val)
3047 {
3048 asm330lhhxg1_ctrl4_c_t ctrl4_c;
3049 int32_t ret;
3050
3051 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3052
3053 switch (ctrl4_c.i2c_disable)
3054 {
3055 case ASM330LHHXG1_I2C_ENABLE:
3056 *val = ASM330LHHXG1_I2C_ENABLE;
3057 break;
3058 case ASM330LHHXG1_I2C_DISABLE:
3059 *val = ASM330LHHXG1_I2C_DISABLE;
3060 break;
3061 default:
3062 *val = ASM330LHHXG1_I2C_ENABLE;
3063 break;
3064 }
3065 return ret;
3066 }
3067
3068 /**
3069 * @brief I3C Enable/Disable communication protocol.[set]
3070 *
3071 * @param ctx Read / write interface definitions.(ptr)
3072 * @param val Change the values of i3c_disable in reg CTRL9_XL
3073 * @retval Interface status (MANDATORY: return 0 -> no Error).
3074 *
3075 */
asm330lhhxg1_i3c_disable_set(const stmdev_ctx_t * ctx,asm330lhhxg1_i3c_disable_t val)3076 int32_t asm330lhhxg1_i3c_disable_set(const stmdev_ctx_t *ctx,
3077 asm330lhhxg1_i3c_disable_t val)
3078 {
3079 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
3080 asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb;
3081 int32_t ret;
3082
3083 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3084 if (ret == 0)
3085 {
3086 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3087 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL,
3088 (uint8_t *)&ctrl9_xl, 1);
3089 }
3090 if (ret == 0)
3091 {
3092 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB,
3093 (uint8_t *)&i3c_bus_avb, 1);
3094 }
3095 if (ret == 0)
3096 {
3097 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3098 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB,
3099 (uint8_t *)&i3c_bus_avb, 1);
3100 }
3101 return ret;
3102 }
3103
3104 /**
3105 * @brief I3C Enable/Disable communication protocol.[get]
3106 *
3107 * @param ctx Read / write interface definitions.(ptr)
3108 * @param val Change the values of i3c_disable in reg CTRL9_XL
3109 * @retval Interface status (MANDATORY: return 0 -> no Error).
3110 *
3111 */
asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t * ctx,asm330lhhxg1_i3c_disable_t * val)3112 int32_t asm330lhhxg1_i3c_disable_get(const stmdev_ctx_t *ctx,
3113 asm330lhhxg1_i3c_disable_t *val)
3114 {
3115 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
3116 asm330lhhxg1_i3c_bus_avb_t i3c_bus_avb;
3117 int32_t ret;
3118
3119 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3120 if (ret == 0)
3121 {
3122 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_I3C_BUS_AVB,
3123 (uint8_t *)&i3c_bus_avb, 1);
3124 }
3125 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
3126 {
3127 case ASM330LHHXG1_I3C_DISABLE:
3128 *val = ASM330LHHXG1_I3C_DISABLE;
3129 break;
3130 case ASM330LHHXG1_I3C_ENABLE_T_50us:
3131 *val = ASM330LHHXG1_I3C_ENABLE_T_50us;
3132 break;
3133 case ASM330LHHXG1_I3C_ENABLE_T_2us:
3134 *val = ASM330LHHXG1_I3C_ENABLE_T_2us;
3135 break;
3136 case ASM330LHHXG1_I3C_ENABLE_T_1ms:
3137 *val = ASM330LHHXG1_I3C_ENABLE_T_1ms;
3138 break;
3139 case ASM330LHHXG1_I3C_ENABLE_T_25ms:
3140 *val = ASM330LHHXG1_I3C_ENABLE_T_25ms;
3141 break;
3142 default:
3143 *val = ASM330LHHXG1_I3C_DISABLE;
3144 break;
3145 }
3146 return ret;
3147 }
3148
3149 /**
3150 * @}
3151 *
3152 */
3153
3154 /**
3155 * @defgroup ASM330LHHXG1_interrupt_pins
3156 * @brief This section groups all the functions that manage
3157 * interrupt pins
3158 * @{
3159 *
3160 */
3161
3162 /**
3163 * @brief Select the signal that need to route on int1 pad.[set]
3164 *
3165 * @param ctx read / write interface definitions
3166 * @param val struct of registers: INT1_CTRL,
3167 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3168 * FSM_INT1_B
3169 *
3170 */
asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t * ctx,asm330lhhxg1_pin_int1_route_t * val)3171 int32_t asm330lhhxg1_pin_int1_route_set(const stmdev_ctx_t *ctx,
3172 asm330lhhxg1_pin_int1_route_t *val)
3173 {
3174 asm330lhhxg1_pin_int2_route_t pin_int2_route;
3175 asm330lhhxg1_int_cfg1_t int_cfg1;
3176 int32_t ret;
3177
3178 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3179 if (ret == 0)
3180 {
3181 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MLC_INT1,
3182 (uint8_t *)&val->mlc_int1, 1);
3183 }
3184 if (ret == 0)
3185 {
3186 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT1,
3187 (uint8_t *)&val->emb_func_int1, 1);
3188 }
3189 if (ret == 0)
3190 {
3191 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT1_A,
3192 (uint8_t *)&val->fsm_int1_a, 1);
3193 }
3194 if (ret == 0)
3195 {
3196 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT1_B,
3197 (uint8_t *)&val->fsm_int1_b, 1);
3198 }
3199 if (ret == 0)
3200 {
3201 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3202 }
3203
3204 if (ret == 0)
3205 {
3206 if ((val->emb_func_int1.int1_fsm_lc
3207 | val->fsm_int1_a.int1_fsm1
3208 | val->fsm_int1_a.int1_fsm2
3209 | val->fsm_int1_a.int1_fsm3
3210 | val->fsm_int1_a.int1_fsm4
3211 | val->fsm_int1_a.int1_fsm5
3212 | val->fsm_int1_a.int1_fsm6
3213 | val->fsm_int1_a.int1_fsm7
3214 | val->fsm_int1_a.int1_fsm8
3215 | val->fsm_int1_b.int1_fsm9
3216 | val->fsm_int1_b.int1_fsm10
3217 | val->fsm_int1_b.int1_fsm11
3218 | val->fsm_int1_b.int1_fsm12
3219 | val->fsm_int1_b.int1_fsm13
3220 | val->fsm_int1_b.int1_fsm14
3221 | val->fsm_int1_b.int1_fsm15
3222 | val->fsm_int1_b.int1_fsm16
3223 | val->mlc_int1.int1_mlc1
3224 | val->mlc_int1.int1_mlc2
3225 | val->mlc_int1.int1_mlc3
3226 | val->mlc_int1.int1_mlc4
3227 | val->mlc_int1.int1_mlc5
3228 | val->mlc_int1.int1_mlc6
3229 | val->mlc_int1.int1_mlc7
3230 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
3231 {
3232 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3233 }
3234 else
3235 {
3236 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3237 }
3238 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT1_CTRL,
3239 (uint8_t *)&val->int1_ctrl, 1);
3240 }
3241 if (ret == 0)
3242 {
3243 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3244 }
3245 if (ret == 0)
3246 {
3247 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3248 }
3249
3250 if (ret == 0)
3251 {
3252 ret = asm330lhhxg1_pin_int2_route_get(ctx, &pin_int2_route);
3253 }
3254 if (ret == 0)
3255 {
3256 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3257 | pin_int2_route.int2_ctrl.int2_drdy_g
3258 | pin_int2_route.int2_ctrl.int2_drdy_temp
3259 | pin_int2_route.int2_ctrl.int2_drdy_xl
3260 | pin_int2_route.int2_ctrl.int2_fifo_full
3261 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3262 | pin_int2_route.int2_ctrl.int2_fifo_th
3263 | pin_int2_route.md2_cfg.int2_6d
3264 | pin_int2_route.md2_cfg.int2_ff
3265 | pin_int2_route.md2_cfg.int2_wu
3266 | pin_int2_route.md2_cfg.int2_sleep_change
3267 | val->int1_ctrl.den_drdy_flag
3268 | val->int1_ctrl.int1_boot
3269 | val->int1_ctrl.int1_cnt_bdr
3270 | val->int1_ctrl.int1_drdy_g
3271 | val->int1_ctrl.int1_drdy_xl
3272 | val->int1_ctrl.int1_fifo_full
3273 | val->int1_ctrl.int1_fifo_ovr
3274 | val->int1_ctrl.int1_fifo_th
3275 | val->md1_cfg.int1_shub
3276 | val->md1_cfg.int1_6d
3277 | val->md1_cfg.int1_ff
3278 | val->md1_cfg.int1_wu
3279 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3280 {
3281 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3282 }
3283 else
3284 {
3285 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3286 }
3287 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3288 }
3289 return ret;
3290 }
3291
3292 /**
3293 * @brief Select the signal that need to route on int1 pad.[get]
3294 *
3295 * @param ctx read / write interface definitions
3296 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3297 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3298 *
3299 */
asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t * ctx,asm330lhhxg1_pin_int1_route_t * val)3300 int32_t asm330lhhxg1_pin_int1_route_get(const stmdev_ctx_t *ctx,
3301 asm330lhhxg1_pin_int1_route_t *val)
3302 {
3303 int32_t ret;
3304
3305 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3306 if (ret == 0)
3307 {
3308 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_INT1,
3309 (uint8_t *)&val->mlc_int1, 1);
3310 }
3311 if (ret == 0)
3312 {
3313 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT1,
3314 (uint8_t *)&val->emb_func_int1, 1);
3315 }
3316 if (ret == 0)
3317 {
3318 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT1_A,
3319 (uint8_t *)&val->fsm_int1_a, 1);
3320 }
3321 if (ret == 0)
3322 {
3323 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT1_B,
3324 (uint8_t *)&val->fsm_int1_b, 1);
3325 }
3326 if (ret == 0)
3327 {
3328 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3329 }
3330 if (ret == 0)
3331 {
3332
3333 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT1_CTRL,
3334 (uint8_t *)&val->int1_ctrl, 1);
3335 }
3336 if (ret == 0)
3337 {
3338 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3339 }
3340
3341 return ret;
3342 }
3343
3344 /**
3345 * @brief Select the signal that need to route on int2 pad.[set]
3346 *
3347 * @param ctx read / write interface definitions
3348 * @param val union of registers INT2_CTRL, MD2_CFG,
3349 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3350 *
3351 */
asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t * ctx,asm330lhhxg1_pin_int2_route_t * val)3352 int32_t asm330lhhxg1_pin_int2_route_set(const stmdev_ctx_t *ctx,
3353 asm330lhhxg1_pin_int2_route_t *val)
3354 {
3355 asm330lhhxg1_pin_int1_route_t pin_int1_route;
3356 asm330lhhxg1_int_cfg1_t int_cfg1;
3357 int32_t ret;
3358
3359 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3360 if (ret == 0)
3361 {
3362 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MLC_INT2,
3363 (uint8_t *)&val->mlc_int2, 1);
3364 }
3365 if (ret == 0)
3366 {
3367 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT2,
3368 (uint8_t *)&val->emb_func_int2, 1);
3369 }
3370 if (ret == 0)
3371 {
3372 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT2_A,
3373 (uint8_t *)&val->fsm_int2_a, 1);
3374 }
3375 if (ret == 0)
3376 {
3377 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_INT2_B,
3378 (uint8_t *)&val->fsm_int2_b, 1);
3379 }
3380 if (ret == 0)
3381 {
3382 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3383 }
3384
3385 if (ret == 0)
3386 {
3387 if ((val->emb_func_int2.int2_fsm_lc
3388 | val->fsm_int2_a.int2_fsm1
3389 | val->fsm_int2_a.int2_fsm2
3390 | val->fsm_int2_a.int2_fsm3
3391 | val->fsm_int2_a.int2_fsm4
3392 | val->fsm_int2_a.int2_fsm5
3393 | val->fsm_int2_a.int2_fsm6
3394 | val->fsm_int2_a.int2_fsm7
3395 | val->fsm_int2_a.int2_fsm8
3396 | val->fsm_int2_b.int2_fsm9
3397 | val->fsm_int2_b.int2_fsm10
3398 | val->fsm_int2_b.int2_fsm11
3399 | val->fsm_int2_b.int2_fsm12
3400 | val->fsm_int2_b.int2_fsm13
3401 | val->fsm_int2_b.int2_fsm14
3402 | val->fsm_int2_b.int2_fsm15
3403 | val->fsm_int2_b.int2_fsm16
3404 | val->mlc_int2.int2_mlc1
3405 | val->mlc_int2.int2_mlc2
3406 | val->mlc_int2.int2_mlc3
3407 | val->mlc_int2.int2_mlc4
3408 | val->mlc_int2.int2_mlc5
3409 | val->mlc_int2.int2_mlc6
3410 | val->mlc_int2.int2_mlc7
3411 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
3412 {
3413 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3414 }
3415 else
3416 {
3417 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3418 }
3419 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT2_CTRL,
3420 (uint8_t *)&val->int2_ctrl, 1);
3421 }
3422 if (ret == 0)
3423 {
3424 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3425 }
3426 if (ret == 0)
3427 {
3428 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3429 }
3430
3431 if (ret == 0)
3432 {
3433 ret = asm330lhhxg1_pin_int1_route_get(ctx, &pin_int1_route);
3434 }
3435
3436 if (ret == 0)
3437 {
3438 if ((val->int2_ctrl.int2_cnt_bdr
3439 | val->int2_ctrl.int2_drdy_g
3440 | val->int2_ctrl.int2_drdy_temp
3441 | val->int2_ctrl.int2_drdy_xl
3442 | val->int2_ctrl.int2_fifo_full
3443 | val->int2_ctrl.int2_fifo_ovr
3444 | val->int2_ctrl.int2_fifo_th
3445 | val->md2_cfg.int2_6d
3446 | val->md2_cfg.int2_ff
3447 | val->md2_cfg.int2_wu
3448 | val->md2_cfg.int2_sleep_change
3449 | pin_int1_route.int1_ctrl.den_drdy_flag
3450 | pin_int1_route.int1_ctrl.int1_boot
3451 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3452 | pin_int1_route.int1_ctrl.int1_drdy_g
3453 | pin_int1_route.int1_ctrl.int1_drdy_xl
3454 | pin_int1_route.int1_ctrl.int1_fifo_full
3455 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3456 | pin_int1_route.int1_ctrl.int1_fifo_th
3457 | pin_int1_route.md1_cfg.int1_6d
3458 | pin_int1_route.md1_cfg.int1_ff
3459 | pin_int1_route.md1_cfg.int1_wu
3460 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3461 {
3462 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3463 }
3464 else
3465 {
3466 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3467 }
3468 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3469 }
3470 return ret;
3471 }
3472
3473 /**
3474 * @brief Select the signal that need to route on int2 pad.[get]
3475 *
3476 * @param ctx read / write interface definitions
3477 * @param val union of registers INT2_CTRL, MD2_CFG,
3478 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3479 *
3480 */
asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t * ctx,asm330lhhxg1_pin_int2_route_t * val)3481 int32_t asm330lhhxg1_pin_int2_route_get(const stmdev_ctx_t *ctx,
3482 asm330lhhxg1_pin_int2_route_t *val)
3483 {
3484 int32_t ret;
3485
3486 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3487 if (ret == 0)
3488 {
3489 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_INT2,
3490 (uint8_t *)&val->mlc_int2, 1);
3491 }
3492 if (ret == 0)
3493 {
3494 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INT2,
3495 (uint8_t *)&val->emb_func_int2, 1);
3496 }
3497 if (ret == 0)
3498 {
3499 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT2_A,
3500 (uint8_t *)&val->fsm_int2_a, 1);
3501 }
3502 if (ret == 0)
3503 {
3504 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_INT2_B,
3505 (uint8_t *)&val->fsm_int2_b, 1);
3506 }
3507 if (ret == 0)
3508 {
3509 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3510 }
3511 if (ret == 0)
3512 {
3513
3514 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT2_CTRL,
3515 (uint8_t *)&val->int2_ctrl, 1);
3516 }
3517 if (ret == 0)
3518 {
3519 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3520 }
3521 return ret;
3522 }
3523
3524 /**
3525 * @brief Push-pull/open drain selection on interrupt pads.[set]
3526 *
3527 * @param ctx Read / write interface definitions.(ptr)
3528 * @param val Change the values of pp_od in reg CTRL3_C
3529 * @retval Interface status (MANDATORY: return 0 -> no Error).
3530 *
3531 */
asm330lhhxg1_pin_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_pp_od_t val)3532 int32_t asm330lhhxg1_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t val)
3533 {
3534 asm330lhhxg1_ctrl3_c_t ctrl3_c;
3535 int32_t ret;
3536
3537 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3538 if (ret == 0)
3539 {
3540 ctrl3_c.pp_od = (uint8_t)val;
3541 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3542 }
3543 return ret;
3544 }
3545
3546 /**
3547 * @brief Push-pull/open drain selection on interrupt pads.[get]
3548 *
3549 * @param ctx Read / write interface definitions.(ptr)
3550 * @param val Get the values of pp_od in reg CTRL3_C
3551 * @retval Interface status (MANDATORY: return 0 -> no Error).
3552 *
3553 */
asm330lhhxg1_pin_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_pp_od_t * val)3554 int32_t asm330lhhxg1_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhxg1_pp_od_t *val)
3555 {
3556 asm330lhhxg1_ctrl3_c_t ctrl3_c;
3557 int32_t ret;
3558
3559 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3560
3561 switch (ctrl3_c.pp_od)
3562 {
3563 case ASM330LHHXG1_PUSH_PULL:
3564 *val = ASM330LHHXG1_PUSH_PULL;
3565 break;
3566 case ASM330LHHXG1_OPEN_DRAIN:
3567 *val = ASM330LHHXG1_OPEN_DRAIN;
3568 break;
3569 default:
3570 *val = ASM330LHHXG1_PUSH_PULL;
3571 break;
3572 }
3573 return ret;
3574 }
3575
3576 /**
3577 * @brief Interrupt active-high/low.[set]
3578 *
3579 * @param ctx Read / write interface definitions.(ptr)
3580 * @param val Change the values of h_lactive in reg CTRL3_C
3581 * @retval Interface status (MANDATORY: return 0 -> no Error).
3582 *
3583 */
asm330lhhxg1_pin_polarity_set(const stmdev_ctx_t * ctx,asm330lhhxg1_h_lactive_t val)3584 int32_t asm330lhhxg1_pin_polarity_set(const stmdev_ctx_t *ctx,
3585 asm330lhhxg1_h_lactive_t val)
3586 {
3587 asm330lhhxg1_ctrl3_c_t ctrl3_c;
3588 int32_t ret;
3589
3590 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3591 if (ret == 0)
3592 {
3593 ctrl3_c.h_lactive = (uint8_t)val;
3594 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3595 }
3596 return ret;
3597 }
3598
3599 /**
3600 * @brief Interrupt active-high/low.[get]
3601 *
3602 * @param ctx Read / write interface definitions.(ptr)
3603 * @param val Get the values of h_lactive in reg CTRL3_C
3604 * @retval Interface status (MANDATORY: return 0 -> no Error).
3605 *
3606 */
asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t * ctx,asm330lhhxg1_h_lactive_t * val)3607 int32_t asm330lhhxg1_pin_polarity_get(const stmdev_ctx_t *ctx,
3608 asm330lhhxg1_h_lactive_t *val)
3609 {
3610 asm330lhhxg1_ctrl3_c_t ctrl3_c;
3611 int32_t ret;
3612
3613 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3614
3615 switch (ctrl3_c.h_lactive)
3616 {
3617 case ASM330LHHXG1_ACTIVE_HIGH:
3618 *val = ASM330LHHXG1_ACTIVE_HIGH;
3619 break;
3620 case ASM330LHHXG1_ACTIVE_LOW:
3621 *val = ASM330LHHXG1_ACTIVE_LOW;
3622 break;
3623 default:
3624 *val = ASM330LHHXG1_ACTIVE_HIGH;
3625 break;
3626 }
3627 return ret;
3628 }
3629
3630 /**
3631 * @brief All interrupt signals become available on INT1 pin.[set]
3632 *
3633 * @param ctx Read / write interface definitions.(ptr)
3634 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3635 * @retval Interface status (MANDATORY: return 0 -> no Error).
3636 *
3637 */
asm330lhhxg1_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3638 int32_t asm330lhhxg1_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3639 {
3640 asm330lhhxg1_ctrl4_c_t ctrl4_c;
3641 int32_t ret;
3642
3643 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3644 if (ret == 0)
3645 {
3646 ctrl4_c.int2_on_int1 = (uint8_t)val;
3647 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3648 }
3649 return ret;
3650 }
3651
3652 /**
3653 * @brief All interrupt signals become available on INT1 pin.[get]
3654 *
3655 * @param ctx Read / write interface definitions.(ptr)
3656 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3657 * @retval Interface status (MANDATORY: return 0 -> no Error).
3658 *
3659 */
asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3660 int32_t asm330lhhxg1_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3661 {
3662 asm330lhhxg1_ctrl4_c_t ctrl4_c;
3663 int32_t ret;
3664
3665 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3666 *val = ctrl4_c.int2_on_int1;
3667
3668 return ret;
3669 }
3670
3671 /**
3672 * @brief All interrupt signals notification mode.[set]
3673 *
3674 * @param ctx Read / write interface definitions.(ptr)
3675 * @param val Change the values of lir in reg INT_CFG0
3676 * @retval Interface status (MANDATORY: return 0 -> no Error).
3677 *
3678 */
asm330lhhxg1_int_notification_set(const stmdev_ctx_t * ctx,asm330lhhxg1_lir_t val)3679 int32_t asm330lhhxg1_int_notification_set(const stmdev_ctx_t *ctx,
3680 asm330lhhxg1_lir_t val)
3681 {
3682 asm330lhhxg1_int_cfg0_t int_cfg0;
3683 asm330lhhxg1_page_rw_t page_rw;
3684 int32_t ret;
3685
3686 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3687 if (ret == 0)
3688 {
3689 int_cfg0.lir = (uint8_t)val & 0x01U;
3690 int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3691 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0,
3692 (uint8_t *)&int_cfg0, 1);
3693 }
3694 if (ret == 0)
3695 {
3696 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3697 }
3698 if (ret == 0)
3699 {
3700 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
3701 }
3702 if (ret == 0)
3703 {
3704 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3705 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
3706 }
3707 if (ret == 0)
3708 {
3709 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3710 }
3711 return ret;
3712 }
3713
3714 /**
3715 * @brief All interrupt signals notification mode.[get]
3716 *
3717 * @param ctx Read / write interface definitions.(ptr)
3718 * @param val Get the values of lir in reg INT_CFG0
3719 * @retval Interface status (MANDATORY: return 0 -> no Error).
3720 *
3721 */
asm330lhhxg1_int_notification_get(const stmdev_ctx_t * ctx,asm330lhhxg1_lir_t * val)3722 int32_t asm330lhhxg1_int_notification_get(const stmdev_ctx_t *ctx,
3723 asm330lhhxg1_lir_t *val)
3724 {
3725 asm330lhhxg1_int_cfg0_t int_cfg0;
3726 asm330lhhxg1_page_rw_t page_rw;
3727 int32_t ret;
3728
3729 *val = ASM330LHHXG1_ALL_INT_PULSED;
3730 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3731
3732 if (ret == 0)
3733 {
3734 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
3735 }
3736 if (ret == 0)
3737 {
3738 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_RW, (uint8_t *)&page_rw, 1);
3739 }
3740 if (ret == 0)
3741 {
3742 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
3743 }
3744 switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir)
3745 {
3746 case ASM330LHHXG1_ALL_INT_PULSED:
3747 *val = ASM330LHHXG1_ALL_INT_PULSED;
3748 break;
3749 case ASM330LHHXG1_BASE_LATCHED_EMB_PULSED:
3750 *val = ASM330LHHXG1_BASE_LATCHED_EMB_PULSED;
3751 break;
3752 case ASM330LHHXG1_BASE_PULSED_EMB_LATCHED:
3753 *val = ASM330LHHXG1_BASE_PULSED_EMB_LATCHED;
3754 break;
3755 case ASM330LHHXG1_ALL_INT_LATCHED:
3756 *val = ASM330LHHXG1_ALL_INT_LATCHED;
3757 break;
3758 default:
3759 *val = ASM330LHHXG1_ALL_INT_PULSED;
3760 break;
3761 }
3762 return ret;
3763 }
3764
3765 /**
3766 * @}
3767 *
3768 */
3769
3770 /**
3771 * @defgroup ASM330LHHXG1_Wake_Up_event
3772 * @brief This section groups all the functions that manage the
3773 * Wake Up event generation.
3774 * @{
3775 *
3776 */
3777
3778 /**
3779 * @brief Weight of 1 LSB of wakeup threshold.[set]
3780 * 0: 1 LSB =FS_XL / 64
3781 * 1: 1 LSB = FS_XL / 256
3782 *
3783 * @param ctx Read / write interface definitions.(ptr)
3784 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
3785 * @retval Interface status (MANDATORY: return 0 -> no Error).
3786 *
3787 */
asm330lhhxg1_wkup_ths_weight_set(const stmdev_ctx_t * ctx,asm330lhhxg1_wake_ths_w_t val)3788 int32_t asm330lhhxg1_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
3789 asm330lhhxg1_wake_ths_w_t val)
3790 {
3791 asm330lhhxg1_wake_up_dur_t wake_up_dur;
3792 int32_t ret;
3793
3794 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3795 (uint8_t *)&wake_up_dur, 1);
3796 if (ret == 0)
3797 {
3798 wake_up_dur.wake_ths_w = (uint8_t)val;
3799 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3800 (uint8_t *)&wake_up_dur, 1);
3801 }
3802 return ret;
3803 }
3804
3805 /**
3806 * @brief Weight of 1 LSB of wakeup threshold.[get]
3807 * 0: 1 LSB =FS_XL / 64
3808 * 1: 1 LSB = FS_XL / 256
3809 *
3810 * @param ctx Read / write interface definitions.(ptr)
3811 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
3812 * @retval Interface status (MANDATORY: return 0 -> no Error).
3813 *
3814 */
asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t * ctx,asm330lhhxg1_wake_ths_w_t * val)3815 int32_t asm330lhhxg1_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
3816 asm330lhhxg1_wake_ths_w_t *val)
3817 {
3818 asm330lhhxg1_wake_up_dur_t wake_up_dur;
3819 int32_t ret;
3820
3821 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3822 (uint8_t *)&wake_up_dur, 1);
3823
3824 switch (wake_up_dur.wake_ths_w)
3825 {
3826 case ASM330LHHXG1_LSb_FS_DIV_64:
3827 *val = ASM330LHHXG1_LSb_FS_DIV_64;
3828 break;
3829 case ASM330LHHXG1_LSb_FS_DIV_256:
3830 *val = ASM330LHHXG1_LSb_FS_DIV_256;
3831 break;
3832 default:
3833 *val = ASM330LHHXG1_LSb_FS_DIV_64;
3834 break;
3835 }
3836 return ret;
3837 }
3838
3839 /**
3840 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3841 * WAKE_UP_DUR.[set]
3842 *
3843 * @param ctx Read / write interface definitions.(ptr)
3844 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3845 * @retval Interface status (MANDATORY: return 0 -> no Error).
3846 *
3847 */
asm330lhhxg1_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3848 int32_t asm330lhhxg1_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3849 {
3850 asm330lhhxg1_wake_up_ths_t wake_up_ths;
3851 int32_t ret;
3852
3853 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3854 (uint8_t *)&wake_up_ths, 1);
3855 if (ret == 0)
3856 {
3857 wake_up_ths.wk_ths = (uint8_t)val;
3858 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3859 (uint8_t *)&wake_up_ths, 1);
3860 }
3861 return ret;
3862 }
3863
3864 /**
3865 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3866 * WAKE_UP_DUR.[get]
3867 *
3868 * @param ctx Read / write interface definitions.(ptr)
3869 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3870 * @retval Interface status (MANDATORY: return 0 -> no Error).
3871 *
3872 */
asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3873 int32_t asm330lhhxg1_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3874 {
3875 asm330lhhxg1_wake_up_ths_t wake_up_ths;
3876 int32_t ret;
3877
3878 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3879 (uint8_t *)&wake_up_ths, 1);
3880 *val = wake_up_ths.wk_ths;
3881
3882 return ret;
3883 }
3884
3885 /**
3886 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
3887 *
3888 * @param ctx Read / write interface definitions.(ptr)
3889 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3890 * @retval Interface status (MANDATORY: return 0 -> no Error).
3891 *
3892 */
asm330lhhxg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)3893 int32_t asm330lhhxg1_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val)
3894 {
3895 asm330lhhxg1_wake_up_ths_t wake_up_ths;
3896 int32_t ret;
3897
3898 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3899 (uint8_t *)&wake_up_ths, 1);
3900 if (ret == 0)
3901 {
3902 wake_up_ths.usr_off_on_wu = (uint8_t)val;
3903 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3904 (uint8_t *)&wake_up_ths, 1);
3905 }
3906 return ret;
3907 }
3908
3909 /**
3910 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
3911 *
3912 * @param ctx Read / write interface definitions.(ptr)
3913 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3914 * @retval Interface status (MANDATORY: return 0 -> no Error).
3915 *
3916 */
asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)3917 int32_t asm330lhhxg1_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
3918 uint8_t *val)
3919 {
3920 asm330lhhxg1_wake_up_ths_t wake_up_ths;
3921 int32_t ret;
3922
3923 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_THS,
3924 (uint8_t *)&wake_up_ths, 1);
3925 *val = wake_up_ths.usr_off_on_wu;
3926
3927 return ret;
3928 }
3929
3930 /**
3931 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
3932 *
3933 * @param ctx Read / write interface definitions.(ptr)
3934 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3935 * @retval Interface status (MANDATORY: return 0 -> no Error).
3936 *
3937 */
asm330lhhxg1_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3938 int32_t asm330lhhxg1_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3939 {
3940 asm330lhhxg1_wake_up_dur_t wake_up_dur;
3941 int32_t ret;
3942
3943 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3944 (uint8_t *)&wake_up_dur, 1);
3945 if (ret == 0)
3946 {
3947 wake_up_dur.wake_dur = (uint8_t)val;
3948 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3949 (uint8_t *)&wake_up_dur, 1);
3950 }
3951 return ret;
3952 }
3953
3954 /**
3955 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3956 *
3957 * @param ctx Read / write interface definitions.(ptr)
3958 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3959 * @retval Interface status (MANDATORY: return 0 -> no Error).
3960 *
3961 */
asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3962 int32_t asm330lhhxg1_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3963 {
3964 asm330lhhxg1_wake_up_dur_t wake_up_dur;
3965 int32_t ret;
3966
3967 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
3968 (uint8_t *)&wake_up_dur, 1);
3969 *val = wake_up_dur.wake_dur;
3970
3971 return ret;
3972 }
3973
3974 /**
3975 * @}
3976 *
3977 */
3978
3979 /**
3980 * @defgroup ASM330LHHXG1_ Activity/Inactivity_detection
3981 * @brief This section groups all the functions concerning
3982 * activity/inactivity detection.
3983 * @{
3984 *
3985 */
3986
3987 /**
3988 * @brief Enables gyroscope Sleep mode.[set]
3989 *
3990 * @param ctx Read / write interface definitions.(ptr)
3991 * @param val Change the values of sleep_g in reg CTRL4_C
3992 * @retval Interface status (MANDATORY: return 0 -> no Error).
3993 *
3994 */
asm330lhhxg1_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)3995 int32_t asm330lhhxg1_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
3996 {
3997 asm330lhhxg1_ctrl4_c_t ctrl4_c;
3998 int32_t ret;
3999
4000 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4001 if (ret == 0)
4002 {
4003 ctrl4_c.sleep_g = (uint8_t)val;
4004 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4005 }
4006 return ret;
4007 }
4008
4009 /**
4010 * @brief Enables gyroscope Sleep mode.[get]
4011 *
4012 * @param ctx Read / write interface definitions.(ptr)
4013 * @param val Change the values of sleep_g in reg CTRL4_C
4014 * @retval Interface status (MANDATORY: return 0 -> no Error).
4015 *
4016 */
asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4017 int32_t asm330lhhxg1_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4018 {
4019 asm330lhhxg1_ctrl4_c_t ctrl4_c;
4020 int32_t ret;
4021
4022 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4023 *val = ctrl4_c.sleep_g;
4024
4025 return ret;
4026 }
4027
4028 /**
4029 * @brief Drives the sleep status instead of sleep change on INT pins
4030 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4031 * are enabled).[set]
4032 *
4033 * @param ctx Read / write interface definitions.(ptr)
4034 * @param val Change the values of sleep_status_on_int in reg INT_CFG0
4035 * @retval Interface status (MANDATORY: return 0 -> no Error).
4036 *
4037 */
asm330lhhxg1_act_pin_notification_set(const stmdev_ctx_t * ctx,asm330lhhxg1_sleep_status_on_int_t val)4038 int32_t asm330lhhxg1_act_pin_notification_set(const stmdev_ctx_t *ctx,
4039 asm330lhhxg1_sleep_status_on_int_t val)
4040 {
4041 asm330lhhxg1_int_cfg0_t int_cfg0;
4042 int32_t ret;
4043
4044 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4045 if (ret == 0)
4046 {
4047 int_cfg0. sleep_status_on_int = (uint8_t)val;
4048 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG0,
4049 (uint8_t *)&int_cfg0, 1);
4050 }
4051 return ret;
4052 }
4053
4054 /**
4055 * @brief Drives the sleep status instead of sleep change on INT pins
4056 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4057 * are enabled).[get]
4058 *
4059 * @param ctx Read / write interface definitions.(ptr)
4060 * @param val Get the values of sleep_status_on_int in reg INT_CFG0
4061 * @retval Interface status (MANDATORY: return 0 -> no Error).
4062 *
4063 */
asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t * ctx,asm330lhhxg1_sleep_status_on_int_t * val)4064 int32_t asm330lhhxg1_act_pin_notification_get(const stmdev_ctx_t *ctx,
4065 asm330lhhxg1_sleep_status_on_int_t *val)
4066 {
4067 asm330lhhxg1_int_cfg0_t int_cfg0;
4068 int32_t ret;
4069
4070 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4071 switch (int_cfg0. sleep_status_on_int)
4072 {
4073 case ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT:
4074 *val = ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT;
4075 break;
4076 case ASM330LHHXG1_DRIVE_SLEEP_STATUS:
4077 *val = ASM330LHHXG1_DRIVE_SLEEP_STATUS;
4078 break;
4079 default:
4080 *val = ASM330LHHXG1_DRIVE_SLEEP_CHG_EVENT;
4081 break;
4082 }
4083 return ret;
4084 }
4085
4086 /**
4087 * @brief Enable inactivity function.[set]
4088 *
4089 * @param ctx Read / write interface definitions.(ptr)
4090 * @param val Change the values of inact_en in reg INT_CFG1
4091 * @retval Interface status (MANDATORY: return 0 -> no Error).
4092 *
4093 */
asm330lhhxg1_act_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_inact_en_t val)4094 int32_t asm330lhhxg1_act_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_inact_en_t val)
4095 {
4096 asm330lhhxg1_int_cfg1_t int_cfg1;
4097 int32_t ret;
4098
4099 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4100 if (ret == 0)
4101 {
4102 int_cfg1.inact_en = (uint8_t)val;
4103 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4104 }
4105 return ret;
4106 }
4107
4108 /**
4109 * @brief Enable inactivity function.[get]
4110 *
4111 * @param ctx Read / write interface definitions.(ptr)
4112 * @param val Get the values of inact_en in reg INT_CFG1
4113 * @retval Interface status (MANDATORY: return 0 -> no Error).
4114 *
4115 */
asm330lhhxg1_act_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_inact_en_t * val)4116 int32_t asm330lhhxg1_act_mode_get(const stmdev_ctx_t *ctx,
4117 asm330lhhxg1_inact_en_t *val)
4118 {
4119 asm330lhhxg1_int_cfg1_t int_cfg1;
4120 int32_t ret;
4121
4122 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4123
4124 switch (int_cfg1.inact_en)
4125 {
4126 case ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED:
4127 *val = ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED;
4128 break;
4129 case ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED:
4130 *val = ASM330LHHXG1_XL_12Hz5_GY_NOT_AFFECTED;
4131 break;
4132 case ASM330LHHXG1_XL_12Hz5_GY_SLEEP:
4133 *val = ASM330LHHXG1_XL_12Hz5_GY_SLEEP;
4134 break;
4135 case ASM330LHHXG1_XL_12Hz5_GY_PD:
4136 *val = ASM330LHHXG1_XL_12Hz5_GY_PD;
4137 break;
4138 default:
4139 *val = ASM330LHHXG1_XL_AND_GY_NOT_AFFECTED;
4140 break;
4141 }
4142 return ret;
4143 }
4144
4145 /**
4146 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
4147 *
4148 * @param ctx Read / write interface definitions.(ptr)
4149 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4150 * @retval Interface status (MANDATORY: return 0 -> no Error).
4151 *
4152 */
asm330lhhxg1_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4153 int32_t asm330lhhxg1_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4154 {
4155 asm330lhhxg1_wake_up_dur_t wake_up_dur;
4156 int32_t ret;
4157
4158 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4159 (uint8_t *)&wake_up_dur, 1);
4160 if (ret == 0)
4161 {
4162 wake_up_dur.sleep_dur = (uint8_t)val;
4163 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4164 (uint8_t *)&wake_up_dur, 1);
4165 }
4166 return ret;
4167 }
4168
4169 /**
4170 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
4171 *
4172 * @param ctx Read / write interface definitions.(ptr)
4173 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4174 * @retval Interface status (MANDATORY: return 0 -> no Error).
4175 *
4176 */
asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4177 int32_t asm330lhhxg1_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4178 {
4179 asm330lhhxg1_wake_up_dur_t wake_up_dur;
4180 int32_t ret;
4181
4182 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4183 (uint8_t *)&wake_up_dur, 1);
4184 *val = wake_up_dur.sleep_dur;
4185
4186 return ret;
4187 }
4188
4189 /**
4190 * @}
4191 *
4192 */
4193
4194 /**
4195 * @defgroup ASM330LHHXG1_ Six_position_detection(6D/4D)
4196 * @brief This section groups all the functions concerning six
4197 * position detection (6D).
4198 * @{
4199 *
4200 */
4201
4202 /**
4203 * @brief Threshold for 4D/6D function.[set]
4204 *
4205 * @param ctx Read / write interface definitions.(ptr)
4206 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4207 * @retval Interface status (MANDATORY: return 0 -> no Error).
4208 *
4209 */
asm330lhhxg1_6d_threshold_set(const stmdev_ctx_t * ctx,asm330lhhxg1_sixd_ths_t val)4210 int32_t asm330lhhxg1_6d_threshold_set(const stmdev_ctx_t *ctx,
4211 asm330lhhxg1_sixd_ths_t val)
4212 {
4213 asm330lhhxg1_ths_6d_t ths_6d;
4214 int32_t ret;
4215
4216 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D,
4217 (uint8_t *)&ths_6d, 1);
4218 if (ret == 0)
4219 {
4220 ths_6d.sixd_ths = (uint8_t)val;
4221 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_THS_6D,
4222 (uint8_t *)&ths_6d, 1);
4223 }
4224 return ret;
4225 }
4226
4227 /**
4228 * @brief Threshold for 4D/6D function.[get]
4229 *
4230 * @param ctx Read / write interface definitions.(ptr)
4231 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4232 * @retval Interface status (MANDATORY: return 0 -> no Error).
4233 *
4234 */
asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t * ctx,asm330lhhxg1_sixd_ths_t * val)4235 int32_t asm330lhhxg1_6d_threshold_get(const stmdev_ctx_t *ctx,
4236 asm330lhhxg1_sixd_ths_t *val)
4237 {
4238 asm330lhhxg1_ths_6d_t ths_6d;
4239 int32_t ret;
4240
4241 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D,
4242 (uint8_t *)&ths_6d, 1);
4243
4244 switch (ths_6d.sixd_ths)
4245 {
4246 case ASM330LHHXG1_DEG_80:
4247 *val = ASM330LHHXG1_DEG_80;
4248 break;
4249 case ASM330LHHXG1_DEG_70:
4250 *val = ASM330LHHXG1_DEG_70;
4251 break;
4252 case ASM330LHHXG1_DEG_60:
4253 *val = ASM330LHHXG1_DEG_60;
4254 break;
4255 case ASM330LHHXG1_DEG_50:
4256 *val = ASM330LHHXG1_DEG_50;
4257 break;
4258 default:
4259 *val = ASM330LHHXG1_DEG_80;
4260 break;
4261 }
4262 return ret;
4263 }
4264
4265 /**
4266 * @brief 4D orientation detection enable.[set]
4267 *
4268 * @param ctx Read / write interface definitions.(ptr)
4269 * @param val Change the values of d4d_en in reg TAP_THS_6D
4270 * @retval Interface status (MANDATORY: return 0 -> no Error).
4271 *
4272 */
asm330lhhxg1_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4273 int32_t asm330lhhxg1_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4274 {
4275 asm330lhhxg1_ths_6d_t ths_6d;
4276 int32_t ret;
4277
4278 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D,
4279 (uint8_t *)&ths_6d, 1);
4280 if (ret == 0)
4281 {
4282 ths_6d.d4d_en = (uint8_t)val;
4283 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_THS_6D,
4284 (uint8_t *)&ths_6d, 1);
4285 }
4286 return ret;
4287 }
4288
4289 /**
4290 * @brief 4D orientation detection enable.[get]
4291 *
4292 * @param ctx Read / write interface definitions.(ptr)
4293 * @param val Change the values of d4d_en in reg TAP_THS_6D
4294 * @retval Interface status (MANDATORY: return 0 -> no Error).
4295 *
4296 */
asm330lhhxg1_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4297 int32_t asm330lhhxg1_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4298 {
4299 asm330lhhxg1_ths_6d_t ths_6d;
4300 int32_t ret;
4301
4302 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_THS_6D,
4303 (uint8_t *)&ths_6d, 1);
4304 *val = ths_6d.d4d_en;
4305
4306 return ret;
4307 }
4308
4309 /**
4310 * @}
4311 *
4312 */
4313
4314 /**
4315 * @defgroup ASM330LHHXG1_free_fall
4316 * @brief This section group all the functions concerning the free
4317 * fall detection.
4318 * @{
4319 *
4320 */
4321
4322 /**
4323 * @brief Free fall threshold setting.[set]
4324 *
4325 * @param ctx Read / write interface definitions.(ptr)
4326 * @param val Change the values of ff_ths in reg FREE_FALL
4327 * @retval Interface status (MANDATORY: return 0 -> no Error).
4328 *
4329 */
asm330lhhxg1_ff_threshold_set(const stmdev_ctx_t * ctx,asm330lhhxg1_ff_ths_t val)4330 int32_t asm330lhhxg1_ff_threshold_set(const stmdev_ctx_t *ctx,
4331 asm330lhhxg1_ff_ths_t val)
4332 {
4333 asm330lhhxg1_free_fall_t free_fall;
4334 int32_t ret;
4335
4336 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, (uint8_t *)&free_fall, 1);
4337 if (ret == 0)
4338 {
4339 free_fall.ff_ths = (uint8_t)val;
4340 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FREE_FALL,
4341 (uint8_t *)&free_fall, 1);
4342 }
4343 return ret;
4344 }
4345
4346 /**
4347 * @brief Free fall threshold setting.[get]
4348 *
4349 * @param ctx Read / write interface definitions.(ptr)
4350 * @param val Get the values of ff_ths in reg FREE_FALL
4351 * @retval Interface status (MANDATORY: return 0 -> no Error).
4352 *
4353 */
asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t * ctx,asm330lhhxg1_ff_ths_t * val)4354 int32_t asm330lhhxg1_ff_threshold_get(const stmdev_ctx_t *ctx,
4355 asm330lhhxg1_ff_ths_t *val)
4356 {
4357 asm330lhhxg1_free_fall_t free_fall;
4358 int32_t ret;
4359
4360 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL, (uint8_t *)&free_fall, 1);
4361
4362 switch (free_fall.ff_ths)
4363 {
4364 case ASM330LHHXG1_FF_TSH_156mg:
4365 *val = ASM330LHHXG1_FF_TSH_156mg;
4366 break;
4367 case ASM330LHHXG1_FF_TSH_219mg:
4368 *val = ASM330LHHXG1_FF_TSH_219mg;
4369 break;
4370 case ASM330LHHXG1_FF_TSH_250mg:
4371 *val = ASM330LHHXG1_FF_TSH_250mg;
4372 break;
4373 case ASM330LHHXG1_FF_TSH_312mg:
4374 *val = ASM330LHHXG1_FF_TSH_312mg;
4375 break;
4376 case ASM330LHHXG1_FF_TSH_344mg:
4377 *val = ASM330LHHXG1_FF_TSH_344mg;
4378 break;
4379 case ASM330LHHXG1_FF_TSH_406mg:
4380 *val = ASM330LHHXG1_FF_TSH_406mg;
4381 break;
4382 case ASM330LHHXG1_FF_TSH_469mg:
4383 *val = ASM330LHHXG1_FF_TSH_469mg;
4384 break;
4385 case ASM330LHHXG1_FF_TSH_500mg:
4386 *val = ASM330LHHXG1_FF_TSH_500mg;
4387 break;
4388 default:
4389 *val = ASM330LHHXG1_FF_TSH_156mg;
4390 break;
4391 }
4392 return ret;
4393 }
4394
4395 /**
4396 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
4397 *
4398 * @param ctx Read / write interface definitions.(ptr)
4399 * @param val Change the values of ff_dur in reg FREE_FALL
4400 * @retval Interface status (MANDATORY: return 0 -> no Error).
4401 *
4402 */
asm330lhhxg1_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4403 int32_t asm330lhhxg1_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4404 {
4405 asm330lhhxg1_wake_up_dur_t wake_up_dur;
4406 asm330lhhxg1_free_fall_t free_fall;
4407 int32_t ret;
4408
4409 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4410 (uint8_t *)&wake_up_dur, 1);
4411 if (ret == 0)
4412 {
4413 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4414 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4415 (uint8_t *)&wake_up_dur, 1);
4416 }
4417 if (ret == 0)
4418 {
4419 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL,
4420 (uint8_t *)&free_fall, 1);
4421 }
4422 if (ret == 0)
4423 {
4424 free_fall.ff_dur = val & 0x1FU;
4425 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FREE_FALL,
4426 (uint8_t *)&free_fall, 1);
4427 }
4428 return ret;
4429 }
4430
4431 /**
4432 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
4433 *
4434 * @param ctx Read / write interface definitions.(ptr)
4435 * @param val Change the values of ff_dur in reg FREE_FALL
4436 * @retval Interface status (MANDATORY: return 0 -> no Error).
4437 *
4438 */
asm330lhhxg1_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4439 int32_t asm330lhhxg1_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4440 {
4441 asm330lhhxg1_wake_up_dur_t wake_up_dur;
4442 asm330lhhxg1_free_fall_t free_fall;
4443 int32_t ret;
4444
4445 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_WAKE_UP_DUR,
4446 (uint8_t *)&wake_up_dur, 1);
4447
4448 if (ret == 0)
4449 {
4450 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FREE_FALL,
4451 (uint8_t *)&free_fall, 1);
4452 }
4453 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4454
4455 return ret;
4456 }
4457
4458 /**
4459 * @}
4460 *
4461 */
4462
4463 /**
4464 * @defgroup ASM330LHHXG1_fifo
4465 * @brief This section group all the functions concerning
4466 * the fifo usage
4467 * @{
4468 *
4469 */
4470
4471 /**
4472 * @brief FIFO watermark level selection.[set]
4473 *
4474 * @param ctx Read / write interface definitions.(ptr)
4475 * @param val Change the values of wtm in reg FIFO_CTRL1
4476 * @retval Interface status (MANDATORY: return 0 -> no Error).
4477 *
4478 */
asm330lhhxg1_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)4479 int32_t asm330lhhxg1_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
4480 {
4481 asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1;
4482 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4483 int32_t ret;
4484
4485 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4486 (uint8_t *)&fifo_ctrl2, 1);
4487 if (ret == 0)
4488 {
4489 fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
4490 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4491 (uint8_t *)&fifo_ctrl2, 1);
4492 }
4493 if (ret == 0)
4494 {
4495 fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
4496 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL1,
4497 (uint8_t *)&fifo_ctrl1, 1);
4498 }
4499
4500 return ret;
4501 }
4502
4503 /**
4504 * @brief FIFO watermark level selection.[get]
4505 *
4506 * @param ctx Read / write interface definitions.(ptr)
4507 * @param val Change the values of wtm in reg FIFO_CTRL1
4508 * @retval Interface status (MANDATORY: return 0 -> no Error).
4509 *
4510 */
asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)4511 int32_t asm330lhhxg1_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
4512 {
4513 asm330lhhxg1_fifo_ctrl1_t fifo_ctrl1;
4514 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4515 int32_t ret;
4516
4517 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4518 (uint8_t *)&fifo_ctrl2, 1);
4519 if (ret == 0)
4520 {
4521 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL1,
4522 (uint8_t *)&fifo_ctrl1, 1);
4523 }
4524 *val = fifo_ctrl2.wtm;
4525 *val = (*val * 256U) + fifo_ctrl1.wtm;
4526 return ret;
4527 }
4528
4529 /**
4530 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4531 *
4532 * @param ctx Read / write interface definitions.(ptr)
4533 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4534 * @retval Interface status (MANDATORY: return 0 -> no Error).
4535 *
4536 */
asm330lhhxg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4537 int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4538 uint8_t val)
4539 {
4540 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4541 int32_t ret;
4542
4543 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4544 (uint8_t *)&fifo_ctrl2, 1);
4545 if (ret == 0)
4546 {
4547 fifo_ctrl2.odrchg_en = (uint8_t)val;
4548 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4549 (uint8_t *)&fifo_ctrl2, 1);
4550 }
4551
4552 return ret;
4553 }
4554
4555 /**
4556 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4557 *
4558 * @param ctx Read / write interface definitions.(ptr)
4559 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4560 * @retval Interface status (MANDATORY: return 0 -> no Error).
4561 *
4562 */
asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4563 int32_t asm330lhhxg1_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4564 uint8_t *val)
4565 {
4566 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4567 int32_t ret;
4568
4569 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4570 (uint8_t *)&fifo_ctrl2, 1);
4571 *val = fifo_ctrl2.odrchg_en;
4572
4573 return ret;
4574 }
4575
4576 /**
4577 * @brief Sensing chain FIFO stop values memorization at threshold
4578 * level.[set]
4579 *
4580 * @param ctx Read / write interface definitions.(ptr)
4581 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4582 * @retval Interface status (MANDATORY: return 0 -> no Error).
4583 *
4584 */
asm330lhhxg1_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4585 int32_t asm330lhhxg1_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4586 {
4587 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4588 int32_t ret;
4589
4590 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4591 (uint8_t *)&fifo_ctrl2, 1);
4592 if (ret == 0)
4593 {
4594 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
4595 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4596 (uint8_t *)&fifo_ctrl2, 1);
4597 }
4598 return ret;
4599 }
4600
4601 /**
4602 * @brief Sensing chain FIFO stop values memorization at threshold
4603 * level.[get]
4604 *
4605 * @param ctx Read / write interface definitions.(ptr)
4606 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4607 * @retval Interface status (MANDATORY: return 0 -> no Error).
4608 *
4609 */
asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)4610 int32_t asm330lhhxg1_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4611 {
4612 asm330lhhxg1_fifo_ctrl2_t fifo_ctrl2;
4613 int32_t ret;
4614
4615 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL2,
4616 (uint8_t *)&fifo_ctrl2, 1);
4617 *val = fifo_ctrl2.stop_on_wtm;
4618
4619 return ret;
4620 }
4621
4622 /**
4623 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4624 * for accelerometer data.[set]
4625 *
4626 * @param ctx Read / write interface definitions.(ptr)
4627 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
4628 * @retval Interface status (MANDATORY: return 0 -> no Error).
4629 *
4630 */
asm330lhhxg1_fifo_xl_batch_set(const stmdev_ctx_t * ctx,asm330lhhxg1_bdr_xl_t val)4631 int32_t asm330lhhxg1_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
4632 asm330lhhxg1_bdr_xl_t val)
4633 {
4634 asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3;
4635 int32_t ret;
4636
4637 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4638 (uint8_t *)&fifo_ctrl3, 1);
4639 if (ret == 0)
4640 {
4641 fifo_ctrl3.bdr_xl = (uint8_t)val;
4642 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4643 (uint8_t *)&fifo_ctrl3, 1);
4644 }
4645 return ret;
4646 }
4647
4648 /**
4649 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4650 * for accelerometer data.[get]
4651 *
4652 * @param ctx Read / write interface definitions.(ptr)
4653 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
4654 * @retval Interface status (MANDATORY: return 0 -> no Error).
4655 *
4656 */
asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t * ctx,asm330lhhxg1_bdr_xl_t * val)4657 int32_t asm330lhhxg1_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
4658 asm330lhhxg1_bdr_xl_t *val)
4659 {
4660 asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3;
4661 int32_t ret;
4662
4663 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4664 (uint8_t *)&fifo_ctrl3, 1);
4665
4666 switch (fifo_ctrl3.bdr_xl)
4667 {
4668 case ASM330LHHXG1_XL_NOT_BATCHED:
4669 *val = ASM330LHHXG1_XL_NOT_BATCHED;
4670 break;
4671 case ASM330LHHXG1_XL_BATCHED_AT_12Hz5:
4672 *val = ASM330LHHXG1_XL_BATCHED_AT_12Hz5;
4673 break;
4674 case ASM330LHHXG1_XL_BATCHED_AT_26Hz:
4675 *val = ASM330LHHXG1_XL_BATCHED_AT_26Hz;
4676 break;
4677 case ASM330LHHXG1_XL_BATCHED_AT_52Hz:
4678 *val = ASM330LHHXG1_XL_BATCHED_AT_52Hz;
4679 break;
4680 case ASM330LHHXG1_XL_BATCHED_AT_104Hz:
4681 *val = ASM330LHHXG1_XL_BATCHED_AT_104Hz;
4682 break;
4683 case ASM330LHHXG1_XL_BATCHED_AT_208Hz:
4684 *val = ASM330LHHXG1_XL_BATCHED_AT_208Hz;
4685 break;
4686 case ASM330LHHXG1_XL_BATCHED_AT_417Hz:
4687 *val = ASM330LHHXG1_XL_BATCHED_AT_417Hz;
4688 break;
4689 case ASM330LHHXG1_XL_BATCHED_AT_833Hz:
4690 *val = ASM330LHHXG1_XL_BATCHED_AT_833Hz;
4691 break;
4692 case ASM330LHHXG1_XL_BATCHED_AT_1667Hz:
4693 *val = ASM330LHHXG1_XL_BATCHED_AT_1667Hz;
4694 break;
4695 case ASM330LHHXG1_XL_BATCHED_AT_3333Hz:
4696 *val = ASM330LHHXG1_XL_BATCHED_AT_3333Hz;
4697 break;
4698 case ASM330LHHXG1_XL_BATCHED_AT_6667Hz:
4699 *val = ASM330LHHXG1_XL_BATCHED_AT_6667Hz;
4700 break;
4701 case ASM330LHHXG1_XL_BATCHED_AT_1Hz6:
4702 *val = ASM330LHHXG1_XL_BATCHED_AT_1Hz6;
4703 break;
4704 default:
4705 *val = ASM330LHHXG1_XL_NOT_BATCHED;
4706 break;
4707 }
4708 return ret;
4709 }
4710
4711 /**
4712 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4713 * for gyroscope data.[set]
4714 *
4715 * @param ctx Read / write interface definitions.(ptr)
4716 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
4717 * @retval Interface status (MANDATORY: return 0 -> no Error).
4718 *
4719 */
asm330lhhxg1_fifo_gy_batch_set(const stmdev_ctx_t * ctx,asm330lhhxg1_bdr_gy_t val)4720 int32_t asm330lhhxg1_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
4721 asm330lhhxg1_bdr_gy_t val)
4722 {
4723 asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3;
4724 int32_t ret;
4725
4726 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4727 (uint8_t *)&fifo_ctrl3, 1);
4728 if (ret == 0)
4729 {
4730 fifo_ctrl3.bdr_gy = (uint8_t)val;
4731 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4732 (uint8_t *)&fifo_ctrl3, 1);
4733 }
4734 return ret;
4735 }
4736
4737 /**
4738 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4739 * for gyroscope data.[get]
4740 *
4741 * @param ctx Read / write interface definitions.(ptr)
4742 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
4743 * @retval Interface status (MANDATORY: return 0 -> no Error).
4744 *
4745 */
asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t * ctx,asm330lhhxg1_bdr_gy_t * val)4746 int32_t asm330lhhxg1_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
4747 asm330lhhxg1_bdr_gy_t *val)
4748 {
4749 asm330lhhxg1_fifo_ctrl3_t fifo_ctrl3;
4750 int32_t ret;
4751
4752 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL3,
4753 (uint8_t *)&fifo_ctrl3, 1);
4754
4755 switch (fifo_ctrl3.bdr_gy)
4756 {
4757 case ASM330LHHXG1_GY_NOT_BATCHED:
4758 *val = ASM330LHHXG1_GY_NOT_BATCHED;
4759 break;
4760 case ASM330LHHXG1_GY_BATCHED_AT_12Hz5:
4761 *val = ASM330LHHXG1_GY_BATCHED_AT_12Hz5;
4762 break;
4763 case ASM330LHHXG1_GY_BATCHED_AT_26Hz:
4764 *val = ASM330LHHXG1_GY_BATCHED_AT_26Hz;
4765 break;
4766 case ASM330LHHXG1_GY_BATCHED_AT_52Hz:
4767 *val = ASM330LHHXG1_GY_BATCHED_AT_52Hz;
4768 break;
4769 case ASM330LHHXG1_GY_BATCHED_AT_104Hz:
4770 *val = ASM330LHHXG1_GY_BATCHED_AT_104Hz;
4771 break;
4772 case ASM330LHHXG1_GY_BATCHED_AT_208Hz:
4773 *val = ASM330LHHXG1_GY_BATCHED_AT_208Hz;
4774 break;
4775 case ASM330LHHXG1_GY_BATCHED_AT_417Hz:
4776 *val = ASM330LHHXG1_GY_BATCHED_AT_417Hz;
4777 break;
4778 case ASM330LHHXG1_GY_BATCHED_AT_833Hz:
4779 *val = ASM330LHHXG1_GY_BATCHED_AT_833Hz;
4780 break;
4781 case ASM330LHHXG1_GY_BATCHED_AT_1667Hz:
4782 *val = ASM330LHHXG1_GY_BATCHED_AT_1667Hz;
4783 break;
4784 case ASM330LHHXG1_GY_BATCHED_AT_3333Hz:
4785 *val = ASM330LHHXG1_GY_BATCHED_AT_3333Hz;
4786 break;
4787 case ASM330LHHXG1_GY_BATCHED_AT_6667Hz:
4788 *val = ASM330LHHXG1_GY_BATCHED_AT_6667Hz;
4789 break;
4790 case ASM330LHHXG1_GY_BATCHED_AT_6Hz5:
4791 *val = ASM330LHHXG1_GY_BATCHED_AT_6Hz5;
4792 break;
4793 default:
4794 *val = ASM330LHHXG1_GY_NOT_BATCHED;
4795 break;
4796 }
4797 return ret;
4798 }
4799
4800 /**
4801 * @brief FIFO mode selection.[set]
4802 *
4803 * @param ctx Read / write interface definitions.(ptr)
4804 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
4805 * @retval Interface status (MANDATORY: return 0 -> no Error).
4806 *
4807 */
asm330lhhxg1_fifo_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_fifo_mode_t val)4808 int32_t asm330lhhxg1_fifo_mode_set(const stmdev_ctx_t *ctx,
4809 asm330lhhxg1_fifo_mode_t val)
4810 {
4811 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4812 int32_t ret;
4813
4814 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4815 (uint8_t *)&fifo_ctrl4, 1);
4816 if (ret == 0)
4817 {
4818 fifo_ctrl4.fifo_mode = (uint8_t)val;
4819 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4820 (uint8_t *)&fifo_ctrl4, 1);
4821 }
4822 return ret;
4823 }
4824
4825 /**
4826 * @brief FIFO mode selection.[get]
4827 *
4828 * @param ctx Read / write interface definitions.(ptr)
4829 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
4830 * @retval Interface status (MANDATORY: return 0 -> no Error).
4831 *
4832 */
asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fifo_mode_t * val)4833 int32_t asm330lhhxg1_fifo_mode_get(const stmdev_ctx_t *ctx,
4834 asm330lhhxg1_fifo_mode_t *val)
4835 {
4836 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4837 int32_t ret;
4838
4839 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4840 (uint8_t *)&fifo_ctrl4, 1);
4841
4842 switch (fifo_ctrl4.fifo_mode)
4843 {
4844 case ASM330LHHXG1_BYPASS_MODE:
4845 *val = ASM330LHHXG1_BYPASS_MODE;
4846 break;
4847 case ASM330LHHXG1_FIFO_MODE:
4848 *val = ASM330LHHXG1_FIFO_MODE;
4849 break;
4850 case ASM330LHHXG1_STREAM_TO_FIFO_MODE:
4851 *val = ASM330LHHXG1_STREAM_TO_FIFO_MODE;
4852 break;
4853 case ASM330LHHXG1_BYPASS_TO_STREAM_MODE:
4854 *val = ASM330LHHXG1_BYPASS_TO_STREAM_MODE;
4855 break;
4856 case ASM330LHHXG1_STREAM_MODE:
4857 *val = ASM330LHHXG1_STREAM_MODE;
4858 break;
4859 case ASM330LHHXG1_BYPASS_TO_FIFO_MODE:
4860 *val = ASM330LHHXG1_BYPASS_TO_FIFO_MODE;
4861 break;
4862 default:
4863 *val = ASM330LHHXG1_BYPASS_MODE;
4864 break;
4865 }
4866 return ret;
4867 }
4868
4869 /**
4870 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4871 * for temperature data.[set]
4872 *
4873 * @param ctx Read / write interface definitions.(ptr)
4874 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
4875 * @retval Interface status (MANDATORY: return 0 -> no Error).
4876 *
4877 */
asm330lhhxg1_fifo_temp_batch_set(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_t_batch_t val)4878 int32_t asm330lhhxg1_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4879 asm330lhhxg1_odr_t_batch_t val)
4880 {
4881 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4882 int32_t ret;
4883
4884 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4885 (uint8_t *)&fifo_ctrl4, 1);
4886 if (ret == 0)
4887 {
4888 fifo_ctrl4.odr_t_batch = (uint8_t)val;
4889 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4890 (uint8_t *)&fifo_ctrl4, 1);
4891 }
4892 return ret;
4893 }
4894
4895 /**
4896 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4897 * for temperature data.[get]
4898 *
4899 * @param ctx Read / write interface definitions.(ptr)
4900 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
4901 * @retval Interface status (MANDATORY: return 0 -> no Error).
4902 *
4903 */
asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t * ctx,asm330lhhxg1_odr_t_batch_t * val)4904 int32_t asm330lhhxg1_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4905 asm330lhhxg1_odr_t_batch_t *val)
4906 {
4907 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4908 int32_t ret;
4909
4910 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4911 (uint8_t *)&fifo_ctrl4, 1);
4912
4913 switch (fifo_ctrl4.odr_t_batch)
4914 {
4915 case ASM330LHHXG1_TEMP_NOT_BATCHED:
4916 *val = ASM330LHHXG1_TEMP_NOT_BATCHED;
4917 break;
4918 case ASM330LHHXG1_TEMP_BATCHED_AT_52Hz:
4919 *val = ASM330LHHXG1_TEMP_BATCHED_AT_52Hz;
4920 break;
4921 case ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5:
4922 *val = ASM330LHHXG1_TEMP_BATCHED_AT_12Hz5;
4923 break;
4924 case ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6:
4925 *val = ASM330LHHXG1_TEMP_BATCHED_AT_1Hz6;
4926 break;
4927 default:
4928 *val = ASM330LHHXG1_TEMP_NOT_BATCHED;
4929 break;
4930 }
4931 return ret;
4932 }
4933
4934 /**
4935 * @brief Selects decimation for timestamp batching in FIFO.
4936 * Writing rate will be the maximum rate between XL and
4937 * GYRO BDR divided by decimation decoder.[set]
4938 *
4939 * @param ctx Read / write interface definitions.(ptr)
4940 * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4
4941 * @retval Interface status (MANDATORY: return 0 -> no Error).
4942 *
4943 */
asm330lhhxg1_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,asm330lhhxg1_dec_ts_batch_t val)4944 int32_t asm330lhhxg1_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
4945 asm330lhhxg1_dec_ts_batch_t val)
4946 {
4947 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4948 int32_t ret;
4949
4950 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4951 (uint8_t *)&fifo_ctrl4, 1);
4952 if (ret == 0)
4953 {
4954 fifo_ctrl4.dec_ts_batch = (uint8_t)val;
4955 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4956 (uint8_t *)&fifo_ctrl4, 1);
4957 }
4958 return ret;
4959 }
4960
4961 /**
4962 * @brief Selects decimation for timestamp batching in FIFO.
4963 * Writing rate will be the maximum rate between XL and
4964 * GYRO BDR divided by decimation decoder.[get]
4965 *
4966 * @param ctx Read / write interface definitions.(ptr)
4967 * @param val Get the values of dec_ts_batch in reg
4968 * FIFO_CTRL4
4969 * @retval Interface status (MANDATORY: return 0 -> no Error).
4970 *
4971 */
asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,asm330lhhxg1_dec_ts_batch_t * val)4972 int32_t asm330lhhxg1_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
4973 asm330lhhxg1_dec_ts_batch_t *val)
4974 {
4975 asm330lhhxg1_fifo_ctrl4_t fifo_ctrl4;
4976 int32_t ret;
4977
4978 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_CTRL4,
4979 (uint8_t *)&fifo_ctrl4, 1);
4980
4981 switch (fifo_ctrl4.dec_ts_batch)
4982 {
4983 case ASM330LHHXG1_NO_DECIMATION:
4984 *val = ASM330LHHXG1_NO_DECIMATION;
4985 break;
4986 case ASM330LHHXG1_DEC_1:
4987 *val = ASM330LHHXG1_DEC_1;
4988 break;
4989 case ASM330LHHXG1_DEC_8:
4990 *val = ASM330LHHXG1_DEC_8;
4991 break;
4992 case ASM330LHHXG1_DEC_32:
4993 *val = ASM330LHHXG1_DEC_32;
4994 break;
4995 default:
4996 *val = ASM330LHHXG1_NO_DECIMATION;
4997 break;
4998 }
4999 return ret;
5000 }
5001
5002 /**
5003 * @brief Selects the trigger for the internal counter of batching events
5004 * between XL and gyro.[set]
5005 *
5006 * @param ctx Read / write interface definitions.(ptr)
5007 * @param val Change the values of trig_counter_bdr in
5008 * reg COUNTER_BDR_REG1
5009 * @retval Interface status (MANDATORY: return 0 -> no Error).
5010 *
5011 */
asm330lhhxg1_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,asm330lhhxg1_trig_counter_bdr_t val)5012 int32_t asm330lhhxg1_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
5013 asm330lhhxg1_trig_counter_bdr_t val)
5014 {
5015 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
5016 int32_t ret;
5017
5018 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5019 (uint8_t *)&counter_bdr_reg1, 1);
5020 if (ret == 0)
5021 {
5022 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
5023 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5024 (uint8_t *)&counter_bdr_reg1, 1);
5025 }
5026 return ret;
5027 }
5028
5029 /**
5030 * @brief Selects the trigger for the internal counter of batching events
5031 * between XL and gyro.[get]
5032 *
5033 * @param ctx Read / write interface definitions.(ptr)
5034 * @param val Get the values of trig_counter_bdr
5035 * in reg COUNTER_BDR_REG1
5036 * @retval Interface status (MANDATORY: return 0 -> no Error).
5037 *
5038 */
asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,asm330lhhxg1_trig_counter_bdr_t * val)5039 int32_t asm330lhhxg1_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
5040 asm330lhhxg1_trig_counter_bdr_t *val)
5041 {
5042 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
5043 int32_t ret;
5044
5045 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5046 (uint8_t *)&counter_bdr_reg1, 1);
5047
5048 switch (counter_bdr_reg1.trig_counter_bdr)
5049 {
5050 case ASM330LHHXG1_XL_BATCH_EVENT:
5051 *val = ASM330LHHXG1_XL_BATCH_EVENT;
5052 break;
5053 case ASM330LHHXG1_GYRO_BATCH_EVENT:
5054 *val = ASM330LHHXG1_GYRO_BATCH_EVENT;
5055 break;
5056 default:
5057 *val = ASM330LHHXG1_XL_BATCH_EVENT;
5058 break;
5059 }
5060 return ret;
5061 }
5062
5063 /**
5064 * @brief Resets the internal counter of batching events for a single sensor.
5065 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5066 *
5067 * @param ctx Read / write interface definitions.(ptr)
5068 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5069 * @retval Interface status (MANDATORY: return 0 -> no Error).
5070 *
5071 */
asm330lhhxg1_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)5072 int32_t asm330lhhxg1_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val)
5073 {
5074 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
5075 int32_t ret;
5076
5077 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5078 (uint8_t *)&counter_bdr_reg1, 1);
5079 if (ret == 0)
5080 {
5081 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
5082 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5083 (uint8_t *)&counter_bdr_reg1, 1);
5084 }
5085 return ret;
5086 }
5087
5088 /**
5089 * @brief Resets the internal counter of batching events for a single sensor.
5090 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5091 *
5092 * @param ctx Read / write interface definitions.(ptr)
5093 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5094 * @retval Interface status (MANDATORY: return 0 -> no Error).
5095 *
5096 */
asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)5097 int32_t asm330lhhxg1_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val)
5098 {
5099 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
5100 int32_t ret;
5101
5102 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5103 (uint8_t *)&counter_bdr_reg1, 1);
5104 *val = counter_bdr_reg1.rst_counter_bdr;
5105
5106 return ret;
5107 }
5108
5109 /**
5110 * @brief Batch data rate counter.[set]
5111 *
5112 * @param ctx Read / write interface definitions.(ptr)
5113 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5114 * and COUNTER_BDR_REG1.
5115 * @retval Interface status (MANDATORY: return 0 -> no Error).
5116 *
5117 */
asm330lhhxg1_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5118 int32_t asm330lhhxg1_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
5119 {
5120 asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg1;
5121 asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2;
5122 int32_t ret;
5123
5124 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5125 (uint8_t *)&counter_bdr_reg1, 1);
5126 if (ret == 0)
5127 {
5128 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
5129 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5130 (uint8_t *)&counter_bdr_reg1, 1);
5131 }
5132 if (ret == 0)
5133 {
5134 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
5135 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2,
5136 (uint8_t *)&counter_bdr_reg2, 1);
5137 }
5138 return ret;
5139 }
5140
5141 /**
5142 * @brief Batch data rate counter.[get]
5143 *
5144 * @param ctx Read / write interface definitions.(ptr)
5145 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5146 * and COUNTER_BDR_REG1.
5147 * @retval Interface status (MANDATORY: return 0 -> no Error).
5148 *
5149 */
asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5150 int32_t asm330lhhxg1_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5151 uint16_t *val)
5152 {
5153 asm330lhhxg1_counter_bdr_reg1_t counter_bdr_reg1;
5154 asm330lhhxg1_counter_bdr_reg2_t counter_bdr_reg2;
5155 int32_t ret;
5156
5157 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG1,
5158 (uint8_t *)&counter_bdr_reg1, 1);
5159 if (ret == 0)
5160 {
5161 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_COUNTER_BDR_REG2,
5162 (uint8_t *)&counter_bdr_reg2, 1);
5163 }
5164
5165 *val = counter_bdr_reg1.cnt_bdr_th;
5166 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
5167 return ret;
5168 }
5169
5170 /**
5171 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
5172 *
5173 * @param ctx Read / write interface definitions.(ptr)
5174 * @param val Change the values of diff_fifo in reg FIFO_STATUS1
5175 * @retval Interface status (MANDATORY: return 0 -> no Error).
5176 *
5177 */
asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5178 int32_t asm330lhhxg1_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
5179 {
5180 asm330lhhxg1_fifo_status1_t fifo_status1;
5181 asm330lhhxg1_fifo_status2_t fifo_status2;
5182 int32_t ret;
5183
5184 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS1,
5185 (uint8_t *)&fifo_status1, 1);
5186 if (ret == 0)
5187 {
5188 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2,
5189 (uint8_t *)&fifo_status2, 1);
5190
5191 *val = fifo_status2.diff_fifo;
5192 *val = (*val * 256U) + fifo_status1.diff_fifo;
5193 }
5194 return ret;
5195 }
5196
5197 /**
5198 * @brief Smart FIFO status.[get]
5199 *
5200 * @param ctx Read / write interface definitions.(ptr)
5201 * @param val Registers FIFO_STATUS2
5202 * @retval Interface status (MANDATORY: return 0 -> no Error).
5203 *
5204 */
asm330lhhxg1_fifo_status_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fifo_status2_t * val)5205 int32_t asm330lhhxg1_fifo_status_get(const stmdev_ctx_t *ctx,
5206 asm330lhhxg1_fifo_status2_t *val)
5207 {
5208 int32_t ret;
5209 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2, (uint8_t *)val, 1);
5210 return ret;
5211 }
5212
5213 /**
5214 * @brief Smart FIFO full status.[get]
5215 *
5216 * @param ctx Read / write interface definitions.(ptr)
5217 * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2
5218 * @retval Interface status (MANDATORY: return 0 -> no Error).
5219 *
5220 */
asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5221 int32_t asm330lhhxg1_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5222 {
5223 asm330lhhxg1_fifo_status2_t fifo_status2;
5224 int32_t ret;
5225
5226 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2,
5227 (uint8_t *)&fifo_status2, 1);
5228 *val = fifo_status2.fifo_full_ia;
5229
5230 return ret;
5231 }
5232
5233 /**
5234 * @brief FIFO overrun status.[get]
5235 *
5236 * @param ctx Read / write interface definitions.(ptr)
5237 * @param val Change the values of fifo_over_run_latched in
5238 * reg FIFO_STATUS2
5239 * @retval Interface status (MANDATORY: return 0 -> no Error).
5240 *
5241 */
asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5242 int32_t asm330lhhxg1_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5243 {
5244 asm330lhhxg1_fifo_status2_t fifo_status2;
5245 int32_t ret;
5246
5247 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2,
5248 (uint8_t *)&fifo_status2, 1);
5249 *val = fifo_status2. fifo_ovr_ia;
5250
5251 return ret;
5252 }
5253
5254 /**
5255 * @brief FIFO watermark status.[get]
5256 *
5257 * @param ctx Read / write interface definitions.(ptr)
5258 * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2
5259 * @retval Interface status (MANDATORY: return 0 -> no Error).
5260 *
5261 */
asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5262 int32_t asm330lhhxg1_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5263 {
5264 asm330lhhxg1_fifo_status2_t fifo_status2;
5265 int32_t ret;
5266
5267 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_STATUS2,
5268 (uint8_t *)&fifo_status2, 1);
5269 *val = fifo_status2.fifo_wtm_ia;
5270
5271 return ret;
5272 }
5273
5274 /**
5275 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
5276 *
5277 * @param ctx Read / write interface definitions.(ptr)
5278 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
5279 * @retval Interface status (MANDATORY: return 0 -> no Error).
5280 *
5281 */
asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fifo_tag_t * val)5282 int32_t asm330lhhxg1_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
5283 asm330lhhxg1_fifo_tag_t *val)
5284 {
5285 asm330lhhxg1_fifo_data_out_tag_t fifo_data_out_tag;
5286 int32_t ret;
5287
5288 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FIFO_DATA_OUT_TAG,
5289 (uint8_t *)&fifo_data_out_tag, 1);
5290
5291 switch (fifo_data_out_tag.tag_sensor)
5292 {
5293 case ASM330LHHXG1_GYRO_NC_TAG:
5294 *val = ASM330LHHXG1_GYRO_NC_TAG;
5295 break;
5296 case ASM330LHHXG1_XL_NC_TAG:
5297 *val = ASM330LHHXG1_XL_NC_TAG;
5298 break;
5299 case ASM330LHHXG1_TEMPERATURE_TAG:
5300 *val = ASM330LHHXG1_TEMPERATURE_TAG;
5301 break;
5302 case ASM330LHHXG1_TIMESTAMP_TAG:
5303 *val = ASM330LHHXG1_TIMESTAMP_TAG;
5304 break;
5305 case ASM330LHHXG1_CFG_CHANGE_TAG:
5306 *val = ASM330LHHXG1_CFG_CHANGE_TAG;
5307 break;
5308 case ASM330LHHXG1_SENSORHUB_SLAVE0_TAG:
5309 *val = ASM330LHHXG1_SENSORHUB_SLAVE0_TAG;
5310 break;
5311 case ASM330LHHXG1_SENSORHUB_SLAVE1_TAG:
5312 *val = ASM330LHHXG1_SENSORHUB_SLAVE1_TAG;
5313 break;
5314 case ASM330LHHXG1_SENSORHUB_SLAVE2_TAG:
5315 *val = ASM330LHHXG1_SENSORHUB_SLAVE2_TAG;
5316 break;
5317 case ASM330LHHXG1_SENSORHUB_SLAVE3_TAG:
5318 *val = ASM330LHHXG1_SENSORHUB_SLAVE3_TAG;
5319 break;
5320 case ASM330LHHXG1_SENSORHUB_NACK_TAG:
5321 *val = ASM330LHHXG1_SENSORHUB_NACK_TAG;
5322 break;
5323 default:
5324 *val = ASM330LHHXG1_SENSORHUB_NACK_TAG;
5325 break;
5326 }
5327 return ret;
5328 }
5329
5330 /**
5331 * @brief Enable FIFO batching data of first slave.[set]
5332 *
5333 * @param ctx Read / write interface definitions.(ptr)
5334 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
5335 * @retval Interface status (MANDATORY: return 0 -> no Error).
5336 *
5337 */
asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)5338 int32_t asm330lhhxg1_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val)
5339 {
5340 asm330lhhxg1_slv0_config_t slv0_config;
5341 int32_t ret;
5342
5343 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5344
5345 if (ret == 0)
5346 {
5347 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
5348 (uint8_t *)&slv0_config, 1);
5349 }
5350 if (ret == 0)
5351 {
5352 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
5353 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
5354 (uint8_t *)&slv0_config, 1);
5355 }
5356 if (ret == 0)
5357 {
5358 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5359 }
5360 return ret;
5361 }
5362
5363 /**
5364 * @brief Enable FIFO batching data of first slave.[get]
5365 *
5366 * @param ctx Read / write interface definitions.(ptr)
5367 * @param val Change the values of batch_ext_sens_0_en in
5368 * reg SLV0_CONFIG
5369 * @retval Interface status (MANDATORY: return 0 -> no Error).
5370 *
5371 */
asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)5372 int32_t asm330lhhxg1_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val)
5373 {
5374 asm330lhhxg1_slv0_config_t slv0_config;
5375 int32_t ret;
5376
5377 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5378
5379 if (ret == 0)
5380 {
5381 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
5382 (uint8_t *)&slv0_config, 1);
5383 }
5384 if (ret == 0)
5385 {
5386 *val = slv0_config. batch_ext_sens_0_en;
5387 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5388 }
5389 return ret;
5390 }
5391
5392 /**
5393 * @brief Enable FIFO batching data of second slave.[set]
5394 *
5395 * @param ctx Read / write interface definitions.(ptr)
5396 * @param val Change the values of batch_ext_sens_1_en in
5397 * reg SLV1_CONFIG
5398 * @retval Interface status (MANDATORY: return 0 -> no Error).
5399 *
5400 */
asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)5401 int32_t asm330lhhxg1_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val)
5402 {
5403 asm330lhhxg1_slv1_config_t slv1_config;
5404 int32_t ret;
5405
5406 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5407 if (ret == 0)
5408 {
5409 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG,
5410 (uint8_t *)&slv1_config, 1);
5411 }
5412 if (ret == 0)
5413 {
5414 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
5415 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG,
5416 (uint8_t *)&slv1_config, 1);
5417 }
5418 if (ret == 0)
5419 {
5420 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5421 }
5422 return ret;
5423 }
5424
5425 /**
5426 * @brief Enable FIFO batching data of second slave.[get]
5427 *
5428 * @param ctx Read / write interface definitions.(ptr)
5429 * @param val Change the values of batch_ext_sens_1_en in
5430 * reg SLV1_CONFIG
5431 * @retval Interface status (MANDATORY: return 0 -> no Error).
5432 *
5433 */
asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)5434 int32_t asm330lhhxg1_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5435 {
5436 asm330lhhxg1_slv1_config_t slv1_config;
5437 int32_t ret;
5438
5439 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5440
5441 if (ret == 0)
5442 {
5443 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG,
5444 (uint8_t *)&slv1_config, 1);
5445 *val = slv1_config. batch_ext_sens_1_en;
5446 }
5447 if (ret == 0)
5448 {
5449 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5450 }
5451 return ret;
5452 }
5453
5454 /**
5455 * @brief Enable FIFO batching data of third slave.[set]
5456 *
5457 * @param ctx Read / write interface definitions.(ptr)
5458 * @param val Change the values of batch_ext_sens_2_en in
5459 * reg SLV2_CONFIG
5460 * @retval Interface status (MANDATORY: return 0 -> no Error).
5461 *
5462 */
asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)5463 int32_t asm330lhhxg1_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val)
5464 {
5465 asm330lhhxg1_slv2_config_t slv2_config;
5466 int32_t ret;
5467
5468 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5469
5470 if (ret == 0)
5471 {
5472 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG,
5473 (uint8_t *)&slv2_config, 1);
5474 }
5475 if (ret == 0)
5476 {
5477 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
5478 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG,
5479 (uint8_t *)&slv2_config, 1);
5480 }
5481 if (ret == 0)
5482 {
5483 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5484 }
5485 return ret;
5486 }
5487
5488 /**
5489 * @brief Enable FIFO batching data of third slave.[get]
5490 *
5491 * @param ctx Read / write interface definitions.(ptr)
5492 * @param val Change the values of batch_ext_sens_2_en in
5493 * reg SLV2_CONFIG
5494 * @retval Interface status (MANDATORY: return 0 -> no Error).
5495 *
5496 */
asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)5497 int32_t asm330lhhxg1_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val)
5498 {
5499 asm330lhhxg1_slv2_config_t slv2_config;
5500 int32_t ret;
5501
5502 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5503 if (ret == 0)
5504 {
5505 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG,
5506 (uint8_t *)&slv2_config, 1);
5507 }
5508 if (ret == 0)
5509 {
5510 *val = slv2_config. batch_ext_sens_2_en;
5511 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5512 }
5513 return ret;
5514 }
5515
5516 /**
5517 * @brief Enable FIFO batching data of fourth slave.[set]
5518 *
5519 * @param ctx Read / write interface definitions.(ptr)
5520 * @param val Change the values of batch_ext_sens_3_en in
5521 * reg SLV3_CONFIG
5522 * @retval Interface status (MANDATORY: return 0 -> no Error).
5523 *
5524 */
asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)5525 int32_t asm330lhhxg1_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val)
5526 {
5527 asm330lhhxg1_slv3_config_t slv3_config;
5528 int32_t ret;
5529
5530 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5531 if (ret == 0)
5532 {
5533 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG,
5534 (uint8_t *)&slv3_config, 1);
5535 }
5536 if (ret == 0)
5537 {
5538 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
5539 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG,
5540 (uint8_t *)&slv3_config, 1);
5541 }
5542 if (ret == 0)
5543 {
5544 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5545 }
5546 return ret;
5547 }
5548
5549 /**
5550 * @brief Enable FIFO batching data of fourth slave.[get]
5551 *
5552 * @param ctx Read / write interface definitions.(ptr)
5553 * @param val Change the values of batch_ext_sens_3_en in
5554 * reg SLV3_CONFIG
5555 * @retval Interface status (MANDATORY: return 0 -> no Error).
5556 *
5557 */
asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)5558 int32_t asm330lhhxg1_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val)
5559 {
5560 asm330lhhxg1_slv3_config_t slv3_config;
5561 int32_t ret;
5562
5563 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
5564
5565 if (ret == 0)
5566 {
5567 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG,
5568 (uint8_t *)&slv3_config, 1);
5569 *val = slv3_config. batch_ext_sens_3_en;
5570 }
5571 if (ret == 0)
5572 {
5573 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
5574 }
5575 return ret;
5576 }
5577
5578 /**
5579 * @}
5580 *
5581 */
5582
5583 /**
5584 * @defgroup ASM330LHHXG1_DEN_functionality
5585 * @brief This section groups all the functions concerning
5586 * DEN functionality.
5587 * @{
5588 *
5589 */
5590
5591 /**
5592 * @brief DEN functionality marking mode.[set]
5593 *
5594 * @param ctx Read / write interface definitions.(ptr)
5595 * @param val Change the values of den_mode in reg CTRL6_C
5596 * @retval Interface status (MANDATORY: return 0 -> no Error).
5597 *
5598 */
asm330lhhxg1_den_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_den_mode_t val)5599 int32_t asm330lhhxg1_den_mode_set(const stmdev_ctx_t *ctx, asm330lhhxg1_den_mode_t val)
5600 {
5601 asm330lhhxg1_ctrl6_c_t ctrl6_c;
5602 int32_t ret;
5603
5604 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5605 if (ret == 0)
5606 {
5607 ctrl6_c.den_mode = (uint8_t)val;
5608 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5609 }
5610 return ret;
5611 }
5612
5613 /**
5614 * @brief DEN functionality marking mode.[get]
5615 *
5616 * @param ctx Read / write interface definitions.(ptr)
5617 * @param val Get the values of den_mode in reg CTRL6_C
5618 * @retval Interface status (MANDATORY: return 0 -> no Error).
5619 *
5620 */
asm330lhhxg1_den_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_den_mode_t * val)5621 int32_t asm330lhhxg1_den_mode_get(const stmdev_ctx_t *ctx,
5622 asm330lhhxg1_den_mode_t *val)
5623 {
5624 asm330lhhxg1_ctrl6_c_t ctrl6_c;
5625 int32_t ret;
5626
5627 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5628
5629 switch (ctrl6_c.den_mode)
5630 {
5631 case ASM330LHHXG1_DEN_DISABLE:
5632 *val = ASM330LHHXG1_DEN_DISABLE;
5633 break;
5634 case ASM330LHHXG1_LEVEL_FIFO:
5635 *val = ASM330LHHXG1_LEVEL_FIFO;
5636 break;
5637 case ASM330LHHXG1_LEVEL_LETCHED:
5638 *val = ASM330LHHXG1_LEVEL_LETCHED;
5639 break;
5640 case ASM330LHHXG1_LEVEL_TRIGGER:
5641 *val = ASM330LHHXG1_LEVEL_TRIGGER;
5642 break;
5643 case ASM330LHHXG1_EDGE_TRIGGER:
5644 *val = ASM330LHHXG1_EDGE_TRIGGER;
5645 break;
5646 default:
5647 *val = ASM330LHHXG1_DEN_DISABLE;
5648 break;
5649 }
5650 return ret;
5651 }
5652
5653 /**
5654 * @brief DEN active level configuration.[set]
5655 *
5656 * @param ctx Read / write interface definitions.(ptr)
5657 * @param val Change the values of den_lh in reg CTRL9_XL
5658 * @retval Interface status (MANDATORY: return 0 -> no Error).
5659 *
5660 */
asm330lhhxg1_den_polarity_set(const stmdev_ctx_t * ctx,asm330lhhxg1_den_lh_t val)5661 int32_t asm330lhhxg1_den_polarity_set(const stmdev_ctx_t *ctx,
5662 asm330lhhxg1_den_lh_t val)
5663 {
5664 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5665 int32_t ret;
5666
5667 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5668 if (ret == 0)
5669 {
5670 ctrl9_xl.den_lh = (uint8_t)val;
5671 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL,
5672 (uint8_t *)&ctrl9_xl, 1);
5673 }
5674 return ret;
5675 }
5676
5677 /**
5678 * @brief DEN active level configuration.[get]
5679 *
5680 * @param ctx Read / write interface definitions.(ptr)
5681 * @param val Get the values of den_lh in reg CTRL9_XL
5682 * @retval Interface status (MANDATORY: return 0 -> no Error).
5683 *
5684 */
asm330lhhxg1_den_polarity_get(const stmdev_ctx_t * ctx,asm330lhhxg1_den_lh_t * val)5685 int32_t asm330lhhxg1_den_polarity_get(const stmdev_ctx_t *ctx,
5686 asm330lhhxg1_den_lh_t *val)
5687 {
5688 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5689 int32_t ret;
5690
5691 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5692
5693 switch (ctrl9_xl.den_lh)
5694 {
5695 case ASM330LHHXG1_DEN_ACT_LOW:
5696 *val = ASM330LHHXG1_DEN_ACT_LOW;
5697 break;
5698 case ASM330LHHXG1_DEN_ACT_HIGH:
5699 *val = ASM330LHHXG1_DEN_ACT_HIGH;
5700 break;
5701 default:
5702 *val = ASM330LHHXG1_DEN_ACT_LOW;
5703 break;
5704 }
5705 return ret;
5706 }
5707
5708 /**
5709 * @brief DEN configuration.[set]
5710 *
5711 * @param ctx Read / write interface definitions.(ptr)
5712 * @param val Change the values of den_xl_g in reg CTRL9_XL
5713 * @retval Interface status (MANDATORY: return 0 -> no Error).
5714 *
5715 */
asm330lhhxg1_den_enable_set(const stmdev_ctx_t * ctx,asm330lhhxg1_den_xl_g_t val)5716 int32_t asm330lhhxg1_den_enable_set(const stmdev_ctx_t *ctx,
5717 asm330lhhxg1_den_xl_g_t val)
5718 {
5719 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5720 int32_t ret;
5721
5722 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5723 if (ret == 0)
5724 {
5725 ctrl9_xl.den_xl_g = (uint8_t)val;
5726 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL,
5727 (uint8_t *)&ctrl9_xl, 1);
5728 }
5729 return ret;
5730 }
5731
5732 /**
5733 * @brief DEN configuration.[get]
5734 *
5735 * @param ctx Read / write interface definitions.(ptr)
5736 * @param val Get the values of den_xl_g in reg CTRL9_XL
5737 * @retval Interface status (MANDATORY: return 0 -> no Error).
5738 *
5739 */
asm330lhhxg1_den_enable_get(const stmdev_ctx_t * ctx,asm330lhhxg1_den_xl_g_t * val)5740 int32_t asm330lhhxg1_den_enable_get(const stmdev_ctx_t *ctx,
5741 asm330lhhxg1_den_xl_g_t *val)
5742 {
5743 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5744 int32_t ret;
5745
5746 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5747
5748 switch (ctrl9_xl.den_xl_g)
5749 {
5750 case ASM330LHHXG1_STAMP_IN_GY_DATA:
5751 *val = ASM330LHHXG1_STAMP_IN_GY_DATA;
5752 break;
5753 case ASM330LHHXG1_STAMP_IN_XL_DATA:
5754 *val = ASM330LHHXG1_STAMP_IN_XL_DATA;
5755 break;
5756 case ASM330LHHXG1_STAMP_IN_GY_XL_DATA:
5757 *val = ASM330LHHXG1_STAMP_IN_GY_XL_DATA;
5758 break;
5759 default:
5760 *val = ASM330LHHXG1_STAMP_IN_GY_DATA;
5761 break;
5762 }
5763 return ret;
5764 }
5765
5766 /**
5767 * @brief DEN value stored in LSB of X-axis.[set]
5768 *
5769 * @param ctx Read / write interface definitions.(ptr)
5770 * @param val Change the values of den_z in reg CTRL9_XL
5771 * @retval Interface status (MANDATORY: return 0 -> no Error).
5772 *
5773 */
asm330lhhxg1_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)5774 int32_t asm330lhhxg1_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5775 {
5776 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5777 int32_t ret;
5778
5779 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5780 if (ret == 0)
5781 {
5782 ctrl9_xl.den_z = (uint8_t)val;
5783 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL,
5784 (uint8_t *)&ctrl9_xl, 1);
5785 }
5786 return ret;
5787 }
5788
5789 /**
5790 * @brief DEN value stored in LSB of X-axis.[get]
5791 *
5792 * @param ctx Read / write interface definitions.(ptr)
5793 * @param val Change the values of den_z in reg CTRL9_XL
5794 * @retval Interface status (MANDATORY: return 0 -> no Error).
5795 *
5796 */
asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5797 int32_t asm330lhhxg1_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
5798 {
5799 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5800 int32_t ret;
5801
5802 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5803 *val = ctrl9_xl.den_z;
5804
5805 return ret;
5806 }
5807
5808 /**
5809 * @brief DEN value stored in LSB of Y-axis.[set]
5810 *
5811 * @param ctx Read / write interface definitions.(ptr)
5812 * @param val Change the values of den_y in reg CTRL9_XL
5813 * @retval Interface status (MANDATORY: return 0 -> no Error).
5814 *
5815 */
asm330lhhxg1_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)5816 int32_t asm330lhhxg1_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5817 {
5818 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5819 int32_t ret;
5820
5821 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5822 if (ret == 0)
5823 {
5824 ctrl9_xl.den_y = (uint8_t)val;
5825 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL,
5826 (uint8_t *)&ctrl9_xl, 1);
5827 }
5828 return ret;
5829 }
5830
5831 /**
5832 * @brief DEN value stored in LSB of Y-axis.[get]
5833 *
5834 * @param ctx Read / write interface definitions.(ptr)
5835 * @param val Change the values of den_y in reg CTRL9_XL
5836 * @retval Interface status (MANDATORY: return 0 -> no Error).
5837 *
5838 */
asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5839 int32_t asm330lhhxg1_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
5840 {
5841 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5842 int32_t ret;
5843
5844 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5845 *val = ctrl9_xl.den_y;
5846
5847 return ret;
5848 }
5849
5850 /**
5851 * @brief DEN value stored in LSB of Z-axis.[set]
5852 *
5853 * @param ctx Read / write interface definitions.(ptr)
5854 * @param val Change the values of den_x in reg CTRL9_XL
5855 * @retval Interface status (MANDATORY: return 0 -> no Error).
5856 *
5857 */
asm330lhhxg1_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)5858 int32_t asm330lhhxg1_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5859 {
5860 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5861 int32_t ret;
5862
5863 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5864 if (ret == 0)
5865 {
5866 ctrl9_xl.den_x = (uint8_t)val;
5867 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5868 }
5869 return ret;
5870 }
5871
5872 /**
5873 * @brief DEN value stored in LSB of Z-axis.[get]
5874 *
5875 * @param ctx Read / write interface definitions.(ptr)
5876 * @param val Change the values of den_x in reg CTRL9_XL
5877 * @retval Interface status (MANDATORY: return 0 -> no Error).
5878 *
5879 */
asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5880 int32_t asm330lhhxg1_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
5881 {
5882 asm330lhhxg1_ctrl9_xl_t ctrl9_xl;
5883 int32_t ret;
5884
5885 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5886 *val = ctrl9_xl.den_x;
5887
5888 return ret;
5889 }
5890
5891 /**
5892 * @}
5893 *
5894 */
5895
5896 /**
5897 * @defgroup ASM330LHHXG1_ magnetometer_sensor
5898 * @brief This section groups all the functions that manage additional
5899 * magnetometer sensor.
5900 * @{
5901 *
5902 */
5903
5904 /**
5905 * @brief External magnetometer sensitivity value register.[set]
5906 *
5907 * @param ctx Read / write interface definitions.(ptr)
5908 * @param buff Buffer that contains data to write
5909 * @retval Interface status (MANDATORY: return 0 -> no Error).
5910 *
5911 */
asm330lhhxg1_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)5912 int32_t asm330lhhxg1_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
5913 {
5914 uint8_t buff[2];
5915 int32_t ret;
5916
5917 buff[1] = (uint8_t)(val / 256U);
5918 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5919 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_L, &buff[0]);
5920 if (ret == 0)
5921 {
5922 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_H, &buff[1]);
5923 }
5924 return ret;
5925 }
5926
5927 /**
5928 * @brief External magnetometer sensitivity value register.[get]
5929 *
5930 * @param ctx Read / write interface definitions.(ptr)
5931 * @param buff Buffer that stores data read
5932 * @retval Interface status (MANDATORY: return 0 -> no Error).
5933 *
5934 */
asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)5935 int32_t asm330lhhxg1_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
5936 {
5937 uint8_t buff[2];
5938 int32_t ret;
5939
5940 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_L, &buff[0]);
5941 if (ret == 0)
5942 {
5943 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SENSITIVITY_H, &buff[1]);
5944 *val = buff[1];
5945 *val = (*val * 256U) + buff[0];
5946 }
5947 return ret;
5948 }
5949
5950 /**
5951 * @brief Offset for hard-iron compensation register (r/w).[set]
5952 *
5953 * @param ctx Read / write interface definitions.(ptr)
5954 * @param buff Buffer that contains data to write
5955 * @retval Interface status (MANDATORY: return 0 -> no Error).
5956 *
5957 */
asm330lhhxg1_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)5958 int32_t asm330lhhxg1_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
5959 {
5960 uint8_t buff[6];
5961 int32_t ret;
5962 uint8_t i;
5963
5964 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
5965 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
5966 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
5967 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
5968 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
5969 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
5970
5971 i = 0x00U;
5972 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFX_L, &buff[i]);
5973 if (ret == 0)
5974 {
5975 i++;
5976 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFX_H, &buff[i]);
5977 }
5978 if (ret == 0)
5979 {
5980 i++;
5981 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFY_L, &buff[i]);
5982 }
5983 if (ret == 0)
5984 {
5985 i++;
5986 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFY_H, &buff[i]);
5987 }
5988 if (ret == 0)
5989 {
5990 i++;
5991 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFZ_L, &buff[i]);
5992 }
5993 if (ret == 0)
5994 {
5995 i++;
5996 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_OFFZ_H, &buff[i]);
5997 }
5998 return ret;
5999 }
6000
6001 /**
6002 * @brief Offset for hard-iron compensation register (r/w).[get]
6003 *
6004 * @param ctx Read / write interface definitions.(ptr)
6005 * @param buff Buffer that stores data read
6006 * @retval Interface status (MANDATORY: return 0 -> no Error).
6007 *
6008 */
asm330lhhxg1_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)6009 int32_t asm330lhhxg1_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
6010 {
6011 uint8_t buff[6];
6012 int32_t ret;
6013 uint8_t i;
6014
6015 i = 0x00U;
6016 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFX_L, &buff[i]);
6017
6018 if (ret == 0)
6019 {
6020 i++;
6021 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFX_H, &buff[i]);
6022 }
6023 if (ret == 0)
6024 {
6025 i++;
6026 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFY_L, &buff[i]);
6027 }
6028 if (ret == 0)
6029 {
6030 i++;
6031 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFY_H, &buff[i]);
6032 }
6033 if (ret == 0)
6034 {
6035 i++;
6036 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFZ_L, &buff[i]);
6037 }
6038 if (ret == 0)
6039 {
6040 i++;
6041 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_OFFZ_H, &buff[i]);
6042 }
6043 val[0] = (int16_t)buff[1];
6044 val[0] = (val[0] * 256) + (int16_t)buff[0];
6045 val[1] = (int16_t)buff[3];
6046 val[1] = (val[1] * 256) + (int16_t)buff[2];
6047 val[2] = (int16_t)buff[5];
6048 val[2] = (val[2] * 256) + (int16_t)buff[4];
6049
6050 return ret;
6051 }
6052
6053 /**
6054 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
6055 * The value is expressed as half-precision floating-point format:
6056 * SEEEEEFFFFFFFFFF
6057 * S: 1 sign bit;
6058 * E: 5 exponent bits;
6059 * F: 10 fraction bits).[set]
6060 *
6061 * @param ctx Read / write interface definitions.(ptr)
6062 * @param buff Buffer that contains data to write
6063 * @retval Interface status (MANDATORY: return 0 -> no Error).
6064 *
6065 */
asm330lhhxg1_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)6066 int32_t asm330lhhxg1_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
6067 {
6068 uint8_t buff[12];
6069 int32_t ret;
6070 uint8_t i;
6071
6072 buff[1] = (uint8_t)(val[0] / 256U);
6073 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
6074 buff[3] = (uint8_t)(val[1] / 256U);
6075 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
6076 buff[5] = (uint8_t)(val[2] / 256U);
6077 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
6078 buff[7] = (uint8_t)(val[3] / 256U);
6079 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
6080 buff[9] = (uint8_t)(val[4] / 256U);
6081 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
6082 buff[11] = (uint8_t)(val[5] / 256U);
6083 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
6084
6085 i = 0x00U;
6086 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XX_L, &buff[i]);
6087 if (ret == 0)
6088 {
6089 i++;
6090 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XX_H, &buff[i]);
6091 }
6092 if (ret == 0)
6093 {
6094 i++;
6095 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XY_L, &buff[i]);
6096 }
6097 if (ret == 0)
6098 {
6099 i++;
6100 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XY_H, &buff[i]);
6101 }
6102 if (ret == 0)
6103 {
6104 i++;
6105 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_L, &buff[i]);
6106 }
6107 if (ret == 0)
6108 {
6109 i++;
6110 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_H, &buff[i]);
6111 }
6112 if (ret == 0)
6113 {
6114 i++;
6115 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YY_L, &buff[i]);
6116 }
6117 if (ret == 0)
6118 {
6119 i++;
6120 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YY_H, &buff[i]);
6121 }
6122 if (ret == 0)
6123 {
6124 i++;
6125 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_L, &buff[i]);
6126 }
6127 if (ret == 0)
6128 {
6129 i++;
6130 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_H, &buff[i]);
6131 }
6132 if (ret == 0)
6133 {
6134 i++;
6135 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_L, &buff[i]);
6136 }
6137 if (ret == 0)
6138 {
6139 i++;
6140 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_H, &buff[i]);
6141 }
6142 return ret;
6143 }
6144
6145 /**
6146 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
6147 * The value is expressed as half-precision floating-point format:
6148 * SEEEEEFFFFFFFFFF
6149 * S: 1 sign bit;
6150 * E: 5 exponent bits;
6151 * F: 10 fraction bits).[get]
6152 *
6153 * @param ctx Read / write interface definitions.(ptr)
6154 * @param buff Buffer that stores data read
6155 * @retval Interface status (MANDATORY: return 0 -> no Error).
6156 *
6157 */
asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)6158 int32_t asm330lhhxg1_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
6159 {
6160 uint8_t buff[12];
6161 int32_t ret;
6162 uint8_t i;
6163
6164 i = 0x00U;
6165 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XX_L, &buff[i]);
6166 if (ret == 0)
6167 {
6168 i++;
6169 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XX_H, &buff[i]);
6170 }
6171 if (ret == 0)
6172 {
6173 i++;
6174 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XY_L, &buff[i]);
6175 }
6176 if (ret == 0)
6177 {
6178 i++;
6179 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XY_H, &buff[i]);
6180 }
6181 if (ret == 0)
6182 {
6183 i++;
6184 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_L, &buff[i]);
6185 }
6186 if (ret == 0)
6187 {
6188 i++;
6189 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_XZ_H, &buff[i]);
6190 }
6191 if (ret == 0)
6192 {
6193 i++;
6194 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YY_L, &buff[i]);
6195 }
6196 if (ret == 0)
6197 {
6198 i++;
6199 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YY_H, &buff[i]);
6200 }
6201 if (ret == 0)
6202 {
6203 i++;
6204 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_L, &buff[i]);
6205 }
6206 if (ret == 0)
6207 {
6208 i++;
6209 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_YZ_H, &buff[i]);
6210 }
6211 if (ret == 0)
6212 {
6213 i++;
6214 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_L, &buff[i]);
6215 }
6216 if (ret == 0)
6217 {
6218 i++;
6219 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_SI_ZZ_H, &buff[i]);
6220 }
6221
6222 val[0] = buff[1];
6223 val[0] = (val[0] * 256U) + buff[0];
6224 val[1] = buff[3];
6225 val[1] = (val[1] * 256U) + buff[2];
6226 val[2] = buff[5];
6227 val[2] = (val[2] * 256U) + buff[4];
6228 val[3] = buff[7];
6229 val[3] = (val[3] * 256U) + buff[6];
6230 val[4] = buff[9];
6231 val[4] = (val[4] * 256U) + buff[8];
6232 val[5] = buff[11];
6233 val[6] = (val[5] * 256U) + buff[10];
6234
6235 return ret;
6236 }
6237
6238 /**
6239 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
6240 * accelerometer/gyroscope axes orientation).[set]
6241 *
6242 * @param ctx Read / write interface definitions.(ptr)
6243 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
6244 * @retval Interface status (MANDATORY: return 0 -> no Error).
6245 *
6246 */
asm330lhhxg1_mag_z_orient_set(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_z_axis_t val)6247 int32_t asm330lhhxg1_mag_z_orient_set(const stmdev_ctx_t *ctx,
6248 asm330lhhxg1_mag_z_axis_t val)
6249 {
6250 asm330lhhxg1_mag_cfg_a_t mag_cfg_a;
6251 int32_t ret;
6252
6253 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6254 (uint8_t *)&mag_cfg_a);
6255
6256 if (ret == 0)
6257 {
6258 mag_cfg_a.mag_z_axis = (uint8_t)val;
6259 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6260 (uint8_t *)&mag_cfg_a);
6261 }
6262 return ret;
6263 }
6264
6265 /**
6266 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
6267 * accelerometer/gyroscope axes orientation).[get]
6268 *
6269 * @param ctx Read / write interface definitions.(ptr)
6270 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
6271 * @retval Interface status (MANDATORY: return 0 -> no Error).
6272 *
6273 */
asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_z_axis_t * val)6274 int32_t asm330lhhxg1_mag_z_orient_get(const stmdev_ctx_t *ctx,
6275 asm330lhhxg1_mag_z_axis_t *val)
6276 {
6277 asm330lhhxg1_mag_cfg_a_t mag_cfg_a;
6278 int32_t ret;
6279 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6280 (uint8_t *)&mag_cfg_a);
6281
6282 switch (mag_cfg_a.mag_z_axis)
6283 {
6284 case ASM330LHHXG1_Z_EQ_Y:
6285 *val = ASM330LHHXG1_Z_EQ_Y;
6286 break;
6287 case ASM330LHHXG1_Z_EQ_MIN_Y:
6288 *val = ASM330LHHXG1_Z_EQ_MIN_Y;
6289 break;
6290 case ASM330LHHXG1_Z_EQ_X:
6291 *val = ASM330LHHXG1_Z_EQ_X;
6292 break;
6293 case ASM330LHHXG1_Z_EQ_MIN_X:
6294 *val = ASM330LHHXG1_Z_EQ_MIN_X;
6295 break;
6296 case ASM330LHHXG1_Z_EQ_MIN_Z:
6297 *val = ASM330LHHXG1_Z_EQ_MIN_Z;
6298 break;
6299 case ASM330LHHXG1_Z_EQ_Z:
6300 *val = ASM330LHHXG1_Z_EQ_Z;
6301 break;
6302 default:
6303 *val = ASM330LHHXG1_Z_EQ_Y;
6304 break;
6305 }
6306 return ret;
6307 }
6308
6309 /**
6310 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
6311 * accelerometer/gyroscope axes orientation).[set]
6312 *
6313 * @param ctx Read / write interface definitions.(ptr)
6314 * @param val Change the values of mag_y_axis in
6315 * reg MAG_CFG_A
6316 * @retval Interface status (MANDATORY: return 0 -> no Error).
6317 *
6318 */
asm330lhhxg1_mag_y_orient_set(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_y_axis_t val)6319 int32_t asm330lhhxg1_mag_y_orient_set(const stmdev_ctx_t *ctx,
6320 asm330lhhxg1_mag_y_axis_t val)
6321 {
6322 asm330lhhxg1_mag_cfg_a_t mag_cfg_a;
6323 int32_t ret;
6324
6325 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6326 (uint8_t *)&mag_cfg_a);
6327 if (ret == 0)
6328 {
6329 mag_cfg_a.mag_y_axis = (uint8_t)val;
6330 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6331 (uint8_t *)&mag_cfg_a);
6332 }
6333 return ret;
6334 }
6335
6336 /**
6337 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
6338 * accelerometer/gyroscope axes orientation).[get]
6339 *
6340 * @param ctx Read / write interface definitions.(ptr)
6341 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
6342 * @retval Interface status (MANDATORY: return 0 -> no Error).
6343 *
6344 */
asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_y_axis_t * val)6345 int32_t asm330lhhxg1_mag_y_orient_get(const stmdev_ctx_t *ctx,
6346 asm330lhhxg1_mag_y_axis_t *val)
6347 {
6348 asm330lhhxg1_mag_cfg_a_t mag_cfg_a;
6349 int32_t ret;
6350
6351 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_A,
6352 (uint8_t *)&mag_cfg_a);
6353
6354 switch (mag_cfg_a.mag_y_axis)
6355 {
6356 case ASM330LHHXG1_Y_EQ_Y:
6357 *val = ASM330LHHXG1_Y_EQ_Y;
6358 break;
6359 case ASM330LHHXG1_Y_EQ_MIN_Y:
6360 *val = ASM330LHHXG1_Y_EQ_MIN_Y;
6361 break;
6362 case ASM330LHHXG1_Y_EQ_X:
6363 *val = ASM330LHHXG1_Y_EQ_X;
6364 break;
6365 case ASM330LHHXG1_Y_EQ_MIN_X:
6366 *val = ASM330LHHXG1_Y_EQ_MIN_X;
6367 break;
6368 case ASM330LHHXG1_Y_EQ_MIN_Z:
6369 *val = ASM330LHHXG1_Y_EQ_MIN_Z;
6370 break;
6371 case ASM330LHHXG1_Y_EQ_Z:
6372 *val = ASM330LHHXG1_Y_EQ_Z;
6373 break;
6374 default:
6375 *val = ASM330LHHXG1_Y_EQ_Y;
6376 break;
6377 }
6378 return ret;
6379 }
6380
6381 /**
6382 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
6383 * accelerometer/gyroscope axes orientation).[set]
6384 *
6385 * @param ctx Read / write interface definitions.(ptr)
6386 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
6387 * @retval Interface status (MANDATORY: return 0 -> no Error).
6388 *
6389 */
asm330lhhxg1_mag_x_orient_set(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_x_axis_t val)6390 int32_t asm330lhhxg1_mag_x_orient_set(const stmdev_ctx_t *ctx,
6391 asm330lhhxg1_mag_x_axis_t val)
6392 {
6393 asm330lhhxg1_mag_cfg_b_t mag_cfg_b;
6394 int32_t ret;
6395
6396 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_B,
6397 (uint8_t *)&mag_cfg_b);
6398 if (ret == 0)
6399 {
6400 mag_cfg_b.mag_x_axis = (uint8_t)val;
6401 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MAG_CFG_B,
6402 (uint8_t *)&mag_cfg_b);
6403 }
6404 return ret;
6405 }
6406
6407 /**
6408 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
6409 * accelerometer/gyroscope axes orientation).[get]
6410 *
6411 * @param ctx Read / write interface definitions.(ptr)
6412 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
6413 * @retval Interface status (MANDATORY: return 0 -> no Error).
6414 *
6415 */
asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t * ctx,asm330lhhxg1_mag_x_axis_t * val)6416 int32_t asm330lhhxg1_mag_x_orient_get(const stmdev_ctx_t *ctx,
6417 asm330lhhxg1_mag_x_axis_t *val)
6418 {
6419 asm330lhhxg1_mag_cfg_b_t mag_cfg_b;
6420 int32_t ret;
6421
6422 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MAG_CFG_B,
6423 (uint8_t *)&mag_cfg_b);
6424
6425 switch (mag_cfg_b.mag_x_axis)
6426 {
6427 case ASM330LHHXG1_X_EQ_Y:
6428 *val = ASM330LHHXG1_X_EQ_Y;
6429 break;
6430 case ASM330LHHXG1_X_EQ_MIN_Y:
6431 *val = ASM330LHHXG1_X_EQ_MIN_Y;
6432 break;
6433 case ASM330LHHXG1_X_EQ_X:
6434 *val = ASM330LHHXG1_X_EQ_X;
6435 break;
6436 case ASM330LHHXG1_X_EQ_MIN_X:
6437 *val = ASM330LHHXG1_X_EQ_MIN_X;
6438 break;
6439 case ASM330LHHXG1_X_EQ_MIN_Z:
6440 *val = ASM330LHHXG1_X_EQ_MIN_Z;
6441 break;
6442 case ASM330LHHXG1_X_EQ_Z:
6443 *val = ASM330LHHXG1_X_EQ_Z;
6444 break;
6445 default:
6446 *val = ASM330LHHXG1_X_EQ_Y;
6447 break;
6448 }
6449 return ret;
6450 }
6451
6452 /**
6453 * @}
6454 *
6455 */
6456
6457 /**
6458 * @defgroup ASM330LHHXG1_finite_state_machine
6459 * @brief This section groups all the functions that manage the
6460 * state_machine.
6461 * @{
6462 *
6463 */
6464
6465 /**
6466 * @brief FSM status register[get]
6467 *
6468 * @param ctx read / write interface definitions
6469 * @param val register ASM330LHHXG1_FSM_STATUS_A_MAINPAGE,
6470 * ASM330LHHXG1_FSM_STATUS_B_MAINPAGE
6471 *
6472 */
asm330lhhxg1_fsm_status_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fsm_status_t * val)6473 int32_t asm330lhhxg1_fsm_status_get(const stmdev_ctx_t *ctx,
6474 asm330lhhxg1_fsm_status_t *val)
6475 {
6476 asm330lhhxg1_fsm_status_a_mainpage_t status_a;
6477 asm330lhhxg1_fsm_status_b_mainpage_t status_b;
6478 int32_t ret;
6479
6480 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_A_MAINPAGE,
6481 (uint8_t *)&status_a, 1);
6482 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_STATUS_B_MAINPAGE,
6483 (uint8_t *)&status_b, 1);
6484
6485 val->fsm1 = status_a.is_fsm1;
6486 val->fsm2 = status_a.is_fsm2;
6487 val->fsm3 = status_a.is_fsm3;
6488 val->fsm4 = status_a.is_fsm4;
6489 val->fsm5 = status_a.is_fsm5;
6490 val->fsm6 = status_a.is_fsm6;
6491 val->fsm7 = status_a.is_fsm7;
6492 val->fsm8 = status_a.is_fsm8;
6493 val->fsm9 = status_b.is_fsm9;
6494 val->fsm10 = status_b.is_fsm10;
6495 val->fsm11 = status_b.is_fsm11;
6496 val->fsm12 = status_b.is_fsm12;
6497 val->fsm13 = status_b.is_fsm13;
6498 val->fsm14 = status_b.is_fsm14;
6499 val->fsm15 = status_b.is_fsm15;
6500 val->fsm16 = status_b.is_fsm16;
6501 return ret;
6502 }
6503
6504 /**
6505 * @brief prgsens_out: [get] Output value of all FSMs.
6506 *
6507 * @param ctx_t *ctx: read / write interface definitions
6508 * @param uint8_t * : buffer that stores data read
6509 *
6510 */
asm330lhhxg1_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)6511 int32_t asm330lhhxg1_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6512 {
6513 int32_t ret;
6514 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6515 if (ret == 0)
6516 {
6517 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_OUTS1, buff, 16);
6518 }
6519 if (ret == 0)
6520 {
6521 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6522 }
6523 return ret;
6524 }
6525
6526 /**
6527 * @brief Interrupt status bit for FSM long counter timeout interrupt
6528 * event.[get]
6529 *
6530 * @param ctx Read / write interface definitions.(ptr)
6531 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
6532 * @retval Interface status (MANDATORY: return 0 -> no Error).
6533 *
6534 */
asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)6535 int32_t asm330lhhxg1_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
6536 uint8_t *val)
6537 {
6538 asm330lhhxg1_emb_func_status_t emb_func_status;
6539 int32_t ret;
6540
6541 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6542 if (ret == 0)
6543 {
6544 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_STATUS,
6545 (uint8_t *)&emb_func_status, 1);
6546 }
6547 if (ret == 0)
6548 {
6549 *val = emb_func_status.is_fsm_lc;
6550 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6551 }
6552 return ret;
6553 }
6554
asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t * ctx,uint8_t val)6555 int32_t asm330lhhxg1_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val)
6556 {
6557 asm330lhhxg1_page_sel_t page_sel;
6558 int32_t ret;
6559
6560 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6561 if (ret == 0)
6562 {
6563 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL,
6564 (uint8_t *)&page_sel, 1);
6565
6566 page_sel.emb_func_clk_dis = val;
6567 }
6568
6569 ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6570
6571 return ret;
6572 }
6573
asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t * ctx,uint8_t * val)6574 int32_t asm330lhhxg1_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val)
6575 {
6576 asm330lhhxg1_page_sel_t page_sel;
6577 int32_t ret;
6578
6579 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6580 if (ret == 0)
6581 {
6582 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_PAGE_SEL,
6583 (uint8_t *)&page_sel, 1);
6584
6585 *val = page_sel.emb_func_clk_dis;
6586 }
6587
6588 ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6589
6590 return ret;
6591 }
6592
6593 /**
6594 * @brief Embedded final state machine functions mode.[set]
6595 *
6596 * @param ctx Read / write interface definitions.(ptr)
6597 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
6598 * @retval Interface status (MANDATORY: return 0 -> no Error).
6599 *
6600 */
asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)6601 int32_t asm330lhhxg1_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
6602 {
6603 int32_t ret;
6604 asm330lhhxg1_emb_func_en_b_t emb_func_en_b;
6605
6606 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6607
6608 if (ret == 0)
6609 {
6610 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6611 (uint8_t *)&emb_func_en_b, 1);
6612 }
6613 if (ret == 0)
6614 {
6615 emb_func_en_b.fsm_en = (uint8_t)val;
6616 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6617 (uint8_t *)&emb_func_en_b, 1);
6618 }
6619 if (ret == 0)
6620 {
6621 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6622 }
6623 return ret;
6624 }
6625
6626 /**
6627 * @brief Embedded final state machine functions mode.[get]
6628 *
6629 * @param ctx Read / write interface definitions.(ptr)
6630 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
6631 * @retval Interface status (MANDATORY: return 0 -> no Error).
6632 *
6633 */
asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)6634 int32_t asm330lhhxg1_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
6635 {
6636 int32_t ret;
6637 asm330lhhxg1_emb_func_en_b_t emb_func_en_b;
6638
6639 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6640 if (ret == 0)
6641 {
6642 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6643 (uint8_t *)&emb_func_en_b, 1);
6644 }
6645 if (ret == 0)
6646 {
6647 *val = emb_func_en_b.fsm_en;
6648 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6649 (uint8_t *)&emb_func_en_b, 1);
6650 }
6651 if (ret == 0)
6652 {
6653 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6654 }
6655 return ret;
6656 }
6657
6658 /**
6659 * @brief Embedded final state machine functions mode.[set]
6660 *
6661 * @param ctx Read / write interface definitions.(ptr)
6662 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
6663 * @retval Interface status (MANDATORY: return 0 -> no Error).
6664 *
6665 */
asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t * ctx,asm330lhhxg1_emb_fsm_enable_t * val)6666 int32_t asm330lhhxg1_fsm_enable_set(const stmdev_ctx_t *ctx,
6667 asm330lhhxg1_emb_fsm_enable_t *val)
6668 {
6669 asm330lhhxg1_emb_func_en_b_t emb_func_en_b;
6670 int32_t ret;
6671
6672 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6673 if (ret == 0)
6674 {
6675 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_ENABLE_A,
6676 (uint8_t *)&val->fsm_enable_a, 1);
6677 }
6678 if (ret == 0)
6679 {
6680 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_ENABLE_B,
6681 (uint8_t *)&val->fsm_enable_b, 1);
6682 }
6683 if (ret == 0)
6684 {
6685 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6686 (uint8_t *)&emb_func_en_b, 1);
6687 }
6688 if (ret == 0)
6689 {
6690 if ((val->fsm_enable_a.fsm1_en |
6691 val->fsm_enable_a.fsm2_en |
6692 val->fsm_enable_a.fsm3_en |
6693 val->fsm_enable_a.fsm4_en |
6694 val->fsm_enable_a.fsm5_en |
6695 val->fsm_enable_a.fsm6_en |
6696 val->fsm_enable_a.fsm7_en |
6697 val->fsm_enable_a.fsm8_en |
6698 val->fsm_enable_b.fsm9_en |
6699 val->fsm_enable_b.fsm10_en |
6700 val->fsm_enable_b.fsm11_en |
6701 val->fsm_enable_b.fsm12_en |
6702 val->fsm_enable_b.fsm13_en |
6703 val->fsm_enable_b.fsm14_en |
6704 val->fsm_enable_b.fsm15_en |
6705 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
6706 {
6707 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6708 }
6709 else
6710 {
6711 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6712 }
6713 }
6714 if (ret == 0)
6715 {
6716 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B,
6717 (uint8_t *)&emb_func_en_b, 1);
6718 }
6719 if (ret == 0)
6720 {
6721 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6722 }
6723 return ret;
6724 }
6725
6726 /**
6727 * @brief Embedded final state machine functions mode.[get]
6728 *
6729 * @param ctx Read / write interface definitions.(ptr)
6730 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
6731 * @retval Interface status (MANDATORY: return 0 -> no Error).
6732 *
6733 */
asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t * ctx,asm330lhhxg1_emb_fsm_enable_t * val)6734 int32_t asm330lhhxg1_fsm_enable_get(const stmdev_ctx_t *ctx,
6735 asm330lhhxg1_emb_fsm_enable_t *val)
6736 {
6737 int32_t ret;
6738
6739 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6740 if (ret == 0)
6741 {
6742 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_ENABLE_A,
6743 (uint8_t *)&val->fsm_enable_a, 1);
6744 }
6745 if (ret == 0)
6746 {
6747 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_ENABLE_B,
6748 (uint8_t *)&val->fsm_enable_b, 1);
6749 }
6750 if (ret == 0)
6751 {
6752 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6753 }
6754 return ret;
6755 }
6756
6757 /**
6758 * @brief FSM long counter status register. Long counter value is an
6759 * unsigned integer value (16-bit format).[set]
6760 *
6761 * @param ctx Read / write interface definitions.(ptr)
6762 * @param buff Buffer that contains data to write
6763 * @retval Interface status (MANDATORY: return 0 -> no Error).
6764 *
6765 */
asm330lhhxg1_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6766 int32_t asm330lhhxg1_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6767 {
6768 uint8_t buff[2];
6769 int32_t ret;
6770
6771 buff[1] = (uint8_t)(val / 256U);
6772 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6773
6774 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6775 if (ret == 0)
6776 {
6777 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2);
6778 }
6779 if (ret == 0)
6780 {
6781 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6782 }
6783 return ret;
6784 }
6785
6786 /**
6787 * @brief FSM long counter status register. Long counter value is an
6788 * unsigned integer value (16-bit format).[get]
6789 *
6790 * @param ctx Read / write interface definitions.(ptr)
6791 * @param buff Buffer that stores data read
6792 * @retval Interface status (MANDATORY: return 0 -> no Error).
6793 *
6794 */
asm330lhhxg1_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)6795 int32_t asm330lhhxg1_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
6796 {
6797 uint8_t buff[2];
6798 int32_t ret;
6799
6800 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6801 if (ret == 0)
6802 {
6803 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_L, buff, 2);
6804 *val = buff[1];
6805 *val = (*val * 256U) + buff[0];
6806 }
6807 if (ret == 0)
6808 {
6809 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6810 }
6811 return ret;
6812 }
6813
6814 /**
6815 * @brief Clear FSM long counter value.[set]
6816 *
6817 * @param ctx Read / write interface definitions.(ptr)
6818 * @param val Change the values of fsm_lc_clr in reg
6819 * FSM_LONG_COUNTER_CLEAR
6820 * @retval Interface status (MANDATORY: return 0 -> no Error).
6821 *
6822 */
asm330lhhxg1_long_clr_set(const stmdev_ctx_t * ctx,asm330lhhxg1_fsm_lc_clr_t val)6823 int32_t asm330lhhxg1_long_clr_set(const stmdev_ctx_t *ctx,
6824 asm330lhhxg1_fsm_lc_clr_t val)
6825 {
6826 asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear;
6827 int32_t ret;
6828
6829 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6830 if (ret == 0)
6831 {
6832 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR,
6833 (uint8_t *)&fsm_long_counter_clear, 1);
6834 }
6835 if (ret == 0)
6836 {
6837 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
6838 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR,
6839 (uint8_t *)&fsm_long_counter_clear, 1);
6840 }
6841 if (ret == 0)
6842 {
6843 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6844 }
6845 return ret;
6846 }
6847
6848 /**
6849 * @brief Clear FSM long counter value.[get]
6850 *
6851 * @param ctx Read / write interface definitions.(ptr)
6852 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
6853 * @retval Interface status (MANDATORY: return 0 -> no Error).
6854 *
6855 */
asm330lhhxg1_long_clr_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fsm_lc_clr_t * val)6856 int32_t asm330lhhxg1_long_clr_get(const stmdev_ctx_t *ctx,
6857 asm330lhhxg1_fsm_lc_clr_t *val)
6858 {
6859 asm330lhhxg1_fsm_long_counter_clear_t fsm_long_counter_clear;
6860 int32_t ret;
6861
6862 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6863
6864 if (ret == 0)
6865 {
6866 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_FSM_LONG_COUNTER_CLEAR,
6867 (uint8_t *)&fsm_long_counter_clear, 1);
6868 }
6869 if (ret == 0)
6870 {
6871 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6872 }
6873 switch (fsm_long_counter_clear.fsm_lc_clr)
6874 {
6875 case ASM330LHHXG1_LC_NORMAL:
6876 *val = ASM330LHHXG1_LC_NORMAL;
6877 break;
6878 case ASM330LHHXG1_LC_CLEAR:
6879 *val = ASM330LHHXG1_LC_CLEAR;
6880 break;
6881 case ASM330LHHXG1_LC_CLEAR_DONE:
6882 *val = ASM330LHHXG1_LC_CLEAR_DONE;
6883 break;
6884 default:
6885 *val = ASM330LHHXG1_LC_NORMAL;
6886 break;
6887 }
6888 return ret;
6889 }
6890
6891 /**
6892 * @brief Finite State Machine ODR configuration.[set]
6893 *
6894 * @param ctx Read / write interface definitions.(ptr)
6895 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6896 * @retval Interface status (MANDATORY: return 0 -> no Error).
6897 *
6898 */
asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhxg1_fsm_odr_t val)6899 int32_t asm330lhhxg1_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6900 asm330lhhxg1_fsm_odr_t val)
6901 {
6902 asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6903 int32_t ret;
6904
6905 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6906
6907 if (ret == 0)
6908 {
6909 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B,
6910 (uint8_t *)&emb_func_odr_cfg_b, 1);
6911 }
6912 if (ret == 0)
6913 {
6914 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
6915 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
6916 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
6917 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B,
6918 (uint8_t *)&emb_func_odr_cfg_b, 1);
6919 }
6920 if (ret == 0)
6921 {
6922 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6923 }
6924 return ret;
6925 }
6926
6927 /**
6928 * @brief Finite State Machine ODR configuration.[get]
6929 *
6930 * @param ctx Read / write interface definitions.(ptr)
6931 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6932 * @retval Interface status (MANDATORY: return 0 -> no Error).
6933 *
6934 */
asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhxg1_fsm_odr_t * val)6935 int32_t asm330lhhxg1_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6936 asm330lhhxg1_fsm_odr_t *val)
6937 {
6938 asm330lhhxg1_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6939 int32_t ret;
6940
6941 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6942
6943 if (ret == 0)
6944 {
6945 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_B,
6946 (uint8_t *)&emb_func_odr_cfg_b, 1);
6947 }
6948 if (ret == 0)
6949 {
6950 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
6951 }
6952 switch (emb_func_odr_cfg_b.fsm_odr)
6953 {
6954 case ASM330LHHXG1_ODR_FSM_12Hz5:
6955 *val = ASM330LHHXG1_ODR_FSM_12Hz5;
6956 break;
6957 case ASM330LHHXG1_ODR_FSM_26Hz:
6958 *val = ASM330LHHXG1_ODR_FSM_26Hz;
6959 break;
6960 case ASM330LHHXG1_ODR_FSM_52Hz:
6961 *val = ASM330LHHXG1_ODR_FSM_52Hz;
6962 break;
6963 case ASM330LHHXG1_ODR_FSM_104Hz:
6964 *val = ASM330LHHXG1_ODR_FSM_104Hz;
6965 break;
6966 default:
6967 *val = ASM330LHHXG1_ODR_FSM_12Hz5;
6968 break;
6969 }
6970 return ret;
6971 }
6972
6973 /**
6974 * @brief FSM initialization request.[set]
6975 *
6976 * @param ctx Read / write interface definitions.(ptr)
6977 * @param val Change the values of fsm_init in reg FSM_INIT
6978 * @retval Interface status (MANDATORY: return 0 -> no Error).
6979 *
6980 */
asm330lhhxg1_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)6981 int32_t asm330lhhxg1_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
6982 {
6983 asm330lhhxg1_emb_func_init_b_t emb_func_init_b;
6984 int32_t ret;
6985
6986 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
6987
6988 if (ret == 0)
6989 {
6990 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
6991 (uint8_t *)&emb_func_init_b, 1);
6992 }
6993 if (ret == 0)
6994 {
6995 emb_func_init_b.fsm_init = (uint8_t)val;
6996 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
6997 (uint8_t *)&emb_func_init_b, 1);
6998 }
6999 if (ret == 0)
7000 {
7001 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7002 }
7003 return ret;
7004 }
7005
7006 /**
7007 * @brief FSM initialization request.[get]
7008 *
7009 * @param ctx Read / write interface definitions.(ptr)
7010 * @param val Change the values of fsm_init in reg FSM_INIT
7011 * @retval Interface status (MANDATORY: return 0 -> no Error).
7012 *
7013 */
asm330lhhxg1_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)7014 int32_t asm330lhhxg1_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
7015 {
7016 asm330lhhxg1_emb_func_init_b_t emb_func_init_b;
7017 int32_t ret;
7018
7019 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7020 if (ret == 0)
7021 {
7022 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7023 (uint8_t *)&emb_func_init_b, 1);
7024 }
7025 if (ret == 0)
7026 {
7027 *val = emb_func_init_b.fsm_init;
7028 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7029 }
7030 return ret;
7031 }
7032
7033 /**
7034 * @brief FSM long counter timeout register (r/w). The long counter
7035 * timeout value is an unsigned integer value (16-bit format).
7036 * When the long counter value reached this value, the FSM
7037 * generates an interrupt.[set]
7038 *
7039 * @param ctx Read / write interface definitions.(ptr)
7040 * @param buff Buffer that contains data to write
7041 * @retval Interface status (MANDATORY: return 0 -> no Error).
7042 *
7043 */
asm330lhhxg1_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)7044 int32_t asm330lhhxg1_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val)
7045 {
7046 uint8_t buff[2];
7047 int32_t ret;
7048
7049 buff[1] = (uint8_t)(val / 256U);
7050 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7051 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_L, &buff[0]);
7052
7053 if (ret == 0)
7054 {
7055 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_H,
7056 &buff[1]);
7057 }
7058 return ret;
7059 }
7060
7061 /**
7062 * @brief FSM long counter timeout register (r/w). The long counter
7063 * timeout value is an unsigned integer value (16-bit format).
7064 * When the long counter value reached this value, the FSM generates
7065 * an interrupt.[get]
7066 *
7067 * @param ctx Read / write interface definitions.(ptr)
7068 * @param buff Buffer that stores data read
7069 * @retval Interface status (MANDATORY: return 0 -> no Error).
7070 *
7071 */
asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)7072 int32_t asm330lhhxg1_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val)
7073 {
7074 uint8_t buff[2];
7075 int32_t ret;
7076
7077 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_L, &buff[0]);
7078
7079 if (ret == 0)
7080 {
7081 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_LC_TIMEOUT_H,
7082 &buff[1]);
7083 *val = buff[1];
7084 *val = (*val * 256U) + buff[0];
7085 }
7086 return ret;
7087 }
7088
7089 /**
7090 * @brief FSM number of programs register.[set]
7091 *
7092 * @param ctx Read / write interface definitions.(ptr)
7093 * @param buff Buffer that contains data to write
7094 * @retval Interface status (MANDATORY: return 0 -> no Error).
7095 *
7096 */
asm330lhhxg1_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)7097 int32_t asm330lhhxg1_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff)
7098 {
7099 int32_t ret;
7100
7101 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS, buff);
7102
7103 if (ret == 0)
7104 {
7105 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS + 0x01U,
7106 buff);
7107 }
7108 return ret;
7109 }
7110
7111 /**
7112 * @brief FSM number of programs register.[get]
7113 *
7114 * @param ctx Read / write interface definitions.(ptr)
7115 * @param buff Buffer that stores data read
7116 * @retval Interface status (MANDATORY: return 0 -> no Error).
7117 *
7118 */
asm330lhhxg1_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)7119 int32_t asm330lhhxg1_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7120 {
7121 int32_t ret;
7122
7123 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_PROGRAMS, buff);
7124
7125 return ret;
7126 }
7127
7128 /**
7129 * @brief FSM start address register (r/w). First available address is
7130 * 0x033C.[set]
7131 *
7132 * @param ctx Read / write interface definitions.(ptr)
7133 * @param buff Buffer that contains data to write
7134 * @retval Interface status (MANDATORY: return 0 -> no Error).
7135 *
7136 */
asm330lhhxg1_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7137 int32_t asm330lhhxg1_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7138 {
7139 uint8_t buff[2];
7140 int32_t ret;
7141
7142 buff[1] = (uint8_t)(val / 256U);
7143 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7144
7145 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_START_ADD_L, &buff[0]);
7146 if (ret == 0)
7147 {
7148 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_FSM_START_ADD_H, &buff[1]);
7149 }
7150 return ret;
7151 }
7152
7153 /**
7154 * @brief FSM start address register (r/w). First available address
7155 * is 0x033C.[get]
7156 *
7157 * @param ctx Read / write interface definitions.(ptr)
7158 * @param buff Buffer that stores data read
7159 * @retval Interface status (MANDATORY: return 0 -> no Error).
7160 *
7161 */
asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7162 int32_t asm330lhhxg1_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7163 {
7164 uint8_t buff[2];
7165 int32_t ret;
7166
7167 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_START_ADD_L, &buff[0]);
7168 if (ret == 0)
7169 {
7170 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_FSM_START_ADD_H, &buff[1]);
7171 *val = buff[1];
7172 *val = (*val * 256U) + buff[0];
7173 }
7174 return ret;
7175 }
7176
7177 /**
7178 * @}
7179 *
7180 */
7181
7182 /**
7183 * @addtogroup Machine Learning Core
7184 * @brief This section group all the functions concerning the
7185 * usage of Machine Learning Core
7186 * @{
7187 *
7188 */
7189
7190 /**
7191 * @brief Enable Machine Learning Core.[set]
7192 *
7193 * @param ctx read / write interface definitions
7194 * @param val change the values of mlc_en in
7195 * reg EMB_FUNC_EN_B and mlc_init
7196 * in EMB_FUNC_INIT_B
7197 *
7198 */
asm330lhhxg1_mlc_set(const stmdev_ctx_t * ctx,uint8_t val)7199 int32_t asm330lhhxg1_mlc_set(const stmdev_ctx_t *ctx, uint8_t val)
7200 {
7201 asm330lhhxg1_emb_func_en_b_t reg;
7202 int32_t ret;
7203
7204 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7205 if (ret == 0)
7206 {
7207 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7208 }
7209 if (ret == 0)
7210 {
7211 reg.mlc_en = val;
7212 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7213 }
7214 if ((val != PROPERTY_DISABLE) && (ret == 0))
7215 {
7216 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7217 (uint8_t *)®, 1);
7218 if (ret == 0)
7219 {
7220 reg.mlc_en = val;
7221 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7222 (uint8_t *)®, 1);
7223 }
7224 }
7225 if (ret == 0)
7226 {
7227 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7228 }
7229 return ret;
7230 }
7231
7232 /**
7233 * @brief Enable Machine Learning Core.[get]
7234 *
7235 * @param ctx read / write interface definitions
7236 * @param val Get the values of mlc_en in
7237 * reg EMB_FUNC_EN_B
7238 *
7239 */
asm330lhhxg1_mlc_get(const stmdev_ctx_t * ctx,uint8_t * val)7240 int32_t asm330lhhxg1_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val)
7241 {
7242 asm330lhhxg1_emb_func_en_b_t reg;
7243 int32_t ret;
7244
7245 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7246 if (ret == 0)
7247 {
7248 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7249 }
7250 if (ret == 0)
7251 {
7252 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7253 *val = reg.mlc_en;
7254 }
7255 return ret;
7256 }
7257
7258 /**
7259 * @brief Machine Learning Core status register[get]
7260 *
7261 * @param ctx read / write interface definitions
7262 * @param val register MLC_STATUS_MAINPAGE
7263 *
7264 */
asm330lhhxg1_mlc_status_get(const stmdev_ctx_t * ctx,asm330lhhxg1_mlc_status_mainpage_t * val)7265 int32_t asm330lhhxg1_mlc_status_get(const stmdev_ctx_t *ctx,
7266 asm330lhhxg1_mlc_status_mainpage_t *val)
7267 {
7268 return asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC_STATUS_MAINPAGE,
7269 (uint8_t *) val, 1);
7270 }
7271
7272 /**
7273 * @brief Machine Learning Core data rate selection.[set]
7274 *
7275 * @param ctx read / write interface definitions
7276 * @param val get the values of mlc_odr in
7277 * reg EMB_FUNC_ODR_CFG_C
7278 *
7279 */
asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhxg1_mlc_odr_t val)7280 int32_t asm330lhhxg1_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7281 asm330lhhxg1_mlc_odr_t val)
7282 {
7283 asm330lhhxg1_emb_func_odr_cfg_c_t reg;
7284 int32_t ret;
7285
7286 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7287 if (ret == 0)
7288 {
7289 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C,
7290 (uint8_t *)®, 1);
7291 }
7292 if (ret == 0)
7293 {
7294 reg.mlc_odr = (uint8_t)val;
7295 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C,
7296 (uint8_t *)®, 1);
7297 }
7298 if (ret == 0)
7299 {
7300 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7301 }
7302
7303 return ret;
7304 }
7305
7306 /**
7307 * @brief Machine Learning Core data rate selection.[get]
7308 *
7309 * @param ctx read / write interface definitions
7310 * @param val change the values of mlc_odr in
7311 * reg EMB_FUNC_ODR_CFG_C
7312 *
7313 */
asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhxg1_mlc_odr_t * val)7314 int32_t asm330lhhxg1_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7315 asm330lhhxg1_mlc_odr_t *val)
7316 {
7317 asm330lhhxg1_emb_func_odr_cfg_c_t reg;
7318 int32_t ret;
7319
7320 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7321 if (ret == 0)
7322 {
7323 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_ODR_CFG_C,
7324 (uint8_t *)®, 1);
7325 }
7326 if (ret == 0)
7327 {
7328 switch (reg.mlc_odr)
7329 {
7330 case ASM330LHHXG1_ODR_PRGS_12Hz5:
7331 *val = ASM330LHHXG1_ODR_PRGS_12Hz5;
7332 break;
7333 case ASM330LHHXG1_ODR_PRGS_26Hz:
7334 *val = ASM330LHHXG1_ODR_PRGS_26Hz;
7335 break;
7336 case ASM330LHHXG1_ODR_PRGS_52Hz:
7337 *val = ASM330LHHXG1_ODR_PRGS_52Hz;
7338 break;
7339 case ASM330LHHXG1_ODR_PRGS_104Hz:
7340 *val = ASM330LHHXG1_ODR_PRGS_104Hz;
7341 break;
7342 default:
7343 *val = ASM330LHHXG1_ODR_PRGS_12Hz5;
7344 break;
7345 }
7346 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7347 }
7348 return ret;
7349 }
7350
7351 /**
7352 * @brief MLC initialization request.[set]
7353 *
7354 * @param ctx Read / write interface definitions.(ptr)
7355 * @param val Change the values of mlc_init
7356 * @retval Interface status (MANDATORY: return 0 -> no Error).
7357 *
7358 */
asm330lhhxg1_mlc_init_set(const stmdev_ctx_t * ctx,uint8_t val)7359 int32_t asm330lhhxg1_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val)
7360 {
7361 asm330lhhxg1_emb_func_init_b_t emb_func_init_b;
7362 int32_t ret;
7363
7364 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7365
7366 if (ret == 0)
7367 {
7368 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7369 (uint8_t *)&emb_func_init_b, 1);
7370 }
7371 if (ret == 0)
7372 {
7373 emb_func_init_b.mlc_init = (uint8_t)val;
7374 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7375 (uint8_t *)&emb_func_init_b, 1);
7376 }
7377
7378 ret += asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7379
7380 return ret;
7381 }
7382
7383 /**
7384 * @brief MLC initialization request.[get]
7385 *
7386 * @param ctx Read / write interface definitions.(ptr)
7387 * @param val Get the values of mlc_init
7388 * @retval Interface status (MANDATORY: return 0 -> no Error).
7389 *
7390 */
asm330lhhxg1_mlc_init_get(const stmdev_ctx_t * ctx,uint8_t * val)7391 int32_t asm330lhhxg1_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
7392 {
7393 asm330lhhxg1_emb_func_init_b_t emb_func_init_b;
7394 int32_t ret;
7395
7396 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7397 if (ret == 0)
7398 {
7399 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_EMB_FUNC_INIT_B,
7400 (uint8_t *)&emb_func_init_b, 1);
7401 }
7402 if (ret == 0)
7403 {
7404 *val = emb_func_init_b.mlc_init;
7405 }
7406
7407 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7408
7409 return ret;
7410 }
7411
7412 /**
7413 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
7414 *
7415 * @param ctx_t *ctx: read / write interface definitions
7416 * @param uint8_t * : buffer that stores data read
7417 *
7418 */
asm330lhhxg1_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)7419 int32_t asm330lhhxg1_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7420 {
7421 int32_t ret;
7422 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_EMBEDDED_FUNC_BANK);
7423 if (ret == 0)
7424 {
7425 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MLC0_SRC, buff, 8);
7426 }
7427 if (ret == 0)
7428 {
7429 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7430 }
7431 return ret;
7432 }
7433
7434 /**
7435 * @brief External magnetometer sensitivity value register for
7436 * Machine Learning Core.[set]
7437 *
7438 * @param ctx read / write interface definitions
7439 * @param buff buffer that contains data to write
7440 *
7441 */
asm330lhhxg1_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7442 int32_t asm330lhhxg1_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7443 {
7444 uint8_t buff[2];
7445 int32_t ret;
7446
7447 buff[1] = (uint8_t)(val / 256U);
7448 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7449 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_L,
7450 &buff[0]);
7451 if (ret == 0)
7452 {
7453 ret = asm330lhhxg1_ln_pg_write_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_H,
7454 &buff[1]);
7455 }
7456 return ret;
7457 }
7458
7459 /**
7460 * @brief External magnetometer sensitivity value register for
7461 * Machine Learning Core.[get]
7462 *
7463 * @param ctx read / write interface definitions
7464 * @param buff buffer that stores data read
7465 *
7466 */
asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7467 int32_t asm330lhhxg1_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7468 {
7469 uint8_t buff[2];
7470 int32_t ret;
7471
7472 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_L,
7473 &buff[0]);
7474 if (ret == 0)
7475 {
7476 ret = asm330lhhxg1_ln_pg_read_byte(ctx, ASM330LHHXG1_MLC_MAG_SENSITIVITY_H,
7477 &buff[1]);
7478 *val = buff[1];
7479 *val = (*val * 256U) + buff[0];
7480 }
7481 return ret;
7482 }
7483
7484 /**
7485 * @}
7486 *
7487 */
7488
7489 /**
7490 * @defgroup ASM330LHHXG1_Sensor_hub
7491 * @brief This section groups all the functions that manage the
7492 * sensor hub.
7493 * @{
7494 *
7495 */
7496
7497 /**
7498 * @brief Sensor hub output registers.[get]
7499 *
7500 * @param ctx Read / write interface definitions.(ptr)
7501 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
7502 * @retval Interface status (MANDATORY: return 0 -> no Error).
7503 *
7504 */
asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t * ctx,asm330lhhxg1_emb_sh_read_t * val)7505 int32_t asm330lhhxg1_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
7506 asm330lhhxg1_emb_sh_read_t *val)
7507 {
7508 int32_t ret;
7509
7510 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7511
7512 if (ret == 0)
7513 {
7514 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SENSOR_HUB_1, (uint8_t *)val, 18);
7515 }
7516 if (ret == 0)
7517 {
7518 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7519 }
7520 return ret;
7521 }
7522
7523 /**
7524 * @brief Number of external sensors to be read by the sensor hub.[set]
7525 *
7526 * @param ctx Read / write interface definitions.(ptr)
7527 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
7528 * @retval Interface status (MANDATORY: return 0 -> no Error).
7529 *
7530 */
asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t * ctx,asm330lhhxg1_aux_sens_on_t val)7531 int32_t asm330lhhxg1_sh_slave_connected_set(const stmdev_ctx_t *ctx,
7532 asm330lhhxg1_aux_sens_on_t val)
7533 {
7534 asm330lhhxg1_master_config_t master_config;
7535 int32_t ret;
7536
7537 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7538
7539 if (ret == 0)
7540 {
7541 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7542 (uint8_t *)&master_config, 1);
7543 }
7544 if (ret == 0)
7545 {
7546 master_config.aux_sens_on = (uint8_t)val;
7547 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7548 (uint8_t *)&master_config, 1);
7549 }
7550 if (ret == 0)
7551 {
7552 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7553 }
7554 return ret;
7555 }
7556
7557 /**
7558 * @brief Number of external sensors to be read by the sensor hub.[get]
7559 *
7560 * @param ctx Read / write interface definitions.(ptr)
7561 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
7562 * @retval Interface status (MANDATORY: return 0 -> no Error).
7563 *
7564 */
asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t * ctx,asm330lhhxg1_aux_sens_on_t * val)7565 int32_t asm330lhhxg1_sh_slave_connected_get(const stmdev_ctx_t *ctx,
7566 asm330lhhxg1_aux_sens_on_t *val)
7567 {
7568 asm330lhhxg1_master_config_t master_config;
7569 int32_t ret;
7570
7571 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7572
7573 if (ret == 0)
7574 {
7575 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7576 (uint8_t *)&master_config, 1);
7577 }
7578 if (ret == 0)
7579 {
7580 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7581 }
7582 switch (master_config.aux_sens_on)
7583 {
7584 case ASM330LHHXG1_SLV_0:
7585 *val = ASM330LHHXG1_SLV_0;
7586 break;
7587 case ASM330LHHXG1_SLV_0_1:
7588 *val = ASM330LHHXG1_SLV_0_1;
7589 break;
7590 case ASM330LHHXG1_SLV_0_1_2:
7591 *val = ASM330LHHXG1_SLV_0_1_2;
7592 break;
7593 case ASM330LHHXG1_SLV_0_1_2_3:
7594 *val = ASM330LHHXG1_SLV_0_1_2_3;
7595 break;
7596 default:
7597 *val = ASM330LHHXG1_SLV_0;
7598 break;
7599 }
7600 return ret;
7601 }
7602
7603 /**
7604 * @brief Sensor hub I2C master enable.[set]
7605 *
7606 * @param ctx Read / write interface definitions.(ptr)
7607 * @param val Change the values of master_on in reg MASTER_CONFIG
7608 * @retval Interface status (MANDATORY: return 0 -> no Error).
7609 *
7610 */
asm330lhhxg1_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)7611 int32_t asm330lhhxg1_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
7612 {
7613 asm330lhhxg1_master_config_t master_config;
7614 int32_t ret;
7615
7616 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7617
7618 if (ret == 0)
7619 {
7620 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7621 (uint8_t *)&master_config, 1);
7622 }
7623 if (ret == 0)
7624 {
7625 master_config.master_on = (uint8_t)val;
7626 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7627 (uint8_t *)&master_config, 1);
7628 }
7629 if (ret == 0)
7630 {
7631 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7632 }
7633 return ret;
7634 }
7635
7636 /**
7637 * @brief Sensor hub I2C master enable.[get]
7638 *
7639 * @param ctx Read / write interface definitions.(ptr)
7640 * @param val Change the values of master_on in reg MASTER_CONFIG
7641 * @retval Interface status (MANDATORY: return 0 -> no Error).
7642 *
7643 */
asm330lhhxg1_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)7644 int32_t asm330lhhxg1_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
7645 {
7646 asm330lhhxg1_master_config_t master_config;
7647 int32_t ret;
7648
7649 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7650
7651 if (ret == 0)
7652 {
7653 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7654 (uint8_t *)&master_config, 1);
7655 }
7656 if (ret == 0)
7657 {
7658 *val = master_config.master_on;
7659 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7660 }
7661 return ret;
7662 }
7663
7664 /**
7665 * @brief Master I2C pull-up enable.[set]
7666 *
7667 * @param ctx Read / write interface definitions.(ptr)
7668 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
7669 * @retval Interface status (MANDATORY: return 0 -> no Error).
7670 *
7671 */
asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_shub_pu_en_t val)7672 int32_t asm330lhhxg1_sh_pin_mode_set(const stmdev_ctx_t *ctx,
7673 asm330lhhxg1_shub_pu_en_t val)
7674 {
7675 asm330lhhxg1_master_config_t master_config;
7676 int32_t ret;
7677
7678 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7679
7680 if (ret == 0)
7681 {
7682 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7683 (uint8_t *)&master_config, 1);
7684 }
7685 if (ret == 0)
7686 {
7687 master_config.shub_pu_en = (uint8_t)val;
7688 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7689 (uint8_t *)&master_config, 1);
7690 }
7691 if (ret == 0)
7692 {
7693 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7694 }
7695 return ret;
7696 }
7697
7698 /**
7699 * @brief Master I2C pull-up enable.[get]
7700 *
7701 * @param ctx Read / write interface definitions.(ptr)
7702 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
7703 * @retval Interface status (MANDATORY: return 0 -> no Error).
7704 *
7705 */
asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_shub_pu_en_t * val)7706 int32_t asm330lhhxg1_sh_pin_mode_get(const stmdev_ctx_t *ctx,
7707 asm330lhhxg1_shub_pu_en_t *val)
7708 {
7709 asm330lhhxg1_master_config_t master_config;
7710 int32_t ret;
7711
7712 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7713 if (ret == 0)
7714 {
7715 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7716 (uint8_t *)&master_config, 1);
7717 }
7718 if (ret == 0)
7719 {
7720 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7721 }
7722 switch (master_config.shub_pu_en)
7723 {
7724 case ASM330LHHXG1_EXT_PULL_UP:
7725 *val = ASM330LHHXG1_EXT_PULL_UP;
7726 break;
7727 case ASM330LHHXG1_INTERNAL_PULL_UP:
7728 *val = ASM330LHHXG1_INTERNAL_PULL_UP;
7729 break;
7730 default:
7731 *val = ASM330LHHXG1_EXT_PULL_UP;
7732 break;
7733 }
7734 return ret;
7735 }
7736
7737 /**
7738 * @brief I2C interface pass-through.[set]
7739 *
7740 * @param ctx Read / write interface definitions.(ptr)
7741 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7742 * @retval Interface status (MANDATORY: return 0 -> no Error).
7743 *
7744 */
asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)7745 int32_t asm330lhhxg1_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
7746 {
7747 asm330lhhxg1_master_config_t master_config;
7748 int32_t ret;
7749
7750 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7751
7752 if (ret == 0)
7753 {
7754 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7755 (uint8_t *)&master_config, 1);
7756 }
7757 if (ret == 0)
7758 {
7759 master_config.pass_through_mode = (uint8_t)val;
7760 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7761 (uint8_t *)&master_config, 1);
7762 }
7763 if (ret == 0)
7764 {
7765 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7766 }
7767 return ret;
7768 }
7769
7770 /**
7771 * @brief I2C interface pass-through.[get]
7772 *
7773 * @param ctx Read / write interface definitions.(ptr)
7774 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7775 * @retval Interface status (MANDATORY: return 0 -> no Error).
7776 *
7777 */
asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)7778 int32_t asm330lhhxg1_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
7779 {
7780 asm330lhhxg1_master_config_t master_config;
7781 int32_t ret;
7782
7783 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7784
7785 if (ret == 0)
7786 {
7787 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7788 (uint8_t *)&master_config, 1);
7789 }
7790 if (ret == 0)
7791 {
7792 *val = master_config.pass_through_mode;
7793 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7794 }
7795 return ret;
7796 }
7797
7798 /**
7799 * @brief Sensor hub trigger signal selection.[set]
7800 *
7801 * @param ctx Read / write interface definitions.(ptr)
7802 * @param val Change the values of start_config in reg MASTER_CONFIG
7803 * @retval Interface status (MANDATORY: return 0 -> no Error).
7804 *
7805 */
asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_start_config_t val)7806 int32_t asm330lhhxg1_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
7807 asm330lhhxg1_start_config_t val)
7808 {
7809 asm330lhhxg1_master_config_t master_config;
7810 int32_t ret;
7811
7812 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7813
7814 if (ret == 0)
7815 {
7816 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7817 (uint8_t *)&master_config, 1);
7818 }
7819 if (ret == 0)
7820 {
7821 master_config.start_config = (uint8_t)val;
7822 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7823 (uint8_t *)&master_config, 1);
7824 }
7825 if (ret == 0)
7826 {
7827 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7828 }
7829 return ret;
7830 }
7831
7832 /**
7833 * @brief Sensor hub trigger signal selection.[get]
7834 *
7835 * @param ctx Read / write interface definitions.(ptr)
7836 * @param val Get the values of start_config in reg MASTER_CONFIG
7837 * @retval Interface status (MANDATORY: return 0 -> no Error).
7838 *
7839 */
asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_start_config_t * val)7840 int32_t asm330lhhxg1_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
7841 asm330lhhxg1_start_config_t *val)
7842 {
7843 asm330lhhxg1_master_config_t master_config;
7844 int32_t ret;
7845
7846 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7847
7848 if (ret == 0)
7849 {
7850 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7851 (uint8_t *)&master_config, 1);
7852 }
7853 if (ret == 0)
7854 {
7855 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7856 }
7857 switch (master_config.start_config)
7858 {
7859 case ASM330LHHXG1_EXT_ON_INT2_PIN:
7860 *val = ASM330LHHXG1_EXT_ON_INT2_PIN;
7861 break;
7862 case ASM330LHHXG1_XL_GY_DRDY:
7863 *val = ASM330LHHXG1_XL_GY_DRDY;
7864 break;
7865 default:
7866 *val = ASM330LHHXG1_EXT_ON_INT2_PIN;
7867 break;
7868 }
7869 return ret;
7870 }
7871
7872 /**
7873 * @brief Slave 0 write operation is performed only at the first sensor
7874 * hub cycle.[set]
7875 *
7876 * @param ctx Read / write interface definitions.(ptr)
7877 * @param val Change the values of write_once in reg MASTER_CONFIG
7878 * @retval Interface status (MANDATORY: return 0 -> no Error).
7879 *
7880 */
asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t * ctx,asm330lhhxg1_write_once_t val)7881 int32_t asm330lhhxg1_sh_write_mode_set(const stmdev_ctx_t *ctx,
7882 asm330lhhxg1_write_once_t val)
7883 {
7884 asm330lhhxg1_master_config_t master_config;
7885 int32_t ret;
7886
7887 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7888
7889 if (ret == 0)
7890 {
7891 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7892 (uint8_t *)&master_config, 1);
7893 }
7894 if (ret == 0)
7895 {
7896 master_config.write_once = (uint8_t)val;
7897 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7898 (uint8_t *)&master_config, 1);
7899 }
7900 if (ret == 0)
7901 {
7902 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7903 }
7904 return ret;
7905 }
7906
7907 /**
7908 * @brief Slave 0 write operation is performed only at the first sensor
7909 * hub cycle.[get]
7910 *
7911 * @param ctx Read / write interface definitions.(ptr)
7912 * @param val Get the values of write_once in reg MASTER_CONFIG
7913 * @retval Interface status (MANDATORY: return 0 -> no Error).
7914 *
7915 */
asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t * ctx,asm330lhhxg1_write_once_t * val)7916 int32_t asm330lhhxg1_sh_write_mode_get(const stmdev_ctx_t *ctx,
7917 asm330lhhxg1_write_once_t *val)
7918 {
7919 asm330lhhxg1_master_config_t master_config;
7920 int32_t ret;
7921
7922 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7923
7924 if (ret == 0)
7925 {
7926 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7927 (uint8_t *)&master_config, 1);
7928 }
7929 if (ret == 0)
7930 {
7931 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7932 }
7933 switch (master_config.write_once)
7934 {
7935 case ASM330LHHXG1_EACH_SH_CYCLE:
7936 *val = ASM330LHHXG1_EACH_SH_CYCLE;
7937 break;
7938 case ASM330LHHXG1_ONLY_FIRST_CYCLE:
7939 *val = ASM330LHHXG1_ONLY_FIRST_CYCLE;
7940 break;
7941 default:
7942 *val = ASM330LHHXG1_EACH_SH_CYCLE;
7943 break;
7944 }
7945 return ret;
7946 }
7947
7948 /**
7949 * @brief Reset Master logic and output registers.[set]
7950 *
7951 * @param ctx Read / write interface definitions.(ptr)
7952 * @retval Interface status (MANDATORY: return 0 -> no Error).
7953 *
7954 */
asm330lhhxg1_sh_reset_set(const stmdev_ctx_t * ctx)7955 int32_t asm330lhhxg1_sh_reset_set(const stmdev_ctx_t *ctx)
7956 {
7957 asm330lhhxg1_master_config_t master_config;
7958 int32_t ret;
7959
7960 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
7961
7962 if (ret == 0)
7963 {
7964 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7965 (uint8_t *)&master_config, 1);
7966 }
7967 if (ret == 0)
7968 {
7969 master_config.rst_master_regs = PROPERTY_ENABLE;
7970 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7971 (uint8_t *)&master_config, 1);
7972 }
7973 if (ret == 0)
7974 {
7975 master_config.rst_master_regs = PROPERTY_DISABLE;
7976 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
7977 (uint8_t *)&master_config, 1);
7978 }
7979 if (ret == 0)
7980 {
7981 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
7982 }
7983 return ret;
7984 }
7985
7986 /**
7987 * @brief Reset Master logic and output registers.[get]
7988 *
7989 * @param ctx Read / write interface definitions.(ptr)
7990 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
7991 * @retval Interface status (MANDATORY: return 0 -> no Error).
7992 *
7993 */
asm330lhhxg1_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)7994 int32_t asm330lhhxg1_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
7995 {
7996 asm330lhhxg1_master_config_t master_config;
7997 int32_t ret;
7998
7999 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8000
8001 if (ret == 0)
8002 {
8003 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_MASTER_CONFIG,
8004 (uint8_t *)&master_config, 1);
8005 *val = master_config.rst_master_regs;
8006 }
8007 if (ret == 0)
8008 {
8009 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8010 }
8011 return ret;
8012 }
8013
8014 /**
8015 * @brief Rate at which the master communicates.[set]
8016 *
8017 * @param ctx Read / write interface definitions.(ptr)
8018 * @param val Change the values of shub_odr in reg SLV0_CONFIG
8019 * @retval Interface status (MANDATORY: return 0 -> no Error).
8020 *
8021 */
asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhxg1_shub_odr_t val)8022 int32_t asm330lhhxg1_sh_data_rate_set(const stmdev_ctx_t *ctx,
8023 asm330lhhxg1_shub_odr_t val)
8024 {
8025 asm330lhhxg1_slv0_config_t slv0_config;
8026 int32_t ret;
8027
8028 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8029
8030 if (ret == 0)
8031 {
8032 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
8033 (uint8_t *)&slv0_config, 1);
8034 }
8035 if (ret == 0)
8036 {
8037 slv0_config.shub_odr = (uint8_t)val;
8038 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
8039 (uint8_t *)&slv0_config, 1);
8040 }
8041 if (ret == 0)
8042 {
8043 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8044 }
8045 return ret;
8046 }
8047
8048 /**
8049 * @brief Rate at which the master communicates.[get]
8050 *
8051 * @param ctx Read / write interface definitions.(ptr)
8052 * @param val Get the values of shub_odr in reg slv1_CONFIG
8053 * @retval Interface status (MANDATORY: return 0 -> no Error).
8054 *
8055 */
asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhxg1_shub_odr_t * val)8056 int32_t asm330lhhxg1_sh_data_rate_get(const stmdev_ctx_t *ctx,
8057 asm330lhhxg1_shub_odr_t *val)
8058 {
8059 asm330lhhxg1_slv0_config_t slv0_config;
8060 int32_t ret;
8061
8062 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8063
8064 if (ret == 0)
8065 {
8066 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
8067 (uint8_t *)&slv0_config, 1);
8068 }
8069 if (ret == 0)
8070 {
8071 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8072 }
8073 switch (slv0_config.shub_odr)
8074 {
8075 case ASM330LHHXG1_SH_ODR_104Hz:
8076 *val = ASM330LHHXG1_SH_ODR_104Hz;
8077 break;
8078 case ASM330LHHXG1_SH_ODR_52Hz:
8079 *val = ASM330LHHXG1_SH_ODR_52Hz;
8080 break;
8081 case ASM330LHHXG1_SH_ODR_26Hz:
8082 *val = ASM330LHHXG1_SH_ODR_26Hz;
8083 break;
8084 case ASM330LHHXG1_SH_ODR_13Hz:
8085 *val = ASM330LHHXG1_SH_ODR_13Hz;
8086 break;
8087 default:
8088 *val = ASM330LHHXG1_SH_ODR_104Hz;
8089 break;
8090 }
8091 return ret;
8092 }
8093
8094 /**
8095 * @brief Configure slave 0 for perform a write.[set]
8096 *
8097 * @param ctx Read / write interface definitions.(ptr)
8098 * @param val Structure that contain
8099 * - uint8_t slv0_add; 8 bit i2c device address
8100 * - uint8_t slv0_subadd; 8 bit register device address
8101 * - uint8_t slv0_data; 8 bit data to write
8102 * @retval Interface status (MANDATORY: return 0 -> no Error).
8103 *
8104 */
asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t * ctx,asm330lhhxg1_sh_cfg_write_t * val)8105 int32_t asm330lhhxg1_sh_cfg_write(const stmdev_ctx_t *ctx,
8106 asm330lhhxg1_sh_cfg_write_t *val)
8107 {
8108 asm330lhhxg1_slv0_add_t slv0_add;
8109 int32_t ret;
8110
8111 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8112
8113 if (ret == 0)
8114 {
8115 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
8116 slv0_add.rw_0 = 0;
8117 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_ADD,
8118 (uint8_t *) & (slv0_add), 1);
8119 }
8120 if (ret == 0)
8121 {
8122 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_SUBADD,
8123 (uint8_t *) & (val->slv0_subadd), 1);
8124 }
8125 if (ret == 0)
8126 {
8127 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_DATAWRITE_SLV0,
8128 (uint8_t *) & (val->slv0_data), 1);
8129 }
8130 if (ret == 0)
8131 {
8132 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8133 }
8134 return ret;
8135 }
8136
8137 /**
8138 * @brief Configure slave 0 for perform a write/read.[get]
8139 *
8140 * @param ctx Read / write interface definitions.(ptr)
8141 * @param val Structure that contain
8142 * - uint8_t slv_add; 8 bit i2c device address
8143 * - uint8_t slv_subadd; 8 bit register device address
8144 * - uint8_t slv_len; num of bit to read
8145 * @retval Interface status (MANDATORY: return 0 -> no Error).
8146 *
8147 */
asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,asm330lhhxg1_sh_cfg_read_t * val)8148 int32_t asm330lhhxg1_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
8149 asm330lhhxg1_sh_cfg_read_t *val)
8150 {
8151 asm330lhhxg1_slv0_config_t slv0_config;
8152 asm330lhhxg1_slv0_add_t slv0_add;
8153 int32_t ret;
8154
8155 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8156
8157 if (ret == 0)
8158 {
8159 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
8160 slv0_add.rw_0 = 1;
8161 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_ADD,
8162 (uint8_t *) & (slv0_add), 1);
8163 }
8164 if (ret == 0)
8165 {
8166 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_SUBADD,
8167 &(val->slv_subadd), 1);
8168 }
8169 if (ret == 0)
8170 {
8171 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
8172 (uint8_t *)&slv0_config, 1);
8173 }
8174 if (ret == 0)
8175 {
8176 slv0_config.slave0_numop = val->slv_len;
8177 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV0_CONFIG,
8178 (uint8_t *)&slv0_config, 1);
8179 }
8180 if (ret == 0)
8181 {
8182 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8183 }
8184 return ret;
8185 }
8186
8187 /**
8188 * @brief Configure slave 0 for perform a write/read.[get]
8189 *
8190 * @param ctx Read / write interface definitions.(ptr)
8191 * @param val Structure that contain
8192 * - uint8_t slv_add; 8 bit i2c device address
8193 * - uint8_t slv_subadd; 8 bit register device address
8194 * - uint8_t slv_len; num of bit to read
8195 * @retval Interface status (MANDATORY: return 0 -> no Error).
8196 *
8197 */
asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,asm330lhhxg1_sh_cfg_read_t * val)8198 int32_t asm330lhhxg1_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
8199 asm330lhhxg1_sh_cfg_read_t *val)
8200 {
8201 asm330lhhxg1_slv1_config_t slv1_config;
8202 asm330lhhxg1_slv1_add_t slv1_add;
8203 int32_t ret;
8204
8205 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8206 if (ret == 0)
8207 {
8208 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
8209 slv1_add.r_1 = 1;
8210 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_ADD, (uint8_t *)&slv1_add, 1);
8211 }
8212 if (ret == 0)
8213 {
8214 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_SUBADD,
8215 &(val->slv_subadd), 1);
8216 }
8217 if (ret == 0)
8218 {
8219 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV1_CONFIG,
8220 (uint8_t *)&slv1_config, 1);
8221 }
8222 if (ret == 0)
8223 {
8224 slv1_config.slave1_numop = val->slv_len;
8225 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV1_CONFIG,
8226 (uint8_t *)&slv1_config, 1);
8227 }
8228 if (ret == 0)
8229 {
8230 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8231 }
8232 return ret;
8233 }
8234
8235 /**
8236 * @brief Configure slave 2 for perform a write/read.[get]
8237 *
8238 * @param ctx Read / write interface definitions.(ptr)
8239 * @param val Structure that contain
8240 * - uint8_t slv_add; 8 bit i2c device address
8241 * - uint8_t slv_subadd; 8 bit register device address
8242 * - uint8_t slv_len; num of bit to read
8243 * @retval Interface status (MANDATORY: return 0 -> no Error).
8244 *
8245 */
asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,asm330lhhxg1_sh_cfg_read_t * val)8246 int32_t asm330lhhxg1_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
8247 asm330lhhxg1_sh_cfg_read_t *val)
8248 {
8249 asm330lhhxg1_slv2_config_t slv2_config;
8250 asm330lhhxg1_slv2_add_t slv2_add;
8251 int32_t ret;
8252
8253 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8254
8255 if (ret == 0)
8256 {
8257 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
8258 slv2_add.r_2 = 1;
8259 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_ADD,
8260 (uint8_t *)&slv2_add, 1);
8261 }
8262 if (ret == 0)
8263 {
8264 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_SUBADD,
8265 (uint8_t *) & (val->slv_subadd), 1);
8266 }
8267 if (ret == 0)
8268 {
8269 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV2_CONFIG,
8270 (uint8_t *)&slv2_config, 1);
8271 }
8272 if (ret == 0)
8273 {
8274 slv2_config.slave2_numop = val->slv_len;
8275 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV2_CONFIG,
8276 (uint8_t *)&slv2_config, 1);
8277 }
8278 if (ret == 0)
8279 {
8280 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8281 }
8282 return ret;
8283 }
8284
8285 /**
8286 * @brief Configure slave 3 for perform a write/read.[get]
8287 *
8288 * @param ctx Read / write interface definitions.(ptr)
8289 * @param val Structure that contain
8290 * - uint8_t slv_add; 8 bit i2c device address
8291 * - uint8_t slv_subadd; 8 bit register device address
8292 * - uint8_t slv_len; num of bit to read
8293 * @retval Interface status (MANDATORY: return 0 -> no Error).
8294 *
8295 */
asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,asm330lhhxg1_sh_cfg_read_t * val)8296 int32_t asm330lhhxg1_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
8297 asm330lhhxg1_sh_cfg_read_t *val)
8298 {
8299 asm330lhhxg1_slv3_config_t slv3_config;
8300 asm330lhhxg1_slv3_add_t slv3_add;
8301 int32_t ret;
8302
8303 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8304
8305 if (ret == 0)
8306 {
8307 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
8308 slv3_add.r_3 = 1;
8309 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_ADD,
8310 (uint8_t *)&slv3_add, 1);
8311 }
8312 if (ret == 0)
8313 {
8314 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_SUBADD,
8315 &(val->slv_subadd), 1);
8316 }
8317 if (ret == 0)
8318 {
8319 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_SLV3_CONFIG,
8320 (uint8_t *)&slv3_config, 1);
8321 }
8322 if (ret == 0)
8323 {
8324 slv3_config.slave3_numop = val->slv_len;
8325 ret = asm330lhhxg1_write_reg(ctx, ASM330LHHXG1_SLV3_CONFIG,
8326 (uint8_t *)&slv3_config, 1);
8327 }
8328 if (ret == 0)
8329 {
8330 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8331 }
8332 return ret;
8333 }
8334
8335 /**
8336 * @brief Sensor hub source register.[get]
8337 *
8338 * @param ctx Read / write interface definitions.(ptr)
8339 * @param val Registers from STATUS_MASTER
8340 * @retval Interface status (MANDATORY: return 0 -> no Error).
8341 *
8342 */
asm330lhhxg1_sh_status_get(const stmdev_ctx_t * ctx,asm330lhhxg1_status_master_t * val)8343 int32_t asm330lhhxg1_sh_status_get(const stmdev_ctx_t *ctx,
8344 asm330lhhxg1_status_master_t *val)
8345 {
8346 int32_t ret;
8347
8348 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_SENSOR_HUB_BANK);
8349
8350 if (ret == 0)
8351 {
8352 ret = asm330lhhxg1_read_reg(ctx, ASM330LHHXG1_STATUS_MASTER, (uint8_t *)val, 1);
8353 }
8354 if (ret == 0)
8355 {
8356 ret = asm330lhhxg1_mem_bank_set(ctx, ASM330LHHXG1_USER_BANK);
8357 }
8358 return ret;
8359 }
8360
8361 /**
8362 * @}
8363 *
8364 */
8365
8366 /**
8367 * @}
8368 *
8369 */
8370
8371 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8372
