1 /*
2 ******************************************************************************
3 * @file asm330lhhx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ASM330LHHX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "asm330lhhx_reg.h"
21
22 /**
23 * @defgroup ASM330LHHX
24 * @brief This file provides a set of functions needed to drive the
25 * asm330lhhx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ASM330LHHX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
asm330lhhx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak asm330lhhx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
asm330lhhx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak asm330lhhx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup ASM330LHHX_Sensitivity
96 * @brief These functions convert raw-data into engineering units.
97 * @{
98 *
99 */
100
asm330lhhx_from_fs2g_to_mg(int16_t lsb)101 float_t asm330lhhx_from_fs2g_to_mg(int16_t lsb)
102 {
103 return ((float_t)lsb * 0.061f);
104 }
105
asm330lhhx_from_fs4g_to_mg(int16_t lsb)106 float_t asm330lhhx_from_fs4g_to_mg(int16_t lsb)
107 {
108 return ((float_t)lsb * 0.122f);
109 }
110
asm330lhhx_from_fs8g_to_mg(int16_t lsb)111 float_t asm330lhhx_from_fs8g_to_mg(int16_t lsb)
112 {
113 return ((float_t)lsb * 0.244f);
114 }
115
asm330lhhx_from_fs16g_to_mg(int16_t lsb)116 float_t asm330lhhx_from_fs16g_to_mg(int16_t lsb)
117 {
118 return ((float_t)lsb * 0.488f);
119 }
120
asm330lhhx_from_fs125dps_to_mdps(int16_t lsb)121 float_t asm330lhhx_from_fs125dps_to_mdps(int16_t lsb)
122 {
123 return ((float_t)lsb * 4.375f);
124 }
125
asm330lhhx_from_fs250dps_to_mdps(int16_t lsb)126 float_t asm330lhhx_from_fs250dps_to_mdps(int16_t lsb)
127 {
128 return ((float_t)lsb * 8.75f);
129 }
130
asm330lhhx_from_fs500dps_to_mdps(int16_t lsb)131 float_t asm330lhhx_from_fs500dps_to_mdps(int16_t lsb)
132 {
133 return ((float_t)lsb * 17.50f);
134 }
135
asm330lhhx_from_fs1000dps_to_mdps(int16_t lsb)136 float_t asm330lhhx_from_fs1000dps_to_mdps(int16_t lsb)
137 {
138 return ((float_t)lsb * 35.0f);
139 }
140
asm330lhhx_from_fs2000dps_to_mdps(int16_t lsb)141 float_t asm330lhhx_from_fs2000dps_to_mdps(int16_t lsb)
142 {
143 return ((float_t)lsb * 70.0f);
144 }
145
asm330lhhx_from_fs4000dps_to_mdps(int16_t lsb)146 float_t asm330lhhx_from_fs4000dps_to_mdps(int16_t lsb)
147 {
148 return ((float_t)lsb * 140.0f);
149 }
150
asm330lhhx_from_lsb_to_celsius(int16_t lsb)151 float_t asm330lhhx_from_lsb_to_celsius(int16_t lsb)
152 {
153 return (((float_t)lsb / 256.0f) + 25.0f);
154 }
155
asm330lhhx_from_lsb_to_nsec(int32_t lsb)156 float_t asm330lhhx_from_lsb_to_nsec(int32_t lsb)
157 {
158 return ((float_t)lsb * 25000.0f);
159 }
160
161 /**
162 * @}
163 *
164 */
165
166 /**
167 * @defgroup LSM9DS1_Data_generation
168 * @brief This section groups all the functions concerning data
169 * generation
170 * @{
171 *
172 */
173
174 /**
175 * @brief Accelerometer full-scale selection[set]
176 *
177 * @param ctx Read / write interface definitions.(ptr)
178 * @param val Change the values of fs_xl in reg CTRL1_XL
179 * @retval Interface status (MANDATORY: return 0 -> no Error).
180 *
181 */
asm330lhhx_xl_full_scale_set(const stmdev_ctx_t * ctx,asm330lhhx_fs_xl_t val)182 int32_t asm330lhhx_xl_full_scale_set(const stmdev_ctx_t *ctx,
183 asm330lhhx_fs_xl_t val)
184 {
185 asm330lhhx_ctrl1_xl_t ctrl1_xl;
186 int32_t ret;
187
188 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
189 if (ret == 0)
190 {
191 ctrl1_xl.fs_xl = (uint8_t)val;
192 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL1_XL,
193 (uint8_t *)&ctrl1_xl, 1);
194 }
195 return ret;
196 }
197
198 /**
199 * @brief Accelerometer full-scale selection.[get]
200 *
201 * @param ctx Read / write interface definitions.(ptr)
202 * @param val Get the values of fs_xl in reg CTRL1_XL
203 * @retval Interface status (MANDATORY: return 0 -> no Error).
204 *
205 */
asm330lhhx_xl_full_scale_get(const stmdev_ctx_t * ctx,asm330lhhx_fs_xl_t * val)206 int32_t asm330lhhx_xl_full_scale_get(const stmdev_ctx_t *ctx,
207 asm330lhhx_fs_xl_t *val)
208 {
209 asm330lhhx_ctrl1_xl_t ctrl1_xl;
210 int32_t ret;
211
212 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
213 switch (ctrl1_xl.fs_xl)
214 {
215 case ASM330LHHX_2g:
216 *val = ASM330LHHX_2g;
217 break;
218 case ASM330LHHX_16g:
219 *val = ASM330LHHX_16g;
220 break;
221 case ASM330LHHX_4g:
222 *val = ASM330LHHX_4g;
223 break;
224 case ASM330LHHX_8g:
225 *val = ASM330LHHX_8g;
226 break;
227 default:
228 *val = ASM330LHHX_2g;
229 break;
230 }
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer UI data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions.(ptr)
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
asm330lhhx_xl_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhx_odr_xl_t val)242 int32_t asm330lhhx_xl_data_rate_set(const stmdev_ctx_t *ctx,
243 asm330lhhx_odr_xl_t val)
244 {
245 asm330lhhx_odr_xl_t odr_xl = val;
246 asm330lhhx_emb_fsm_enable_t fsm_enable;
247 asm330lhhx_fsm_odr_t fsm_odr;
248 asm330lhhx_ctrl1_xl_t ctrl1_xl;
249 asm330lhhx_mlc_odr_t mlc_odr;
250 uint8_t mlc_enable;
251 int32_t ret;
252
253 /* Check the Finite State Machine data rate constraints */
254 ret = asm330lhhx_fsm_enable_get(ctx, &fsm_enable);
255 if (ret == 0)
256 {
257 if ((fsm_enable.fsm_enable_a.fsm1_en |
258 fsm_enable.fsm_enable_a.fsm2_en |
259 fsm_enable.fsm_enable_a.fsm3_en |
260 fsm_enable.fsm_enable_a.fsm4_en |
261 fsm_enable.fsm_enable_a.fsm5_en |
262 fsm_enable.fsm_enable_a.fsm6_en |
263 fsm_enable.fsm_enable_a.fsm7_en |
264 fsm_enable.fsm_enable_a.fsm8_en |
265 fsm_enable.fsm_enable_b.fsm9_en |
266 fsm_enable.fsm_enable_b.fsm10_en |
267 fsm_enable.fsm_enable_b.fsm11_en |
268 fsm_enable.fsm_enable_b.fsm12_en |
269 fsm_enable.fsm_enable_b.fsm13_en |
270 fsm_enable.fsm_enable_b.fsm14_en |
271 fsm_enable.fsm_enable_b.fsm15_en |
272 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
273 {
274
275 ret = asm330lhhx_fsm_data_rate_get(ctx, &fsm_odr);
276 if (ret == 0)
277 {
278 switch (fsm_odr)
279 {
280 case ASM330LHHX_ODR_FSM_12Hz5:
281
282 if (val == ASM330LHHX_XL_ODR_OFF)
283 {
284 odr_xl = ASM330LHHX_XL_ODR_12Hz5;
285
286 }
287 else
288 {
289 odr_xl = val;
290 }
291 break;
292 case ASM330LHHX_ODR_FSM_26Hz:
293
294 if (val == ASM330LHHX_XL_ODR_OFF)
295 {
296 odr_xl = ASM330LHHX_XL_ODR_26Hz;
297
298 }
299 else if (val == ASM330LHHX_XL_ODR_12Hz5)
300 {
301 odr_xl = ASM330LHHX_XL_ODR_26Hz;
302
303 }
304 else
305 {
306 odr_xl = val;
307 }
308 break;
309 case ASM330LHHX_ODR_FSM_52Hz:
310
311 if (val == ASM330LHHX_XL_ODR_OFF)
312 {
313 odr_xl = ASM330LHHX_XL_ODR_52Hz;
314
315 }
316 else if (val == ASM330LHHX_XL_ODR_12Hz5)
317 {
318 odr_xl = ASM330LHHX_XL_ODR_52Hz;
319
320 }
321 else if (val == ASM330LHHX_XL_ODR_26Hz)
322 {
323 odr_xl = ASM330LHHX_XL_ODR_52Hz;
324
325 }
326 else
327 {
328 odr_xl = val;
329 }
330 break;
331 case ASM330LHHX_ODR_FSM_104Hz:
332
333 if (val == ASM330LHHX_XL_ODR_OFF)
334 {
335 odr_xl = ASM330LHHX_XL_ODR_104Hz;
336
337 }
338 else if (val == ASM330LHHX_XL_ODR_12Hz5)
339 {
340 odr_xl = ASM330LHHX_XL_ODR_104Hz;
341
342 }
343 else if (val == ASM330LHHX_XL_ODR_26Hz)
344 {
345 odr_xl = ASM330LHHX_XL_ODR_104Hz;
346
347 }
348 else if (val == ASM330LHHX_XL_ODR_52Hz)
349 {
350 odr_xl = ASM330LHHX_XL_ODR_104Hz;
351
352 }
353 else
354 {
355 odr_xl = val;
356 }
357 break;
358 default:
359 odr_xl = val;
360 break;
361 }
362 }
363 }
364 }
365
366 /* Check the Machine Learning Core data rate constraints */
367 mlc_enable = PROPERTY_DISABLE;
368 if (ret == 0)
369 {
370 ret = asm330lhhx_mlc_get(ctx, &mlc_enable);
371 if (mlc_enable == PROPERTY_ENABLE)
372 {
373
374 ret = asm330lhhx_mlc_data_rate_get(ctx, &mlc_odr);
375 if (ret == 0)
376 {
377 switch (mlc_odr)
378 {
379 case ASM330LHHX_ODR_PRGS_12Hz5:
380
381 if (val == ASM330LHHX_XL_ODR_OFF)
382 {
383 odr_xl = ASM330LHHX_XL_ODR_12Hz5;
384
385 }
386 else
387 {
388 odr_xl = val;
389 }
390 break;
391 case ASM330LHHX_ODR_PRGS_26Hz:
392 if (val == ASM330LHHX_XL_ODR_OFF)
393 {
394 odr_xl = ASM330LHHX_XL_ODR_26Hz;
395
396 }
397 else if (val == ASM330LHHX_XL_ODR_12Hz5)
398 {
399 odr_xl = ASM330LHHX_XL_ODR_26Hz;
400
401 }
402 else
403 {
404 odr_xl = val;
405 }
406 break;
407 case ASM330LHHX_ODR_PRGS_52Hz:
408
409 if (val == ASM330LHHX_XL_ODR_OFF)
410 {
411 odr_xl = ASM330LHHX_XL_ODR_52Hz;
412
413 }
414 else if (val == ASM330LHHX_XL_ODR_12Hz5)
415 {
416 odr_xl = ASM330LHHX_XL_ODR_52Hz;
417
418 }
419 else if (val == ASM330LHHX_XL_ODR_26Hz)
420 {
421 odr_xl = ASM330LHHX_XL_ODR_52Hz;
422
423 }
424 else
425 {
426 odr_xl = val;
427 }
428 break;
429 case ASM330LHHX_ODR_PRGS_104Hz:
430 if (val == ASM330LHHX_XL_ODR_OFF)
431 {
432 odr_xl = ASM330LHHX_XL_ODR_104Hz;
433
434 }
435 else if (val == ASM330LHHX_XL_ODR_12Hz5)
436 {
437 odr_xl = ASM330LHHX_XL_ODR_104Hz;
438
439 }
440 else if (val == ASM330LHHX_XL_ODR_26Hz)
441 {
442 odr_xl = ASM330LHHX_XL_ODR_104Hz;
443
444 }
445 else if (val == ASM330LHHX_XL_ODR_52Hz)
446 {
447 odr_xl = ASM330LHHX_XL_ODR_104Hz;
448
449 }
450 else
451 {
452 odr_xl = val;
453 }
454 break;
455 default:
456 odr_xl = val;
457 break;
458 }
459 }
460 }
461 }
462
463 if (ret == 0)
464 {
465 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
466 }
467 if (ret == 0)
468 {
469 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
470 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL1_XL,
471 (uint8_t *)&ctrl1_xl, 1);
472 }
473 return ret;
474 }
475
476 /**
477 * @brief Accelerometer UI data rate selection.[get]
478 *
479 * @param ctx Read / write interface definitions.(ptr)
480 * @param val Get the values of odr_xl in reg CTRL1_XL
481 * @retval Interface status (MANDATORY: return 0 -> no Error).
482 *
483 */
asm330lhhx_xl_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhx_odr_xl_t * val)484 int32_t asm330lhhx_xl_data_rate_get(const stmdev_ctx_t *ctx,
485 asm330lhhx_odr_xl_t *val)
486 {
487 asm330lhhx_ctrl1_xl_t ctrl1_xl;
488 int32_t ret;
489
490 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
491 switch (ctrl1_xl.odr_xl)
492 {
493 case ASM330LHHX_XL_ODR_OFF:
494 *val = ASM330LHHX_XL_ODR_OFF;
495 break;
496 case ASM330LHHX_XL_ODR_12Hz5:
497 *val = ASM330LHHX_XL_ODR_12Hz5;
498 break;
499 case ASM330LHHX_XL_ODR_26Hz:
500 *val = ASM330LHHX_XL_ODR_26Hz;
501 break;
502 case ASM330LHHX_XL_ODR_52Hz:
503 *val = ASM330LHHX_XL_ODR_52Hz;
504 break;
505 case ASM330LHHX_XL_ODR_104Hz:
506 *val = ASM330LHHX_XL_ODR_104Hz;
507 break;
508 case ASM330LHHX_XL_ODR_208Hz:
509 *val = ASM330LHHX_XL_ODR_208Hz;
510 break;
511 case ASM330LHHX_XL_ODR_417Hz:
512 *val = ASM330LHHX_XL_ODR_417Hz;
513 break;
514 case ASM330LHHX_XL_ODR_833Hz:
515 *val = ASM330LHHX_XL_ODR_833Hz;
516 break;
517 case ASM330LHHX_XL_ODR_1667Hz:
518 *val = ASM330LHHX_XL_ODR_1667Hz;
519 break;
520 case ASM330LHHX_XL_ODR_3333Hz:
521 *val = ASM330LHHX_XL_ODR_3333Hz;
522 break;
523 case ASM330LHHX_XL_ODR_6667Hz:
524 *val = ASM330LHHX_XL_ODR_6667Hz;
525 break;
526 case ASM330LHHX_XL_ODR_1Hz6:
527 *val = ASM330LHHX_XL_ODR_1Hz6;
528 break;
529 default:
530 *val = ASM330LHHX_XL_ODR_OFF;
531 break;
532 }
533 return ret;
534 }
535
536 /**
537 * @brief Gyroscope UI chain full-scale selection.[set]
538 *
539 * @param ctx Read / write interface definitions.(ptr)
540 * @param val Change the values of fs_g in reg CTRL2_G
541 * @retval Interface status (MANDATORY: return 0 -> no Error).
542 *
543 */
asm330lhhx_gy_full_scale_set(const stmdev_ctx_t * ctx,asm330lhhx_fs_g_t val)544 int32_t asm330lhhx_gy_full_scale_set(const stmdev_ctx_t *ctx,
545 asm330lhhx_fs_g_t val)
546 {
547 asm330lhhx_ctrl2_g_t ctrl2_g;
548 int32_t ret;
549
550 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
551 if (ret == 0)
552 {
553 ctrl2_g.fs_g = (uint8_t)val;
554 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
555 }
556 return ret;
557 }
558
559 /**
560 * @brief Gyroscope UI chain full-scale selection.[get]
561 *
562 * @param ctx Read / write interface definitions.(ptr)
563 * @param val Get the values of fs_g in reg CTRL2_G
564 * @retval Interface status (MANDATORY: return 0 -> no Error).
565 *
566 */
asm330lhhx_gy_full_scale_get(const stmdev_ctx_t * ctx,asm330lhhx_fs_g_t * val)567 int32_t asm330lhhx_gy_full_scale_get(const stmdev_ctx_t *ctx,
568 asm330lhhx_fs_g_t *val)
569 {
570 asm330lhhx_ctrl2_g_t ctrl2_g;
571 int32_t ret;
572
573 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
574 switch (ctrl2_g.fs_g)
575 {
576 case ASM330LHHX_125dps:
577 *val = ASM330LHHX_125dps;
578 break;
579 case ASM330LHHX_250dps:
580 *val = ASM330LHHX_250dps;
581 break;
582 case ASM330LHHX_500dps:
583 *val = ASM330LHHX_500dps;
584 break;
585 case ASM330LHHX_1000dps:
586 *val = ASM330LHHX_1000dps;
587 break;
588 case ASM330LHHX_2000dps:
589 *val = ASM330LHHX_2000dps;
590 break;
591 case ASM330LHHX_4000dps:
592 *val = ASM330LHHX_4000dps;
593 break;
594 default:
595 *val = ASM330LHHX_125dps;
596 break;
597 }
598 return ret;
599 }
600
601 /**
602 * @brief Gyroscope data rate.[set]
603 *
604 * @param ctx Read / write interface definitions.(ptr)
605 * @param val Change the values of odr_g in reg CTRL2_G
606 * @retval Interface status (MANDATORY: return 0 -> no Error).
607 *
608 */
asm330lhhx_gy_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhx_odr_g_t val)609 int32_t asm330lhhx_gy_data_rate_set(const stmdev_ctx_t *ctx,
610 asm330lhhx_odr_g_t val)
611 {
612 asm330lhhx_odr_g_t odr_gy = val;
613 asm330lhhx_emb_fsm_enable_t fsm_enable;
614 asm330lhhx_fsm_odr_t fsm_odr;
615 asm330lhhx_ctrl2_g_t ctrl2_g;
616 asm330lhhx_mlc_odr_t mlc_odr;
617 uint8_t mlc_enable;
618 int32_t ret;
619
620 /* Check the Finite State Machine data rate constraints */
621 ret = asm330lhhx_fsm_enable_get(ctx, &fsm_enable);
622 if (ret == 0)
623 {
624 if ((fsm_enable.fsm_enable_a.fsm1_en |
625 fsm_enable.fsm_enable_a.fsm2_en |
626 fsm_enable.fsm_enable_a.fsm3_en |
627 fsm_enable.fsm_enable_a.fsm4_en |
628 fsm_enable.fsm_enable_a.fsm5_en |
629 fsm_enable.fsm_enable_a.fsm6_en |
630 fsm_enable.fsm_enable_a.fsm7_en |
631 fsm_enable.fsm_enable_a.fsm8_en |
632 fsm_enable.fsm_enable_b.fsm9_en |
633 fsm_enable.fsm_enable_b.fsm10_en |
634 fsm_enable.fsm_enable_b.fsm11_en |
635 fsm_enable.fsm_enable_b.fsm12_en |
636 fsm_enable.fsm_enable_b.fsm13_en |
637 fsm_enable.fsm_enable_b.fsm14_en |
638 fsm_enable.fsm_enable_b.fsm15_en |
639 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
640 {
641
642 ret = asm330lhhx_fsm_data_rate_get(ctx, &fsm_odr);
643 if (ret == 0)
644 {
645 switch (fsm_odr)
646 {
647 case ASM330LHHX_ODR_FSM_12Hz5:
648
649 if (val == ASM330LHHX_GY_ODR_OFF)
650 {
651 odr_gy = ASM330LHHX_GY_ODR_12Hz5;
652
653 }
654 else
655 {
656 odr_gy = val;
657 }
658 break;
659 case ASM330LHHX_ODR_FSM_26Hz:
660
661 if (val == ASM330LHHX_GY_ODR_OFF)
662 {
663 odr_gy = ASM330LHHX_GY_ODR_26Hz;
664
665 }
666 else if (val == ASM330LHHX_GY_ODR_12Hz5)
667 {
668 odr_gy = ASM330LHHX_GY_ODR_26Hz;
669
670 }
671 else
672 {
673 odr_gy = val;
674 }
675 break;
676 case ASM330LHHX_ODR_FSM_52Hz:
677
678 if (val == ASM330LHHX_GY_ODR_OFF)
679 {
680 odr_gy = ASM330LHHX_GY_ODR_52Hz;
681
682 }
683 else if (val == ASM330LHHX_GY_ODR_12Hz5)
684 {
685 odr_gy = ASM330LHHX_GY_ODR_52Hz;
686
687 }
688 else if (val == ASM330LHHX_GY_ODR_26Hz)
689 {
690 odr_gy = ASM330LHHX_GY_ODR_52Hz;
691
692 }
693 else
694 {
695 odr_gy = val;
696 }
697 break;
698 case ASM330LHHX_ODR_FSM_104Hz:
699
700 if (val == ASM330LHHX_GY_ODR_OFF)
701 {
702 odr_gy = ASM330LHHX_GY_ODR_104Hz;
703
704 }
705 else if (val == ASM330LHHX_GY_ODR_12Hz5)
706 {
707 odr_gy = ASM330LHHX_GY_ODR_104Hz;
708
709 }
710 else if (val == ASM330LHHX_GY_ODR_26Hz)
711 {
712 odr_gy = ASM330LHHX_GY_ODR_104Hz;
713
714 }
715 else if (val == ASM330LHHX_GY_ODR_52Hz)
716 {
717 odr_gy = ASM330LHHX_GY_ODR_104Hz;
718
719 }
720 else
721 {
722 odr_gy = val;
723 }
724 break;
725 default:
726 odr_gy = val;
727 break;
728 }
729 }
730 }
731 }
732
733 /* Check the Machine Learning Core data rate constraints */
734 mlc_enable = PROPERTY_DISABLE;
735 if (ret == 0)
736 {
737 ret = asm330lhhx_mlc_get(ctx, &mlc_enable);
738 if (mlc_enable == PROPERTY_ENABLE)
739 {
740
741 ret = asm330lhhx_mlc_data_rate_get(ctx, &mlc_odr);
742 if (ret == 0)
743 {
744 switch (mlc_odr)
745 {
746 case ASM330LHHX_ODR_PRGS_12Hz5:
747
748 if (val == ASM330LHHX_GY_ODR_OFF)
749 {
750 odr_gy = ASM330LHHX_GY_ODR_12Hz5;
751
752 }
753 else
754 {
755 odr_gy = val;
756 }
757 break;
758 case ASM330LHHX_ODR_PRGS_26Hz:
759
760 if (val == ASM330LHHX_GY_ODR_OFF)
761 {
762 odr_gy = ASM330LHHX_GY_ODR_26Hz;
763
764 }
765 else if (val == ASM330LHHX_GY_ODR_12Hz5)
766 {
767 odr_gy = ASM330LHHX_GY_ODR_26Hz;
768
769 }
770 else
771 {
772 odr_gy = val;
773 }
774 break;
775 case ASM330LHHX_ODR_PRGS_52Hz:
776
777 if (val == ASM330LHHX_GY_ODR_OFF)
778 {
779 odr_gy = ASM330LHHX_GY_ODR_52Hz;
780
781 }
782 else if (val == ASM330LHHX_GY_ODR_12Hz5)
783 {
784 odr_gy = ASM330LHHX_GY_ODR_52Hz;
785
786 }
787 else if (val == ASM330LHHX_GY_ODR_26Hz)
788 {
789 odr_gy = ASM330LHHX_GY_ODR_52Hz;
790
791 }
792 else
793 {
794 odr_gy = val;
795 }
796 break;
797 case ASM330LHHX_ODR_PRGS_104Hz:
798
799 if (val == ASM330LHHX_GY_ODR_OFF)
800 {
801 odr_gy = ASM330LHHX_GY_ODR_104Hz;
802
803 }
804 else if (val == ASM330LHHX_GY_ODR_12Hz5)
805 {
806 odr_gy = ASM330LHHX_GY_ODR_104Hz;
807
808 }
809 else if (val == ASM330LHHX_GY_ODR_26Hz)
810 {
811 odr_gy = ASM330LHHX_GY_ODR_104Hz;
812
813 }
814 else if (val == ASM330LHHX_GY_ODR_52Hz)
815 {
816 odr_gy = ASM330LHHX_GY_ODR_104Hz;
817
818 }
819 else
820 {
821 odr_gy = val;
822 }
823 break;
824 default:
825 odr_gy = val;
826 break;
827 }
828 }
829 }
830 }
831
832 if (ret == 0)
833 {
834 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
835 }
836 if (ret == 0)
837 {
838 ctrl2_g.odr_g = (uint8_t)odr_gy;
839 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
840 }
841 return ret;
842 }
843
844 /**
845 * @brief Gyroscope data rate.[get]
846 *
847 * @param ctx Read / write interface definitions.(ptr)
848 * @param val Get the values of odr_g in reg CTRL2_G
849 * @retval Interface status (MANDATORY: return 0 -> no Error).
850 *
851 */
asm330lhhx_gy_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhx_odr_g_t * val)852 int32_t asm330lhhx_gy_data_rate_get(const stmdev_ctx_t *ctx,
853 asm330lhhx_odr_g_t *val)
854 {
855 asm330lhhx_ctrl2_g_t ctrl2_g;
856 int32_t ret;
857
858 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
859 switch (ctrl2_g.odr_g)
860 {
861 case ASM330LHHX_GY_ODR_OFF:
862 *val = ASM330LHHX_GY_ODR_OFF;
863 break;
864 case ASM330LHHX_GY_ODR_12Hz5:
865 *val = ASM330LHHX_GY_ODR_12Hz5;
866 break;
867 case ASM330LHHX_GY_ODR_26Hz:
868 *val = ASM330LHHX_GY_ODR_26Hz;
869 break;
870 case ASM330LHHX_GY_ODR_52Hz:
871 *val = ASM330LHHX_GY_ODR_52Hz;
872 break;
873 case ASM330LHHX_GY_ODR_104Hz:
874 *val = ASM330LHHX_GY_ODR_104Hz;
875 break;
876 case ASM330LHHX_GY_ODR_208Hz:
877 *val = ASM330LHHX_GY_ODR_208Hz;
878 break;
879 case ASM330LHHX_GY_ODR_417Hz:
880 *val = ASM330LHHX_GY_ODR_417Hz;
881 break;
882 case ASM330LHHX_GY_ODR_833Hz:
883 *val = ASM330LHHX_GY_ODR_833Hz;
884 break;
885 case ASM330LHHX_GY_ODR_1667Hz:
886 *val = ASM330LHHX_GY_ODR_1667Hz;
887 break;
888 case ASM330LHHX_GY_ODR_3333Hz:
889 *val = ASM330LHHX_GY_ODR_3333Hz;
890 break;
891 case ASM330LHHX_GY_ODR_6667Hz:
892 *val = ASM330LHHX_GY_ODR_6667Hz;
893 break;
894 default:
895 *val = ASM330LHHX_GY_ODR_OFF;
896 break;
897 }
898 return ret;
899 }
900
901 /**
902 * @brief Block data update.[set]
903 *
904 * @param ctx Read / write interface definitions.(ptr)
905 * @param val Change the values of bdu in reg CTRL3_C
906 * @retval Interface status (MANDATORY: return 0 -> no Error).
907 *
908 */
asm330lhhx_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)909 int32_t asm330lhhx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
910 {
911 asm330lhhx_ctrl3_c_t ctrl3_c;
912 int32_t ret;
913
914 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
915 if (ret == 0)
916 {
917 ctrl3_c.bdu = (uint8_t)val;
918 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
919 }
920 return ret;
921 }
922
923 /**
924 * @brief Block data update.[get]
925 *
926 * @param ctx Read / write interface definitions.(ptr)
927 * @param val Change the values of bdu in reg CTRL3_C
928 * @retval Interface status (MANDATORY: return 0 -> no Error).
929 *
930 */
asm330lhhx_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)931 int32_t asm330lhhx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
932 {
933 asm330lhhx_ctrl3_c_t ctrl3_c;
934 int32_t ret;
935
936 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
937 *val = ctrl3_c.bdu;
938
939 return ret;
940 }
941
942 /**
943 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
944 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
945 *
946 * @param ctx Read / write interface definitions.(ptr)
947 * @param val Change the values of usr_off_w in reg CTRL6_C
948 * @retval Interface status (MANDATORY: return 0 -> no Error).
949 *
950 */
asm330lhhx_xl_offset_weight_set(const stmdev_ctx_t * ctx,asm330lhhx_usr_off_w_t val)951 int32_t asm330lhhx_xl_offset_weight_set(const stmdev_ctx_t *ctx,
952 asm330lhhx_usr_off_w_t val)
953 {
954 asm330lhhx_ctrl6_c_t ctrl6_c;
955 int32_t ret;
956
957 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
958 if (ret == 0)
959 {
960 ctrl6_c.usr_off_w = (uint8_t)val;
961 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
962 }
963 return ret;
964 }
965
966 /**
967 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
968 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
969 *
970 * @param ctx Read / write interface definitions.(ptr)
971 * @param val Get the values of usr_off_w in reg CTRL6_C
972 * @retval Interface status (MANDATORY: return 0 -> no Error).
973 *
974 */
asm330lhhx_xl_offset_weight_get(const stmdev_ctx_t * ctx,asm330lhhx_usr_off_w_t * val)975 int32_t asm330lhhx_xl_offset_weight_get(const stmdev_ctx_t *ctx,
976 asm330lhhx_usr_off_w_t *val)
977 {
978 asm330lhhx_ctrl6_c_t ctrl6_c;
979 int32_t ret;
980
981 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
982
983 switch (ctrl6_c.usr_off_w)
984 {
985 case ASM330LHHX_LSb_1mg:
986 *val = ASM330LHHX_LSb_1mg;
987 break;
988 case ASM330LHHX_LSb_16mg:
989 *val = ASM330LHHX_LSb_16mg;
990 break;
991 default:
992 *val = ASM330LHHX_LSb_1mg;
993 break;
994 }
995 return ret;
996 }
997
998 /**
999 * @brief Accelerometer power mode.[set]
1000 *
1001 * @param ctx Read / write interface definitions.(ptr)
1002 * @param val Change the values of xl_hm_mode in reg CTRL6_C
1003 * @retval Interface status (MANDATORY: return 0 -> no Error).
1004 *
1005 */
asm330lhhx_xl_power_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_xl_hm_mode_t val)1006 int32_t asm330lhhx_xl_power_mode_set(const stmdev_ctx_t *ctx,
1007 asm330lhhx_xl_hm_mode_t val)
1008 {
1009 asm330lhhx_ctrl6_c_t ctrl6_c;
1010 int32_t ret;
1011
1012 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1013 if (ret == 0)
1014 {
1015 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1016 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1017 }
1018 return ret;
1019 }
1020
1021 /**
1022 * @brief Accelerometer power mode[get]
1023 *
1024 * @param ctx Read / write interface definitions.(ptr)
1025 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1026 * @retval Interface status (MANDATORY: return 0 -> no Error).
1027 *
1028 */
asm330lhhx_xl_power_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_xl_hm_mode_t * val)1029 int32_t asm330lhhx_xl_power_mode_get(const stmdev_ctx_t *ctx,
1030 asm330lhhx_xl_hm_mode_t *val)
1031 {
1032 asm330lhhx_ctrl6_c_t ctrl6_c;
1033 int32_t ret;
1034
1035 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1036 switch (ctrl6_c.xl_hm_mode)
1037 {
1038 case ASM330LHHX_HIGH_PERFORMANCE_MD:
1039 *val = ASM330LHHX_HIGH_PERFORMANCE_MD;
1040 break;
1041 case ASM330LHHX_LOW_NORMAL_POWER_MD:
1042 *val = ASM330LHHX_LOW_NORMAL_POWER_MD;
1043 break;
1044 default:
1045 *val = ASM330LHHX_HIGH_PERFORMANCE_MD;
1046 break;
1047 }
1048 return ret;
1049 }
1050
1051 /**
1052 * @brief Operating mode for gyroscope.[set]
1053 *
1054 * @param ctx Read / write interface definitions.(ptr)
1055 * @param val Change the values of g_hm_mode in reg CTRL7_G
1056 * @retval Interface status (MANDATORY: return 0 -> no Error).
1057 *
1058 */
asm330lhhx_gy_power_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_g_hm_mode_t val)1059 int32_t asm330lhhx_gy_power_mode_set(const stmdev_ctx_t *ctx,
1060 asm330lhhx_g_hm_mode_t val)
1061 {
1062 asm330lhhx_ctrl7_g_t ctrl7_g;
1063 int32_t ret;
1064
1065 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1066 if (ret == 0)
1067 {
1068 ctrl7_g.g_hm_mode = (uint8_t)val;
1069 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1070 }
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1076 *
1077 * @param ctx Read / write interface definitions.(ptr)
1078 * @param val Get the values of g_hm_mode in reg CTRL7_G
1079 * @retval Interface status (MANDATORY: return 0 -> no Error).
1080 *
1081 */
asm330lhhx_gy_power_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_g_hm_mode_t * val)1082 int32_t asm330lhhx_gy_power_mode_get(const stmdev_ctx_t *ctx,
1083 asm330lhhx_g_hm_mode_t *val)
1084 {
1085 asm330lhhx_ctrl7_g_t ctrl7_g;
1086 int32_t ret;
1087
1088 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1089 switch (ctrl7_g.g_hm_mode)
1090 {
1091 case ASM330LHHX_GY_HIGH_PERFORMANCE:
1092 *val = ASM330LHHX_GY_HIGH_PERFORMANCE;
1093 break;
1094 case ASM330LHHX_GY_NORMAL:
1095 *val = ASM330LHHX_GY_NORMAL;
1096 break;
1097 default:
1098 *val = ASM330LHHX_GY_HIGH_PERFORMANCE;
1099 break;
1100 }
1101 return ret;
1102 }
1103
1104 /**
1105 * @brief Read all the interrupt flag of the device.
1106 *[get]
1107 * @param ctx Read / write interface definitions.(ptr)
1108 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1109 * TAP_SRC; D6D_SRC; STATUS_REG;
1110 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1111 * @retval Interface status (MANDATORY: return 0 -> no Error).
1112 *
1113 */
asm330lhhx_all_sources_get(const stmdev_ctx_t * ctx,asm330lhhx_all_sources_t * val)1114 int32_t asm330lhhx_all_sources_get(const stmdev_ctx_t *ctx,
1115 asm330lhhx_all_sources_t *val)
1116 {
1117 int32_t ret;
1118
1119 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_ALL_INT_SRC,
1120 (uint8_t *)&val->all_int_src, 1);
1121 if (ret == 0)
1122 {
1123 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_SRC,
1124 (uint8_t *)&val->wake_up_src, 1);
1125 }
1126 if (ret == 0)
1127 {
1128 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_D6D_SRC,
1129 (uint8_t *)&val->d6d_src, 1);
1130 }
1131 if (ret == 0)
1132 {
1133 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG,
1134 (uint8_t *)&val->status_reg, 1);
1135 }
1136 if (ret == 0)
1137 {
1138 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
1139 }
1140 if (ret == 0)
1141 {
1142 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_STATUS,
1143 (uint8_t *)&val->emb_func_status, 1);
1144 }
1145 if (ret == 0)
1146 {
1147 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A,
1148 (uint8_t *)&val->fsm_status_a, 1);
1149 }
1150 if (ret == 0)
1151 {
1152 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B,
1153 (uint8_t *)&val->fsm_status_b, 1);
1154 }
1155 if (ret == 0)
1156 {
1157 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_STATUS,
1158 (uint8_t *)&val->mlc_status, 1);
1159 }
1160 if (ret == 0)
1161 {
1162 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
1163 }
1164
1165 return ret;
1166 }
1167
1168 /**
1169 * @brief The STATUS_REG register is read by the primary interface.[get]
1170 *
1171 * @param ctx Read / write interface definitions.(ptr)
1172 * @param val Get register STATUS_REG
1173 * @retval Interface status (MANDATORY: return 0 -> no Error).
1174 *
1175 */
asm330lhhx_status_reg_get(const stmdev_ctx_t * ctx,asm330lhhx_status_reg_t * val)1176 int32_t asm330lhhx_status_reg_get(const stmdev_ctx_t *ctx,
1177 asm330lhhx_status_reg_t *val)
1178 {
1179 int32_t ret;
1180 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG, (uint8_t *) val, 1);
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Accelerometer new data available.[get]
1186 *
1187 * @param ctx Read / write interface definitions.(ptr)
1188 * @param val Get the values of xlda in reg STATUS_REG
1189 * @retval Interface status (MANDATORY: return 0 -> no Error).
1190 *
1191 */
asm330lhhx_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1192 int32_t asm330lhhx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1193 {
1194 asm330lhhx_status_reg_t status_reg;
1195 int32_t ret;
1196
1197 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG,
1198 (uint8_t *)&status_reg, 1);
1199 *val = status_reg.xlda;
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Gyroscope new data available.[get]
1206 *
1207 * @param ctx Read / write interface definitions.(ptr)
1208 * @param val Get the values of gda in reg STATUS_REG
1209 * @retval Interface status (MANDATORY: return 0 -> no Error).
1210 *
1211 */
asm330lhhx_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1212 int32_t asm330lhhx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1213 {
1214 asm330lhhx_status_reg_t status_reg;
1215 int32_t ret;
1216
1217 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG,
1218 (uint8_t *)&status_reg, 1);
1219 *val = status_reg.gda;
1220
1221 return ret;
1222 }
1223
1224 /**
1225 * @brief Temperature new data available.[get]
1226 *
1227 * @param ctx Read / write interface definitions.(ptr)
1228 * @param val Get the values of tda in reg STATUS_REG
1229 * @retval Interface status (MANDATORY: return 0 -> no Error).
1230 *
1231 */
asm330lhhx_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1232 int32_t asm330lhhx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1233 {
1234 asm330lhhx_status_reg_t status_reg;
1235 int32_t ret;
1236
1237 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_REG,
1238 (uint8_t *)&status_reg, 1);
1239 *val = status_reg.tda;
1240
1241 return ret;
1242 }
1243
1244 /**
1245 * @brief Accelerometer X-axis user offset correction expressed in two’s
1246 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1247 * The value must be in the range [-127 127].[set]
1248 *
1249 * @param ctx Read / write interface definitions.(ptr)
1250 * @param buff Buffer that contains data to write
1251 * @retval Interface status (MANDATORY: return 0 -> no Error).
1252 *
1253 */
asm330lhhx_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1254 int32_t asm330lhhx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1255 {
1256 int32_t ret;
1257 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_X_OFS_USR, buff, 1);
1258 return ret;
1259 }
1260
1261 /**
1262 * @brief Accelerometer X-axis user offset correction expressed in two’s
1263 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1264 * The value must be in the range [-127 127].[get]
1265 *
1266 * @param ctx Read / write interface definitions.(ptr)
1267 * @param buff Buffer that stores data read
1268 * @retval Interface status (MANDATORY: return 0 -> no Error).
1269 *
1270 */
asm330lhhx_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1271 int32_t asm330lhhx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1272 {
1273 int32_t ret;
1274 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_X_OFS_USR, buff, 1);
1275 return ret;
1276 }
1277
1278 /**
1279 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1280 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1281 * The value must be in the range [-127 127].[set]
1282 *
1283 * @param ctx Read / write interface definitions.(ptr)
1284 * @param buff Buffer that contains data to write
1285 * @retval Interface status (MANDATORY: return 0 -> no Error).
1286 *
1287 */
asm330lhhx_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1288 int32_t asm330lhhx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1289 {
1290 int32_t ret;
1291 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_Y_OFS_USR, buff, 1);
1292 return ret;
1293 }
1294
1295 /**
1296 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1297 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1298 * The value must be in the range [-127 127].[get]
1299 *
1300 * @param ctx Read / write interface definitions.(ptr)
1301 * @param buff Buffer that stores data read
1302 * @retval Interface status (MANDATORY: return 0 -> no Error).
1303 *
1304 */
asm330lhhx_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1305 int32_t asm330lhhx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1306 {
1307 int32_t ret;
1308 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_Y_OFS_USR, buff, 1);
1309 return ret;
1310 }
1311
1312 /**
1313 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1314 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1315 * The value must be in the range [-127 127].[set]
1316 *
1317 * @param ctx Read / write interface definitions.(ptr)
1318 * @param buff Buffer that contains data to write
1319 * @retval Interface status (MANDATORY: return 0 -> no Error).
1320 *
1321 */
asm330lhhx_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1322 int32_t asm330lhhx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1323 {
1324 int32_t ret;
1325 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_Z_OFS_USR, buff, 1);
1326 return ret;
1327 }
1328
1329 /**
1330 * @brief Accelerometer X-axis user offset correction expressed in two’s
1331 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1332 * The value must be in the range [-127 127].[get]
1333 *
1334 * @param ctx Read / write interface definitions.(ptr)
1335 * @param buff Buffer that stores data read
1336 * @retval Interface status (MANDATORY: return 0 -> no Error).
1337 *
1338 */
asm330lhhx_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1339 int32_t asm330lhhx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1340 {
1341 int32_t ret;
1342 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_Z_OFS_USR, buff, 1);
1343 return ret;
1344 }
1345
1346 /**
1347 * @brief Enables user offset on out.[set]
1348 *
1349 * @param ctx Read / write interface definitions.(ptr)
1350 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1351 * @retval Interface status (MANDATORY: return 0 -> no Error).
1352 *
1353 */
asm330lhhx_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1354 int32_t asm330lhhx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1355 {
1356 asm330lhhx_ctrl7_g_t ctrl7_g;
1357 int32_t ret;
1358
1359 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1360 if (ret == 0)
1361 {
1362 ctrl7_g.usr_off_on_out = (uint8_t)val;
1363 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1364 }
1365 return ret;
1366 }
1367
1368 /**
1369 * @brief Get user offset on out flag.[get]
1370 *
1371 * @param ctx Read / write interface definitions.(ptr)
1372 * @param val Get values of usr_off_on_out in reg CTRL7_G
1373 * @retval Interface status (MANDATORY: return 0 -> no Error).
1374 *
1375 */
asm330lhhx_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1376 int32_t asm330lhhx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1377 {
1378 asm330lhhx_ctrl7_g_t ctrl7_g;
1379 int32_t ret;
1380
1381 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1382 *val = ctrl7_g.usr_off_on_out;
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @}
1389 *
1390 */
1391
1392 /**
1393 * @defgroup ASM330LHHX_Timestamp
1394 * @brief This section groups all the functions that manage the
1395 * timestamp generation.
1396 * @{
1397 *
1398 */
1399
1400 /**
1401 * @brief Reset timestamp counter.[set]
1402 *
1403 * @param ctx Read / write interface definitions.(ptr)
1404 * @retval Interface status (MANDATORY: return 0 -> no Error).
1405 *
1406 */
asm330lhhx_timestamp_rst(const stmdev_ctx_t * ctx)1407 int32_t asm330lhhx_timestamp_rst(const stmdev_ctx_t *ctx)
1408 {
1409 uint8_t rst_val = 0xAA;
1410
1411 return asm330lhhx_write_reg(ctx, ASM330LHHX_TIMESTAMP2, &rst_val, 1);
1412 }
1413
1414 /**
1415 * @brief Enables timestamp counter.[set]
1416 *
1417 * @param ctx Read / write interface definitions.(ptr)
1418 * @param val Change the values of timestamp_en in reg CTRL10_C
1419 * @retval Interface status (MANDATORY: return 0 -> no Error).
1420 *
1421 */
asm330lhhx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1422 int32_t asm330lhhx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1423 {
1424 asm330lhhx_ctrl10_c_t ctrl10_c;
1425 int32_t ret;
1426
1427 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1428 if (ret == 0)
1429 {
1430 ctrl10_c.timestamp_en = (uint8_t)val;
1431 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL10_C,
1432 (uint8_t *)&ctrl10_c, 1);
1433 }
1434 return ret;
1435 }
1436
1437 /**
1438 * @brief Enables timestamp counter.[get]
1439 *
1440 * @param ctx Read / write interface definitions.(ptr)
1441 * @param val Change the values of timestamp_en in reg CTRL10_C
1442 * @retval Interface status (MANDATORY: return 0 -> no Error).
1443 *
1444 */
asm330lhhx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1445 int32_t asm330lhhx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1446 {
1447 asm330lhhx_ctrl10_c_t ctrl10_c;
1448 int32_t ret;
1449
1450 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1451 *val = ctrl10_c.timestamp_en;
1452
1453 return ret;
1454 }
1455
1456 /**
1457 * @brief Timestamp first data output register (r).
1458 * The value is expressed as a 32-bit word and the bit resolution
1459 * is 25 μs.[get]
1460 *
1461 * @param ctx Read / write interface definitions.(ptr)
1462 * @param buff Buffer that stores data read
1463 * @retval Interface status (MANDATORY: return 0 -> no Error).
1464 *
1465 */
asm330lhhx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1466 int32_t asm330lhhx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1467 {
1468 uint8_t buff[4];
1469 int32_t ret;
1470
1471 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_TIMESTAMP0, buff, 4);
1472 *val = buff[3];
1473 *val = (*val * 256U) + buff[2];
1474 *val = (*val * 256U) + buff[1];
1475 *val = (*val * 256U) + buff[0];
1476
1477 return ret;
1478 }
1479
1480 /**
1481 * @}
1482 *
1483 */
1484
1485 /**
1486 * @defgroup ASM330LHHX_Data output
1487 * @brief This section groups all the data output functions.
1488 * @{
1489 *
1490 */
1491
1492 /**
1493 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1494 *
1495 * @param ctx Read / write interface definitions.(ptr)
1496 * @param val Change the values of rounding in reg CTRL5_C
1497 * @retval Interface status (MANDATORY: return 0 -> no Error).
1498 *
1499 */
asm330lhhx_rounding_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_rounding_t val)1500 int32_t asm330lhhx_rounding_mode_set(const stmdev_ctx_t *ctx,
1501 asm330lhhx_rounding_t val)
1502 {
1503 asm330lhhx_ctrl5_c_t ctrl5_c;
1504 int32_t ret;
1505
1506 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1507 if (ret == 0)
1508 {
1509 ctrl5_c.rounding = (uint8_t)val;
1510 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1511 }
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief Gyroscope UI chain full-scale selection.[get]
1517 *
1518 * @param ctx Read / write interface definitions.(ptr)
1519 * @param val Get the values of rounding in reg CTRL5_C
1520 * @retval Interface status (MANDATORY: return 0 -> no Error).
1521 *
1522 */
asm330lhhx_rounding_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_rounding_t * val)1523 int32_t asm330lhhx_rounding_mode_get(const stmdev_ctx_t *ctx,
1524 asm330lhhx_rounding_t *val)
1525 {
1526 asm330lhhx_ctrl5_c_t ctrl5_c;
1527 int32_t ret;
1528
1529 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1530 switch (ctrl5_c.rounding)
1531 {
1532 case ASM330LHHX_NO_ROUND:
1533 *val = ASM330LHHX_NO_ROUND;
1534 break;
1535 case ASM330LHHX_ROUND_XL:
1536 *val = ASM330LHHX_ROUND_XL;
1537 break;
1538 case ASM330LHHX_ROUND_GY:
1539 *val = ASM330LHHX_ROUND_GY;
1540 break;
1541 case ASM330LHHX_ROUND_GY_XL:
1542 *val = ASM330LHHX_ROUND_GY_XL;
1543 break;
1544 default:
1545 *val = ASM330LHHX_NO_ROUND;
1546 break;
1547 }
1548 return ret;
1549 }
1550
1551 /**
1552 * @brief Temperature data output register (r).
1553 * L and H registers together express a 16-bit word in two’s
1554 * complement.[get]
1555 *
1556 * @param ctx Read / write interface definitions.(ptr)
1557 * @param buff Buffer that stores data read
1558 * @retval Interface status (MANDATORY: return 0 -> no Error).
1559 *
1560 */
asm330lhhx_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1561 int32_t asm330lhhx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1562 {
1563 uint8_t buff[2];
1564 int32_t ret;
1565
1566 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUT_TEMP_L, buff, 2);
1567 *val = (int16_t)buff[1];
1568 *val = (*val * 256) + (int16_t)buff[0];
1569
1570 return ret;
1571 }
1572
1573 /**
1574 * @brief Angular rate sensor. The value is expressed as a 16-bit
1575 * word in two’s complement.[get]
1576 *
1577 * @param ctx Read / write interface definitions.(ptr)
1578 * @param buff Buffer that stores data read
1579 * @retval Interface status (MANDATORY: return 0 -> no Error).
1580 *
1581 */
asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1582 int32_t asm330lhhx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1583 {
1584 uint8_t buff[6];
1585 int32_t ret;
1586 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUTX_L_G, buff, 6);
1587
1588 val[0] = (int16_t)buff[1];
1589 val[0] = (val[0] * 256) + (int16_t)buff[0];
1590 val[1] = (int16_t)buff[3];
1591 val[1] = (val[1] * 256) + (int16_t)buff[2];
1592 val[2] = (int16_t)buff[5];
1593 val[2] = (val[2] * 256) + (int16_t)buff[4];
1594
1595 return ret;
1596 }
1597
1598 /**
1599 * @brief Linear acceleration output register. The value is expressed as a
1600 * 16-bit word in two’s complement.[get]
1601 *
1602 * @param ctx Read / write interface definitions.(ptr)
1603 * @param buff Buffer that stores data read
1604 * @retval Interface status (MANDATORY: return 0 -> no Error).
1605 *
1606 */
asm330lhhx_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1607 int32_t asm330lhhx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1608 {
1609 uint8_t buff[6];
1610 int32_t ret;
1611 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_OUTX_L_A, buff, 6);
1612
1613 val[0] = (int16_t)buff[1];
1614 val[0] = (val[0] * 256) + (int16_t)buff[0];
1615 val[1] = (int16_t)buff[3];
1616 val[1] = (val[1] * 256) + (int16_t)buff[2];
1617 val[2] = (int16_t)buff[5];
1618 val[2] = (val[2] * 256) + (int16_t)buff[4];
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief FIFO data output.[get]
1625 *
1626 * @param ctx Read / write interface definitions.(ptr)
1627 * @param buff Buffer that stores data read
1628 * @retval Interface status (MANDATORY: return 0 -> no Error).
1629 *
1630 */
asm330lhhx_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * val)1631 int32_t asm330lhhx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val)
1632 {
1633 int32_t ret;
1634 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_DATA_OUT_X_L, val, 6);
1635 return ret;
1636 }
1637
1638 /**
1639 * @}
1640 *
1641 */
1642
1643 /**
1644 * @defgroup ASM330LHHX_common
1645 * @brief This section groups common useful functions.
1646 * @{
1647 *
1648 */
1649
1650 /**
1651 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1652 * with respect to the typical.[set]
1653 * Step: 0.15%. 8-bit format, 2's complement.
1654 *
1655 * @param ctx Read / write interface definitions.(ptr)
1656 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1657 * @retval Interface status (MANDATORY: return 0 -> no Error).
1658 *
1659 */
asm330lhhx_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1660 int32_t asm330lhhx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1661 {
1662 asm330lhhx_internal_freq_fine_t internal_freq_fine;
1663 int32_t ret;
1664
1665 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INTERNAL_FREQ_FINE,
1666 (uint8_t *)&internal_freq_fine, 1);
1667 if (ret == 0)
1668 {
1669 internal_freq_fine.freq_fine = (uint8_t)val;
1670 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INTERNAL_FREQ_FINE,
1671 (uint8_t *)&internal_freq_fine, 1);
1672 }
1673 return ret;
1674 }
1675
1676 /**
1677 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1678 * with respect to the typical.[get]
1679 * Step: 0.15%. 8-bit format, 2's complement.
1680 *
1681 * @param ctx Read / write interface definitions.(ptr)
1682 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1683 * @retval Interface status (MANDATORY: return 0 -> no Error).
1684 *
1685 */
asm330lhhx_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1686 int32_t asm330lhhx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1687 {
1688 asm330lhhx_internal_freq_fine_t internal_freq_fine;
1689 int32_t ret;
1690
1691 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INTERNAL_FREQ_FINE,
1692 (uint8_t *)&internal_freq_fine, 1);
1693 *val = internal_freq_fine.freq_fine;
1694
1695 return ret;
1696 }
1697
1698 /**
1699 * @brief Enable access to the embedded functions/sensor hub configuration
1700 * registers.[set]
1701 *
1702 * @param ctx Read / write interface definitions.(ptr)
1703 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1704 * @retval Interface status (MANDATORY: return 0 -> no Error).
1705 *
1706 */
asm330lhhx_mem_bank_set(const stmdev_ctx_t * ctx,asm330lhhx_reg_access_t val)1707 int32_t asm330lhhx_mem_bank_set(const stmdev_ctx_t *ctx,
1708 asm330lhhx_reg_access_t val)
1709 {
1710 asm330lhhx_func_cfg_access_t func_cfg_access;
1711 int32_t ret;
1712
1713 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FUNC_CFG_ACCESS,
1714 (uint8_t *)&func_cfg_access, 1);
1715 if (ret == 0)
1716 {
1717 func_cfg_access.reg_access = (uint8_t)val;
1718 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FUNC_CFG_ACCESS,
1719 (uint8_t *)&func_cfg_access, 1);
1720 }
1721 return ret;
1722 }
1723
1724 /**
1725 * @brief Enable access to the embedded functions/sensor hub configuration
1726 * registers.[get]
1727 *
1728 * @param ctx Read / write interface definitions.(ptr)
1729 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1730 * @retval Interface status (MANDATORY: return 0 -> no Error).
1731 *
1732 */
asm330lhhx_mem_bank_get(const stmdev_ctx_t * ctx,asm330lhhx_reg_access_t * val)1733 int32_t asm330lhhx_mem_bank_get(const stmdev_ctx_t *ctx,
1734 asm330lhhx_reg_access_t *val)
1735 {
1736 asm330lhhx_func_cfg_access_t func_cfg_access;
1737 int32_t ret;
1738
1739 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FUNC_CFG_ACCESS,
1740 (uint8_t *)&func_cfg_access, 1);
1741 switch (func_cfg_access.reg_access)
1742 {
1743 case ASM330LHHX_USER_BANK:
1744 *val = ASM330LHHX_USER_BANK;
1745 break;
1746 case ASM330LHHX_SENSOR_HUB_BANK:
1747 *val = ASM330LHHX_SENSOR_HUB_BANK;
1748 break;
1749 case ASM330LHHX_EMBEDDED_FUNC_BANK:
1750 *val = ASM330LHHX_EMBEDDED_FUNC_BANK;
1751 break;
1752 default:
1753 *val = ASM330LHHX_USER_BANK;
1754 break;
1755 }
1756 return ret;
1757 }
1758
1759 /**
1760 * @brief Write a line(byte) in a page.[set]
1761 *
1762 * @param ctx Read / write interface definitions.(ptr)
1763 * @param add Page line address
1764 * @param val Value to write
1765 * @retval Interface status (MANDATORY: return 0 -> no Error).
1766 *
1767 */
asm330lhhx_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1768 int32_t asm330lhhx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
1769 uint8_t *val)
1770 {
1771 asm330lhhx_page_rw_t page_rw;
1772 asm330lhhx_page_sel_t page_sel;
1773 asm330lhhx_page_address_t page_address;
1774 int32_t ret;
1775
1776 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
1777 if (ret == 0)
1778 {
1779 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1780 }
1781 if (ret == 0)
1782 {
1783 page_rw.page_rw = 0x02U; /* page_write enable */
1784 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1785 }
1786 if (ret == 0)
1787 {
1788 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1789 }
1790 if (ret == 0)
1791 {
1792 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1793 page_sel.not_used_01 = 1;
1794 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL,
1795 (uint8_t *)&page_sel, 1);
1796 }
1797 if (ret == 0)
1798 {
1799 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1800 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS,
1801 (uint8_t *)&page_address, 1);
1802 }
1803 if (ret == 0)
1804 {
1805 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_VALUE, val, 1);
1806 }
1807 if (ret == 0)
1808 {
1809 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1810 }
1811 if (ret == 0)
1812 {
1813 page_rw.page_rw = 0x00; /* page_write disable */
1814 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1815 }
1816 if (ret == 0)
1817 {
1818 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
1819 }
1820 return ret;
1821 }
1822
1823 /**
1824 * @brief Write buffer in a page.[set]
1825 *
1826 * @param ctx Read / write interface definitions.(ptr)
1827 * @param buf Page line address.(ptr)
1828 * @param val Value to write.
1829 * @param len buffer lenght.
1830 * @retval Interface status (MANDATORY: return 0 -> no Error).
1831 *
1832 */
asm330lhhx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1833 int32_t asm330lhhx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
1834 uint8_t *buf, uint8_t len)
1835 {
1836 asm330lhhx_page_rw_t page_rw;
1837 asm330lhhx_page_sel_t page_sel;
1838 asm330lhhx_page_address_t page_address;
1839 int32_t ret;
1840 uint8_t msb, lsb;
1841 uint8_t i ;
1842
1843 msb = (uint8_t)(add / 256U);
1844 lsb = (uint8_t)(add - (msb * 256U));
1845
1846 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
1847 if (ret == 0)
1848 {
1849 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1850 }
1851 if (ret == 0)
1852 {
1853 page_rw.page_rw = 0x02U; /* page_write enable*/
1854 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1855 }
1856 if (ret == 0)
1857 {
1858 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1859 }
1860 if (ret == 0)
1861 {
1862 page_sel.page_sel = msb;
1863 page_sel.not_used_01 = 1;
1864 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL,
1865 (uint8_t *)&page_sel, 1);
1866 }
1867 if (ret == 0)
1868 {
1869 page_address.page_addr = lsb;
1870 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS,
1871 (uint8_t *)&page_address, 1);
1872 }
1873 for (i = 0; i < len; i++)
1874 {
1875 if (ret == 0)
1876 {
1877 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_VALUE, &buf[i], 1);
1878 if (ret == 0)
1879 {
1880 /* Check if page wrap */
1881 if (lsb == 0x00U)
1882 {
1883 msb++;
1884 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL,
1885 (uint8_t *)&page_sel, 1);
1886 }
1887 lsb++;
1888 }
1889 if (ret == 0)
1890 {
1891 page_sel.page_sel = msb;
1892 page_sel.not_used_01 = 1;
1893 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL,
1894 (uint8_t *)&page_sel, 1);
1895 }
1896 }
1897 }
1898
1899 if (ret == 0)
1900 {
1901 page_sel.page_sel = 0;
1902 page_sel.not_used_01 = 1;
1903 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL,
1904 (uint8_t *)&page_sel, 1);
1905 }
1906 if (ret == 0)
1907 {
1908 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1909 }
1910 if (ret == 0)
1911 {
1912 page_rw.page_rw = 0x00U; /* page_write disable */
1913 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1914 }
1915 if (ret == 0)
1916 {
1917 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
1918 }
1919 return ret;
1920 }
1921
1922 /**
1923 * @brief Read a line(byte) in a page.[get]
1924 *
1925 * @param ctx Read / write interface definitions.(ptr)
1926 * @param add Page line address.
1927 * @param val Read value.(ptr)
1928 * @retval Interface status (MANDATORY: return 0 -> no Error).
1929 *
1930 */
asm330lhhx_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1931 int32_t asm330lhhx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
1932 uint8_t *val)
1933 {
1934 asm330lhhx_page_rw_t page_rw;
1935 asm330lhhx_page_sel_t page_sel;
1936 asm330lhhx_page_address_t page_address;
1937 int32_t ret;
1938
1939 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
1940 if (ret == 0)
1941 {
1942 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1943 }
1944 if (ret == 0)
1945 {
1946 page_rw.page_rw = 0x01U; /* page_read enable*/
1947 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1948 }
1949 if (ret == 0)
1950 {
1951 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1952 }
1953 if (ret == 0)
1954 {
1955 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1956 page_sel.not_used_01 = 1;
1957 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_SEL,
1958 (uint8_t *)&page_sel, 1);
1959 }
1960 if (ret == 0)
1961 {
1962 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1963 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_ADDRESS,
1964 (uint8_t *)&page_address, 1);
1965 }
1966 if (ret == 0)
1967 {
1968 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_VALUE, val, 2);
1969 }
1970 if (ret == 0)
1971 {
1972 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1973 }
1974 if (ret == 0)
1975 {
1976 page_rw.page_rw = 0x00U; /* page_read disable */
1977 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
1978 }
1979 if (ret == 0)
1980 {
1981 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
1982 }
1983 return ret;
1984 }
1985
1986 /**
1987 * @brief Data-ready pulsed / letched mode.[set]
1988 *
1989 * @param ctx Read / write interface definitions.(ptr)
1990 * @param val Change the values of dataready_pulsed in
1991 * reg COUNTER_BDR_REG1
1992 * @retval Interface status (MANDATORY: return 0 -> no Error).
1993 *
1994 */
asm330lhhx_data_ready_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_dataready_pulsed_t val)1995 int32_t asm330lhhx_data_ready_mode_set(const stmdev_ctx_t *ctx,
1996 asm330lhhx_dataready_pulsed_t val)
1997 {
1998 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
1999 int32_t ret;
2000
2001 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
2002 (uint8_t *)&counter_bdr_reg1, 1);
2003 if (ret == 0)
2004 {
2005 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2006 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
2007 (uint8_t *)&counter_bdr_reg1, 1);
2008 }
2009 return ret;
2010 }
2011
2012 /**
2013 * @brief Data-ready pulsed / letched mode.[get]
2014 *
2015 * @param ctx Read / write interface definitions.(ptr)
2016 * @param val Get the values of dataready_pulsed in
2017 * reg COUNTER_BDR_REG1
2018 * @retval Interface status (MANDATORY: return 0 -> no Error).
2019 *
2020 */
asm330lhhx_data_ready_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_dataready_pulsed_t * val)2021 int32_t asm330lhhx_data_ready_mode_get(const stmdev_ctx_t *ctx,
2022 asm330lhhx_dataready_pulsed_t *val)
2023 {
2024 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
2025 int32_t ret;
2026
2027 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
2028 (uint8_t *)&counter_bdr_reg1, 1);
2029 switch (counter_bdr_reg1.dataready_pulsed)
2030 {
2031 case ASM330LHHX_DRDY_LATCHED:
2032 *val = ASM330LHHX_DRDY_LATCHED;
2033 break;
2034 case ASM330LHHX_DRDY_PULSED:
2035 *val = ASM330LHHX_DRDY_PULSED;
2036 break;
2037 default:
2038 *val = ASM330LHHX_DRDY_LATCHED;
2039 break;
2040 }
2041 return ret;
2042 }
2043
2044 /**
2045 * @brief Device Who am I.[get]
2046 *
2047 * @param ctx Read / write interface definitions.(ptr)
2048 * @param buff Buffer that stores data read
2049 * @retval Interface status (MANDATORY: return 0 -> no Error).
2050 *
2051 */
asm330lhhx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2052 int32_t asm330lhhx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2053 {
2054 int32_t ret;
2055 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WHO_AM_I, buff, 1);
2056 return ret;
2057 }
2058
2059 /**
2060 * @brief Software reset. Restore the default values in user registers.[set]
2061 *
2062 * @param ctx Read / write interface definitions.(ptr)
2063 * @param val Change the values of sw_reset in reg CTRL3_C
2064 * @retval Interface status (MANDATORY: return 0 -> no Error).
2065 *
2066 */
asm330lhhx_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2067 int32_t asm330lhhx_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2068 {
2069 asm330lhhx_ctrl3_c_t ctrl3_c;
2070 int32_t ret;
2071
2072 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2073 if (ret == 0)
2074 {
2075 ctrl3_c.sw_reset = (uint8_t)val;
2076 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2077 }
2078 return ret;
2079 }
2080
2081 /**
2082 * @brief Software reset. Restore the default values in user registers.[get]
2083 *
2084 * @param ctx Read / write interface definitions.(ptr)
2085 * @param val Change the values of sw_reset in reg CTRL3_C
2086 * @retval Interface status (MANDATORY: return 0 -> no Error).
2087 *
2088 */
asm330lhhx_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2089 int32_t asm330lhhx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2090 {
2091 asm330lhhx_ctrl3_c_t ctrl3_c;
2092 int32_t ret;
2093
2094 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2095 *val = ctrl3_c.sw_reset;
2096
2097 return ret;
2098 }
2099
2100 /**
2101 * @brief Register address automatically incremented during a multiple byte
2102 * access with a serial interface.[set]
2103 *
2104 * @param ctx Read / write interface definitions.(ptr)
2105 * @param val Change the values of if_inc in reg CTRL3_C
2106 * @retval Interface status (MANDATORY: return 0 -> no Error).
2107 *
2108 */
asm330lhhx_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2109 int32_t asm330lhhx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2110 {
2111 asm330lhhx_ctrl3_c_t ctrl3_c;
2112 int32_t ret;
2113
2114 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2115 if (ret == 0)
2116 {
2117 ctrl3_c.if_inc = (uint8_t)val;
2118 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2119 }
2120 return ret;
2121 }
2122
2123 /**
2124 * @brief Register address automatically incremented during a multiple byte
2125 * access with a serial interface.[get]
2126 *
2127 * @param ctx Read / write interface definitions.(ptr)
2128 * @param val Change the values of if_inc in reg CTRL3_C
2129 * @retval Interface status (MANDATORY: return 0 -> no Error).
2130 *
2131 */
asm330lhhx_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2132 int32_t asm330lhhx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2133 {
2134 asm330lhhx_ctrl3_c_t ctrl3_c;
2135 int32_t ret;
2136
2137 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2138 *val = ctrl3_c.if_inc;
2139
2140 return ret;
2141 }
2142
2143 /**
2144 * @brief Reboot memory content. Reload the calibration parameters.[set]
2145 *
2146 * @param ctx Read / write interface definitions.(ptr)
2147 * @param val Change the values of boot in reg CTRL3_C
2148 * @retval Interface status (MANDATORY: return 0 -> no Error).
2149 *
2150 */
asm330lhhx_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2151 int32_t asm330lhhx_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2152 {
2153 asm330lhhx_ctrl3_c_t ctrl3_c;
2154 int32_t ret;
2155
2156 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2157 if (ret == 0)
2158 {
2159 ctrl3_c.boot = (uint8_t)val;
2160 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2161 }
2162 return ret;
2163 }
2164
2165 /**
2166 * @brief Reboot memory content. Reload the calibration parameters.[get]
2167 *
2168 * @param ctx Read / write interface definitions.(ptr)
2169 * @param val Change the values of boot in reg CTRL3_C
2170 * @retval Interface status (MANDATORY: return 0 -> no Error).
2171 *
2172 */
asm330lhhx_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2173 int32_t asm330lhhx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2174 {
2175 asm330lhhx_ctrl3_c_t ctrl3_c;
2176 int32_t ret;
2177
2178 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2179 *val = ctrl3_c.boot;
2180
2181 return ret;
2182 }
2183
2184
2185
2186 /**
2187 * @brief Linear acceleration sensor self-test enable.[set]
2188 *
2189 * @param ctx Read / write interface definitions.(ptr)
2190 * @param val Change the values of st_xl in reg CTRL5_C
2191 * @retval Interface status (MANDATORY: return 0 -> no Error).
2192 *
2193 */
asm330lhhx_xl_self_test_set(const stmdev_ctx_t * ctx,asm330lhhx_st_xl_t val)2194 int32_t asm330lhhx_xl_self_test_set(const stmdev_ctx_t *ctx,
2195 asm330lhhx_st_xl_t val)
2196 {
2197 asm330lhhx_ctrl5_c_t ctrl5_c;
2198 int32_t ret;
2199
2200 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2201 if (ret == 0)
2202 {
2203 ctrl5_c.st_xl = (uint8_t)val;
2204 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2205 }
2206 return ret;
2207 }
2208
2209 /**
2210 * @brief Linear acceleration sensor self-test enable.[get]
2211 *
2212 * @param ctx Read / write interface definitions.(ptr)
2213 * @param val Get the values of st_xl in reg CTRL5_C
2214 * @retval Interface status (MANDATORY: return 0 -> no Error).
2215 *
2216 */
asm330lhhx_xl_self_test_get(const stmdev_ctx_t * ctx,asm330lhhx_st_xl_t * val)2217 int32_t asm330lhhx_xl_self_test_get(const stmdev_ctx_t *ctx,
2218 asm330lhhx_st_xl_t *val)
2219 {
2220 asm330lhhx_ctrl5_c_t ctrl5_c;
2221 int32_t ret;
2222
2223 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2224
2225 switch (ctrl5_c.st_xl)
2226 {
2227 case ASM330LHHX_XL_ST_DISABLE:
2228 *val = ASM330LHHX_XL_ST_DISABLE;
2229 break;
2230 case ASM330LHHX_XL_ST_POSITIVE:
2231 *val = ASM330LHHX_XL_ST_POSITIVE;
2232 break;
2233 case ASM330LHHX_XL_ST_NEGATIVE:
2234 *val = ASM330LHHX_XL_ST_NEGATIVE;
2235 break;
2236 default:
2237 *val = ASM330LHHX_XL_ST_DISABLE;
2238 break;
2239 }
2240 return ret;
2241 }
2242
2243 /**
2244 * @brief Angular rate sensor self-test enable.[set]
2245 *
2246 * @param ctx Read / write interface definitions.(ptr)
2247 * @param val Change the values of st_g in reg CTRL5_C
2248 * @retval Interface status (MANDATORY: return 0 -> no Error).
2249 *
2250 */
asm330lhhx_gy_self_test_set(const stmdev_ctx_t * ctx,asm330lhhx_st_g_t val)2251 int32_t asm330lhhx_gy_self_test_set(const stmdev_ctx_t *ctx,
2252 asm330lhhx_st_g_t val)
2253 {
2254 asm330lhhx_ctrl5_c_t ctrl5_c;
2255 int32_t ret;
2256
2257 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2258 if (ret == 0)
2259 {
2260 ctrl5_c.st_g = (uint8_t)val;
2261 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2262 }
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief Angular rate sensor self-test enable.[get]
2268 *
2269 * @param ctx Read / write interface definitions.(ptr)
2270 * @param val Get the values of st_g in reg CTRL5_C
2271 * @retval Interface status (MANDATORY: return 0 -> no Error).
2272 *
2273 */
asm330lhhx_gy_self_test_get(const stmdev_ctx_t * ctx,asm330lhhx_st_g_t * val)2274 int32_t asm330lhhx_gy_self_test_get(const stmdev_ctx_t *ctx,
2275 asm330lhhx_st_g_t *val)
2276 {
2277 asm330lhhx_ctrl5_c_t ctrl5_c;
2278 int32_t ret;
2279
2280 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2281
2282 switch (ctrl5_c.st_g)
2283 {
2284 case ASM330LHHX_GY_ST_DISABLE:
2285 *val = ASM330LHHX_GY_ST_DISABLE;
2286 break;
2287 case ASM330LHHX_GY_ST_POSITIVE:
2288 *val = ASM330LHHX_GY_ST_POSITIVE;
2289 break;
2290 case ASM330LHHX_GY_ST_NEGATIVE:
2291 *val = ASM330LHHX_GY_ST_NEGATIVE;
2292 break;
2293 default:
2294 *val = ASM330LHHX_GY_ST_DISABLE;
2295 break;
2296 }
2297 return ret;
2298 }
2299
2300 /**
2301 * @}
2302 *
2303 */
2304
2305 /**
2306 * @defgroup ASM330LHHX_filters
2307 * @brief This section group all the functions concerning the
2308 * filters configuration
2309 * @{
2310 *
2311 */
2312
2313 /**
2314 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2315 *
2316 * @param ctx Read / write interface definitions.(ptr)
2317 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2318 * @retval Interface status (MANDATORY: return 0 -> no Error).
2319 *
2320 */
asm330lhhx_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2321 int32_t asm330lhhx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2322 {
2323 asm330lhhx_ctrl1_xl_t ctrl1_xl;
2324 int32_t ret;
2325
2326 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2327 if (ret == 0)
2328 {
2329 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2330 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL1_XL,
2331 (uint8_t *)&ctrl1_xl, 1);
2332 }
2333 return ret;
2334 }
2335
2336 /**
2337 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2338 *
2339 * @param ctx Read / write interface definitions.(ptr)
2340 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2341 * @retval Interface status (MANDATORY: return 0 -> no Error).
2342 *
2343 */
asm330lhhx_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2344 int32_t asm330lhhx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2345 {
2346 asm330lhhx_ctrl1_xl_t ctrl1_xl;
2347 int32_t ret;
2348
2349 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2350 *val = ctrl1_xl.lpf2_xl_en;
2351
2352 return ret;
2353 }
2354
2355 /**
2356 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2357 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2358 *
2359 * @param ctx Read / write interface definitions.(ptr)
2360 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2361 * @retval Interface status (MANDATORY: return 0 -> no Error).
2362 *
2363 */
asm330lhhx_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2364 int32_t asm330lhhx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2365 {
2366 asm330lhhx_ctrl4_c_t ctrl4_c;
2367 int32_t ret;
2368
2369 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2370 if (ret == 0)
2371 {
2372 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2373 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2374 }
2375 return ret;
2376 }
2377
2378 /**
2379 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2380 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2381 *
2382 * @param ctx Read / write interface definitions.(ptr)
2383 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2384 * @retval Interface status (MANDATORY: return 0 -> no Error).
2385 *
2386 */
asm330lhhx_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2387 int32_t asm330lhhx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2388 {
2389 asm330lhhx_ctrl4_c_t ctrl4_c;
2390 int32_t ret;
2391
2392 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2393 *val = ctrl4_c.lpf1_sel_g;
2394
2395 return ret;
2396 }
2397
2398 /**
2399 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2400 * (XL and Gyro independently masked).[set]
2401 *
2402 * @param ctx Read / write interface definitions.(ptr)
2403 * @param val Change the values of drdy_mask in reg CTRL4_C
2404 * @retval Interface status (MANDATORY: return 0 -> no Error).
2405 *
2406 */
asm330lhhx_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2407 int32_t asm330lhhx_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2408 {
2409 asm330lhhx_ctrl4_c_t ctrl4_c;
2410 int32_t ret;
2411
2412 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2413 if (ret == 0)
2414 {
2415 ctrl4_c.drdy_mask = (uint8_t)val;
2416 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2417 }
2418 return ret;
2419 }
2420
2421 /**
2422 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2423 * (XL and Gyro independently masked).[get]
2424 *
2425 * @param ctx Read / write interface definitions.(ptr)
2426 * @param val Change the values of drdy_mask in reg CTRL4_C
2427 * @retval Interface status (MANDATORY: return 0 -> no Error).
2428 *
2429 */
asm330lhhx_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2430 int32_t asm330lhhx_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2431 uint8_t *val)
2432 {
2433 asm330lhhx_ctrl4_c_t ctrl4_c;
2434 int32_t ret;
2435
2436 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2437 *val = ctrl4_c.drdy_mask;
2438
2439 return ret;
2440 }
2441
2442 /**
2443 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2444 *
2445 * @param ctx Read / write interface definitions.(ptr)
2446 * @param val Change the values of ftype in reg CTRL6_C
2447 * @retval Interface status (MANDATORY: return 0 -> no Error).
2448 *
2449 */
asm330lhhx_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,asm330lhhx_ftype_t val)2450 int32_t asm330lhhx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2451 asm330lhhx_ftype_t val)
2452 {
2453 asm330lhhx_ctrl6_c_t ctrl6_c;
2454 int32_t ret;
2455
2456 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2457 if (ret == 0)
2458 {
2459 ctrl6_c.ftype = (uint8_t)val;
2460 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2461 }
2462 return ret;
2463 }
2464
2465 /**
2466 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2467 *
2468 * @param ctx Read / write interface definitions.(ptr)
2469 * @param val Get the values of ftype in reg CTRL6_C
2470 * @retval Interface status (MANDATORY: return 0 -> no Error).
2471 *
2472 */
asm330lhhx_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,asm330lhhx_ftype_t * val)2473 int32_t asm330lhhx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2474 asm330lhhx_ftype_t *val)
2475 {
2476 asm330lhhx_ctrl6_c_t ctrl6_c;
2477 int32_t ret;
2478
2479 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2480
2481 switch (ctrl6_c.ftype)
2482 {
2483 case ASM330LHHX_ULTRA_LIGHT:
2484 *val = ASM330LHHX_ULTRA_LIGHT;
2485 break;
2486 case ASM330LHHX_VERY_LIGHT:
2487 *val = ASM330LHHX_VERY_LIGHT;
2488 break;
2489 case ASM330LHHX_LIGHT:
2490 *val = ASM330LHHX_LIGHT;
2491 break;
2492 case ASM330LHHX_MEDIUM:
2493 *val = ASM330LHHX_MEDIUM;
2494 break;
2495 case ASM330LHHX_STRONG:
2496 *val = ASM330LHHX_STRONG;
2497 break;
2498 case ASM330LHHX_VERY_STRONG:
2499 *val = ASM330LHHX_VERY_STRONG;
2500 break;
2501 case ASM330LHHX_AGGRESSIVE:
2502 *val = ASM330LHHX_AGGRESSIVE;
2503 break;
2504 case ASM330LHHX_XTREME:
2505 *val = ASM330LHHX_XTREME;
2506 break;
2507 default:
2508 *val = ASM330LHHX_ULTRA_LIGHT;
2509 break;
2510 }
2511 return ret;
2512 }
2513
2514 /**
2515 * @brief Low pass filter 2 on 6D function selection.[set]
2516 *
2517 * @param ctx Read / write interface definitions.(ptr)
2518 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2519 * @retval Interface status (MANDATORY: return 0 -> no Error).
2520 *
2521 */
asm330lhhx_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2522 int32_t asm330lhhx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2523 {
2524 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2525 int32_t ret;
2526
2527 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2528 if (ret == 0)
2529 {
2530 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2531 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL8_XL,
2532 (uint8_t *)&ctrl8_xl, 1);
2533 }
2534 return ret;
2535 }
2536
2537 /**
2538 * @brief Low pass filter 2 on 6D function selection.[get]
2539 *
2540 * @param ctx Read / write interface definitions.(ptr)
2541 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2542 * @retval Interface status (MANDATORY: return 0 -> no Error).
2543 *
2544 */
asm330lhhx_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2545 int32_t asm330lhhx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2546 {
2547 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2548 int32_t ret;
2549
2550 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2551 *val = ctrl8_xl.low_pass_on_6d;
2552
2553 return ret;
2554 }
2555
2556 /**
2557 * @brief Accelerometer slope filter / high-pass filter selection
2558 * on output.[set]
2559 *
2560 * @param ctx Read / write interface definitions.(ptr)
2561 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2562 * @retval Interface status (MANDATORY: return 0 -> no Error).
2563 *
2564 */
asm330lhhx_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,asm330lhhx_hp_slope_xl_en_t val)2565 int32_t asm330lhhx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2566 asm330lhhx_hp_slope_xl_en_t val)
2567 {
2568 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2569 int32_t ret;
2570
2571 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2572 if (ret == 0)
2573 {
2574 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2575 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2576 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2577 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL8_XL,
2578 (uint8_t *)&ctrl8_xl, 1);
2579 }
2580 return ret;
2581 }
2582
2583 /**
2584 * @brief Accelerometer slope filter / high-pass filter selection on
2585 * output.[get]
2586 *
2587 * @param ctx Read / write interface definitions.(ptr)
2588 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2589 * @retval Interface status (MANDATORY: return 0 -> no Error).
2590 *
2591 */
asm330lhhx_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,asm330lhhx_hp_slope_xl_en_t * val)2592 int32_t asm330lhhx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2593 asm330lhhx_hp_slope_xl_en_t *val)
2594 {
2595 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2596 int32_t ret;
2597
2598 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2599 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) +
2600 ctrl8_xl.hpcf_xl))
2601 {
2602 case ASM330LHHX_HP_PATH_DISABLE_ON_OUT:
2603 *val = ASM330LHHX_HP_PATH_DISABLE_ON_OUT;
2604 break;
2605 case ASM330LHHX_SLOPE_ODR_DIV_4:
2606 *val = ASM330LHHX_SLOPE_ODR_DIV_4;
2607 break;
2608 case ASM330LHHX_HP_ODR_DIV_10:
2609 *val = ASM330LHHX_HP_ODR_DIV_10;
2610 break;
2611 case ASM330LHHX_HP_ODR_DIV_20:
2612 *val = ASM330LHHX_HP_ODR_DIV_20;
2613 break;
2614 case ASM330LHHX_HP_ODR_DIV_45:
2615 *val = ASM330LHHX_HP_ODR_DIV_45;
2616 break;
2617 case ASM330LHHX_HP_ODR_DIV_100:
2618 *val = ASM330LHHX_HP_ODR_DIV_100;
2619 break;
2620 case ASM330LHHX_HP_ODR_DIV_200:
2621 *val = ASM330LHHX_HP_ODR_DIV_200;
2622 break;
2623 case ASM330LHHX_HP_ODR_DIV_400:
2624 *val = ASM330LHHX_HP_ODR_DIV_400;
2625 break;
2626 case ASM330LHHX_HP_ODR_DIV_800:
2627 *val = ASM330LHHX_HP_ODR_DIV_800;
2628 break;
2629 case ASM330LHHX_HP_REF_MD_ODR_DIV_10:
2630 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_10;
2631 break;
2632 case ASM330LHHX_HP_REF_MD_ODR_DIV_20:
2633 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_20;
2634 break;
2635 case ASM330LHHX_HP_REF_MD_ODR_DIV_45:
2636 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_45;
2637 break;
2638 case ASM330LHHX_HP_REF_MD_ODR_DIV_100:
2639 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_100;
2640 break;
2641 case ASM330LHHX_HP_REF_MD_ODR_DIV_200:
2642 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_200;
2643 break;
2644 case ASM330LHHX_HP_REF_MD_ODR_DIV_400:
2645 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_400;
2646 break;
2647 case ASM330LHHX_HP_REF_MD_ODR_DIV_800:
2648 *val = ASM330LHHX_HP_REF_MD_ODR_DIV_800;
2649 break;
2650 case ASM330LHHX_LP_ODR_DIV_10:
2651 *val = ASM330LHHX_LP_ODR_DIV_10;
2652 break;
2653 case ASM330LHHX_LP_ODR_DIV_20:
2654 *val = ASM330LHHX_LP_ODR_DIV_20;
2655 break;
2656 case ASM330LHHX_LP_ODR_DIV_45:
2657 *val = ASM330LHHX_LP_ODR_DIV_45;
2658 break;
2659 case ASM330LHHX_LP_ODR_DIV_100:
2660 *val = ASM330LHHX_LP_ODR_DIV_100;
2661 break;
2662 case ASM330LHHX_LP_ODR_DIV_200:
2663 *val = ASM330LHHX_LP_ODR_DIV_200;
2664 break;
2665 case ASM330LHHX_LP_ODR_DIV_400:
2666 *val = ASM330LHHX_LP_ODR_DIV_400;
2667 break;
2668 case ASM330LHHX_LP_ODR_DIV_800:
2669 *val = ASM330LHHX_LP_ODR_DIV_800;
2670 break;
2671 default:
2672 *val = ASM330LHHX_HP_PATH_DISABLE_ON_OUT;
2673 break;
2674 }
2675 return ret;
2676 }
2677
2678 /**
2679 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2680 * The filter sets the second samples after writing this bit.
2681 * Active only during device exit from powerdown mode.[set]
2682 *
2683 * @param ctx Read / write interface definitions.(ptr)
2684 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2685 * @retval Interface status (MANDATORY: return 0 -> no Error).
2686 *
2687 */
asm330lhhx_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2688 int32_t asm330lhhx_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2689 {
2690 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2691 int32_t ret;
2692
2693 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2694 if (ret == 0)
2695 {
2696 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2697 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL8_XL,
2698 (uint8_t *)&ctrl8_xl, 1);
2699 }
2700 return ret;
2701 }
2702
2703 /**
2704 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2705 * The filter sets the second samples after writing
2706 * this bit. Active only during device exit from powerdown mode.[get]
2707 *
2708 * @param ctx Read / write interface definitions.(ptr)
2709 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2710 * @retval Interface status (MANDATORY: return 0 -> no Error).
2711 *
2712 */
asm330lhhx_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2713 int32_t asm330lhhx_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2714 {
2715 asm330lhhx_ctrl8_xl_t ctrl8_xl;
2716 int32_t ret;
2717
2718 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2719 *val = ctrl8_xl.fastsettl_mode_xl;
2720
2721 return ret;
2722 }
2723
2724 /**
2725 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2726 * functions.[set]
2727 *
2728 * @param ctx Read / write interface definitions.(ptr)
2729 * @param val Change the values of slope_fds in reg INT_CFG0
2730 * @retval Interface status (MANDATORY: return 0 -> no Error).
2731 *
2732 */
asm330lhhx_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhhx_slope_fds_t val)2733 int32_t asm330lhhx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2734 asm330lhhx_slope_fds_t val)
2735 {
2736 asm330lhhx_int_cfg0_t int_cfg0;
2737 int32_t ret;
2738
2739 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2740 if (ret == 0)
2741 {
2742 int_cfg0.slope_fds = (uint8_t)val;
2743 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG0,
2744 (uint8_t *)&int_cfg0, 1);
2745 }
2746 return ret;
2747 }
2748
2749 /**
2750 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2751 * functions.[get]
2752 *
2753 * @param ctx Read / write interface definitions.(ptr)
2754 * @param val Get the values of slope_fds in reg INT_CFG0
2755 * @retval Interface status (MANDATORY: return 0 -> no Error).
2756 *
2757 */
asm330lhhx_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhhx_slope_fds_t * val)2758 int32_t asm330lhhx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2759 asm330lhhx_slope_fds_t *val)
2760 {
2761 asm330lhhx_int_cfg0_t int_cfg0;
2762 int32_t ret;
2763
2764 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2765 switch (int_cfg0.slope_fds)
2766 {
2767 case ASM330LHHX_USE_SLOPE:
2768 *val = ASM330LHHX_USE_SLOPE;
2769 break;
2770 case ASM330LHHX_USE_HPF:
2771 *val = ASM330LHHX_USE_HPF;
2772 break;
2773 default:
2774 *val = ASM330LHHX_USE_SLOPE;
2775 break;
2776 }
2777 return ret;
2778 }
2779
2780 /**
2781 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2782 * only if the gyro is in HP mode.[set]
2783 *
2784 * @param ctx Read / write interface definitions.(ptr)
2785 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2786 * @retval Interface status (MANDATORY: return 0 -> no Error).
2787 *
2788 */
asm330lhhx_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhhx_hpm_g_t val)2789 int32_t asm330lhhx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2790 asm330lhhx_hpm_g_t val)
2791 {
2792 asm330lhhx_ctrl7_g_t ctrl7_g;
2793 int32_t ret;
2794
2795 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2796 if (ret == 0)
2797 {
2798 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2799 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2800 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2801 }
2802 return ret;
2803 }
2804
2805 /**
2806 * @brief Enables gyroscope digital high-pass filter. The filter is
2807 * enabled only if the gyro is in HP mode.[get]
2808 *
2809 * @param ctx Read / write interface definitions.(ptr)
2810 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2811 * @retval Interface status (MANDATORY: return 0 -> no Error).
2812 *
2813 */
asm330lhhx_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhhx_hpm_g_t * val)2814 int32_t asm330lhhx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
2815 asm330lhhx_hpm_g_t *val)
2816 {
2817 asm330lhhx_ctrl7_g_t ctrl7_g;
2818 int32_t ret;
2819
2820 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2821
2822 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
2823 {
2824 case ASM330LHHX_HP_FILTER_NONE:
2825 *val = ASM330LHHX_HP_FILTER_NONE;
2826 break;
2827 case ASM330LHHX_HP_FILTER_16mHz:
2828 *val = ASM330LHHX_HP_FILTER_16mHz;
2829 break;
2830 case ASM330LHHX_HP_FILTER_65mHz:
2831 *val = ASM330LHHX_HP_FILTER_65mHz;
2832 break;
2833 case ASM330LHHX_HP_FILTER_260mHz:
2834 *val = ASM330LHHX_HP_FILTER_260mHz;
2835 break;
2836 case ASM330LHHX_HP_FILTER_1Hz04:
2837 *val = ASM330LHHX_HP_FILTER_1Hz04;
2838 break;
2839 default:
2840 *val = ASM330LHHX_HP_FILTER_NONE;
2841 break;
2842 }
2843 return ret;
2844 }
2845
2846 /**
2847 * @}
2848 *
2849 */
2850
2851 /**
2852 * @defgroup ASM330LHHX_ serial_interface
2853 * @brief This section groups all the functions concerning main
2854 * serial interface management (not auxiliary)
2855 * @{
2856 *
2857 */
2858
2859 /**
2860 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2861 *
2862 * @param ctx Read / write interface definitions.(ptr)
2863 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
2864 * @retval Interface status (MANDATORY: return 0 -> no Error).
2865 *
2866 */
asm330lhhx_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_sdo_pu_en_t val)2867 int32_t asm330lhhx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2868 asm330lhhx_sdo_pu_en_t val)
2869 {
2870 asm330lhhx_pin_ctrl_t pin_ctrl;
2871 int32_t ret;
2872
2873 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2874 if (ret == 0)
2875 {
2876 pin_ctrl.sdo_pu_en = (uint8_t)val;
2877 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2878 }
2879 return ret;
2880 }
2881
2882 /**
2883 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2884 *
2885 * @param ctx Read / write interface definitions.(ptr)
2886 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2887 * @retval Interface status (MANDATORY: return 0 -> no Error).
2888 *
2889 */
asm330lhhx_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_sdo_pu_en_t * val)2890 int32_t asm330lhhx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2891 asm330lhhx_sdo_pu_en_t *val)
2892 {
2893 asm330lhhx_pin_ctrl_t pin_ctrl;
2894 int32_t ret;
2895
2896 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2897
2898 switch (pin_ctrl.sdo_pu_en)
2899 {
2900 case ASM330LHHX_PULL_UP_DISC:
2901 *val = ASM330LHHX_PULL_UP_DISC;
2902 break;
2903 case ASM330LHHX_PULL_UP_CONNECT:
2904 *val = ASM330LHHX_PULL_UP_CONNECT;
2905 break;
2906 default:
2907 *val = ASM330LHHX_PULL_UP_DISC;
2908 break;
2909 }
2910 return ret;
2911 }
2912
2913 /**
2914 * @brief Connect/Disconnect INT1 pull-down.[set]
2915 *
2916 * @param ctx Read / write interface definitions.(ptr)
2917 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
2918 * @retval Interface status (MANDATORY: return 0 -> no Error).
2919 *
2920 */
asm330lhhx_int1_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_pd_dis_int1_t val)2921 int32_t asm330lhhx_int1_mode_set(const stmdev_ctx_t *ctx,
2922 asm330lhhx_pd_dis_int1_t val)
2923 {
2924 asm330lhhx_i3c_bus_avb_t i3c_bus_avb;
2925 int32_t ret;
2926
2927 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2928 if (ret == 0)
2929 {
2930 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
2931 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_I3C_BUS_AVB,
2932 (uint8_t *)&i3c_bus_avb, 1);
2933 }
2934 return ret;
2935 }
2936
2937 /**
2938 * @brief Connect/Disconnect INT1 pull-down.[get]
2939 *
2940 * @param ctx Read / write interface definitions.(ptr)
2941 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
2942 * @retval Interface status (MANDATORY: return 0 -> no Error).
2943 *
2944 */
asm330lhhx_int1_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_pd_dis_int1_t * val)2945 int32_t asm330lhhx_int1_mode_get(const stmdev_ctx_t *ctx,
2946 asm330lhhx_pd_dis_int1_t *val)
2947 {
2948 asm330lhhx_i3c_bus_avb_t i3c_bus_avb;
2949 int32_t ret;
2950
2951 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2952
2953 switch (i3c_bus_avb.pd_dis_int1)
2954 {
2955 case ASM330LHHX_PULL_DOWN_CONNECT:
2956 *val = ASM330LHHX_PULL_DOWN_CONNECT;
2957 break;
2958 case ASM330LHHX_PULL_DOWN_DISC:
2959 *val = ASM330LHHX_PULL_DOWN_DISC;
2960 break;
2961 default:
2962 *val = ASM330LHHX_PULL_DOWN_CONNECT;
2963 break;
2964 }
2965 return ret;
2966 }
2967
2968 /**
2969 * @brief SPI Serial Interface Mode selection.[set]
2970 *
2971 * @param ctx Read / write interface definitions.(ptr)
2972 * @param val Change the values of sim in reg CTRL3_C
2973 * @retval Interface status (MANDATORY: return 0 -> no Error).
2974 *
2975 */
asm330lhhx_spi_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_sim_t val)2976 int32_t asm330lhhx_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_sim_t val)
2977 {
2978 asm330lhhx_ctrl3_c_t ctrl3_c;
2979 int32_t ret;
2980
2981 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2982 if (ret == 0)
2983 {
2984 ctrl3_c.sim = (uint8_t)val;
2985 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2986 }
2987 return ret;
2988 }
2989
2990 /**
2991 * @brief SPI Serial Interface Mode selection.[get]
2992 *
2993 * @param ctx Read / write interface definitions.(ptr)
2994 * @param val Get the values of sim in reg CTRL3_C
2995 * @retval Interface status (MANDATORY: return 0 -> no Error).
2996 *
2997 */
asm330lhhx_spi_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_sim_t * val)2998 int32_t asm330lhhx_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_sim_t *val)
2999 {
3000 asm330lhhx_ctrl3_c_t ctrl3_c;
3001 int32_t ret;
3002
3003 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3004
3005 switch (ctrl3_c.sim)
3006 {
3007 case ASM330LHHX_SPI_4_WIRE:
3008 *val = ASM330LHHX_SPI_4_WIRE;
3009 break;
3010 case ASM330LHHX_SPI_3_WIRE:
3011 *val = ASM330LHHX_SPI_3_WIRE;
3012 break;
3013 default:
3014 *val = ASM330LHHX_SPI_4_WIRE;
3015 break;
3016 }
3017 return ret;
3018 }
3019
3020 /**
3021 * @brief Disable / Enable I2C interface.[set]
3022 *
3023 * @param ctx Read / write interface definitions.(ptr)
3024 * @param val Change the values of i2c_disable in reg CTRL4_C
3025 * @retval Interface status (MANDATORY: return 0 -> no Error).
3026 *
3027 */
asm330lhhx_i2c_interface_set(const stmdev_ctx_t * ctx,asm330lhhx_i2c_disable_t val)3028 int32_t asm330lhhx_i2c_interface_set(const stmdev_ctx_t *ctx,
3029 asm330lhhx_i2c_disable_t val)
3030 {
3031 asm330lhhx_ctrl4_c_t ctrl4_c;
3032 int32_t ret;
3033
3034 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3035 if (ret == 0)
3036 {
3037 ctrl4_c.i2c_disable = (uint8_t)val;
3038 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3039 }
3040 return ret;
3041 }
3042
3043 /**
3044 * @brief Disable / Enable I2C interface.[get]
3045 *
3046 * @param ctx Read / write interface definitions.(ptr)
3047 * @param val Get the values of i2c reg CTRL4_C
3048 * @retval Interface status (MANDATORY: return 0 -> no Error).
3049 *
3050 */
asm330lhhx_i2c_interface_get(const stmdev_ctx_t * ctx,asm330lhhx_i2c_disable_t * val)3051 int32_t asm330lhhx_i2c_interface_get(const stmdev_ctx_t *ctx,
3052 asm330lhhx_i2c_disable_t *val)
3053 {
3054 asm330lhhx_ctrl4_c_t ctrl4_c;
3055 int32_t ret;
3056
3057 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3058
3059 switch (ctrl4_c.i2c_disable)
3060 {
3061 case ASM330LHHX_I2C_ENABLE:
3062 *val = ASM330LHHX_I2C_ENABLE;
3063 break;
3064 case ASM330LHHX_I2C_DISABLE:
3065 *val = ASM330LHHX_I2C_DISABLE;
3066 break;
3067 default:
3068 *val = ASM330LHHX_I2C_ENABLE;
3069 break;
3070 }
3071 return ret;
3072 }
3073
3074 /**
3075 * @brief I3C Enable/Disable communication protocol.[set]
3076 *
3077 * @param ctx Read / write interface definitions.(ptr)
3078 * @param val Change the values of i3c_disable in reg CTRL9_XL
3079 * @retval Interface status (MANDATORY: return 0 -> no Error).
3080 *
3081 */
asm330lhhx_i3c_disable_set(const stmdev_ctx_t * ctx,asm330lhhx_i3c_disable_t val)3082 int32_t asm330lhhx_i3c_disable_set(const stmdev_ctx_t *ctx,
3083 asm330lhhx_i3c_disable_t val)
3084 {
3085 asm330lhhx_ctrl9_xl_t ctrl9_xl;
3086 asm330lhhx_i3c_bus_avb_t i3c_bus_avb;
3087 int32_t ret;
3088
3089 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3090 if (ret == 0)
3091 {
3092 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3093 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL,
3094 (uint8_t *)&ctrl9_xl, 1);
3095 }
3096 if (ret == 0)
3097 {
3098 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB,
3099 (uint8_t *)&i3c_bus_avb, 1);
3100 }
3101 if (ret == 0)
3102 {
3103 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3104 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_I3C_BUS_AVB,
3105 (uint8_t *)&i3c_bus_avb, 1);
3106 }
3107 return ret;
3108 }
3109
3110 /**
3111 * @brief I3C Enable/Disable communication protocol.[get]
3112 *
3113 * @param ctx Read / write interface definitions.(ptr)
3114 * @param val Change the values of i3c_disable in reg CTRL9_XL
3115 * @retval Interface status (MANDATORY: return 0 -> no Error).
3116 *
3117 */
asm330lhhx_i3c_disable_get(const stmdev_ctx_t * ctx,asm330lhhx_i3c_disable_t * val)3118 int32_t asm330lhhx_i3c_disable_get(const stmdev_ctx_t *ctx,
3119 asm330lhhx_i3c_disable_t *val)
3120 {
3121 asm330lhhx_ctrl9_xl_t ctrl9_xl;
3122 asm330lhhx_i3c_bus_avb_t i3c_bus_avb;
3123 int32_t ret;
3124
3125 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3126 if (ret == 0)
3127 {
3128 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_I3C_BUS_AVB,
3129 (uint8_t *)&i3c_bus_avb, 1);
3130 }
3131 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
3132 {
3133 case ASM330LHHX_I3C_DISABLE:
3134 *val = ASM330LHHX_I3C_DISABLE;
3135 break;
3136 case ASM330LHHX_I3C_ENABLE_T_50us:
3137 *val = ASM330LHHX_I3C_ENABLE_T_50us;
3138 break;
3139 case ASM330LHHX_I3C_ENABLE_T_2us:
3140 *val = ASM330LHHX_I3C_ENABLE_T_2us;
3141 break;
3142 case ASM330LHHX_I3C_ENABLE_T_1ms:
3143 *val = ASM330LHHX_I3C_ENABLE_T_1ms;
3144 break;
3145 case ASM330LHHX_I3C_ENABLE_T_25ms:
3146 *val = ASM330LHHX_I3C_ENABLE_T_25ms;
3147 break;
3148 default:
3149 *val = ASM330LHHX_I3C_DISABLE;
3150 break;
3151 }
3152 return ret;
3153 }
3154
3155 /**
3156 * @}
3157 *
3158 */
3159
3160 /**
3161 * @defgroup ASM330LHHX_interrupt_pins
3162 * @brief This section groups all the functions that manage
3163 * interrupt pins
3164 * @{
3165 *
3166 */
3167
3168 /**
3169 * @brief Select the signal that need to route on int1 pad.[set]
3170 *
3171 * @param ctx read / write interface definitions
3172 * @param val struct of registers: INT1_CTRL,
3173 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3174 * FSM_INT1_B
3175 *
3176 */
asm330lhhx_pin_int1_route_set(const stmdev_ctx_t * ctx,asm330lhhx_pin_int1_route_t * val)3177 int32_t asm330lhhx_pin_int1_route_set(const stmdev_ctx_t *ctx,
3178 asm330lhhx_pin_int1_route_t *val)
3179 {
3180 asm330lhhx_pin_int2_route_t pin_int2_route;
3181 asm330lhhx_int_cfg1_t int_cfg1;
3182 int32_t ret;
3183
3184 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3185 if (ret == 0)
3186 {
3187 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT1,
3188 (uint8_t *)&val->mlc_int1, 1);
3189 }
3190 if (ret == 0)
3191 {
3192 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT1,
3193 (uint8_t *)&val->emb_func_int1, 1);
3194 }
3195 if (ret == 0)
3196 {
3197 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_A,
3198 (uint8_t *)&val->fsm_int1_a, 1);
3199 }
3200 if (ret == 0)
3201 {
3202 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT1_B,
3203 (uint8_t *)&val->fsm_int1_b, 1);
3204 }
3205 if (ret == 0)
3206 {
3207 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3208 }
3209
3210 if (ret == 0)
3211 {
3212 if ((val->emb_func_int1.int1_fsm_lc
3213 | val->fsm_int1_a.int1_fsm1
3214 | val->fsm_int1_a.int1_fsm2
3215 | val->fsm_int1_a.int1_fsm3
3216 | val->fsm_int1_a.int1_fsm4
3217 | val->fsm_int1_a.int1_fsm5
3218 | val->fsm_int1_a.int1_fsm6
3219 | val->fsm_int1_a.int1_fsm7
3220 | val->fsm_int1_a.int1_fsm8
3221 | val->fsm_int1_b.int1_fsm9
3222 | val->fsm_int1_b.int1_fsm10
3223 | val->fsm_int1_b.int1_fsm11
3224 | val->fsm_int1_b.int1_fsm12
3225 | val->fsm_int1_b.int1_fsm13
3226 | val->fsm_int1_b.int1_fsm14
3227 | val->fsm_int1_b.int1_fsm15
3228 | val->fsm_int1_b.int1_fsm16
3229 | val->mlc_int1.int1_mlc1
3230 | val->mlc_int1.int1_mlc2
3231 | val->mlc_int1.int1_mlc3
3232 | val->mlc_int1.int1_mlc4
3233 | val->mlc_int1.int1_mlc5
3234 | val->mlc_int1.int1_mlc6
3235 | val->mlc_int1.int1_mlc7
3236 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
3237 {
3238 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3239 }
3240 else
3241 {
3242 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3243 }
3244 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT1_CTRL,
3245 (uint8_t *)&val->int1_ctrl, 1);
3246 }
3247 if (ret == 0)
3248 {
3249 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3250 }
3251
3252 if (ret == 0)
3253 {
3254 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3255 }
3256
3257 if (ret == 0)
3258 {
3259 ret = asm330lhhx_pin_int2_route_get(ctx, &pin_int2_route);
3260 }
3261 if (ret == 0)
3262 {
3263 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3264 | pin_int2_route.int2_ctrl.int2_drdy_g
3265 | pin_int2_route.int2_ctrl.int2_drdy_temp
3266 | pin_int2_route.int2_ctrl.int2_drdy_xl
3267 | pin_int2_route.int2_ctrl.int2_fifo_full
3268 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3269 | pin_int2_route.int2_ctrl.int2_fifo_th
3270 | pin_int2_route.md2_cfg.int2_6d
3271 | pin_int2_route.md2_cfg.int2_ff
3272 | pin_int2_route.md2_cfg.int2_wu
3273 | pin_int2_route.md2_cfg.int2_sleep_change
3274 | val->int1_ctrl.den_drdy_flag
3275 | val->int1_ctrl.int1_boot
3276 | val->int1_ctrl.int1_cnt_bdr
3277 | val->int1_ctrl.int1_drdy_g
3278 | val->int1_ctrl.int1_drdy_xl
3279 | val->int1_ctrl.int1_fifo_full
3280 | val->int1_ctrl.int1_fifo_ovr
3281 | val->int1_ctrl.int1_fifo_th
3282 | val->md1_cfg.int1_shub
3283 | val->md1_cfg.int1_6d
3284 | val->md1_cfg.int1_ff
3285 | val->md1_cfg.int1_wu
3286 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3287 {
3288 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3289 }
3290 else
3291 {
3292 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3293 }
3294 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3295 }
3296 return ret;
3297 }
3298
3299 /**
3300 * @brief Select the signal that need to route on int1 pad.[get]
3301 *
3302 * @param ctx read / write interface definitions
3303 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3304 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3305 *
3306 */
asm330lhhx_pin_int1_route_get(const stmdev_ctx_t * ctx,asm330lhhx_pin_int1_route_t * val)3307 int32_t asm330lhhx_pin_int1_route_get(const stmdev_ctx_t *ctx,
3308 asm330lhhx_pin_int1_route_t *val)
3309 {
3310 int32_t ret;
3311
3312 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3313 if (ret == 0)
3314 {
3315 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT1,
3316 (uint8_t *)&val->mlc_int1, 1);
3317 }
3318 if (ret == 0)
3319 {
3320 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT1,
3321 (uint8_t *)&val->emb_func_int1, 1);
3322 }
3323 if (ret == 0)
3324 {
3325 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_A,
3326 (uint8_t *)&val->fsm_int1_a, 1);
3327 }
3328 if (ret == 0)
3329 {
3330 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT1_B,
3331 (uint8_t *)&val->fsm_int1_b, 1);
3332 }
3333 if (ret == 0)
3334 {
3335 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3336 }
3337 if (ret == 0)
3338 {
3339
3340 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT1_CTRL,
3341 (uint8_t *)&val->int1_ctrl, 1);
3342 }
3343 if (ret == 0)
3344 {
3345 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3346 }
3347
3348 return ret;
3349 }
3350
3351 /**
3352 * @brief Select the signal that need to route on int2 pad.[set]
3353 *
3354 * @param ctx read / write interface definitions
3355 * @param val union of registers INT2_CTRL, MD2_CFG,
3356 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3357 *
3358 */
asm330lhhx_pin_int2_route_set(const stmdev_ctx_t * ctx,asm330lhhx_pin_int2_route_t * val)3359 int32_t asm330lhhx_pin_int2_route_set(const stmdev_ctx_t *ctx,
3360 asm330lhhx_pin_int2_route_t *val)
3361 {
3362 asm330lhhx_pin_int1_route_t pin_int1_route;
3363 asm330lhhx_int_cfg1_t int_cfg1;
3364 int32_t ret;
3365
3366 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3367 if (ret == 0)
3368 {
3369 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MLC_INT2,
3370 (uint8_t *)&val->mlc_int2, 1);
3371 }
3372 if (ret == 0)
3373 {
3374 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INT2,
3375 (uint8_t *)&val->emb_func_int2, 1);
3376 }
3377 if (ret == 0)
3378 {
3379 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_A,
3380 (uint8_t *)&val->fsm_int2_a, 1);
3381 }
3382 if (ret == 0)
3383 {
3384 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_INT2_B,
3385 (uint8_t *)&val->fsm_int2_b, 1);
3386 }
3387 if (ret == 0)
3388 {
3389 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3390 }
3391
3392 if (ret == 0)
3393 {
3394 if ((val->emb_func_int2.int2_fsm_lc
3395 | val->fsm_int2_a.int2_fsm1
3396 | val->fsm_int2_a.int2_fsm2
3397 | val->fsm_int2_a.int2_fsm3
3398 | val->fsm_int2_a.int2_fsm4
3399 | val->fsm_int2_a.int2_fsm5
3400 | val->fsm_int2_a.int2_fsm6
3401 | val->fsm_int2_a.int2_fsm7
3402 | val->fsm_int2_a.int2_fsm8
3403 | val->fsm_int2_b.int2_fsm9
3404 | val->fsm_int2_b.int2_fsm10
3405 | val->fsm_int2_b.int2_fsm11
3406 | val->fsm_int2_b.int2_fsm12
3407 | val->fsm_int2_b.int2_fsm13
3408 | val->fsm_int2_b.int2_fsm14
3409 | val->fsm_int2_b.int2_fsm15
3410 | val->fsm_int2_b.int2_fsm16
3411 | val->mlc_int2.int2_mlc1
3412 | val->mlc_int2.int2_mlc2
3413 | val->mlc_int2.int2_mlc3
3414 | val->mlc_int2.int2_mlc4
3415 | val->mlc_int2.int2_mlc5
3416 | val->mlc_int2.int2_mlc6
3417 | val->mlc_int2.int2_mlc7
3418 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
3419 {
3420 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3421 }
3422 else
3423 {
3424 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3425 }
3426 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT2_CTRL,
3427 (uint8_t *)&val->int2_ctrl, 1);
3428 }
3429 if (ret == 0)
3430 {
3431 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3432 }
3433 if (ret == 0)
3434 {
3435 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3436 }
3437
3438 if (ret == 0)
3439 {
3440 ret = asm330lhhx_pin_int1_route_get(ctx, &pin_int1_route);
3441 }
3442
3443 if (ret == 0)
3444 {
3445 if ((val->int2_ctrl.int2_cnt_bdr
3446 | val->int2_ctrl.int2_drdy_g
3447 | val->int2_ctrl.int2_drdy_temp
3448 | val->int2_ctrl.int2_drdy_xl
3449 | val->int2_ctrl.int2_fifo_full
3450 | val->int2_ctrl.int2_fifo_ovr
3451 | val->int2_ctrl.int2_fifo_th
3452 | val->md2_cfg.int2_6d
3453 | val->md2_cfg.int2_ff
3454 | val->md2_cfg.int2_wu
3455 | val->md2_cfg.int2_sleep_change
3456 | pin_int1_route.int1_ctrl.den_drdy_flag
3457 | pin_int1_route.int1_ctrl.int1_boot
3458 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3459 | pin_int1_route.int1_ctrl.int1_drdy_g
3460 | pin_int1_route.int1_ctrl.int1_drdy_xl
3461 | pin_int1_route.int1_ctrl.int1_fifo_full
3462 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3463 | pin_int1_route.int1_ctrl.int1_fifo_th
3464 | pin_int1_route.md1_cfg.int1_6d
3465 | pin_int1_route.md1_cfg.int1_ff
3466 | pin_int1_route.md1_cfg.int1_wu
3467 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3468 {
3469 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3470 }
3471 else
3472 {
3473 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3474 }
3475 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3476 }
3477 return ret;
3478 }
3479
3480 /**
3481 * @brief Select the signal that need to route on int2 pad.[get]
3482 *
3483 * @param ctx read / write interface definitions
3484 * @param val union of registers INT2_CTRL, MD2_CFG,
3485 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3486 *
3487 */
asm330lhhx_pin_int2_route_get(const stmdev_ctx_t * ctx,asm330lhhx_pin_int2_route_t * val)3488 int32_t asm330lhhx_pin_int2_route_get(const stmdev_ctx_t *ctx,
3489 asm330lhhx_pin_int2_route_t *val)
3490 {
3491 int32_t ret;
3492
3493 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3494 if (ret == 0)
3495 {
3496 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_INT2,
3497 (uint8_t *)&val->mlc_int2, 1);
3498 }
3499 if (ret == 0)
3500 {
3501 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INT2,
3502 (uint8_t *)&val->emb_func_int2, 1);
3503 }
3504 if (ret == 0)
3505 {
3506 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_A,
3507 (uint8_t *)&val->fsm_int2_a, 1);
3508 }
3509 if (ret == 0)
3510 {
3511 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_INT2_B,
3512 (uint8_t *)&val->fsm_int2_b, 1);
3513 }
3514 if (ret == 0)
3515 {
3516 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3517 }
3518 if (ret == 0)
3519 {
3520
3521 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT2_CTRL,
3522 (uint8_t *)&val->int2_ctrl, 1);
3523 }
3524 if (ret == 0)
3525 {
3526 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3527 }
3528 return ret;
3529 }
3530
3531 /**
3532 * @brief Push-pull/open drain selection on interrupt pads.[set]
3533 *
3534 * @param ctx Read / write interface definitions.(ptr)
3535 * @param val Change the values of pp_od in reg CTRL3_C
3536 * @retval Interface status (MANDATORY: return 0 -> no Error).
3537 *
3538 */
asm330lhhx_pin_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_pp_od_t val)3539 int32_t asm330lhhx_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t val)
3540 {
3541 asm330lhhx_ctrl3_c_t ctrl3_c;
3542 int32_t ret;
3543
3544 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3545 if (ret == 0)
3546 {
3547 ctrl3_c.pp_od = (uint8_t)val;
3548 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3549 }
3550 return ret;
3551 }
3552
3553 /**
3554 * @brief Push-pull/open drain selection on interrupt pads.[get]
3555 *
3556 * @param ctx Read / write interface definitions.(ptr)
3557 * @param val Get the values of pp_od in reg CTRL3_C
3558 * @retval Interface status (MANDATORY: return 0 -> no Error).
3559 *
3560 */
asm330lhhx_pin_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_pp_od_t * val)3561 int32_t asm330lhhx_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhhx_pp_od_t *val)
3562 {
3563 asm330lhhx_ctrl3_c_t ctrl3_c;
3564 int32_t ret;
3565
3566 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3567
3568 switch (ctrl3_c.pp_od)
3569 {
3570 case ASM330LHHX_PUSH_PULL:
3571 *val = ASM330LHHX_PUSH_PULL;
3572 break;
3573 case ASM330LHHX_OPEN_DRAIN:
3574 *val = ASM330LHHX_OPEN_DRAIN;
3575 break;
3576 default:
3577 *val = ASM330LHHX_PUSH_PULL;
3578 break;
3579 }
3580 return ret;
3581 }
3582
3583 /**
3584 * @brief Interrupt active-high/low.[set]
3585 *
3586 * @param ctx Read / write interface definitions.(ptr)
3587 * @param val Change the values of h_lactive in reg CTRL3_C
3588 * @retval Interface status (MANDATORY: return 0 -> no Error).
3589 *
3590 */
asm330lhhx_pin_polarity_set(const stmdev_ctx_t * ctx,asm330lhhx_h_lactive_t val)3591 int32_t asm330lhhx_pin_polarity_set(const stmdev_ctx_t *ctx,
3592 asm330lhhx_h_lactive_t val)
3593 {
3594 asm330lhhx_ctrl3_c_t ctrl3_c;
3595 int32_t ret;
3596
3597 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3598 if (ret == 0)
3599 {
3600 ctrl3_c.h_lactive = (uint8_t)val;
3601 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3602 }
3603 return ret;
3604 }
3605
3606 /**
3607 * @brief Interrupt active-high/low.[get]
3608 *
3609 * @param ctx Read / write interface definitions.(ptr)
3610 * @param val Get the values of h_lactive in reg CTRL3_C
3611 * @retval Interface status (MANDATORY: return 0 -> no Error).
3612 *
3613 */
asm330lhhx_pin_polarity_get(const stmdev_ctx_t * ctx,asm330lhhx_h_lactive_t * val)3614 int32_t asm330lhhx_pin_polarity_get(const stmdev_ctx_t *ctx,
3615 asm330lhhx_h_lactive_t *val)
3616 {
3617 asm330lhhx_ctrl3_c_t ctrl3_c;
3618 int32_t ret;
3619
3620 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3621
3622 switch (ctrl3_c.h_lactive)
3623 {
3624 case ASM330LHHX_ACTIVE_HIGH:
3625 *val = ASM330LHHX_ACTIVE_HIGH;
3626 break;
3627 case ASM330LHHX_ACTIVE_LOW:
3628 *val = ASM330LHHX_ACTIVE_LOW;
3629 break;
3630 default:
3631 *val = ASM330LHHX_ACTIVE_HIGH;
3632 break;
3633 }
3634 return ret;
3635 }
3636
3637 /**
3638 * @brief All interrupt signals become available on INT1 pin.[set]
3639 *
3640 * @param ctx Read / write interface definitions.(ptr)
3641 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3642 * @retval Interface status (MANDATORY: return 0 -> no Error).
3643 *
3644 */
asm330lhhx_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3645 int32_t asm330lhhx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3646 {
3647 asm330lhhx_ctrl4_c_t ctrl4_c;
3648 int32_t ret;
3649
3650 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3651 if (ret == 0)
3652 {
3653 ctrl4_c.int2_on_int1 = (uint8_t)val;
3654 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3655 }
3656 return ret;
3657 }
3658
3659 /**
3660 * @brief All interrupt signals become available on INT1 pin.[get]
3661 *
3662 * @param ctx Read / write interface definitions.(ptr)
3663 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3664 * @retval Interface status (MANDATORY: return 0 -> no Error).
3665 *
3666 */
asm330lhhx_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3667 int32_t asm330lhhx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3668 {
3669 asm330lhhx_ctrl4_c_t ctrl4_c;
3670 int32_t ret;
3671
3672 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3673 *val = ctrl4_c.int2_on_int1;
3674
3675 return ret;
3676 }
3677
3678 /**
3679 * @brief All interrupt signals notification mode.[set]
3680 *
3681 * @param ctx Read / write interface definitions.(ptr)
3682 * @param val Change the values of lir in reg INT_CFG0
3683 * @retval Interface status (MANDATORY: return 0 -> no Error).
3684 *
3685 */
asm330lhhx_int_notification_set(const stmdev_ctx_t * ctx,asm330lhhx_lir_t val)3686 int32_t asm330lhhx_int_notification_set(const stmdev_ctx_t *ctx,
3687 asm330lhhx_lir_t val)
3688 {
3689 asm330lhhx_int_cfg0_t int_cfg0;
3690 asm330lhhx_page_rw_t page_rw;
3691 int32_t ret;
3692
3693 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3694 if (ret == 0)
3695 {
3696 int_cfg0.lir = (uint8_t)val & 0x01U;
3697 int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3698 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG0,
3699 (uint8_t *)&int_cfg0, 1);
3700 }
3701 if (ret == 0)
3702 {
3703 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3704 }
3705 if (ret == 0)
3706 {
3707 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
3708 }
3709 if (ret == 0)
3710 {
3711 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3712 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
3713 }
3714 if (ret == 0)
3715 {
3716 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3717 }
3718 return ret;
3719 }
3720
3721 /**
3722 * @brief All interrupt signals notification mode.[get]
3723 *
3724 * @param ctx Read / write interface definitions.(ptr)
3725 * @param val Get the values of lir in reg INT_CFG0
3726 * @retval Interface status (MANDATORY: return 0 -> no Error).
3727 *
3728 */
asm330lhhx_int_notification_get(const stmdev_ctx_t * ctx,asm330lhhx_lir_t * val)3729 int32_t asm330lhhx_int_notification_get(const stmdev_ctx_t *ctx,
3730 asm330lhhx_lir_t *val)
3731 {
3732 asm330lhhx_int_cfg0_t int_cfg0;
3733 asm330lhhx_page_rw_t page_rw;
3734 int32_t ret;
3735
3736 *val = ASM330LHHX_ALL_INT_PULSED;
3737 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3738
3739 if (ret == 0)
3740 {
3741 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
3742 }
3743 if (ret == 0)
3744 {
3745 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_RW, (uint8_t *)&page_rw, 1);
3746 }
3747 if (ret == 0)
3748 {
3749 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
3750 }
3751 switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir)
3752 {
3753 case ASM330LHHX_ALL_INT_PULSED:
3754 *val = ASM330LHHX_ALL_INT_PULSED;
3755 break;
3756 case ASM330LHHX_BASE_LATCHED_EMB_PULSED:
3757 *val = ASM330LHHX_BASE_LATCHED_EMB_PULSED;
3758 break;
3759 case ASM330LHHX_BASE_PULSED_EMB_LATCHED:
3760 *val = ASM330LHHX_BASE_PULSED_EMB_LATCHED;
3761 break;
3762 case ASM330LHHX_ALL_INT_LATCHED:
3763 *val = ASM330LHHX_ALL_INT_LATCHED;
3764 break;
3765 default:
3766 *val = ASM330LHHX_ALL_INT_PULSED;
3767 break;
3768 }
3769 return ret;
3770 }
3771
3772 /**
3773 * @}
3774 *
3775 */
3776
3777 /**
3778 * @defgroup ASM330LHHX_Wake_Up_event
3779 * @brief This section groups all the functions that manage the
3780 * Wake Up event generation.
3781 * @{
3782 *
3783 */
3784
3785 /**
3786 * @brief Weight of 1 LSB of wakeup threshold.[set]
3787 * 0: 1 LSB =FS_XL / 64
3788 * 1: 1 LSB = FS_XL / 256
3789 *
3790 * @param ctx Read / write interface definitions.(ptr)
3791 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
3792 * @retval Interface status (MANDATORY: return 0 -> no Error).
3793 *
3794 */
asm330lhhx_wkup_ths_weight_set(const stmdev_ctx_t * ctx,asm330lhhx_wake_ths_w_t val)3795 int32_t asm330lhhx_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
3796 asm330lhhx_wake_ths_w_t val)
3797 {
3798 asm330lhhx_wake_up_dur_t wake_up_dur;
3799 int32_t ret;
3800
3801 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3802 (uint8_t *)&wake_up_dur, 1);
3803 if (ret == 0)
3804 {
3805 wake_up_dur.wake_ths_w = (uint8_t)val;
3806 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3807 (uint8_t *)&wake_up_dur, 1);
3808 }
3809 return ret;
3810 }
3811
3812 /**
3813 * @brief Weight of 1 LSB of wakeup threshold.[get]
3814 * 0: 1 LSB =FS_XL / 64
3815 * 1: 1 LSB = FS_XL / 256
3816 *
3817 * @param ctx Read / write interface definitions.(ptr)
3818 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
3819 * @retval Interface status (MANDATORY: return 0 -> no Error).
3820 *
3821 */
asm330lhhx_wkup_ths_weight_get(const stmdev_ctx_t * ctx,asm330lhhx_wake_ths_w_t * val)3822 int32_t asm330lhhx_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
3823 asm330lhhx_wake_ths_w_t *val)
3824 {
3825 asm330lhhx_wake_up_dur_t wake_up_dur;
3826 int32_t ret;
3827
3828 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3829 (uint8_t *)&wake_up_dur, 1);
3830
3831 switch (wake_up_dur.wake_ths_w)
3832 {
3833 case ASM330LHHX_LSb_FS_DIV_64:
3834 *val = ASM330LHHX_LSb_FS_DIV_64;
3835 break;
3836 case ASM330LHHX_LSb_FS_DIV_256:
3837 *val = ASM330LHHX_LSb_FS_DIV_256;
3838 break;
3839 default:
3840 *val = ASM330LHHX_LSb_FS_DIV_64;
3841 break;
3842 }
3843 return ret;
3844 }
3845
3846 /**
3847 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3848 * WAKE_UP_DUR.[set]
3849 *
3850 * @param ctx Read / write interface definitions.(ptr)
3851 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3852 * @retval Interface status (MANDATORY: return 0 -> no Error).
3853 *
3854 */
asm330lhhx_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3855 int32_t asm330lhhx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3856 {
3857 asm330lhhx_wake_up_ths_t wake_up_ths;
3858 int32_t ret;
3859
3860 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3861 (uint8_t *)&wake_up_ths, 1);
3862 if (ret == 0)
3863 {
3864 wake_up_ths.wk_ths = (uint8_t)val;
3865 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3866 (uint8_t *)&wake_up_ths, 1);
3867 }
3868 return ret;
3869 }
3870
3871 /**
3872 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3873 * WAKE_UP_DUR.[get]
3874 *
3875 * @param ctx Read / write interface definitions.(ptr)
3876 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3877 * @retval Interface status (MANDATORY: return 0 -> no Error).
3878 *
3879 */
asm330lhhx_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3880 int32_t asm330lhhx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3881 {
3882 asm330lhhx_wake_up_ths_t wake_up_ths;
3883 int32_t ret;
3884
3885 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3886 (uint8_t *)&wake_up_ths, 1);
3887 *val = wake_up_ths.wk_ths;
3888
3889 return ret;
3890 }
3891
3892 /**
3893 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
3894 *
3895 * @param ctx Read / write interface definitions.(ptr)
3896 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3897 * @retval Interface status (MANDATORY: return 0 -> no Error).
3898 *
3899 */
asm330lhhx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)3900 int32_t asm330lhhx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val)
3901 {
3902 asm330lhhx_wake_up_ths_t wake_up_ths;
3903 int32_t ret;
3904
3905 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3906 (uint8_t *)&wake_up_ths, 1);
3907 if (ret == 0)
3908 {
3909 wake_up_ths.usr_off_on_wu = (uint8_t)val;
3910 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3911 (uint8_t *)&wake_up_ths, 1);
3912 }
3913 return ret;
3914 }
3915
3916 /**
3917 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
3918 *
3919 * @param ctx Read / write interface definitions.(ptr)
3920 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3921 * @retval Interface status (MANDATORY: return 0 -> no Error).
3922 *
3923 */
asm330lhhx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)3924 int32_t asm330lhhx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
3925 uint8_t *val)
3926 {
3927 asm330lhhx_wake_up_ths_t wake_up_ths;
3928 int32_t ret;
3929
3930 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_THS,
3931 (uint8_t *)&wake_up_ths, 1);
3932 *val = wake_up_ths.usr_off_on_wu;
3933
3934 return ret;
3935 }
3936
3937 /**
3938 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
3939 *
3940 * @param ctx Read / write interface definitions.(ptr)
3941 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3942 * @retval Interface status (MANDATORY: return 0 -> no Error).
3943 *
3944 */
asm330lhhx_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3945 int32_t asm330lhhx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3946 {
3947 asm330lhhx_wake_up_dur_t wake_up_dur;
3948 int32_t ret;
3949
3950 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3951 (uint8_t *)&wake_up_dur, 1);
3952 if (ret == 0)
3953 {
3954 wake_up_dur.wake_dur = (uint8_t)val;
3955 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3956 (uint8_t *)&wake_up_dur, 1);
3957 }
3958 return ret;
3959 }
3960
3961 /**
3962 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3963 *
3964 * @param ctx Read / write interface definitions.(ptr)
3965 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3966 * @retval Interface status (MANDATORY: return 0 -> no Error).
3967 *
3968 */
asm330lhhx_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3969 int32_t asm330lhhx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3970 {
3971 asm330lhhx_wake_up_dur_t wake_up_dur;
3972 int32_t ret;
3973
3974 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
3975 (uint8_t *)&wake_up_dur, 1);
3976 *val = wake_up_dur.wake_dur;
3977
3978 return ret;
3979 }
3980
3981 /**
3982 * @}
3983 *
3984 */
3985
3986 /**
3987 * @defgroup ASM330LHHX_ Activity/Inactivity_detection
3988 * @brief This section groups all the functions concerning
3989 * activity/inactivity detection.
3990 * @{
3991 *
3992 */
3993
3994 /**
3995 * @brief Enables gyroscope Sleep mode.[set]
3996 *
3997 * @param ctx Read / write interface definitions.(ptr)
3998 * @param val Change the values of sleep_g in reg CTRL4_C
3999 * @retval Interface status (MANDATORY: return 0 -> no Error).
4000 *
4001 */
asm330lhhx_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4002 int32_t asm330lhhx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4003 {
4004 asm330lhhx_ctrl4_c_t ctrl4_c;
4005 int32_t ret;
4006
4007 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4008 if (ret == 0)
4009 {
4010 ctrl4_c.sleep_g = (uint8_t)val;
4011 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4012 }
4013 return ret;
4014 }
4015
4016 /**
4017 * @brief Enables gyroscope Sleep mode.[get]
4018 *
4019 * @param ctx Read / write interface definitions.(ptr)
4020 * @param val Change the values of sleep_g in reg CTRL4_C
4021 * @retval Interface status (MANDATORY: return 0 -> no Error).
4022 *
4023 */
asm330lhhx_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4024 int32_t asm330lhhx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4025 {
4026 asm330lhhx_ctrl4_c_t ctrl4_c;
4027 int32_t ret;
4028
4029 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4030 *val = ctrl4_c.sleep_g;
4031
4032 return ret;
4033 }
4034
4035 /**
4036 * @brief Drives the sleep status instead of sleep change on INT pins
4037 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4038 * are enabled).[set]
4039 *
4040 * @param ctx Read / write interface definitions.(ptr)
4041 * @param val Change the values of sleep_status_on_int in reg INT_CFG0
4042 * @retval Interface status (MANDATORY: return 0 -> no Error).
4043 *
4044 */
asm330lhhx_act_pin_notification_set(const stmdev_ctx_t * ctx,asm330lhhx_sleep_status_on_int_t val)4045 int32_t asm330lhhx_act_pin_notification_set(const stmdev_ctx_t *ctx,
4046 asm330lhhx_sleep_status_on_int_t val)
4047 {
4048 asm330lhhx_int_cfg0_t int_cfg0;
4049 int32_t ret;
4050
4051 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4052 if (ret == 0)
4053 {
4054 int_cfg0. sleep_status_on_int = (uint8_t)val;
4055 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG0,
4056 (uint8_t *)&int_cfg0, 1);
4057 }
4058 return ret;
4059 }
4060
4061 /**
4062 * @brief Drives the sleep status instead of sleep change on INT pins
4063 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4064 * are enabled).[get]
4065 *
4066 * @param ctx Read / write interface definitions.(ptr)
4067 * @param val Get the values of sleep_status_on_int in reg INT_CFG0
4068 * @retval Interface status (MANDATORY: return 0 -> no Error).
4069 *
4070 */
asm330lhhx_act_pin_notification_get(const stmdev_ctx_t * ctx,asm330lhhx_sleep_status_on_int_t * val)4071 int32_t asm330lhhx_act_pin_notification_get(const stmdev_ctx_t *ctx,
4072 asm330lhhx_sleep_status_on_int_t *val)
4073 {
4074 asm330lhhx_int_cfg0_t int_cfg0;
4075 int32_t ret;
4076
4077 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4078 switch (int_cfg0. sleep_status_on_int)
4079 {
4080 case ASM330LHHX_DRIVE_SLEEP_CHG_EVENT:
4081 *val = ASM330LHHX_DRIVE_SLEEP_CHG_EVENT;
4082 break;
4083 case ASM330LHHX_DRIVE_SLEEP_STATUS:
4084 *val = ASM330LHHX_DRIVE_SLEEP_STATUS;
4085 break;
4086 default:
4087 *val = ASM330LHHX_DRIVE_SLEEP_CHG_EVENT;
4088 break;
4089 }
4090 return ret;
4091 }
4092
4093 /**
4094 * @brief Enable inactivity function.[set]
4095 *
4096 * @param ctx Read / write interface definitions.(ptr)
4097 * @param val Change the values of inact_en in reg INT_CFG1
4098 * @retval Interface status (MANDATORY: return 0 -> no Error).
4099 *
4100 */
asm330lhhx_act_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_inact_en_t val)4101 int32_t asm330lhhx_act_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_inact_en_t val)
4102 {
4103 asm330lhhx_int_cfg1_t int_cfg1;
4104 int32_t ret;
4105
4106 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4107 if (ret == 0)
4108 {
4109 int_cfg1.inact_en = (uint8_t)val;
4110 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4111 }
4112 return ret;
4113 }
4114
4115 /**
4116 * @brief Enable inactivity function.[get]
4117 *
4118 * @param ctx Read / write interface definitions.(ptr)
4119 * @param val Get the values of inact_en in reg INT_CFG1
4120 * @retval Interface status (MANDATORY: return 0 -> no Error).
4121 *
4122 */
asm330lhhx_act_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_inact_en_t * val)4123 int32_t asm330lhhx_act_mode_get(const stmdev_ctx_t *ctx,
4124 asm330lhhx_inact_en_t *val)
4125 {
4126 asm330lhhx_int_cfg1_t int_cfg1;
4127 int32_t ret;
4128
4129 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4130
4131 switch (int_cfg1.inact_en)
4132 {
4133 case ASM330LHHX_XL_AND_GY_NOT_AFFECTED:
4134 *val = ASM330LHHX_XL_AND_GY_NOT_AFFECTED;
4135 break;
4136 case ASM330LHHX_XL_12Hz5_GY_NOT_AFFECTED:
4137 *val = ASM330LHHX_XL_12Hz5_GY_NOT_AFFECTED;
4138 break;
4139 case ASM330LHHX_XL_12Hz5_GY_SLEEP:
4140 *val = ASM330LHHX_XL_12Hz5_GY_SLEEP;
4141 break;
4142 case ASM330LHHX_XL_12Hz5_GY_PD:
4143 *val = ASM330LHHX_XL_12Hz5_GY_PD;
4144 break;
4145 default:
4146 *val = ASM330LHHX_XL_AND_GY_NOT_AFFECTED;
4147 break;
4148 }
4149 return ret;
4150 }
4151
4152 /**
4153 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
4154 *
4155 * @param ctx Read / write interface definitions.(ptr)
4156 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4157 * @retval Interface status (MANDATORY: return 0 -> no Error).
4158 *
4159 */
asm330lhhx_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4160 int32_t asm330lhhx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4161 {
4162 asm330lhhx_wake_up_dur_t wake_up_dur;
4163 int32_t ret;
4164
4165 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4166 (uint8_t *)&wake_up_dur, 1);
4167 if (ret == 0)
4168 {
4169 wake_up_dur.sleep_dur = (uint8_t)val;
4170 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4171 (uint8_t *)&wake_up_dur, 1);
4172 }
4173 return ret;
4174 }
4175
4176 /**
4177 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
4178 *
4179 * @param ctx Read / write interface definitions.(ptr)
4180 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4181 * @retval Interface status (MANDATORY: return 0 -> no Error).
4182 *
4183 */
asm330lhhx_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4184 int32_t asm330lhhx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4185 {
4186 asm330lhhx_wake_up_dur_t wake_up_dur;
4187 int32_t ret;
4188
4189 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4190 (uint8_t *)&wake_up_dur, 1);
4191 *val = wake_up_dur.sleep_dur;
4192
4193 return ret;
4194 }
4195
4196 /**
4197 * @}
4198 *
4199 */
4200
4201 /**
4202 * @defgroup ASM330LHHX_ Six_position_detection(6D/4D)
4203 * @brief This section groups all the functions concerning six
4204 * position detection (6D).
4205 * @{
4206 *
4207 */
4208
4209 /**
4210 * @brief Threshold for 4D/6D function.[set]
4211 *
4212 * @param ctx Read / write interface definitions.(ptr)
4213 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4214 * @retval Interface status (MANDATORY: return 0 -> no Error).
4215 *
4216 */
asm330lhhx_6d_threshold_set(const stmdev_ctx_t * ctx,asm330lhhx_sixd_ths_t val)4217 int32_t asm330lhhx_6d_threshold_set(const stmdev_ctx_t *ctx,
4218 asm330lhhx_sixd_ths_t val)
4219 {
4220 asm330lhhx_ths_6d_t ths_6d;
4221 int32_t ret;
4222
4223 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D,
4224 (uint8_t *)&ths_6d, 1);
4225 if (ret == 0)
4226 {
4227 ths_6d.sixd_ths = (uint8_t)val;
4228 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_THS_6D,
4229 (uint8_t *)&ths_6d, 1);
4230 }
4231 return ret;
4232 }
4233
4234 /**
4235 * @brief Threshold for 4D/6D function.[get]
4236 *
4237 * @param ctx Read / write interface definitions.(ptr)
4238 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4239 * @retval Interface status (MANDATORY: return 0 -> no Error).
4240 *
4241 */
asm330lhhx_6d_threshold_get(const stmdev_ctx_t * ctx,asm330lhhx_sixd_ths_t * val)4242 int32_t asm330lhhx_6d_threshold_get(const stmdev_ctx_t *ctx,
4243 asm330lhhx_sixd_ths_t *val)
4244 {
4245 asm330lhhx_ths_6d_t ths_6d;
4246 int32_t ret;
4247
4248 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D,
4249 (uint8_t *)&ths_6d, 1);
4250
4251 switch (ths_6d.sixd_ths)
4252 {
4253 case ASM330LHHX_DEG_80:
4254 *val = ASM330LHHX_DEG_80;
4255 break;
4256 case ASM330LHHX_DEG_70:
4257 *val = ASM330LHHX_DEG_70;
4258 break;
4259 case ASM330LHHX_DEG_60:
4260 *val = ASM330LHHX_DEG_60;
4261 break;
4262 case ASM330LHHX_DEG_50:
4263 *val = ASM330LHHX_DEG_50;
4264 break;
4265 default:
4266 *val = ASM330LHHX_DEG_80;
4267 break;
4268 }
4269 return ret;
4270 }
4271
4272 /**
4273 * @brief 4D orientation detection enable.[set]
4274 *
4275 * @param ctx Read / write interface definitions.(ptr)
4276 * @param val Change the values of d4d_en in reg TAP_THS_6D
4277 * @retval Interface status (MANDATORY: return 0 -> no Error).
4278 *
4279 */
asm330lhhx_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4280 int32_t asm330lhhx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4281 {
4282 asm330lhhx_ths_6d_t ths_6d;
4283 int32_t ret;
4284
4285 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D,
4286 (uint8_t *)&ths_6d, 1);
4287 if (ret == 0)
4288 {
4289 ths_6d.d4d_en = (uint8_t)val;
4290 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_THS_6D,
4291 (uint8_t *)&ths_6d, 1);
4292 }
4293 return ret;
4294 }
4295
4296 /**
4297 * @brief 4D orientation detection enable.[get]
4298 *
4299 * @param ctx Read / write interface definitions.(ptr)
4300 * @param val Change the values of d4d_en in reg TAP_THS_6D
4301 * @retval Interface status (MANDATORY: return 0 -> no Error).
4302 *
4303 */
asm330lhhx_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4304 int32_t asm330lhhx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4305 {
4306 asm330lhhx_ths_6d_t ths_6d;
4307 int32_t ret;
4308
4309 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_THS_6D,
4310 (uint8_t *)&ths_6d, 1);
4311 *val = ths_6d.d4d_en;
4312
4313 return ret;
4314 }
4315
4316 /**
4317 * @}
4318 *
4319 */
4320
4321 /**
4322 * @defgroup ASM330LHHX_free_fall
4323 * @brief This section group all the functions concerning the free
4324 * fall detection.
4325 * @{
4326 *
4327 */
4328
4329 /**
4330 * @brief Free fall threshold setting.[set]
4331 *
4332 * @param ctx Read / write interface definitions.(ptr)
4333 * @param val Change the values of ff_ths in reg FREE_FALL
4334 * @retval Interface status (MANDATORY: return 0 -> no Error).
4335 *
4336 */
asm330lhhx_ff_threshold_set(const stmdev_ctx_t * ctx,asm330lhhx_ff_ths_t val)4337 int32_t asm330lhhx_ff_threshold_set(const stmdev_ctx_t *ctx,
4338 asm330lhhx_ff_ths_t val)
4339 {
4340 asm330lhhx_free_fall_t free_fall;
4341 int32_t ret;
4342
4343 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL, (uint8_t *)&free_fall, 1);
4344 if (ret == 0)
4345 {
4346 free_fall.ff_ths = (uint8_t)val;
4347 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FREE_FALL,
4348 (uint8_t *)&free_fall, 1);
4349 }
4350 return ret;
4351 }
4352
4353 /**
4354 * @brief Free fall threshold setting.[get]
4355 *
4356 * @param ctx Read / write interface definitions.(ptr)
4357 * @param val Get the values of ff_ths in reg FREE_FALL
4358 * @retval Interface status (MANDATORY: return 0 -> no Error).
4359 *
4360 */
asm330lhhx_ff_threshold_get(const stmdev_ctx_t * ctx,asm330lhhx_ff_ths_t * val)4361 int32_t asm330lhhx_ff_threshold_get(const stmdev_ctx_t *ctx,
4362 asm330lhhx_ff_ths_t *val)
4363 {
4364 asm330lhhx_free_fall_t free_fall;
4365 int32_t ret;
4366
4367 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL, (uint8_t *)&free_fall, 1);
4368
4369 switch (free_fall.ff_ths)
4370 {
4371 case ASM330LHHX_FF_TSH_156mg:
4372 *val = ASM330LHHX_FF_TSH_156mg;
4373 break;
4374 case ASM330LHHX_FF_TSH_219mg:
4375 *val = ASM330LHHX_FF_TSH_219mg;
4376 break;
4377 case ASM330LHHX_FF_TSH_250mg:
4378 *val = ASM330LHHX_FF_TSH_250mg;
4379 break;
4380 case ASM330LHHX_FF_TSH_312mg:
4381 *val = ASM330LHHX_FF_TSH_312mg;
4382 break;
4383 case ASM330LHHX_FF_TSH_344mg:
4384 *val = ASM330LHHX_FF_TSH_344mg;
4385 break;
4386 case ASM330LHHX_FF_TSH_406mg:
4387 *val = ASM330LHHX_FF_TSH_406mg;
4388 break;
4389 case ASM330LHHX_FF_TSH_469mg:
4390 *val = ASM330LHHX_FF_TSH_469mg;
4391 break;
4392 case ASM330LHHX_FF_TSH_500mg:
4393 *val = ASM330LHHX_FF_TSH_500mg;
4394 break;
4395 default:
4396 *val = ASM330LHHX_FF_TSH_156mg;
4397 break;
4398 }
4399 return ret;
4400 }
4401
4402 /**
4403 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
4404 *
4405 * @param ctx Read / write interface definitions.(ptr)
4406 * @param val Change the values of ff_dur in reg FREE_FALL
4407 * @retval Interface status (MANDATORY: return 0 -> no Error).
4408 *
4409 */
asm330lhhx_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4410 int32_t asm330lhhx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4411 {
4412 asm330lhhx_wake_up_dur_t wake_up_dur;
4413 asm330lhhx_free_fall_t free_fall;
4414 int32_t ret;
4415
4416 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4417 (uint8_t *)&wake_up_dur, 1);
4418 if (ret == 0)
4419 {
4420 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4421 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4422 (uint8_t *)&wake_up_dur, 1);
4423 }
4424 if (ret == 0)
4425 {
4426 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL,
4427 (uint8_t *)&free_fall, 1);
4428 }
4429 if (ret == 0)
4430 {
4431 free_fall.ff_dur = val & 0x1FU;
4432 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FREE_FALL,
4433 (uint8_t *)&free_fall, 1);
4434 }
4435 return ret;
4436 }
4437
4438 /**
4439 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
4440 *
4441 * @param ctx Read / write interface definitions.(ptr)
4442 * @param val Change the values of ff_dur in reg FREE_FALL
4443 * @retval Interface status (MANDATORY: return 0 -> no Error).
4444 *
4445 */
asm330lhhx_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4446 int32_t asm330lhhx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4447 {
4448 asm330lhhx_wake_up_dur_t wake_up_dur;
4449 asm330lhhx_free_fall_t free_fall;
4450 int32_t ret;
4451
4452 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_WAKE_UP_DUR,
4453 (uint8_t *)&wake_up_dur, 1);
4454
4455 if (ret == 0)
4456 {
4457 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FREE_FALL,
4458 (uint8_t *)&free_fall, 1);
4459 }
4460 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4461
4462 return ret;
4463 }
4464
4465 /**
4466 * @}
4467 *
4468 */
4469
4470 /**
4471 * @defgroup ASM330LHHX_fifo
4472 * @brief This section group all the functions concerning
4473 * the fifo usage
4474 * @{
4475 *
4476 */
4477
4478 /**
4479 * @brief FIFO watermark level selection.[set]
4480 *
4481 * @param ctx Read / write interface definitions.(ptr)
4482 * @param val Change the values of wtm in reg FIFO_CTRL1
4483 * @retval Interface status (MANDATORY: return 0 -> no Error).
4484 *
4485 */
asm330lhhx_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)4486 int32_t asm330lhhx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
4487 {
4488 asm330lhhx_fifo_ctrl1_t fifo_ctrl1;
4489 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4490 int32_t ret;
4491
4492 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4493 ret += asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4494
4495 if (ret == 0)
4496 {
4497 fifo_ctrl1.wtm = (uint8_t)(val & 0xFFU);
4498 fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
4499 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4500 ret += asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4501 }
4502
4503 return ret;
4504 }
4505
4506 /**
4507 * @brief FIFO watermark level selection.[get]
4508 *
4509 * @param ctx Read / write interface definitions.(ptr)
4510 * @param val Change the values of wtm in reg FIFO_CTRL1
4511 * @retval Interface status (MANDATORY: return 0 -> no Error).
4512 *
4513 */
asm330lhhx_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)4514 int32_t asm330lhhx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
4515 {
4516 asm330lhhx_fifo_ctrl1_t fifo_ctrl1;
4517 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4518 int32_t ret;
4519
4520 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4521 (uint8_t *)&fifo_ctrl2, 1);
4522 if (ret == 0)
4523 {
4524 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL1,
4525 (uint8_t *)&fifo_ctrl1, 1);
4526 }
4527 *val = fifo_ctrl2.wtm;
4528 *val = (*val * 256U) + fifo_ctrl1.wtm;
4529 return ret;
4530 }
4531
4532 /**
4533 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4534 *
4535 * @param ctx Read / write interface definitions.(ptr)
4536 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4537 * @retval Interface status (MANDATORY: return 0 -> no Error).
4538 *
4539 */
asm330lhhx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4540 int32_t asm330lhhx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4541 uint8_t val)
4542 {
4543 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4544 int32_t ret;
4545
4546 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4547 (uint8_t *)&fifo_ctrl2, 1);
4548 if (ret == 0)
4549 {
4550 fifo_ctrl2.odrchg_en = (uint8_t)val;
4551 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4552 (uint8_t *)&fifo_ctrl2, 1);
4553 }
4554
4555 return ret;
4556 }
4557
4558 /**
4559 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4560 *
4561 * @param ctx Read / write interface definitions.(ptr)
4562 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4563 * @retval Interface status (MANDATORY: return 0 -> no Error).
4564 *
4565 */
asm330lhhx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4566 int32_t asm330lhhx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4567 uint8_t *val)
4568 {
4569 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4570 int32_t ret;
4571
4572 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4573 (uint8_t *)&fifo_ctrl2, 1);
4574 *val = fifo_ctrl2.odrchg_en;
4575
4576 return ret;
4577 }
4578
4579 /**
4580 * @brief Sensing chain FIFO stop values memorization at threshold
4581 * level.[set]
4582 *
4583 * @param ctx Read / write interface definitions.(ptr)
4584 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4585 * @retval Interface status (MANDATORY: return 0 -> no Error).
4586 *
4587 */
asm330lhhx_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4588 int32_t asm330lhhx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4589 {
4590 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4591 int32_t ret;
4592
4593 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4594 (uint8_t *)&fifo_ctrl2, 1);
4595 if (ret == 0)
4596 {
4597 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
4598 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4599 (uint8_t *)&fifo_ctrl2, 1);
4600 }
4601 return ret;
4602 }
4603
4604 /**
4605 * @brief Sensing chain FIFO stop values memorization at threshold
4606 * level.[get]
4607 *
4608 * @param ctx Read / write interface definitions.(ptr)
4609 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4610 * @retval Interface status (MANDATORY: return 0 -> no Error).
4611 *
4612 */
asm330lhhx_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)4613 int32_t asm330lhhx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4614 {
4615 asm330lhhx_fifo_ctrl2_t fifo_ctrl2;
4616 int32_t ret;
4617
4618 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL2,
4619 (uint8_t *)&fifo_ctrl2, 1);
4620 *val = fifo_ctrl2.stop_on_wtm;
4621
4622 return ret;
4623 }
4624
4625 /**
4626 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4627 * for accelerometer data.[set]
4628 *
4629 * @param ctx Read / write interface definitions.(ptr)
4630 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
4631 * @retval Interface status (MANDATORY: return 0 -> no Error).
4632 *
4633 */
asm330lhhx_fifo_xl_batch_set(const stmdev_ctx_t * ctx,asm330lhhx_bdr_xl_t val)4634 int32_t asm330lhhx_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
4635 asm330lhhx_bdr_xl_t val)
4636 {
4637 asm330lhhx_fifo_ctrl3_t fifo_ctrl3;
4638 int32_t ret;
4639
4640 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4641 (uint8_t *)&fifo_ctrl3, 1);
4642 if (ret == 0)
4643 {
4644 fifo_ctrl3.bdr_xl = (uint8_t)val;
4645 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4646 (uint8_t *)&fifo_ctrl3, 1);
4647 }
4648 return ret;
4649 }
4650
4651 /**
4652 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4653 * for accelerometer data.[get]
4654 *
4655 * @param ctx Read / write interface definitions.(ptr)
4656 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
4657 * @retval Interface status (MANDATORY: return 0 -> no Error).
4658 *
4659 */
asm330lhhx_fifo_xl_batch_get(const stmdev_ctx_t * ctx,asm330lhhx_bdr_xl_t * val)4660 int32_t asm330lhhx_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
4661 asm330lhhx_bdr_xl_t *val)
4662 {
4663 asm330lhhx_fifo_ctrl3_t fifo_ctrl3;
4664 int32_t ret;
4665
4666 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4667 (uint8_t *)&fifo_ctrl3, 1);
4668
4669 switch (fifo_ctrl3.bdr_xl)
4670 {
4671 case ASM330LHHX_XL_NOT_BATCHED:
4672 *val = ASM330LHHX_XL_NOT_BATCHED;
4673 break;
4674 case ASM330LHHX_XL_BATCHED_AT_12Hz5:
4675 *val = ASM330LHHX_XL_BATCHED_AT_12Hz5;
4676 break;
4677 case ASM330LHHX_XL_BATCHED_AT_26Hz:
4678 *val = ASM330LHHX_XL_BATCHED_AT_26Hz;
4679 break;
4680 case ASM330LHHX_XL_BATCHED_AT_52Hz:
4681 *val = ASM330LHHX_XL_BATCHED_AT_52Hz;
4682 break;
4683 case ASM330LHHX_XL_BATCHED_AT_104Hz:
4684 *val = ASM330LHHX_XL_BATCHED_AT_104Hz;
4685 break;
4686 case ASM330LHHX_XL_BATCHED_AT_208Hz:
4687 *val = ASM330LHHX_XL_BATCHED_AT_208Hz;
4688 break;
4689 case ASM330LHHX_XL_BATCHED_AT_417Hz:
4690 *val = ASM330LHHX_XL_BATCHED_AT_417Hz;
4691 break;
4692 case ASM330LHHX_XL_BATCHED_AT_833Hz:
4693 *val = ASM330LHHX_XL_BATCHED_AT_833Hz;
4694 break;
4695 case ASM330LHHX_XL_BATCHED_AT_1667Hz:
4696 *val = ASM330LHHX_XL_BATCHED_AT_1667Hz;
4697 break;
4698 case ASM330LHHX_XL_BATCHED_AT_3333Hz:
4699 *val = ASM330LHHX_XL_BATCHED_AT_3333Hz;
4700 break;
4701 case ASM330LHHX_XL_BATCHED_AT_6667Hz:
4702 *val = ASM330LHHX_XL_BATCHED_AT_6667Hz;
4703 break;
4704 case ASM330LHHX_XL_BATCHED_AT_1Hz6:
4705 *val = ASM330LHHX_XL_BATCHED_AT_1Hz6;
4706 break;
4707 default:
4708 *val = ASM330LHHX_XL_NOT_BATCHED;
4709 break;
4710 }
4711 return ret;
4712 }
4713
4714 /**
4715 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4716 * for gyroscope data.[set]
4717 *
4718 * @param ctx Read / write interface definitions.(ptr)
4719 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
4720 * @retval Interface status (MANDATORY: return 0 -> no Error).
4721 *
4722 */
asm330lhhx_fifo_gy_batch_set(const stmdev_ctx_t * ctx,asm330lhhx_bdr_gy_t val)4723 int32_t asm330lhhx_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
4724 asm330lhhx_bdr_gy_t val)
4725 {
4726 asm330lhhx_fifo_ctrl3_t fifo_ctrl3;
4727 int32_t ret;
4728
4729 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4730 (uint8_t *)&fifo_ctrl3, 1);
4731 if (ret == 0)
4732 {
4733 fifo_ctrl3.bdr_gy = (uint8_t)val;
4734 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4735 (uint8_t *)&fifo_ctrl3, 1);
4736 }
4737 return ret;
4738 }
4739
4740 /**
4741 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4742 * for gyroscope data.[get]
4743 *
4744 * @param ctx Read / write interface definitions.(ptr)
4745 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
4746 * @retval Interface status (MANDATORY: return 0 -> no Error).
4747 *
4748 */
asm330lhhx_fifo_gy_batch_get(const stmdev_ctx_t * ctx,asm330lhhx_bdr_gy_t * val)4749 int32_t asm330lhhx_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
4750 asm330lhhx_bdr_gy_t *val)
4751 {
4752 asm330lhhx_fifo_ctrl3_t fifo_ctrl3;
4753 int32_t ret;
4754
4755 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL3,
4756 (uint8_t *)&fifo_ctrl3, 1);
4757
4758 switch (fifo_ctrl3.bdr_gy)
4759 {
4760 case ASM330LHHX_GY_NOT_BATCHED:
4761 *val = ASM330LHHX_GY_NOT_BATCHED;
4762 break;
4763 case ASM330LHHX_GY_BATCHED_AT_12Hz5:
4764 *val = ASM330LHHX_GY_BATCHED_AT_12Hz5;
4765 break;
4766 case ASM330LHHX_GY_BATCHED_AT_26Hz:
4767 *val = ASM330LHHX_GY_BATCHED_AT_26Hz;
4768 break;
4769 case ASM330LHHX_GY_BATCHED_AT_52Hz:
4770 *val = ASM330LHHX_GY_BATCHED_AT_52Hz;
4771 break;
4772 case ASM330LHHX_GY_BATCHED_AT_104Hz:
4773 *val = ASM330LHHX_GY_BATCHED_AT_104Hz;
4774 break;
4775 case ASM330LHHX_GY_BATCHED_AT_208Hz:
4776 *val = ASM330LHHX_GY_BATCHED_AT_208Hz;
4777 break;
4778 case ASM330LHHX_GY_BATCHED_AT_417Hz:
4779 *val = ASM330LHHX_GY_BATCHED_AT_417Hz;
4780 break;
4781 case ASM330LHHX_GY_BATCHED_AT_833Hz:
4782 *val = ASM330LHHX_GY_BATCHED_AT_833Hz;
4783 break;
4784 case ASM330LHHX_GY_BATCHED_AT_1667Hz:
4785 *val = ASM330LHHX_GY_BATCHED_AT_1667Hz;
4786 break;
4787 case ASM330LHHX_GY_BATCHED_AT_3333Hz:
4788 *val = ASM330LHHX_GY_BATCHED_AT_3333Hz;
4789 break;
4790 case ASM330LHHX_GY_BATCHED_AT_6667Hz:
4791 *val = ASM330LHHX_GY_BATCHED_AT_6667Hz;
4792 break;
4793 case ASM330LHHX_GY_BATCHED_AT_6Hz5:
4794 *val = ASM330LHHX_GY_BATCHED_AT_6Hz5;
4795 break;
4796 default:
4797 *val = ASM330LHHX_GY_NOT_BATCHED;
4798 break;
4799 }
4800 return ret;
4801 }
4802
4803 /**
4804 * @brief FIFO mode selection.[set]
4805 *
4806 * @param ctx Read / write interface definitions.(ptr)
4807 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
4808 * @retval Interface status (MANDATORY: return 0 -> no Error).
4809 *
4810 */
asm330lhhx_fifo_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_fifo_mode_t val)4811 int32_t asm330lhhx_fifo_mode_set(const stmdev_ctx_t *ctx,
4812 asm330lhhx_fifo_mode_t val)
4813 {
4814 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4815 int32_t ret;
4816
4817 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4818 (uint8_t *)&fifo_ctrl4, 1);
4819 if (ret == 0)
4820 {
4821 fifo_ctrl4.fifo_mode = (uint8_t)val;
4822 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4823 (uint8_t *)&fifo_ctrl4, 1);
4824 }
4825 return ret;
4826 }
4827
4828 /**
4829 * @brief FIFO mode selection.[get]
4830 *
4831 * @param ctx Read / write interface definitions.(ptr)
4832 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
4833 * @retval Interface status (MANDATORY: return 0 -> no Error).
4834 *
4835 */
asm330lhhx_fifo_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_fifo_mode_t * val)4836 int32_t asm330lhhx_fifo_mode_get(const stmdev_ctx_t *ctx,
4837 asm330lhhx_fifo_mode_t *val)
4838 {
4839 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4840 int32_t ret;
4841
4842 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4843 (uint8_t *)&fifo_ctrl4, 1);
4844
4845 switch (fifo_ctrl4.fifo_mode)
4846 {
4847 case ASM330LHHX_BYPASS_MODE:
4848 *val = ASM330LHHX_BYPASS_MODE;
4849 break;
4850 case ASM330LHHX_FIFO_MODE:
4851 *val = ASM330LHHX_FIFO_MODE;
4852 break;
4853 case ASM330LHHX_STREAM_TO_FIFO_MODE:
4854 *val = ASM330LHHX_STREAM_TO_FIFO_MODE;
4855 break;
4856 case ASM330LHHX_BYPASS_TO_STREAM_MODE:
4857 *val = ASM330LHHX_BYPASS_TO_STREAM_MODE;
4858 break;
4859 case ASM330LHHX_STREAM_MODE:
4860 *val = ASM330LHHX_STREAM_MODE;
4861 break;
4862 case ASM330LHHX_BYPASS_TO_FIFO_MODE:
4863 *val = ASM330LHHX_BYPASS_TO_FIFO_MODE;
4864 break;
4865 default:
4866 *val = ASM330LHHX_BYPASS_MODE;
4867 break;
4868 }
4869 return ret;
4870 }
4871
4872 /**
4873 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4874 * for temperature data.[set]
4875 *
4876 * @param ctx Read / write interface definitions.(ptr)
4877 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
4878 * @retval Interface status (MANDATORY: return 0 -> no Error).
4879 *
4880 */
asm330lhhx_fifo_temp_batch_set(const stmdev_ctx_t * ctx,asm330lhhx_odr_t_batch_t val)4881 int32_t asm330lhhx_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4882 asm330lhhx_odr_t_batch_t val)
4883 {
4884 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4885 int32_t ret;
4886
4887 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4888 (uint8_t *)&fifo_ctrl4, 1);
4889 if (ret == 0)
4890 {
4891 fifo_ctrl4.odr_t_batch = (uint8_t)val;
4892 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4893 (uint8_t *)&fifo_ctrl4, 1);
4894 }
4895 return ret;
4896 }
4897
4898 /**
4899 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4900 * for temperature data.[get]
4901 *
4902 * @param ctx Read / write interface definitions.(ptr)
4903 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
4904 * @retval Interface status (MANDATORY: return 0 -> no Error).
4905 *
4906 */
asm330lhhx_fifo_temp_batch_get(const stmdev_ctx_t * ctx,asm330lhhx_odr_t_batch_t * val)4907 int32_t asm330lhhx_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4908 asm330lhhx_odr_t_batch_t *val)
4909 {
4910 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4911 int32_t ret;
4912
4913 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4914 (uint8_t *)&fifo_ctrl4, 1);
4915
4916 switch (fifo_ctrl4.odr_t_batch)
4917 {
4918 case ASM330LHHX_TEMP_NOT_BATCHED:
4919 *val = ASM330LHHX_TEMP_NOT_BATCHED;
4920 break;
4921 case ASM330LHHX_TEMP_BATCHED_AT_52Hz:
4922 *val = ASM330LHHX_TEMP_BATCHED_AT_52Hz;
4923 break;
4924 case ASM330LHHX_TEMP_BATCHED_AT_12Hz5:
4925 *val = ASM330LHHX_TEMP_BATCHED_AT_12Hz5;
4926 break;
4927 case ASM330LHHX_TEMP_BATCHED_AT_1Hz6:
4928 *val = ASM330LHHX_TEMP_BATCHED_AT_1Hz6;
4929 break;
4930 default:
4931 *val = ASM330LHHX_TEMP_NOT_BATCHED;
4932 break;
4933 }
4934 return ret;
4935 }
4936
4937 /**
4938 * @brief Selects decimation for timestamp batching in FIFO.
4939 * Writing rate will be the maximum rate between XL and
4940 * GYRO BDR divided by decimation decoder.[set]
4941 *
4942 * @param ctx Read / write interface definitions.(ptr)
4943 * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4
4944 * @retval Interface status (MANDATORY: return 0 -> no Error).
4945 *
4946 */
asm330lhhx_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,asm330lhhx_dec_ts_batch_t val)4947 int32_t asm330lhhx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
4948 asm330lhhx_dec_ts_batch_t val)
4949 {
4950 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4951 int32_t ret;
4952
4953 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4954 (uint8_t *)&fifo_ctrl4, 1);
4955 if (ret == 0)
4956 {
4957 fifo_ctrl4.dec_ts_batch = (uint8_t)val;
4958 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4959 (uint8_t *)&fifo_ctrl4, 1);
4960 }
4961 return ret;
4962 }
4963
4964 /**
4965 * @brief Selects decimation for timestamp batching in FIFO.
4966 * Writing rate will be the maximum rate between XL and
4967 * GYRO BDR divided by decimation decoder.[get]
4968 *
4969 * @param ctx Read / write interface definitions.(ptr)
4970 * @param val Get the values of dec_ts_batch in reg
4971 * FIFO_CTRL4
4972 * @retval Interface status (MANDATORY: return 0 -> no Error).
4973 *
4974 */
asm330lhhx_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,asm330lhhx_dec_ts_batch_t * val)4975 int32_t asm330lhhx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
4976 asm330lhhx_dec_ts_batch_t *val)
4977 {
4978 asm330lhhx_fifo_ctrl4_t fifo_ctrl4;
4979 int32_t ret;
4980
4981 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_CTRL4,
4982 (uint8_t *)&fifo_ctrl4, 1);
4983
4984 switch (fifo_ctrl4.dec_ts_batch)
4985 {
4986 case ASM330LHHX_NO_DECIMATION:
4987 *val = ASM330LHHX_NO_DECIMATION;
4988 break;
4989 case ASM330LHHX_DEC_1:
4990 *val = ASM330LHHX_DEC_1;
4991 break;
4992 case ASM330LHHX_DEC_8:
4993 *val = ASM330LHHX_DEC_8;
4994 break;
4995 case ASM330LHHX_DEC_32:
4996 *val = ASM330LHHX_DEC_32;
4997 break;
4998 default:
4999 *val = ASM330LHHX_NO_DECIMATION;
5000 break;
5001 }
5002 return ret;
5003 }
5004
5005 /**
5006 * @brief Selects the trigger for the internal counter of batching events
5007 * between XL and gyro.[set]
5008 *
5009 * @param ctx Read / write interface definitions.(ptr)
5010 * @param val Change the values of trig_counter_bdr in
5011 * reg COUNTER_BDR_REG1
5012 * @retval Interface status (MANDATORY: return 0 -> no Error).
5013 *
5014 */
asm330lhhx_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,asm330lhhx_trig_counter_bdr_t val)5015 int32_t asm330lhhx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
5016 asm330lhhx_trig_counter_bdr_t val)
5017 {
5018 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
5019 int32_t ret;
5020
5021 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5022 (uint8_t *)&counter_bdr_reg1, 1);
5023 if (ret == 0)
5024 {
5025 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
5026 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5027 (uint8_t *)&counter_bdr_reg1, 1);
5028 }
5029 return ret;
5030 }
5031
5032 /**
5033 * @brief Selects the trigger for the internal counter of batching events
5034 * between XL and gyro.[get]
5035 *
5036 * @param ctx Read / write interface definitions.(ptr)
5037 * @param val Get the values of trig_counter_bdr
5038 * in reg COUNTER_BDR_REG1
5039 * @retval Interface status (MANDATORY: return 0 -> no Error).
5040 *
5041 */
asm330lhhx_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,asm330lhhx_trig_counter_bdr_t * val)5042 int32_t asm330lhhx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
5043 asm330lhhx_trig_counter_bdr_t *val)
5044 {
5045 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
5046 int32_t ret;
5047
5048 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5049 (uint8_t *)&counter_bdr_reg1, 1);
5050
5051 switch (counter_bdr_reg1.trig_counter_bdr)
5052 {
5053 case ASM330LHHX_XL_BATCH_EVENT:
5054 *val = ASM330LHHX_XL_BATCH_EVENT;
5055 break;
5056 case ASM330LHHX_GYRO_BATCH_EVENT:
5057 *val = ASM330LHHX_GYRO_BATCH_EVENT;
5058 break;
5059 default:
5060 *val = ASM330LHHX_XL_BATCH_EVENT;
5061 break;
5062 }
5063 return ret;
5064 }
5065
5066 /**
5067 * @brief Resets the internal counter of batching events for a single sensor.
5068 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5069 *
5070 * @param ctx Read / write interface definitions.(ptr)
5071 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5072 * @retval Interface status (MANDATORY: return 0 -> no Error).
5073 *
5074 */
asm330lhhx_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)5075 int32_t asm330lhhx_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val)
5076 {
5077 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
5078 int32_t ret;
5079
5080 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5081 (uint8_t *)&counter_bdr_reg1, 1);
5082 if (ret == 0)
5083 {
5084 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
5085 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5086 (uint8_t *)&counter_bdr_reg1, 1);
5087 }
5088 return ret;
5089 }
5090
5091 /**
5092 * @brief Resets the internal counter of batching events for a single sensor.
5093 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5094 *
5095 * @param ctx Read / write interface definitions.(ptr)
5096 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5097 * @retval Interface status (MANDATORY: return 0 -> no Error).
5098 *
5099 */
asm330lhhx_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)5100 int32_t asm330lhhx_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val)
5101 {
5102 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
5103 int32_t ret;
5104
5105 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5106 (uint8_t *)&counter_bdr_reg1, 1);
5107 *val = counter_bdr_reg1.rst_counter_bdr;
5108
5109 return ret;
5110 }
5111
5112 /**
5113 * @brief Batch data rate counter.[set]
5114 *
5115 * @param ctx Read / write interface definitions.(ptr)
5116 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5117 * and COUNTER_BDR_REG1.
5118 * @retval Interface status (MANDATORY: return 0 -> no Error).
5119 *
5120 */
asm330lhhx_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5121 int32_t asm330lhhx_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
5122 {
5123 asm330lhhx_counter_bdr_reg2_t counter_bdr_reg1;
5124 asm330lhhx_counter_bdr_reg2_t counter_bdr_reg2;
5125 int32_t ret;
5126
5127 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5128 (uint8_t *)&counter_bdr_reg1, 1);
5129 if (ret == 0)
5130 {
5131 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
5132 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5133 (uint8_t *)&counter_bdr_reg1, 1);
5134 }
5135 if (ret == 0)
5136 {
5137 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
5138 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_COUNTER_BDR_REG2,
5139 (uint8_t *)&counter_bdr_reg2, 1);
5140 }
5141 return ret;
5142 }
5143
5144 /**
5145 * @brief Batch data rate counter.[get]
5146 *
5147 * @param ctx Read / write interface definitions.(ptr)
5148 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5149 * and COUNTER_BDR_REG1.
5150 * @retval Interface status (MANDATORY: return 0 -> no Error).
5151 *
5152 */
asm330lhhx_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5153 int32_t asm330lhhx_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5154 uint16_t *val)
5155 {
5156 asm330lhhx_counter_bdr_reg1_t counter_bdr_reg1;
5157 asm330lhhx_counter_bdr_reg2_t counter_bdr_reg2;
5158 int32_t ret;
5159
5160 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG1,
5161 (uint8_t *)&counter_bdr_reg1, 1);
5162 if (ret == 0)
5163 {
5164 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_COUNTER_BDR_REG2,
5165 (uint8_t *)&counter_bdr_reg2, 1);
5166 }
5167
5168 *val = counter_bdr_reg1.cnt_bdr_th;
5169 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
5170 return ret;
5171 }
5172
5173 /**
5174 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
5175 *
5176 * @param ctx Read / write interface definitions.(ptr)
5177 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
5178 * @retval Interface status (MANDATORY: return 0 -> no Error).
5179 *
5180 */
asm330lhhx_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5181 int32_t asm330lhhx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
5182 {
5183 uint8_t reg[2];
5184 asm330lhhx_fifo_status1_t *fifo_status1 = (asm330lhhx_fifo_status1_t *)®[0];
5185 asm330lhhx_fifo_status2_t *fifo_status2 = (asm330lhhx_fifo_status2_t *)®[1];
5186 int32_t ret;
5187
5188 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5189 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_STATUS1, (uint8_t *)reg, 2);
5190 if (ret == 0)
5191 {
5192 *val = fifo_status2->diff_fifo;
5193 *val = (*val * 256U) + fifo_status1->diff_fifo;
5194 }
5195
5196 return ret;
5197 }
5198
5199 /**
5200 * @brief Smart FIFO status.[get]
5201 *
5202 * @param ctx Read / write interface definitions.(ptr)
5203 * @param val Read registers FIFO_STATUS2
5204 * @retval Interface status (MANDATORY: return 0 -> no Error).
5205 *
5206 */
asm330lhhx_fifo_status_get(const stmdev_ctx_t * ctx,asm330lhhx_fifo_status2_t * val)5207 int32_t asm330lhhx_fifo_status_get(const stmdev_ctx_t *ctx,
5208 asm330lhhx_fifo_status2_t *val)
5209 {
5210 uint8_t reg[2];
5211 asm330lhhx_fifo_status2_t *fifo_status2 = (asm330lhhx_fifo_status2_t *)®[1];
5212 int32_t ret;
5213
5214 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5215 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_STATUS1, (uint8_t *)reg, 2);
5216 if (ret == 0)
5217 {
5218 *val = *fifo_status2;
5219 }
5220
5221 return ret;
5222 }
5223
5224 /**
5225 * @brief Smart FIFO full status.[get]
5226 *
5227 * @param ctx Read / write interface definitions.(ptr)
5228 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
5229 * @retval Interface status (MANDATORY: return 0 -> no Error).
5230 *
5231 */
asm330lhhx_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5232 int32_t asm330lhhx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5233 {
5234 uint8_t reg[2];
5235 asm330lhhx_fifo_status2_t *fifo_status2 = (asm330lhhx_fifo_status2_t *)®[1];
5236 int32_t ret;
5237
5238 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5239 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_STATUS1, (uint8_t *)reg, 2);
5240 if (ret == 0)
5241 {
5242 *val = fifo_status2->fifo_full_ia;
5243 }
5244
5245 return ret;
5246 }
5247
5248 /**
5249 * @brief FIFO overrun status.[get]
5250 *
5251 * @param ctx Read / write interface definitions.(ptr)
5252 * @param val Read the values of fifo_over_run_latched in
5253 * reg FIFO_STATUS2
5254 * @retval Interface status (MANDATORY: return 0 -> no Error).
5255 *
5256 */
asm330lhhx_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5257 int32_t asm330lhhx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5258 {
5259 uint8_t reg[2];
5260 asm330lhhx_fifo_status2_t *fifo_status2 = (asm330lhhx_fifo_status2_t *)®[1];
5261 int32_t ret;
5262
5263 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5264 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_STATUS1, (uint8_t *)reg, 2);
5265 if (ret == 0)
5266 {
5267 *val = fifo_status2->fifo_ovr_ia;
5268 }
5269
5270 return ret;
5271 }
5272
5273 /**
5274 * @brief FIFO watermark status.[get]
5275 *
5276 * @param ctx Read / write interface definitions.(ptr)
5277 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
5278 * @retval Interface status (MANDATORY: return 0 -> no Error).
5279 *
5280 */
asm330lhhx_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5281 int32_t asm330lhhx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5282 {
5283 uint8_t reg[2];
5284 asm330lhhx_fifo_status2_t *fifo_status2 = (asm330lhhx_fifo_status2_t *)®[1];
5285 int32_t ret;
5286
5287 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5288 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_STATUS1, (uint8_t *)reg, 2);
5289 if (ret == 0)
5290 {
5291 *val = fifo_status2->fifo_wtm_ia;
5292 }
5293
5294 return ret;
5295 }
5296
5297 /**
5298 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
5299 *
5300 * @param ctx Read / write interface definitions.(ptr)
5301 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
5302 * @retval Interface status (MANDATORY: return 0 -> no Error).
5303 *
5304 */
asm330lhhx_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,asm330lhhx_fifo_tag_t * val)5305 int32_t asm330lhhx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
5306 asm330lhhx_fifo_tag_t *val)
5307 {
5308 asm330lhhx_fifo_data_out_tag_t fifo_data_out_tag;
5309 int32_t ret;
5310
5311 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FIFO_DATA_OUT_TAG,
5312 (uint8_t *)&fifo_data_out_tag, 1);
5313
5314 switch (fifo_data_out_tag.tag_sensor)
5315 {
5316 case ASM330LHHX_GYRO_NC_TAG:
5317 *val = ASM330LHHX_GYRO_NC_TAG;
5318 break;
5319 case ASM330LHHX_XL_NC_TAG:
5320 *val = ASM330LHHX_XL_NC_TAG;
5321 break;
5322 case ASM330LHHX_TEMPERATURE_TAG:
5323 *val = ASM330LHHX_TEMPERATURE_TAG;
5324 break;
5325 case ASM330LHHX_TIMESTAMP_TAG:
5326 *val = ASM330LHHX_TIMESTAMP_TAG;
5327 break;
5328 case ASM330LHHX_CFG_CHANGE_TAG:
5329 *val = ASM330LHHX_CFG_CHANGE_TAG;
5330 break;
5331 case ASM330LHHX_SENSORHUB_SLAVE0_TAG:
5332 *val = ASM330LHHX_SENSORHUB_SLAVE0_TAG;
5333 break;
5334 case ASM330LHHX_SENSORHUB_SLAVE1_TAG:
5335 *val = ASM330LHHX_SENSORHUB_SLAVE1_TAG;
5336 break;
5337 case ASM330LHHX_SENSORHUB_SLAVE2_TAG:
5338 *val = ASM330LHHX_SENSORHUB_SLAVE2_TAG;
5339 break;
5340 case ASM330LHHX_SENSORHUB_SLAVE3_TAG:
5341 *val = ASM330LHHX_SENSORHUB_SLAVE3_TAG;
5342 break;
5343 case ASM330LHHX_SENSORHUB_NACK_TAG:
5344 *val = ASM330LHHX_SENSORHUB_NACK_TAG;
5345 break;
5346 default:
5347 *val = ASM330LHHX_XL_NC_TAG;
5348 break;
5349 }
5350 return ret;
5351 }
5352
5353 /**
5354 * @brief Enable FIFO batching data of first slave.[set]
5355 *
5356 * @param ctx Read / write interface definitions.(ptr)
5357 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
5358 * @retval Interface status (MANDATORY: return 0 -> no Error).
5359 *
5360 */
asm330lhhx_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)5361 int32_t asm330lhhx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val)
5362 {
5363 asm330lhhx_slv0_config_t slv0_config;
5364 int32_t ret;
5365
5366 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5367
5368 if (ret == 0)
5369 {
5370 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG,
5371 (uint8_t *)&slv0_config, 1);
5372 }
5373 if (ret == 0)
5374 {
5375 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
5376 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG,
5377 (uint8_t *)&slv0_config, 1);
5378 }
5379 if (ret == 0)
5380 {
5381 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5382 }
5383 return ret;
5384 }
5385
5386 /**
5387 * @brief Enable FIFO batching data of first slave.[get]
5388 *
5389 * @param ctx Read / write interface definitions.(ptr)
5390 * @param val Change the values of batch_ext_sens_0_en in
5391 * reg SLV0_CONFIG
5392 * @retval Interface status (MANDATORY: return 0 -> no Error).
5393 *
5394 */
asm330lhhx_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)5395 int32_t asm330lhhx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val)
5396 {
5397 asm330lhhx_slv0_config_t slv0_config;
5398 int32_t ret;
5399
5400 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5401
5402 if (ret == 0)
5403 {
5404 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG,
5405 (uint8_t *)&slv0_config, 1);
5406 }
5407 if (ret == 0)
5408 {
5409 *val = slv0_config. batch_ext_sens_0_en;
5410 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5411 }
5412 return ret;
5413 }
5414
5415 /**
5416 * @brief Enable FIFO batching data of second slave.[set]
5417 *
5418 * @param ctx Read / write interface definitions.(ptr)
5419 * @param val Change the values of batch_ext_sens_1_en in
5420 * reg SLV1_CONFIG
5421 * @retval Interface status (MANDATORY: return 0 -> no Error).
5422 *
5423 */
asm330lhhx_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)5424 int32_t asm330lhhx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val)
5425 {
5426 asm330lhhx_slv1_config_t slv1_config;
5427 int32_t ret;
5428
5429 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5430 if (ret == 0)
5431 {
5432 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV1_CONFIG,
5433 (uint8_t *)&slv1_config, 1);
5434 }
5435 if (ret == 0)
5436 {
5437 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
5438 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_CONFIG,
5439 (uint8_t *)&slv1_config, 1);
5440 }
5441 if (ret == 0)
5442 {
5443 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5444 }
5445 return ret;
5446 }
5447
5448 /**
5449 * @brief Enable FIFO batching data of second slave.[get]
5450 *
5451 * @param ctx Read / write interface definitions.(ptr)
5452 * @param val Change the values of batch_ext_sens_1_en in
5453 * reg SLV1_CONFIG
5454 * @retval Interface status (MANDATORY: return 0 -> no Error).
5455 *
5456 */
asm330lhhx_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)5457 int32_t asm330lhhx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5458 {
5459 asm330lhhx_slv1_config_t slv1_config;
5460 int32_t ret;
5461
5462 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5463
5464 if (ret == 0)
5465 {
5466 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV1_CONFIG,
5467 (uint8_t *)&slv1_config, 1);
5468 *val = slv1_config. batch_ext_sens_1_en;
5469 }
5470 if (ret == 0)
5471 {
5472 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5473 }
5474 return ret;
5475 }
5476
5477 /**
5478 * @brief Enable FIFO batching data of third slave.[set]
5479 *
5480 * @param ctx Read / write interface definitions.(ptr)
5481 * @param val Change the values of batch_ext_sens_2_en in
5482 * reg SLV2_CONFIG
5483 * @retval Interface status (MANDATORY: return 0 -> no Error).
5484 *
5485 */
asm330lhhx_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)5486 int32_t asm330lhhx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val)
5487 {
5488 asm330lhhx_slv2_config_t slv2_config;
5489 int32_t ret;
5490
5491 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5492
5493 if (ret == 0)
5494 {
5495 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV2_CONFIG,
5496 (uint8_t *)&slv2_config, 1);
5497 }
5498 if (ret == 0)
5499 {
5500 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
5501 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_CONFIG,
5502 (uint8_t *)&slv2_config, 1);
5503 }
5504 if (ret == 0)
5505 {
5506 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5507 }
5508 return ret;
5509 }
5510
5511 /**
5512 * @brief Enable FIFO batching data of third slave.[get]
5513 *
5514 * @param ctx Read / write interface definitions.(ptr)
5515 * @param val Change the values of batch_ext_sens_2_en in
5516 * reg SLV2_CONFIG
5517 * @retval Interface status (MANDATORY: return 0 -> no Error).
5518 *
5519 */
asm330lhhx_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)5520 int32_t asm330lhhx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val)
5521 {
5522 asm330lhhx_slv2_config_t slv2_config;
5523 int32_t ret;
5524
5525 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5526 if (ret == 0)
5527 {
5528 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV2_CONFIG,
5529 (uint8_t *)&slv2_config, 1);
5530 }
5531 if (ret == 0)
5532 {
5533 *val = slv2_config. batch_ext_sens_2_en;
5534 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5535 }
5536 return ret;
5537 }
5538
5539 /**
5540 * @brief Enable FIFO batching data of fourth slave.[set]
5541 *
5542 * @param ctx Read / write interface definitions.(ptr)
5543 * @param val Change the values of batch_ext_sens_3_en in
5544 * reg SLV3_CONFIG
5545 * @retval Interface status (MANDATORY: return 0 -> no Error).
5546 *
5547 */
asm330lhhx_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)5548 int32_t asm330lhhx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val)
5549 {
5550 asm330lhhx_slv3_config_t slv3_config;
5551 int32_t ret;
5552
5553 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5554 if (ret == 0)
5555 {
5556 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV3_CONFIG,
5557 (uint8_t *)&slv3_config, 1);
5558 }
5559 if (ret == 0)
5560 {
5561 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
5562 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_CONFIG,
5563 (uint8_t *)&slv3_config, 1);
5564 }
5565 if (ret == 0)
5566 {
5567 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5568 }
5569 return ret;
5570 }
5571
5572 /**
5573 * @brief Enable FIFO batching data of fourth slave.[get]
5574 *
5575 * @param ctx Read / write interface definitions.(ptr)
5576 * @param val Change the values of batch_ext_sens_3_en in
5577 * reg SLV3_CONFIG
5578 * @retval Interface status (MANDATORY: return 0 -> no Error).
5579 *
5580 */
asm330lhhx_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)5581 int32_t asm330lhhx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val)
5582 {
5583 asm330lhhx_slv3_config_t slv3_config;
5584 int32_t ret;
5585
5586 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
5587
5588 if (ret == 0)
5589 {
5590 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV3_CONFIG,
5591 (uint8_t *)&slv3_config, 1);
5592 *val = slv3_config. batch_ext_sens_3_en;
5593 }
5594 if (ret == 0)
5595 {
5596 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
5597 }
5598 return ret;
5599 }
5600
5601 /**
5602 * @}
5603 *
5604 */
5605
5606 /**
5607 * @defgroup ASM330LHHX_DEN_functionality
5608 * @brief This section groups all the functions concerning
5609 * DEN functionality.
5610 * @{
5611 *
5612 */
5613
5614 /**
5615 * @brief DEN functionality marking mode.[set]
5616 *
5617 * @param ctx Read / write interface definitions.(ptr)
5618 * @param val Change the values of den_mode in reg CTRL6_C
5619 * @retval Interface status (MANDATORY: return 0 -> no Error).
5620 *
5621 */
asm330lhhx_den_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_den_mode_t val)5622 int32_t asm330lhhx_den_mode_set(const stmdev_ctx_t *ctx, asm330lhhx_den_mode_t val)
5623 {
5624 asm330lhhx_ctrl6_c_t ctrl6_c;
5625 int32_t ret;
5626
5627 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5628 if (ret == 0)
5629 {
5630 ctrl6_c.den_mode = (uint8_t)val;
5631 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5632 }
5633 return ret;
5634 }
5635
5636 /**
5637 * @brief DEN functionality marking mode.[get]
5638 *
5639 * @param ctx Read / write interface definitions.(ptr)
5640 * @param val Get the values of den_mode in reg CTRL6_C
5641 * @retval Interface status (MANDATORY: return 0 -> no Error).
5642 *
5643 */
asm330lhhx_den_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_den_mode_t * val)5644 int32_t asm330lhhx_den_mode_get(const stmdev_ctx_t *ctx,
5645 asm330lhhx_den_mode_t *val)
5646 {
5647 asm330lhhx_ctrl6_c_t ctrl6_c;
5648 int32_t ret;
5649
5650 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5651
5652 switch (ctrl6_c.den_mode)
5653 {
5654 case ASM330LHHX_DEN_DISABLE:
5655 *val = ASM330LHHX_DEN_DISABLE;
5656 break;
5657 case ASM330LHHX_LEVEL_FIFO:
5658 *val = ASM330LHHX_LEVEL_FIFO;
5659 break;
5660 case ASM330LHHX_LEVEL_LETCHED:
5661 *val = ASM330LHHX_LEVEL_LETCHED;
5662 break;
5663 case ASM330LHHX_LEVEL_TRIGGER:
5664 *val = ASM330LHHX_LEVEL_TRIGGER;
5665 break;
5666 case ASM330LHHX_EDGE_TRIGGER:
5667 *val = ASM330LHHX_EDGE_TRIGGER;
5668 break;
5669 default:
5670 *val = ASM330LHHX_DEN_DISABLE;
5671 break;
5672 }
5673 return ret;
5674 }
5675
5676 /**
5677 * @brief DEN active level configuration.[set]
5678 *
5679 * @param ctx Read / write interface definitions.(ptr)
5680 * @param val Change the values of den_lh in reg CTRL9_XL
5681 * @retval Interface status (MANDATORY: return 0 -> no Error).
5682 *
5683 */
asm330lhhx_den_polarity_set(const stmdev_ctx_t * ctx,asm330lhhx_den_lh_t val)5684 int32_t asm330lhhx_den_polarity_set(const stmdev_ctx_t *ctx,
5685 asm330lhhx_den_lh_t val)
5686 {
5687 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5688 int32_t ret;
5689
5690 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5691 if (ret == 0)
5692 {
5693 ctrl9_xl.den_lh = (uint8_t)val;
5694 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL,
5695 (uint8_t *)&ctrl9_xl, 1);
5696 }
5697 return ret;
5698 }
5699
5700 /**
5701 * @brief DEN active level configuration.[get]
5702 *
5703 * @param ctx Read / write interface definitions.(ptr)
5704 * @param val Get the values of den_lh in reg CTRL9_XL
5705 * @retval Interface status (MANDATORY: return 0 -> no Error).
5706 *
5707 */
asm330lhhx_den_polarity_get(const stmdev_ctx_t * ctx,asm330lhhx_den_lh_t * val)5708 int32_t asm330lhhx_den_polarity_get(const stmdev_ctx_t *ctx,
5709 asm330lhhx_den_lh_t *val)
5710 {
5711 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5712 int32_t ret;
5713
5714 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5715
5716 switch (ctrl9_xl.den_lh)
5717 {
5718 case ASM330LHHX_DEN_ACT_LOW:
5719 *val = ASM330LHHX_DEN_ACT_LOW;
5720 break;
5721 case ASM330LHHX_DEN_ACT_HIGH:
5722 *val = ASM330LHHX_DEN_ACT_HIGH;
5723 break;
5724 default:
5725 *val = ASM330LHHX_DEN_ACT_LOW;
5726 break;
5727 }
5728 return ret;
5729 }
5730
5731 /**
5732 * @brief DEN configuration.[set]
5733 *
5734 * @param ctx Read / write interface definitions.(ptr)
5735 * @param val Change the values of den_xl_g in reg CTRL9_XL
5736 * @retval Interface status (MANDATORY: return 0 -> no Error).
5737 *
5738 */
asm330lhhx_den_enable_set(const stmdev_ctx_t * ctx,asm330lhhx_den_xl_g_t val)5739 int32_t asm330lhhx_den_enable_set(const stmdev_ctx_t *ctx,
5740 asm330lhhx_den_xl_g_t val)
5741 {
5742 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5743 int32_t ret;
5744
5745 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5746 if (ret == 0)
5747 {
5748 ctrl9_xl.den_xl_g = (uint8_t)val;
5749 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL,
5750 (uint8_t *)&ctrl9_xl, 1);
5751 }
5752 return ret;
5753 }
5754
5755 /**
5756 * @brief DEN configuration.[get]
5757 *
5758 * @param ctx Read / write interface definitions.(ptr)
5759 * @param val Get the values of den_xl_g in reg CTRL9_XL
5760 * @retval Interface status (MANDATORY: return 0 -> no Error).
5761 *
5762 */
asm330lhhx_den_enable_get(const stmdev_ctx_t * ctx,asm330lhhx_den_xl_g_t * val)5763 int32_t asm330lhhx_den_enable_get(const stmdev_ctx_t *ctx,
5764 asm330lhhx_den_xl_g_t *val)
5765 {
5766 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5767 int32_t ret;
5768
5769 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5770
5771 switch (ctrl9_xl.den_xl_g)
5772 {
5773 case ASM330LHHX_STAMP_IN_GY_DATA:
5774 *val = ASM330LHHX_STAMP_IN_GY_DATA;
5775 break;
5776 case ASM330LHHX_STAMP_IN_XL_DATA:
5777 *val = ASM330LHHX_STAMP_IN_XL_DATA;
5778 break;
5779 case ASM330LHHX_STAMP_IN_GY_XL_DATA:
5780 *val = ASM330LHHX_STAMP_IN_GY_XL_DATA;
5781 break;
5782 default:
5783 *val = ASM330LHHX_STAMP_IN_GY_DATA;
5784 break;
5785 }
5786 return ret;
5787 }
5788
5789 /**
5790 * @brief DEN value stored in LSB of X-axis.[set]
5791 *
5792 * @param ctx Read / write interface definitions.(ptr)
5793 * @param val Change the values of den_z in reg CTRL9_XL
5794 * @retval Interface status (MANDATORY: return 0 -> no Error).
5795 *
5796 */
asm330lhhx_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)5797 int32_t asm330lhhx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5798 {
5799 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5800 int32_t ret;
5801
5802 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5803 if (ret == 0)
5804 {
5805 ctrl9_xl.den_z = (uint8_t)val;
5806 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL,
5807 (uint8_t *)&ctrl9_xl, 1);
5808 }
5809 return ret;
5810 }
5811
5812 /**
5813 * @brief DEN value stored in LSB of X-axis.[get]
5814 *
5815 * @param ctx Read / write interface definitions.(ptr)
5816 * @param val Change the values of den_z in reg CTRL9_XL
5817 * @retval Interface status (MANDATORY: return 0 -> no Error).
5818 *
5819 */
asm330lhhx_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5820 int32_t asm330lhhx_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
5821 {
5822 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5823 int32_t ret;
5824
5825 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5826 *val = ctrl9_xl.den_z;
5827
5828 return ret;
5829 }
5830
5831 /**
5832 * @brief DEN value stored in LSB of Y-axis.[set]
5833 *
5834 * @param ctx Read / write interface definitions.(ptr)
5835 * @param val Change the values of den_y in reg CTRL9_XL
5836 * @retval Interface status (MANDATORY: return 0 -> no Error).
5837 *
5838 */
asm330lhhx_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)5839 int32_t asm330lhhx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5840 {
5841 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5842 int32_t ret;
5843
5844 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5845 if (ret == 0)
5846 {
5847 ctrl9_xl.den_y = (uint8_t)val;
5848 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL,
5849 (uint8_t *)&ctrl9_xl, 1);
5850 }
5851 return ret;
5852 }
5853
5854 /**
5855 * @brief DEN value stored in LSB of Y-axis.[get]
5856 *
5857 * @param ctx Read / write interface definitions.(ptr)
5858 * @param val Change the values of den_y in reg CTRL9_XL
5859 * @retval Interface status (MANDATORY: return 0 -> no Error).
5860 *
5861 */
asm330lhhx_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5862 int32_t asm330lhhx_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
5863 {
5864 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5865 int32_t ret;
5866
5867 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5868 *val = ctrl9_xl.den_y;
5869
5870 return ret;
5871 }
5872
5873 /**
5874 * @brief DEN value stored in LSB of Z-axis.[set]
5875 *
5876 * @param ctx Read / write interface definitions.(ptr)
5877 * @param val Change the values of den_x in reg CTRL9_XL
5878 * @retval Interface status (MANDATORY: return 0 -> no Error).
5879 *
5880 */
asm330lhhx_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)5881 int32_t asm330lhhx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5882 {
5883 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5884 int32_t ret;
5885
5886 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5887 if (ret == 0)
5888 {
5889 ctrl9_xl.den_x = (uint8_t)val;
5890 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5891 }
5892 return ret;
5893 }
5894
5895 /**
5896 * @brief DEN value stored in LSB of Z-axis.[get]
5897 *
5898 * @param ctx Read / write interface definitions.(ptr)
5899 * @param val Change the values of den_x in reg CTRL9_XL
5900 * @retval Interface status (MANDATORY: return 0 -> no Error).
5901 *
5902 */
asm330lhhx_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5903 int32_t asm330lhhx_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
5904 {
5905 asm330lhhx_ctrl9_xl_t ctrl9_xl;
5906 int32_t ret;
5907
5908 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5909 *val = ctrl9_xl.den_x;
5910
5911 return ret;
5912 }
5913
5914 /**
5915 * @}
5916 *
5917 */
5918
5919 /**
5920 * @defgroup ASM330LHHX_ magnetometer_sensor
5921 * @brief This section groups all the functions that manage additional
5922 * magnetometer sensor.
5923 * @{
5924 *
5925 */
5926
5927 /**
5928 * @brief External magnetometer sensitivity value register.[set]
5929 *
5930 * @param ctx Read / write interface definitions.(ptr)
5931 * @param buff Buffer that contains data to write
5932 * @retval Interface status (MANDATORY: return 0 -> no Error).
5933 *
5934 */
asm330lhhx_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)5935 int32_t asm330lhhx_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
5936 {
5937 uint8_t buff[2];
5938 int32_t ret;
5939
5940 buff[1] = (uint8_t)(val / 256U);
5941 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5942 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_L, &buff[0]);
5943 if (ret == 0)
5944 {
5945 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_H, &buff[1]);
5946 }
5947 return ret;
5948 }
5949
5950 /**
5951 * @brief External magnetometer sensitivity value register.[get]
5952 *
5953 * @param ctx Read / write interface definitions.(ptr)
5954 * @param buff Buffer that stores data read
5955 * @retval Interface status (MANDATORY: return 0 -> no Error).
5956 *
5957 */
asm330lhhx_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)5958 int32_t asm330lhhx_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
5959 {
5960 uint8_t buff[2];
5961 int32_t ret;
5962
5963 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_L, &buff[0]);
5964 if (ret == 0)
5965 {
5966 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SENSITIVITY_H, &buff[1]);
5967 *val = buff[1];
5968 *val = (*val * 256U) + buff[0];
5969 }
5970 return ret;
5971 }
5972
5973 /**
5974 * @brief Offset for hard-iron compensation register (r/w).[set]
5975 *
5976 * @param ctx Read / write interface definitions.(ptr)
5977 * @param buff Buffer that contains data to write
5978 * @retval Interface status (MANDATORY: return 0 -> no Error).
5979 *
5980 */
asm330lhhx_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)5981 int32_t asm330lhhx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
5982 {
5983 uint8_t buff[6];
5984 int32_t ret;
5985 uint8_t i;
5986
5987 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
5988 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
5989 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
5990 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
5991 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
5992 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
5993
5994 i = 0x00U;
5995 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFX_L, &buff[i]);
5996 if (ret == 0)
5997 {
5998 i++;
5999 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFX_H, &buff[i]);
6000 }
6001 if (ret == 0)
6002 {
6003 i++;
6004 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFY_L, &buff[i]);
6005 }
6006 if (ret == 0)
6007 {
6008 i++;
6009 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFY_H, &buff[i]);
6010 }
6011 if (ret == 0)
6012 {
6013 i++;
6014 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFZ_L, &buff[i]);
6015 }
6016 if (ret == 0)
6017 {
6018 i++;
6019 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_OFFZ_H, &buff[i]);
6020 }
6021 return ret;
6022 }
6023
6024 /**
6025 * @brief Offset for hard-iron compensation register (r/w).[get]
6026 *
6027 * @param ctx Read / write interface definitions.(ptr)
6028 * @param buff Buffer that stores data read
6029 * @retval Interface status (MANDATORY: return 0 -> no Error).
6030 *
6031 */
asm330lhhx_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)6032 int32_t asm330lhhx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
6033 {
6034 uint8_t buff[6];
6035 int32_t ret;
6036 uint8_t i;
6037
6038 i = 0x00U;
6039 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFX_L, &buff[i]);
6040
6041 if (ret == 0)
6042 {
6043 i++;
6044 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFX_H, &buff[i]);
6045 }
6046 if (ret == 0)
6047 {
6048 i++;
6049 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFY_L, &buff[i]);
6050 }
6051 if (ret == 0)
6052 {
6053 i++;
6054 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFY_H, &buff[i]);
6055 }
6056 if (ret == 0)
6057 {
6058 i++;
6059 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFZ_L, &buff[i]);
6060 }
6061 if (ret == 0)
6062 {
6063 i++;
6064 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_OFFZ_H, &buff[i]);
6065 }
6066 val[0] = (int16_t)buff[1];
6067 val[0] = (val[0] * 256) + (int16_t)buff[0];
6068 val[1] = (int16_t)buff[3];
6069 val[1] = (val[1] * 256) + (int16_t)buff[2];
6070 val[2] = (int16_t)buff[5];
6071 val[2] = (val[2] * 256) + (int16_t)buff[4];
6072
6073 return ret;
6074 }
6075
6076 /**
6077 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
6078 * The value is expressed as half-precision floating-point format:
6079 * SEEEEEFFFFFFFFFF
6080 * S: 1 sign bit;
6081 * E: 5 exponent bits;
6082 * F: 10 fraction bits).[set]
6083 *
6084 * @param ctx Read / write interface definitions.(ptr)
6085 * @param buff Buffer that contains data to write
6086 * @retval Interface status (MANDATORY: return 0 -> no Error).
6087 *
6088 */
asm330lhhx_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)6089 int32_t asm330lhhx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
6090 {
6091 uint8_t buff[12];
6092 int32_t ret;
6093 uint8_t i;
6094
6095 buff[1] = (uint8_t)(val[0] / 256U);
6096 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
6097 buff[3] = (uint8_t)(val[1] / 256U);
6098 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
6099 buff[5] = (uint8_t)(val[2] / 256U);
6100 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
6101 buff[7] = (uint8_t)(val[3] / 256U);
6102 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
6103 buff[9] = (uint8_t)(val[4] / 256U);
6104 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
6105 buff[11] = (uint8_t)(val[5] / 256U);
6106 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
6107
6108 i = 0x00U;
6109 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XX_L, &buff[i]);
6110 if (ret == 0)
6111 {
6112 i++;
6113 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XX_H, &buff[i]);
6114 }
6115 if (ret == 0)
6116 {
6117 i++;
6118 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XY_L, &buff[i]);
6119 }
6120 if (ret == 0)
6121 {
6122 i++;
6123 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XY_H, &buff[i]);
6124 }
6125 if (ret == 0)
6126 {
6127 i++;
6128 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XZ_L, &buff[i]);
6129 }
6130 if (ret == 0)
6131 {
6132 i++;
6133 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_XZ_H, &buff[i]);
6134 }
6135 if (ret == 0)
6136 {
6137 i++;
6138 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_YY_L, &buff[i]);
6139 }
6140 if (ret == 0)
6141 {
6142 i++;
6143 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_YY_H, &buff[i]);
6144 }
6145 if (ret == 0)
6146 {
6147 i++;
6148 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_YZ_L, &buff[i]);
6149 }
6150 if (ret == 0)
6151 {
6152 i++;
6153 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_YZ_H, &buff[i]);
6154 }
6155 if (ret == 0)
6156 {
6157 i++;
6158 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_ZZ_L, &buff[i]);
6159 }
6160 if (ret == 0)
6161 {
6162 i++;
6163 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_SI_ZZ_H, &buff[i]);
6164 }
6165 return ret;
6166 }
6167
6168 /**
6169 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
6170 * The value is expressed as half-precision floating-point format:
6171 * SEEEEEFFFFFFFFFF
6172 * S: 1 sign bit;
6173 * E: 5 exponent bits;
6174 * F: 10 fraction bits).[get]
6175 *
6176 * @param ctx Read / write interface definitions.(ptr)
6177 * @param buff Buffer that stores data read
6178 * @retval Interface status (MANDATORY: return 0 -> no Error).
6179 *
6180 */
asm330lhhx_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)6181 int32_t asm330lhhx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
6182 {
6183 uint8_t buff[12];
6184 int32_t ret;
6185 uint8_t i;
6186
6187 i = 0x00U;
6188 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XX_L, &buff[i]);
6189 if (ret == 0)
6190 {
6191 i++;
6192 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XX_H, &buff[i]);
6193 }
6194 if (ret == 0)
6195 {
6196 i++;
6197 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XY_L, &buff[i]);
6198 }
6199 if (ret == 0)
6200 {
6201 i++;
6202 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XY_H, &buff[i]);
6203 }
6204 if (ret == 0)
6205 {
6206 i++;
6207 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XZ_L, &buff[i]);
6208 }
6209 if (ret == 0)
6210 {
6211 i++;
6212 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_XZ_H, &buff[i]);
6213 }
6214 if (ret == 0)
6215 {
6216 i++;
6217 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_YY_L, &buff[i]);
6218 }
6219 if (ret == 0)
6220 {
6221 i++;
6222 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_YY_H, &buff[i]);
6223 }
6224 if (ret == 0)
6225 {
6226 i++;
6227 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_YZ_L, &buff[i]);
6228 }
6229 if (ret == 0)
6230 {
6231 i++;
6232 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_YZ_H, &buff[i]);
6233 }
6234 if (ret == 0)
6235 {
6236 i++;
6237 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_ZZ_L, &buff[i]);
6238 }
6239 if (ret == 0)
6240 {
6241 i++;
6242 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_SI_ZZ_H, &buff[i]);
6243 }
6244
6245 val[0] = buff[1];
6246 val[0] = (val[0] * 256U) + buff[0];
6247 val[1] = buff[3];
6248 val[1] = (val[1] * 256U) + buff[2];
6249 val[2] = buff[5];
6250 val[2] = (val[2] * 256U) + buff[4];
6251 val[3] = buff[7];
6252 val[3] = (val[3] * 256U) + buff[6];
6253 val[4] = buff[9];
6254 val[4] = (val[4] * 256U) + buff[8];
6255 val[5] = buff[11];
6256 val[6] = (val[5] * 256U) + buff[10];
6257
6258 return ret;
6259 }
6260
6261 /**
6262 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
6263 * accelerometer/gyroscope axes orientation).[set]
6264 *
6265 * @param ctx Read / write interface definitions.(ptr)
6266 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
6267 * @retval Interface status (MANDATORY: return 0 -> no Error).
6268 *
6269 */
asm330lhhx_mag_z_orient_set(const stmdev_ctx_t * ctx,asm330lhhx_mag_z_axis_t val)6270 int32_t asm330lhhx_mag_z_orient_set(const stmdev_ctx_t *ctx,
6271 asm330lhhx_mag_z_axis_t val)
6272 {
6273 asm330lhhx_mag_cfg_a_t mag_cfg_a;
6274 int32_t ret;
6275
6276 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A,
6277 (uint8_t *)&mag_cfg_a);
6278
6279 if (ret == 0)
6280 {
6281 mag_cfg_a.mag_z_axis = (uint8_t)val;
6282 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_CFG_A,
6283 (uint8_t *)&mag_cfg_a);
6284 }
6285 return ret;
6286 }
6287
6288 /**
6289 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
6290 * accelerometer/gyroscope axes orientation).[get]
6291 *
6292 * @param ctx Read / write interface definitions.(ptr)
6293 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
6294 * @retval Interface status (MANDATORY: return 0 -> no Error).
6295 *
6296 */
asm330lhhx_mag_z_orient_get(const stmdev_ctx_t * ctx,asm330lhhx_mag_z_axis_t * val)6297 int32_t asm330lhhx_mag_z_orient_get(const stmdev_ctx_t *ctx,
6298 asm330lhhx_mag_z_axis_t *val)
6299 {
6300 asm330lhhx_mag_cfg_a_t mag_cfg_a;
6301 int32_t ret;
6302 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A,
6303 (uint8_t *)&mag_cfg_a);
6304
6305 switch (mag_cfg_a.mag_z_axis)
6306 {
6307 case ASM330LHHX_Z_EQ_Y:
6308 *val = ASM330LHHX_Z_EQ_Y;
6309 break;
6310 case ASM330LHHX_Z_EQ_MIN_Y:
6311 *val = ASM330LHHX_Z_EQ_MIN_Y;
6312 break;
6313 case ASM330LHHX_Z_EQ_X:
6314 *val = ASM330LHHX_Z_EQ_X;
6315 break;
6316 case ASM330LHHX_Z_EQ_MIN_X:
6317 *val = ASM330LHHX_Z_EQ_MIN_X;
6318 break;
6319 case ASM330LHHX_Z_EQ_MIN_Z:
6320 *val = ASM330LHHX_Z_EQ_MIN_Z;
6321 break;
6322 case ASM330LHHX_Z_EQ_Z:
6323 *val = ASM330LHHX_Z_EQ_Z;
6324 break;
6325 default:
6326 *val = ASM330LHHX_Z_EQ_Y;
6327 break;
6328 }
6329 return ret;
6330 }
6331
6332 /**
6333 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
6334 * accelerometer/gyroscope axes orientation).[set]
6335 *
6336 * @param ctx Read / write interface definitions.(ptr)
6337 * @param val Change the values of mag_y_axis in
6338 * reg MAG_CFG_A
6339 * @retval Interface status (MANDATORY: return 0 -> no Error).
6340 *
6341 */
asm330lhhx_mag_y_orient_set(const stmdev_ctx_t * ctx,asm330lhhx_mag_y_axis_t val)6342 int32_t asm330lhhx_mag_y_orient_set(const stmdev_ctx_t *ctx,
6343 asm330lhhx_mag_y_axis_t val)
6344 {
6345 asm330lhhx_mag_cfg_a_t mag_cfg_a;
6346 int32_t ret;
6347
6348 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A,
6349 (uint8_t *)&mag_cfg_a);
6350 if (ret == 0)
6351 {
6352 mag_cfg_a.mag_y_axis = (uint8_t)val;
6353 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_CFG_A,
6354 (uint8_t *)&mag_cfg_a);
6355 }
6356 return ret;
6357 }
6358
6359 /**
6360 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
6361 * accelerometer/gyroscope axes orientation).[get]
6362 *
6363 * @param ctx Read / write interface definitions.(ptr)
6364 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
6365 * @retval Interface status (MANDATORY: return 0 -> no Error).
6366 *
6367 */
asm330lhhx_mag_y_orient_get(const stmdev_ctx_t * ctx,asm330lhhx_mag_y_axis_t * val)6368 int32_t asm330lhhx_mag_y_orient_get(const stmdev_ctx_t *ctx,
6369 asm330lhhx_mag_y_axis_t *val)
6370 {
6371 asm330lhhx_mag_cfg_a_t mag_cfg_a;
6372 int32_t ret;
6373
6374 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_A,
6375 (uint8_t *)&mag_cfg_a);
6376
6377 switch (mag_cfg_a.mag_y_axis)
6378 {
6379 case ASM330LHHX_Y_EQ_Y:
6380 *val = ASM330LHHX_Y_EQ_Y;
6381 break;
6382 case ASM330LHHX_Y_EQ_MIN_Y:
6383 *val = ASM330LHHX_Y_EQ_MIN_Y;
6384 break;
6385 case ASM330LHHX_Y_EQ_X:
6386 *val = ASM330LHHX_Y_EQ_X;
6387 break;
6388 case ASM330LHHX_Y_EQ_MIN_X:
6389 *val = ASM330LHHX_Y_EQ_MIN_X;
6390 break;
6391 case ASM330LHHX_Y_EQ_MIN_Z:
6392 *val = ASM330LHHX_Y_EQ_MIN_Z;
6393 break;
6394 case ASM330LHHX_Y_EQ_Z:
6395 *val = ASM330LHHX_Y_EQ_Z;
6396 break;
6397 default:
6398 *val = ASM330LHHX_Y_EQ_Y;
6399 break;
6400 }
6401 return ret;
6402 }
6403
6404 /**
6405 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
6406 * accelerometer/gyroscope axes orientation).[set]
6407 *
6408 * @param ctx Read / write interface definitions.(ptr)
6409 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
6410 * @retval Interface status (MANDATORY: return 0 -> no Error).
6411 *
6412 */
asm330lhhx_mag_x_orient_set(const stmdev_ctx_t * ctx,asm330lhhx_mag_x_axis_t val)6413 int32_t asm330lhhx_mag_x_orient_set(const stmdev_ctx_t *ctx,
6414 asm330lhhx_mag_x_axis_t val)
6415 {
6416 asm330lhhx_mag_cfg_b_t mag_cfg_b;
6417 int32_t ret;
6418
6419 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_B,
6420 (uint8_t *)&mag_cfg_b);
6421 if (ret == 0)
6422 {
6423 mag_cfg_b.mag_x_axis = (uint8_t)val;
6424 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MAG_CFG_B,
6425 (uint8_t *)&mag_cfg_b);
6426 }
6427 return ret;
6428 }
6429
6430 /**
6431 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
6432 * accelerometer/gyroscope axes orientation).[get]
6433 *
6434 * @param ctx Read / write interface definitions.(ptr)
6435 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
6436 * @retval Interface status (MANDATORY: return 0 -> no Error).
6437 *
6438 */
asm330lhhx_mag_x_orient_get(const stmdev_ctx_t * ctx,asm330lhhx_mag_x_axis_t * val)6439 int32_t asm330lhhx_mag_x_orient_get(const stmdev_ctx_t *ctx,
6440 asm330lhhx_mag_x_axis_t *val)
6441 {
6442 asm330lhhx_mag_cfg_b_t mag_cfg_b;
6443 int32_t ret;
6444
6445 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MAG_CFG_B,
6446 (uint8_t *)&mag_cfg_b);
6447
6448 switch (mag_cfg_b.mag_x_axis)
6449 {
6450 case ASM330LHHX_X_EQ_Y:
6451 *val = ASM330LHHX_X_EQ_Y;
6452 break;
6453 case ASM330LHHX_X_EQ_MIN_Y:
6454 *val = ASM330LHHX_X_EQ_MIN_Y;
6455 break;
6456 case ASM330LHHX_X_EQ_X:
6457 *val = ASM330LHHX_X_EQ_X;
6458 break;
6459 case ASM330LHHX_X_EQ_MIN_X:
6460 *val = ASM330LHHX_X_EQ_MIN_X;
6461 break;
6462 case ASM330LHHX_X_EQ_MIN_Z:
6463 *val = ASM330LHHX_X_EQ_MIN_Z;
6464 break;
6465 case ASM330LHHX_X_EQ_Z:
6466 *val = ASM330LHHX_X_EQ_Z;
6467 break;
6468 default:
6469 *val = ASM330LHHX_X_EQ_Y;
6470 break;
6471 }
6472 return ret;
6473 }
6474
6475 /**
6476 * @}
6477 *
6478 */
6479
6480 /**
6481 * @defgroup ASM330LHHX_finite_state_machine
6482 * @brief This section groups all the functions that manage the
6483 * state_machine.
6484 * @{
6485 *
6486 */
6487
6488 /**
6489 * @brief FSM status register[get]
6490 *
6491 * @param ctx read / write interface definitions
6492 * @param val register ASM330LHHX_FSM_STATUS_A_MAINPAGE,
6493 * ASM330LHHX_FSM_STATUS_B_MAINPAGE
6494 *
6495 */
asm330lhhx_fsm_status_get(const stmdev_ctx_t * ctx,asm330lhhx_fsm_status_t * val)6496 int32_t asm330lhhx_fsm_status_get(const stmdev_ctx_t *ctx,
6497 asm330lhhx_fsm_status_t *val)
6498 {
6499 asm330lhhx_fsm_status_a_mainpage_t status_a;
6500 asm330lhhx_fsm_status_b_mainpage_t status_b;
6501 int32_t ret;
6502
6503 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_A_MAINPAGE,
6504 (uint8_t *)&status_a, 1);
6505 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_STATUS_B_MAINPAGE,
6506 (uint8_t *)&status_b, 1);
6507
6508 val->fsm1 = status_a.is_fsm1;
6509 val->fsm2 = status_a.is_fsm2;
6510 val->fsm3 = status_a.is_fsm3;
6511 val->fsm4 = status_a.is_fsm4;
6512 val->fsm5 = status_a.is_fsm5;
6513 val->fsm6 = status_a.is_fsm6;
6514 val->fsm7 = status_a.is_fsm7;
6515 val->fsm8 = status_a.is_fsm8;
6516 val->fsm9 = status_b.is_fsm9;
6517 val->fsm10 = status_b.is_fsm10;
6518 val->fsm11 = status_b.is_fsm11;
6519 val->fsm12 = status_b.is_fsm12;
6520 val->fsm13 = status_b.is_fsm13;
6521 val->fsm14 = status_b.is_fsm14;
6522 val->fsm15 = status_b.is_fsm15;
6523 val->fsm16 = status_b.is_fsm16;
6524 return ret;
6525 }
6526
6527 /**
6528 * @brief prgsens_out: [get] Output value of all FSMs.
6529 *
6530 * @param ctx_t *ctx: read / write interface definitions
6531 * @param uint8_t * : buffer that stores data read
6532 *
6533 */
asm330lhhx_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)6534 int32_t asm330lhhx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6535 {
6536 int32_t ret;
6537 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6538 if (ret == 0)
6539 {
6540 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_OUTS1, buff, 16);
6541 }
6542 if (ret == 0)
6543 {
6544 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6545 }
6546 return ret;
6547 }
6548
6549 /**
6550 * @brief Interrupt status bit for FSM long counter timeout interrupt
6551 * event.[get]
6552 *
6553 * @param ctx Read / write interface definitions.(ptr)
6554 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
6555 * @retval Interface status (MANDATORY: return 0 -> no Error).
6556 *
6557 */
asm330lhhx_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)6558 int32_t asm330lhhx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
6559 uint8_t *val)
6560 {
6561 asm330lhhx_emb_func_status_t emb_func_status;
6562 int32_t ret;
6563
6564 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6565 if (ret == 0)
6566 {
6567 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_STATUS,
6568 (uint8_t *)&emb_func_status, 1);
6569 }
6570 if (ret == 0)
6571 {
6572 *val = emb_func_status.is_fsm_lc;
6573 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6574 }
6575 return ret;
6576 }
6577
asm330lhhx_emb_func_clk_dis_set(const stmdev_ctx_t * ctx,uint8_t val)6578 int32_t asm330lhhx_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val)
6579 {
6580 asm330lhhx_page_sel_t page_sel;
6581 int32_t ret;
6582
6583 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6584 if (ret == 0)
6585 {
6586 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL,
6587 (uint8_t *)&page_sel, 1);
6588
6589 page_sel.emb_func_clk_dis = val;
6590 }
6591
6592 ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6593
6594 return ret;
6595 }
6596
asm330lhhx_emb_func_clk_dis_get(const stmdev_ctx_t * ctx,uint8_t * val)6597 int32_t asm330lhhx_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val)
6598 {
6599 asm330lhhx_page_sel_t page_sel;
6600 int32_t ret;
6601
6602 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6603 if (ret == 0)
6604 {
6605 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_PAGE_SEL,
6606 (uint8_t *)&page_sel, 1);
6607
6608 *val = page_sel.emb_func_clk_dis;
6609 }
6610
6611 ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6612
6613 return ret;
6614 }
6615
6616 /**
6617 * @brief Embedded final state machine functions mode.[set]
6618 *
6619 * @param ctx Read / write interface definitions.(ptr)
6620 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
6621 * @retval Interface status (MANDATORY: return 0 -> no Error).
6622 *
6623 */
asm330lhhx_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)6624 int32_t asm330lhhx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
6625 {
6626 int32_t ret;
6627 asm330lhhx_emb_func_en_b_t emb_func_en_b;
6628
6629 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6630
6631 if (ret == 0)
6632 {
6633 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6634 (uint8_t *)&emb_func_en_b, 1);
6635 }
6636 if (ret == 0)
6637 {
6638 emb_func_en_b.fsm_en = (uint8_t)val;
6639 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6640 (uint8_t *)&emb_func_en_b, 1);
6641 }
6642 if (ret == 0)
6643 {
6644 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6645 }
6646 return ret;
6647 }
6648
6649 /**
6650 * @brief Embedded final state machine functions mode.[get]
6651 *
6652 * @param ctx Read / write interface definitions.(ptr)
6653 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
6654 * @retval Interface status (MANDATORY: return 0 -> no Error).
6655 *
6656 */
asm330lhhx_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)6657 int32_t asm330lhhx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
6658 {
6659 int32_t ret;
6660 asm330lhhx_emb_func_en_b_t emb_func_en_b;
6661
6662 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6663 if (ret == 0)
6664 {
6665 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6666 (uint8_t *)&emb_func_en_b, 1);
6667 }
6668 if (ret == 0)
6669 {
6670 *val = emb_func_en_b.fsm_en;
6671 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6672 (uint8_t *)&emb_func_en_b, 1);
6673 }
6674 if (ret == 0)
6675 {
6676 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6677 }
6678 return ret;
6679 }
6680
6681 /**
6682 * @brief Embedded final state machine functions mode.[set]
6683 *
6684 * @param ctx Read / write interface definitions.(ptr)
6685 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
6686 * @retval Interface status (MANDATORY: return 0 -> no Error).
6687 *
6688 */
asm330lhhx_fsm_enable_set(const stmdev_ctx_t * ctx,asm330lhhx_emb_fsm_enable_t * val)6689 int32_t asm330lhhx_fsm_enable_set(const stmdev_ctx_t *ctx,
6690 asm330lhhx_emb_fsm_enable_t *val)
6691 {
6692 asm330lhhx_emb_func_en_b_t emb_func_en_b;
6693 int32_t ret;
6694
6695 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6696 if (ret == 0)
6697 {
6698 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_ENABLE_A,
6699 (uint8_t *)&val->fsm_enable_a, 1);
6700 }
6701 if (ret == 0)
6702 {
6703 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_ENABLE_B,
6704 (uint8_t *)&val->fsm_enable_b, 1);
6705 }
6706 if (ret == 0)
6707 {
6708 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6709 (uint8_t *)&emb_func_en_b, 1);
6710 }
6711 if (ret == 0)
6712 {
6713 if ((val->fsm_enable_a.fsm1_en |
6714 val->fsm_enable_a.fsm2_en |
6715 val->fsm_enable_a.fsm3_en |
6716 val->fsm_enable_a.fsm4_en |
6717 val->fsm_enable_a.fsm5_en |
6718 val->fsm_enable_a.fsm6_en |
6719 val->fsm_enable_a.fsm7_en |
6720 val->fsm_enable_a.fsm8_en |
6721 val->fsm_enable_b.fsm9_en |
6722 val->fsm_enable_b.fsm10_en |
6723 val->fsm_enable_b.fsm11_en |
6724 val->fsm_enable_b.fsm12_en |
6725 val->fsm_enable_b.fsm13_en |
6726 val->fsm_enable_b.fsm14_en |
6727 val->fsm_enable_b.fsm15_en |
6728 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
6729 {
6730 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6731 }
6732 else
6733 {
6734 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6735 }
6736 }
6737 if (ret == 0)
6738 {
6739 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B,
6740 (uint8_t *)&emb_func_en_b, 1);
6741 }
6742 if (ret == 0)
6743 {
6744 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6745 }
6746 return ret;
6747 }
6748
6749 /**
6750 * @brief Embedded final state machine functions mode.[get]
6751 *
6752 * @param ctx Read / write interface definitions.(ptr)
6753 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
6754 * @retval Interface status (MANDATORY: return 0 -> no Error).
6755 *
6756 */
asm330lhhx_fsm_enable_get(const stmdev_ctx_t * ctx,asm330lhhx_emb_fsm_enable_t * val)6757 int32_t asm330lhhx_fsm_enable_get(const stmdev_ctx_t *ctx,
6758 asm330lhhx_emb_fsm_enable_t *val)
6759 {
6760 int32_t ret;
6761
6762 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6763 if (ret == 0)
6764 {
6765 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_ENABLE_A,
6766 (uint8_t *)&val->fsm_enable_a, 1);
6767 }
6768 if (ret == 0)
6769 {
6770 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_ENABLE_B,
6771 (uint8_t *)&val->fsm_enable_b, 1);
6772 }
6773 if (ret == 0)
6774 {
6775 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6776 }
6777 return ret;
6778 }
6779
6780 /**
6781 * @brief FSM long counter status register. Long counter value is an
6782 * unsigned integer value (16-bit format).[set]
6783 *
6784 * @param ctx Read / write interface definitions.(ptr)
6785 * @param buff Buffer that contains data to write
6786 * @retval Interface status (MANDATORY: return 0 -> no Error).
6787 *
6788 */
asm330lhhx_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6789 int32_t asm330lhhx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6790 {
6791 uint8_t buff[2];
6792 int32_t ret;
6793
6794 buff[1] = (uint8_t)(val / 256U);
6795 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6796
6797 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6798 if (ret == 0)
6799 {
6800 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_L, buff, 2);
6801 }
6802 if (ret == 0)
6803 {
6804 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6805 }
6806 return ret;
6807 }
6808
6809 /**
6810 * @brief FSM long counter status register. Long counter value is an
6811 * unsigned integer value (16-bit format).[get]
6812 *
6813 * @param ctx Read / write interface definitions.(ptr)
6814 * @param buff Buffer that stores data read
6815 * @retval Interface status (MANDATORY: return 0 -> no Error).
6816 *
6817 */
asm330lhhx_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)6818 int32_t asm330lhhx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
6819 {
6820 uint8_t buff[2];
6821 int32_t ret;
6822
6823 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6824 if (ret == 0)
6825 {
6826 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_L, buff, 2);
6827 *val = buff[1];
6828 *val = (*val * 256U) + buff[0];
6829 }
6830 if (ret == 0)
6831 {
6832 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6833 }
6834 return ret;
6835 }
6836
6837 /**
6838 * @brief Clear FSM long counter value.[set]
6839 *
6840 * @param ctx Read / write interface definitions.(ptr)
6841 * @param val Change the values of fsm_lc_clr in reg
6842 * FSM_LONG_COUNTER_CLEAR
6843 * @retval Interface status (MANDATORY: return 0 -> no Error).
6844 *
6845 */
asm330lhhx_long_clr_set(const stmdev_ctx_t * ctx,asm330lhhx_fsm_lc_clr_t val)6846 int32_t asm330lhhx_long_clr_set(const stmdev_ctx_t *ctx,
6847 asm330lhhx_fsm_lc_clr_t val)
6848 {
6849 asm330lhhx_fsm_long_counter_clear_t fsm_long_counter_clear;
6850 int32_t ret;
6851
6852 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6853 if (ret == 0)
6854 {
6855 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_CLEAR,
6856 (uint8_t *)&fsm_long_counter_clear, 1);
6857 }
6858 if (ret == 0)
6859 {
6860 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
6861 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_CLEAR,
6862 (uint8_t *)&fsm_long_counter_clear, 1);
6863 }
6864 if (ret == 0)
6865 {
6866 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6867 }
6868 return ret;
6869 }
6870
6871 /**
6872 * @brief Clear FSM long counter value.[get]
6873 *
6874 * @param ctx Read / write interface definitions.(ptr)
6875 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
6876 * @retval Interface status (MANDATORY: return 0 -> no Error).
6877 *
6878 */
asm330lhhx_long_clr_get(const stmdev_ctx_t * ctx,asm330lhhx_fsm_lc_clr_t * val)6879 int32_t asm330lhhx_long_clr_get(const stmdev_ctx_t *ctx,
6880 asm330lhhx_fsm_lc_clr_t *val)
6881 {
6882 asm330lhhx_fsm_long_counter_clear_t fsm_long_counter_clear;
6883 int32_t ret;
6884
6885 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6886
6887 if (ret == 0)
6888 {
6889 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_FSM_LONG_COUNTER_CLEAR,
6890 (uint8_t *)&fsm_long_counter_clear, 1);
6891 }
6892 if (ret == 0)
6893 {
6894 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6895 }
6896 switch (fsm_long_counter_clear.fsm_lc_clr)
6897 {
6898 case ASM330LHHX_LC_NORMAL:
6899 *val = ASM330LHHX_LC_NORMAL;
6900 break;
6901 case ASM330LHHX_LC_CLEAR:
6902 *val = ASM330LHHX_LC_CLEAR;
6903 break;
6904 case ASM330LHHX_LC_CLEAR_DONE:
6905 *val = ASM330LHHX_LC_CLEAR_DONE;
6906 break;
6907 default:
6908 *val = ASM330LHHX_LC_NORMAL;
6909 break;
6910 }
6911 return ret;
6912 }
6913
6914 /**
6915 * @brief Finite State Machine ODR configuration.[set]
6916 *
6917 * @param ctx Read / write interface definitions.(ptr)
6918 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6919 * @retval Interface status (MANDATORY: return 0 -> no Error).
6920 *
6921 */
asm330lhhx_fsm_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhx_fsm_odr_t val)6922 int32_t asm330lhhx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6923 asm330lhhx_fsm_odr_t val)
6924 {
6925 asm330lhhx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6926 int32_t ret;
6927
6928 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6929
6930 if (ret == 0)
6931 {
6932 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_B,
6933 (uint8_t *)&emb_func_odr_cfg_b, 1);
6934 }
6935 if (ret == 0)
6936 {
6937 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
6938 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
6939 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
6940 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_B,
6941 (uint8_t *)&emb_func_odr_cfg_b, 1);
6942 }
6943 if (ret == 0)
6944 {
6945 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6946 }
6947 return ret;
6948 }
6949
6950 /**
6951 * @brief Finite State Machine ODR configuration.[get]
6952 *
6953 * @param ctx Read / write interface definitions.(ptr)
6954 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6955 * @retval Interface status (MANDATORY: return 0 -> no Error).
6956 *
6957 */
asm330lhhx_fsm_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhx_fsm_odr_t * val)6958 int32_t asm330lhhx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6959 asm330lhhx_fsm_odr_t *val)
6960 {
6961 asm330lhhx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6962 int32_t ret;
6963
6964 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
6965
6966 if (ret == 0)
6967 {
6968 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_B,
6969 (uint8_t *)&emb_func_odr_cfg_b, 1);
6970 }
6971 if (ret == 0)
6972 {
6973 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
6974 }
6975 switch (emb_func_odr_cfg_b.fsm_odr)
6976 {
6977 case ASM330LHHX_ODR_FSM_12Hz5:
6978 *val = ASM330LHHX_ODR_FSM_12Hz5;
6979 break;
6980 case ASM330LHHX_ODR_FSM_26Hz:
6981 *val = ASM330LHHX_ODR_FSM_26Hz;
6982 break;
6983 case ASM330LHHX_ODR_FSM_52Hz:
6984 *val = ASM330LHHX_ODR_FSM_52Hz;
6985 break;
6986 case ASM330LHHX_ODR_FSM_104Hz:
6987 *val = ASM330LHHX_ODR_FSM_104Hz;
6988 break;
6989 default:
6990 *val = ASM330LHHX_ODR_FSM_12Hz5;
6991 break;
6992 }
6993 return ret;
6994 }
6995
6996 /**
6997 * @brief FSM initialization request.[set]
6998 *
6999 * @param ctx Read / write interface definitions.(ptr)
7000 * @param val Change the values of fsm_init in reg FSM_INIT
7001 * @retval Interface status (MANDATORY: return 0 -> no Error).
7002 *
7003 */
asm330lhhx_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)7004 int32_t asm330lhhx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
7005 {
7006 asm330lhhx_emb_func_init_b_t emb_func_init_b;
7007 int32_t ret;
7008
7009 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7010
7011 if (ret == 0)
7012 {
7013 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7014 (uint8_t *)&emb_func_init_b, 1);
7015 }
7016 if (ret == 0)
7017 {
7018 emb_func_init_b.fsm_init = (uint8_t)val;
7019 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7020 (uint8_t *)&emb_func_init_b, 1);
7021 }
7022 if (ret == 0)
7023 {
7024 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7025 }
7026 return ret;
7027 }
7028
7029 /**
7030 * @brief FSM initialization request.[get]
7031 *
7032 * @param ctx Read / write interface definitions.(ptr)
7033 * @param val Change the values of fsm_init in reg FSM_INIT
7034 * @retval Interface status (MANDATORY: return 0 -> no Error).
7035 *
7036 */
asm330lhhx_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)7037 int32_t asm330lhhx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
7038 {
7039 asm330lhhx_emb_func_init_b_t emb_func_init_b;
7040 int32_t ret;
7041
7042 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7043 if (ret == 0)
7044 {
7045 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7046 (uint8_t *)&emb_func_init_b, 1);
7047 }
7048 if (ret == 0)
7049 {
7050 *val = emb_func_init_b.fsm_init;
7051 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7052 }
7053 return ret;
7054 }
7055
7056 /**
7057 * @brief FSM long counter timeout register (r/w). The long counter
7058 * timeout value is an unsigned integer value (16-bit format).
7059 * When the long counter value reached this value, the FSM
7060 * generates an interrupt.[set]
7061 *
7062 * @param ctx Read / write interface definitions.(ptr)
7063 * @param buff Buffer that contains data to write
7064 * @retval Interface status (MANDATORY: return 0 -> no Error).
7065 *
7066 */
asm330lhhx_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)7067 int32_t asm330lhhx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val)
7068 {
7069 uint8_t buff[2];
7070 int32_t ret;
7071
7072 buff[1] = (uint8_t)(val / 256U);
7073 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7074 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_LC_TIMEOUT_L, &buff[0]);
7075
7076 if (ret == 0)
7077 {
7078 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_LC_TIMEOUT_H,
7079 &buff[1]);
7080 }
7081 return ret;
7082 }
7083
7084 /**
7085 * @brief FSM long counter timeout register (r/w). The long counter
7086 * timeout value is an unsigned integer value (16-bit format).
7087 * When the long counter value reached this value, the FSM generates
7088 * an interrupt.[get]
7089 *
7090 * @param ctx Read / write interface definitions.(ptr)
7091 * @param buff Buffer that stores data read
7092 * @retval Interface status (MANDATORY: return 0 -> no Error).
7093 *
7094 */
asm330lhhx_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)7095 int32_t asm330lhhx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val)
7096 {
7097 uint8_t buff[2];
7098 int32_t ret;
7099
7100 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_LC_TIMEOUT_L, &buff[0]);
7101
7102 if (ret == 0)
7103 {
7104 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_LC_TIMEOUT_H,
7105 &buff[1]);
7106 *val = buff[1];
7107 *val = (*val * 256U) + buff[0];
7108 }
7109 return ret;
7110 }
7111
7112 /**
7113 * @brief FSM number of programs register.[set]
7114 *
7115 * @param ctx Read / write interface definitions.(ptr)
7116 * @param buff Buffer that contains data to write
7117 * @retval Interface status (MANDATORY: return 0 -> no Error).
7118 *
7119 */
asm330lhhx_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)7120 int32_t asm330lhhx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff)
7121 {
7122 int32_t ret;
7123
7124 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_PROGRAMS, buff);
7125
7126 if (ret == 0)
7127 {
7128 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_PROGRAMS + 0x01U,
7129 buff);
7130 }
7131 return ret;
7132 }
7133
7134 /**
7135 * @brief FSM number of programs register.[get]
7136 *
7137 * @param ctx Read / write interface definitions.(ptr)
7138 * @param buff Buffer that stores data read
7139 * @retval Interface status (MANDATORY: return 0 -> no Error).
7140 *
7141 */
asm330lhhx_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)7142 int32_t asm330lhhx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7143 {
7144 int32_t ret;
7145
7146 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_PROGRAMS, buff);
7147
7148 return ret;
7149 }
7150
7151 /**
7152 * @brief FSM start address register (r/w). First available address is
7153 * 0x033C.[set]
7154 *
7155 * @param ctx Read / write interface definitions.(ptr)
7156 * @param buff Buffer that contains data to write
7157 * @retval Interface status (MANDATORY: return 0 -> no Error).
7158 *
7159 */
asm330lhhx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7160 int32_t asm330lhhx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7161 {
7162 uint8_t buff[2];
7163 int32_t ret;
7164
7165 buff[1] = (uint8_t)(val / 256U);
7166 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7167
7168 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_START_ADD_L, &buff[0]);
7169 if (ret == 0)
7170 {
7171 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_FSM_START_ADD_H, &buff[1]);
7172 }
7173 return ret;
7174 }
7175
7176 /**
7177 * @brief FSM start address register (r/w). First available address
7178 * is 0x033C.[get]
7179 *
7180 * @param ctx Read / write interface definitions.(ptr)
7181 * @param buff Buffer that stores data read
7182 * @retval Interface status (MANDATORY: return 0 -> no Error).
7183 *
7184 */
asm330lhhx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7185 int32_t asm330lhhx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7186 {
7187 uint8_t buff[2];
7188 int32_t ret;
7189
7190 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_START_ADD_L, &buff[0]);
7191 if (ret == 0)
7192 {
7193 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_FSM_START_ADD_H, &buff[1]);
7194 *val = buff[1];
7195 *val = (*val * 256U) + buff[0];
7196 }
7197 return ret;
7198 }
7199
7200 /**
7201 * @}
7202 *
7203 */
7204
7205 /**
7206 * @addtogroup Machine Learning Core
7207 * @brief This section group all the functions concerning the
7208 * usage of Machine Learning Core
7209 * @{
7210 *
7211 */
7212
7213 /**
7214 * @brief Enable Machine Learning Core.[set]
7215 *
7216 * @param ctx read / write interface definitions
7217 * @param val change the values of mlc_en in
7218 * reg EMB_FUNC_EN_B and mlc_init
7219 * in EMB_FUNC_INIT_B
7220 *
7221 */
asm330lhhx_mlc_set(const stmdev_ctx_t * ctx,uint8_t val)7222 int32_t asm330lhhx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val)
7223 {
7224 asm330lhhx_emb_func_en_b_t reg;
7225 int32_t ret;
7226
7227 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7228 if (ret == 0)
7229 {
7230 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7231 }
7232 if (ret == 0)
7233 {
7234 reg.mlc_en = val;
7235 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7236 }
7237 if ((val != PROPERTY_DISABLE) && (ret == 0))
7238 {
7239 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7240 (uint8_t *)®, 1);
7241 if (ret == 0)
7242 {
7243 reg.mlc_en = val;
7244 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7245 (uint8_t *)®, 1);
7246 }
7247 }
7248 if (ret == 0)
7249 {
7250 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7251 }
7252 return ret;
7253 }
7254
7255 /**
7256 * @brief Enable Machine Learning Core.[get]
7257 *
7258 * @param ctx read / write interface definitions
7259 * @param val Get the values of mlc_en in
7260 * reg EMB_FUNC_EN_B
7261 *
7262 */
asm330lhhx_mlc_get(const stmdev_ctx_t * ctx,uint8_t * val)7263 int32_t asm330lhhx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val)
7264 {
7265 asm330lhhx_emb_func_en_b_t reg;
7266 int32_t ret;
7267
7268 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7269 if (ret == 0)
7270 {
7271 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
7272 }
7273 if (ret == 0)
7274 {
7275 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7276 *val = reg.mlc_en;
7277 }
7278 return ret;
7279 }
7280
7281 /**
7282 * @brief Machine Learning Core status register[get]
7283 *
7284 * @param ctx read / write interface definitions
7285 * @param val register MLC_STATUS_MAINPAGE
7286 *
7287 */
asm330lhhx_mlc_status_get(const stmdev_ctx_t * ctx,asm330lhhx_mlc_status_mainpage_t * val)7288 int32_t asm330lhhx_mlc_status_get(const stmdev_ctx_t *ctx,
7289 asm330lhhx_mlc_status_mainpage_t *val)
7290 {
7291 return asm330lhhx_read_reg(ctx, ASM330LHHX_MLC_STATUS_MAINPAGE,
7292 (uint8_t *) val, 1);
7293 }
7294
7295 /**
7296 * @brief Machine Learning Core data rate selection.[set]
7297 *
7298 * @param ctx read / write interface definitions
7299 * @param val get the values of mlc_odr in
7300 * reg EMB_FUNC_ODR_CFG_C
7301 *
7302 */
asm330lhhx_mlc_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhx_mlc_odr_t val)7303 int32_t asm330lhhx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7304 asm330lhhx_mlc_odr_t val)
7305 {
7306 asm330lhhx_emb_func_odr_cfg_c_t reg;
7307 int32_t ret;
7308
7309 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7310 if (ret == 0)
7311 {
7312 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_C,
7313 (uint8_t *)®, 1);
7314 }
7315 if (ret == 0)
7316 {
7317 reg.mlc_odr = (uint8_t)val;
7318 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_C,
7319 (uint8_t *)®, 1);
7320 }
7321 if (ret == 0)
7322 {
7323 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7324 }
7325
7326 return ret;
7327 }
7328
7329 /**
7330 * @brief Machine Learning Core data rate selection.[get]
7331 *
7332 * @param ctx read / write interface definitions
7333 * @param val change the values of mlc_odr in
7334 * reg EMB_FUNC_ODR_CFG_C
7335 *
7336 */
asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhx_mlc_odr_t * val)7337 int32_t asm330lhhx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7338 asm330lhhx_mlc_odr_t *val)
7339 {
7340 asm330lhhx_emb_func_odr_cfg_c_t reg;
7341 int32_t ret;
7342
7343 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7344 if (ret == 0)
7345 {
7346 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_ODR_CFG_C,
7347 (uint8_t *)®, 1);
7348 }
7349 if (ret == 0)
7350 {
7351 switch (reg.mlc_odr)
7352 {
7353 case ASM330LHHX_ODR_PRGS_12Hz5:
7354 *val = ASM330LHHX_ODR_PRGS_12Hz5;
7355 break;
7356 case ASM330LHHX_ODR_PRGS_26Hz:
7357 *val = ASM330LHHX_ODR_PRGS_26Hz;
7358 break;
7359 case ASM330LHHX_ODR_PRGS_52Hz:
7360 *val = ASM330LHHX_ODR_PRGS_52Hz;
7361 break;
7362 case ASM330LHHX_ODR_PRGS_104Hz:
7363 *val = ASM330LHHX_ODR_PRGS_104Hz;
7364 break;
7365 default:
7366 *val = ASM330LHHX_ODR_PRGS_12Hz5;
7367 break;
7368 }
7369 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7370 }
7371 return ret;
7372 }
7373
7374 /**
7375 * @brief MLC initialization request.[set]
7376 *
7377 * @param ctx Read / write interface definitions.(ptr)
7378 * @param val Change the values of mlc_init
7379 * @retval Interface status (MANDATORY: return 0 -> no Error).
7380 *
7381 */
asm330lhhx_mlc_init_set(const stmdev_ctx_t * ctx,uint8_t val)7382 int32_t asm330lhhx_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val)
7383 {
7384 asm330lhhx_emb_func_init_b_t emb_func_init_b;
7385 int32_t ret;
7386
7387 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7388
7389 if (ret == 0)
7390 {
7391 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7392 (uint8_t *)&emb_func_init_b, 1);
7393 }
7394 if (ret == 0)
7395 {
7396 emb_func_init_b.mlc_init = (uint8_t)val;
7397 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7398 (uint8_t *)&emb_func_init_b, 1);
7399 }
7400
7401 ret += asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7402
7403 return ret;
7404 }
7405
7406 /**
7407 * @brief MLC initialization request.[get]
7408 *
7409 * @param ctx Read / write interface definitions.(ptr)
7410 * @param val Get the values of mlc_init
7411 * @retval Interface status (MANDATORY: return 0 -> no Error).
7412 *
7413 */
asm330lhhx_mlc_init_get(const stmdev_ctx_t * ctx,uint8_t * val)7414 int32_t asm330lhhx_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
7415 {
7416 asm330lhhx_emb_func_init_b_t emb_func_init_b;
7417 int32_t ret;
7418
7419 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7420 if (ret == 0)
7421 {
7422 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_EMB_FUNC_INIT_B,
7423 (uint8_t *)&emb_func_init_b, 1);
7424 }
7425 if (ret == 0)
7426 {
7427 *val = emb_func_init_b.mlc_init;
7428 }
7429
7430 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7431
7432 return ret;
7433 }
7434
7435 /**
7436 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
7437 *
7438 * @param ctx_t *ctx: read / write interface definitions
7439 * @param uint8_t * : buffer that stores data read
7440 *
7441 */
asm330lhhx_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)7442 int32_t asm330lhhx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7443 {
7444 int32_t ret;
7445 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_EMBEDDED_FUNC_BANK);
7446 if (ret == 0)
7447 {
7448 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MLC0_SRC, buff, 8);
7449 }
7450 if (ret == 0)
7451 {
7452 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7453 }
7454 return ret;
7455 }
7456
7457 /**
7458 * @brief External magnetometer sensitivity value register for
7459 * Machine Learning Core.[set]
7460 *
7461 * @param ctx read / write interface definitions
7462 * @param buff buffer that contains data to write
7463 *
7464 */
asm330lhhx_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7465 int32_t asm330lhhx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7466 {
7467 uint8_t buff[2];
7468 int32_t ret;
7469
7470 buff[1] = (uint8_t)(val / 256U);
7471 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7472 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MLC_MAG_SENSITIVITY_L,
7473 &buff[0]);
7474 if (ret == 0)
7475 {
7476 ret = asm330lhhx_ln_pg_write_byte(ctx, ASM330LHHX_MLC_MAG_SENSITIVITY_H,
7477 &buff[1]);
7478 }
7479 return ret;
7480 }
7481
7482 /**
7483 * @brief External magnetometer sensitivity value register for
7484 * Machine Learning Core.[get]
7485 *
7486 * @param ctx read / write interface definitions
7487 * @param buff buffer that stores data read
7488 *
7489 */
asm330lhhx_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7490 int32_t asm330lhhx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7491 {
7492 uint8_t buff[2];
7493 int32_t ret;
7494
7495 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MLC_MAG_SENSITIVITY_L,
7496 &buff[0]);
7497 if (ret == 0)
7498 {
7499 ret = asm330lhhx_ln_pg_read_byte(ctx, ASM330LHHX_MLC_MAG_SENSITIVITY_H,
7500 &buff[1]);
7501 *val = buff[1];
7502 *val = (*val * 256U) + buff[0];
7503 }
7504 return ret;
7505 }
7506
7507 /**
7508 * @}
7509 *
7510 */
7511
7512 /**
7513 * @defgroup ASM330LHHX_Sensor_hub
7514 * @brief This section groups all the functions that manage the
7515 * sensor hub.
7516 * @{
7517 *
7518 */
7519
7520 /**
7521 * @brief Sensor hub output registers.[get]
7522 *
7523 * @param ctx Read / write interface definitions.(ptr)
7524 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
7525 * @retval Interface status (MANDATORY: return 0 -> no Error).
7526 *
7527 */
asm330lhhx_sh_read_data_raw_get(const stmdev_ctx_t * ctx,asm330lhhx_emb_sh_read_t * val)7528 int32_t asm330lhhx_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
7529 asm330lhhx_emb_sh_read_t *val)
7530 {
7531 int32_t ret;
7532
7533 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7534
7535 if (ret == 0)
7536 {
7537 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SENSOR_HUB_1, (uint8_t *)val, 18);
7538 }
7539 if (ret == 0)
7540 {
7541 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7542 }
7543 return ret;
7544 }
7545
7546 /**
7547 * @brief Number of external sensors to be read by the sensor hub.[set]
7548 *
7549 * @param ctx Read / write interface definitions.(ptr)
7550 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
7551 * @retval Interface status (MANDATORY: return 0 -> no Error).
7552 *
7553 */
asm330lhhx_sh_slave_connected_set(const stmdev_ctx_t * ctx,asm330lhhx_aux_sens_on_t val)7554 int32_t asm330lhhx_sh_slave_connected_set(const stmdev_ctx_t *ctx,
7555 asm330lhhx_aux_sens_on_t val)
7556 {
7557 asm330lhhx_master_config_t master_config;
7558 int32_t ret;
7559
7560 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7561
7562 if (ret == 0)
7563 {
7564 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7565 (uint8_t *)&master_config, 1);
7566 }
7567 if (ret == 0)
7568 {
7569 master_config.aux_sens_on = (uint8_t)val;
7570 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7571 (uint8_t *)&master_config, 1);
7572 }
7573 if (ret == 0)
7574 {
7575 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7576 }
7577 return ret;
7578 }
7579
7580 /**
7581 * @brief Number of external sensors to be read by the sensor hub.[get]
7582 *
7583 * @param ctx Read / write interface definitions.(ptr)
7584 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
7585 * @retval Interface status (MANDATORY: return 0 -> no Error).
7586 *
7587 */
asm330lhhx_sh_slave_connected_get(const stmdev_ctx_t * ctx,asm330lhhx_aux_sens_on_t * val)7588 int32_t asm330lhhx_sh_slave_connected_get(const stmdev_ctx_t *ctx,
7589 asm330lhhx_aux_sens_on_t *val)
7590 {
7591 asm330lhhx_master_config_t master_config;
7592 int32_t ret;
7593
7594 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7595
7596 if (ret == 0)
7597 {
7598 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7599 (uint8_t *)&master_config, 1);
7600 }
7601 if (ret == 0)
7602 {
7603 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7604 }
7605 switch (master_config.aux_sens_on)
7606 {
7607 case ASM330LHHX_SLV_0:
7608 *val = ASM330LHHX_SLV_0;
7609 break;
7610 case ASM330LHHX_SLV_0_1:
7611 *val = ASM330LHHX_SLV_0_1;
7612 break;
7613 case ASM330LHHX_SLV_0_1_2:
7614 *val = ASM330LHHX_SLV_0_1_2;
7615 break;
7616 case ASM330LHHX_SLV_0_1_2_3:
7617 *val = ASM330LHHX_SLV_0_1_2_3;
7618 break;
7619 default:
7620 *val = ASM330LHHX_SLV_0;
7621 break;
7622 }
7623 return ret;
7624 }
7625
7626 /**
7627 * @brief Sensor hub I2C master enable.[set]
7628 *
7629 * @param ctx Read / write interface definitions.(ptr)
7630 * @param val Change the values of master_on in reg MASTER_CONFIG
7631 * @retval Interface status (MANDATORY: return 0 -> no Error).
7632 *
7633 */
asm330lhhx_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)7634 int32_t asm330lhhx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
7635 {
7636 asm330lhhx_master_config_t master_config;
7637 int32_t ret;
7638
7639 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7640
7641 if (ret == 0)
7642 {
7643 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7644 (uint8_t *)&master_config, 1);
7645 }
7646 if (ret == 0)
7647 {
7648 master_config.master_on = (uint8_t)val;
7649 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7650 (uint8_t *)&master_config, 1);
7651 }
7652 if (ret == 0)
7653 {
7654 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7655 }
7656 return ret;
7657 }
7658
7659 /**
7660 * @brief Sensor hub I2C master enable.[get]
7661 *
7662 * @param ctx Read / write interface definitions.(ptr)
7663 * @param val Change the values of master_on in reg MASTER_CONFIG
7664 * @retval Interface status (MANDATORY: return 0 -> no Error).
7665 *
7666 */
asm330lhhx_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)7667 int32_t asm330lhhx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
7668 {
7669 asm330lhhx_master_config_t master_config;
7670 int32_t ret;
7671
7672 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7673
7674 if (ret == 0)
7675 {
7676 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7677 (uint8_t *)&master_config, 1);
7678 }
7679 if (ret == 0)
7680 {
7681 *val = master_config.master_on;
7682 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7683 }
7684 return ret;
7685 }
7686
7687 /**
7688 * @brief Master I2C pull-up enable.[set]
7689 *
7690 * @param ctx Read / write interface definitions.(ptr)
7691 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
7692 * @retval Interface status (MANDATORY: return 0 -> no Error).
7693 *
7694 */
asm330lhhx_sh_pin_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_shub_pu_en_t val)7695 int32_t asm330lhhx_sh_pin_mode_set(const stmdev_ctx_t *ctx,
7696 asm330lhhx_shub_pu_en_t val)
7697 {
7698 asm330lhhx_master_config_t master_config;
7699 int32_t ret;
7700
7701 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7702
7703 if (ret == 0)
7704 {
7705 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7706 (uint8_t *)&master_config, 1);
7707 }
7708 if (ret == 0)
7709 {
7710 master_config.shub_pu_en = (uint8_t)val;
7711 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7712 (uint8_t *)&master_config, 1);
7713 }
7714 if (ret == 0)
7715 {
7716 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7717 }
7718 return ret;
7719 }
7720
7721 /**
7722 * @brief Master I2C pull-up enable.[get]
7723 *
7724 * @param ctx Read / write interface definitions.(ptr)
7725 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
7726 * @retval Interface status (MANDATORY: return 0 -> no Error).
7727 *
7728 */
asm330lhhx_sh_pin_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_shub_pu_en_t * val)7729 int32_t asm330lhhx_sh_pin_mode_get(const stmdev_ctx_t *ctx,
7730 asm330lhhx_shub_pu_en_t *val)
7731 {
7732 asm330lhhx_master_config_t master_config;
7733 int32_t ret;
7734
7735 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7736 if (ret == 0)
7737 {
7738 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7739 (uint8_t *)&master_config, 1);
7740 }
7741 if (ret == 0)
7742 {
7743 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7744 }
7745 switch (master_config.shub_pu_en)
7746 {
7747 case ASM330LHHX_EXT_PULL_UP:
7748 *val = ASM330LHHX_EXT_PULL_UP;
7749 break;
7750 case ASM330LHHX_INTERNAL_PULL_UP:
7751 *val = ASM330LHHX_INTERNAL_PULL_UP;
7752 break;
7753 default:
7754 *val = ASM330LHHX_EXT_PULL_UP;
7755 break;
7756 }
7757 return ret;
7758 }
7759
7760 /**
7761 * @brief I2C interface pass-through.[set]
7762 *
7763 * @param ctx Read / write interface definitions.(ptr)
7764 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7765 * @retval Interface status (MANDATORY: return 0 -> no Error).
7766 *
7767 */
asm330lhhx_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)7768 int32_t asm330lhhx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
7769 {
7770 asm330lhhx_master_config_t master_config;
7771 int32_t ret;
7772
7773 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7774
7775 if (ret == 0)
7776 {
7777 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7778 (uint8_t *)&master_config, 1);
7779 }
7780 if (ret == 0)
7781 {
7782 master_config.pass_through_mode = (uint8_t)val;
7783 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7784 (uint8_t *)&master_config, 1);
7785 }
7786 if (ret == 0)
7787 {
7788 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7789 }
7790 return ret;
7791 }
7792
7793 /**
7794 * @brief I2C interface pass-through.[get]
7795 *
7796 * @param ctx Read / write interface definitions.(ptr)
7797 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7798 * @retval Interface status (MANDATORY: return 0 -> no Error).
7799 *
7800 */
asm330lhhx_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)7801 int32_t asm330lhhx_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
7802 {
7803 asm330lhhx_master_config_t master_config;
7804 int32_t ret;
7805
7806 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7807
7808 if (ret == 0)
7809 {
7810 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7811 (uint8_t *)&master_config, 1);
7812 }
7813 if (ret == 0)
7814 {
7815 *val = master_config.pass_through_mode;
7816 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7817 }
7818 return ret;
7819 }
7820
7821 /**
7822 * @brief Sensor hub trigger signal selection.[set]
7823 *
7824 * @param ctx Read / write interface definitions.(ptr)
7825 * @param val Change the values of start_config in reg MASTER_CONFIG
7826 * @retval Interface status (MANDATORY: return 0 -> no Error).
7827 *
7828 */
asm330lhhx_sh_syncro_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_start_config_t val)7829 int32_t asm330lhhx_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
7830 asm330lhhx_start_config_t val)
7831 {
7832 asm330lhhx_master_config_t master_config;
7833 int32_t ret;
7834
7835 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7836
7837 if (ret == 0)
7838 {
7839 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7840 (uint8_t *)&master_config, 1);
7841 }
7842 if (ret == 0)
7843 {
7844 master_config.start_config = (uint8_t)val;
7845 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7846 (uint8_t *)&master_config, 1);
7847 }
7848 if (ret == 0)
7849 {
7850 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7851 }
7852 return ret;
7853 }
7854
7855 /**
7856 * @brief Sensor hub trigger signal selection.[get]
7857 *
7858 * @param ctx Read / write interface definitions.(ptr)
7859 * @param val Get the values of start_config in reg MASTER_CONFIG
7860 * @retval Interface status (MANDATORY: return 0 -> no Error).
7861 *
7862 */
asm330lhhx_sh_syncro_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_start_config_t * val)7863 int32_t asm330lhhx_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
7864 asm330lhhx_start_config_t *val)
7865 {
7866 asm330lhhx_master_config_t master_config;
7867 int32_t ret;
7868
7869 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7870
7871 if (ret == 0)
7872 {
7873 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7874 (uint8_t *)&master_config, 1);
7875 }
7876 if (ret == 0)
7877 {
7878 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7879 }
7880 switch (master_config.start_config)
7881 {
7882 case ASM330LHHX_EXT_ON_INT2_PIN:
7883 *val = ASM330LHHX_EXT_ON_INT2_PIN;
7884 break;
7885 case ASM330LHHX_XL_GY_DRDY:
7886 *val = ASM330LHHX_XL_GY_DRDY;
7887 break;
7888 default:
7889 *val = ASM330LHHX_EXT_ON_INT2_PIN;
7890 break;
7891 }
7892 return ret;
7893 }
7894
7895 /**
7896 * @brief Slave 0 write operation is performed only at the first sensor
7897 * hub cycle.[set]
7898 *
7899 * @param ctx Read / write interface definitions.(ptr)
7900 * @param val Change the values of write_once in reg MASTER_CONFIG
7901 * @retval Interface status (MANDATORY: return 0 -> no Error).
7902 *
7903 */
asm330lhhx_sh_write_mode_set(const stmdev_ctx_t * ctx,asm330lhhx_write_once_t val)7904 int32_t asm330lhhx_sh_write_mode_set(const stmdev_ctx_t *ctx,
7905 asm330lhhx_write_once_t val)
7906 {
7907 asm330lhhx_master_config_t master_config;
7908 int32_t ret;
7909
7910 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7911
7912 if (ret == 0)
7913 {
7914 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7915 (uint8_t *)&master_config, 1);
7916 }
7917 if (ret == 0)
7918 {
7919 master_config.write_once = (uint8_t)val;
7920 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7921 (uint8_t *)&master_config, 1);
7922 }
7923 if (ret == 0)
7924 {
7925 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7926 }
7927 return ret;
7928 }
7929
7930 /**
7931 * @brief Slave 0 write operation is performed only at the first sensor
7932 * hub cycle.[get]
7933 *
7934 * @param ctx Read / write interface definitions.(ptr)
7935 * @param val Get the values of write_once in reg MASTER_CONFIG
7936 * @retval Interface status (MANDATORY: return 0 -> no Error).
7937 *
7938 */
asm330lhhx_sh_write_mode_get(const stmdev_ctx_t * ctx,asm330lhhx_write_once_t * val)7939 int32_t asm330lhhx_sh_write_mode_get(const stmdev_ctx_t *ctx,
7940 asm330lhhx_write_once_t *val)
7941 {
7942 asm330lhhx_master_config_t master_config;
7943 int32_t ret;
7944
7945 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7946
7947 if (ret == 0)
7948 {
7949 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7950 (uint8_t *)&master_config, 1);
7951 }
7952 if (ret == 0)
7953 {
7954 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
7955 }
7956 switch (master_config.write_once)
7957 {
7958 case ASM330LHHX_EACH_SH_CYCLE:
7959 *val = ASM330LHHX_EACH_SH_CYCLE;
7960 break;
7961 case ASM330LHHX_ONLY_FIRST_CYCLE:
7962 *val = ASM330LHHX_ONLY_FIRST_CYCLE;
7963 break;
7964 default:
7965 *val = ASM330LHHX_EACH_SH_CYCLE;
7966 break;
7967 }
7968 return ret;
7969 }
7970
7971 /**
7972 * @brief Reset Master logic and output registers.[set]
7973 *
7974 * @param ctx Read / write interface definitions.(ptr)
7975 * @retval Interface status (MANDATORY: return 0 -> no Error).
7976 *
7977 */
asm330lhhx_sh_reset_set(const stmdev_ctx_t * ctx)7978 int32_t asm330lhhx_sh_reset_set(const stmdev_ctx_t *ctx)
7979 {
7980 asm330lhhx_master_config_t master_config;
7981 int32_t ret;
7982
7983 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
7984
7985 if (ret == 0)
7986 {
7987 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7988 (uint8_t *)&master_config, 1);
7989 }
7990 if (ret == 0)
7991 {
7992 master_config.rst_master_regs = PROPERTY_ENABLE;
7993 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
7994 (uint8_t *)&master_config, 1);
7995 }
7996 if (ret == 0)
7997 {
7998 master_config.rst_master_regs = PROPERTY_DISABLE;
7999 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_MASTER_CONFIG,
8000 (uint8_t *)&master_config, 1);
8001 }
8002 if (ret == 0)
8003 {
8004 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8005 }
8006 return ret;
8007 }
8008
8009 /**
8010 * @brief Reset Master logic and output registers.[get]
8011 *
8012 * @param ctx Read / write interface definitions.(ptr)
8013 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
8014 * @retval Interface status (MANDATORY: return 0 -> no Error).
8015 *
8016 */
asm330lhhx_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)8017 int32_t asm330lhhx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
8018 {
8019 asm330lhhx_master_config_t master_config;
8020 int32_t ret;
8021
8022 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8023
8024 if (ret == 0)
8025 {
8026 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_MASTER_CONFIG,
8027 (uint8_t *)&master_config, 1);
8028 *val = master_config.rst_master_regs;
8029 }
8030 if (ret == 0)
8031 {
8032 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8033 }
8034 return ret;
8035 }
8036
8037 /**
8038 * @brief Rate at which the master communicates.[set]
8039 *
8040 * @param ctx Read / write interface definitions.(ptr)
8041 * @param val Change the values of shub_odr in reg SLV0_CONFIG
8042 * @retval Interface status (MANDATORY: return 0 -> no Error).
8043 *
8044 */
asm330lhhx_sh_data_rate_set(const stmdev_ctx_t * ctx,asm330lhhx_shub_odr_t val)8045 int32_t asm330lhhx_sh_data_rate_set(const stmdev_ctx_t *ctx,
8046 asm330lhhx_shub_odr_t val)
8047 {
8048 asm330lhhx_slv0_config_t slv0_config;
8049 int32_t ret;
8050
8051 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8052
8053 if (ret == 0)
8054 {
8055 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG,
8056 (uint8_t *)&slv0_config, 1);
8057 }
8058 if (ret == 0)
8059 {
8060 slv0_config.shub_odr = (uint8_t)val;
8061 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG,
8062 (uint8_t *)&slv0_config, 1);
8063 }
8064 if (ret == 0)
8065 {
8066 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8067 }
8068 return ret;
8069 }
8070
8071 /**
8072 * @brief Rate at which the master communicates.[get]
8073 *
8074 * @param ctx Read / write interface definitions.(ptr)
8075 * @param val Get the values of shub_odr in reg slv1_CONFIG
8076 * @retval Interface status (MANDATORY: return 0 -> no Error).
8077 *
8078 */
asm330lhhx_sh_data_rate_get(const stmdev_ctx_t * ctx,asm330lhhx_shub_odr_t * val)8079 int32_t asm330lhhx_sh_data_rate_get(const stmdev_ctx_t *ctx,
8080 asm330lhhx_shub_odr_t *val)
8081 {
8082 asm330lhhx_slv0_config_t slv0_config;
8083 int32_t ret;
8084
8085 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8086
8087 if (ret == 0)
8088 {
8089 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG,
8090 (uint8_t *)&slv0_config, 1);
8091 }
8092 if (ret == 0)
8093 {
8094 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8095 }
8096 switch (slv0_config.shub_odr)
8097 {
8098 case ASM330LHHX_SH_ODR_104Hz:
8099 *val = ASM330LHHX_SH_ODR_104Hz;
8100 break;
8101 case ASM330LHHX_SH_ODR_52Hz:
8102 *val = ASM330LHHX_SH_ODR_52Hz;
8103 break;
8104 case ASM330LHHX_SH_ODR_26Hz:
8105 *val = ASM330LHHX_SH_ODR_26Hz;
8106 break;
8107 case ASM330LHHX_SH_ODR_13Hz:
8108 *val = ASM330LHHX_SH_ODR_13Hz;
8109 break;
8110 default:
8111 *val = ASM330LHHX_SH_ODR_104Hz;
8112 break;
8113 }
8114 return ret;
8115 }
8116
8117 /**
8118 * @brief Configure slave 0 for perform a write.[set]
8119 *
8120 * @param ctx Read / write interface definitions.(ptr)
8121 * @param val Structure that contain
8122 * - uint8_t slv0_add; 8 bit i2c device address
8123 * - uint8_t slv0_subadd; 8 bit register device address
8124 * - uint8_t slv0_data; 8 bit data to write
8125 * @retval Interface status (MANDATORY: return 0 -> no Error).
8126 *
8127 */
asm330lhhx_sh_cfg_write(const stmdev_ctx_t * ctx,asm330lhhx_sh_cfg_write_t * val)8128 int32_t asm330lhhx_sh_cfg_write(const stmdev_ctx_t *ctx,
8129 asm330lhhx_sh_cfg_write_t *val)
8130 {
8131 asm330lhhx_slv0_add_t slv0_add;
8132 int32_t ret;
8133
8134 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8135
8136 if (ret == 0)
8137 {
8138 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
8139 slv0_add.rw_0 = 0;
8140 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_ADD,
8141 (uint8_t *) & (slv0_add), 1);
8142 }
8143 if (ret == 0)
8144 {
8145 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_SUBADD,
8146 (uint8_t *) & (val->slv0_subadd), 1);
8147 }
8148 if (ret == 0)
8149 {
8150 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_DATAWRITE_SLV0,
8151 (uint8_t *) & (val->slv0_data), 1);
8152 }
8153 if (ret == 0)
8154 {
8155 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8156 }
8157 return ret;
8158 }
8159
8160 /**
8161 * @brief Configure slave 0 for perform a write/read.[get]
8162 *
8163 * @param ctx Read / write interface definitions.(ptr)
8164 * @param val Structure that contain
8165 * - uint8_t slv_add; 8 bit i2c device address
8166 * - uint8_t slv_subadd; 8 bit register device address
8167 * - uint8_t slv_len; num of bit to read
8168 * @retval Interface status (MANDATORY: return 0 -> no Error).
8169 *
8170 */
asm330lhhx_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,asm330lhhx_sh_cfg_read_t * val)8171 int32_t asm330lhhx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
8172 asm330lhhx_sh_cfg_read_t *val)
8173 {
8174 asm330lhhx_slv0_config_t slv0_config;
8175 asm330lhhx_slv0_add_t slv0_add;
8176 int32_t ret;
8177
8178 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8179
8180 if (ret == 0)
8181 {
8182 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
8183 slv0_add.rw_0 = 1;
8184 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_ADD,
8185 (uint8_t *) & (slv0_add), 1);
8186 }
8187 if (ret == 0)
8188 {
8189 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_SUBADD,
8190 &(val->slv_subadd), 1);
8191 }
8192 if (ret == 0)
8193 {
8194 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV0_CONFIG,
8195 (uint8_t *)&slv0_config, 1);
8196 }
8197 if (ret == 0)
8198 {
8199 slv0_config.slave0_numop = val->slv_len;
8200 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV0_CONFIG,
8201 (uint8_t *)&slv0_config, 1);
8202 }
8203 if (ret == 0)
8204 {
8205 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8206 }
8207 return ret;
8208 }
8209
8210 /**
8211 * @brief Configure slave 0 for perform a write/read.[get]
8212 *
8213 * @param ctx Read / write interface definitions.(ptr)
8214 * @param val Structure that contain
8215 * - uint8_t slv_add; 8 bit i2c device address
8216 * - uint8_t slv_subadd; 8 bit register device address
8217 * - uint8_t slv_len; num of bit to read
8218 * @retval Interface status (MANDATORY: return 0 -> no Error).
8219 *
8220 */
asm330lhhx_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,asm330lhhx_sh_cfg_read_t * val)8221 int32_t asm330lhhx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
8222 asm330lhhx_sh_cfg_read_t *val)
8223 {
8224 asm330lhhx_slv1_config_t slv1_config;
8225 asm330lhhx_slv1_add_t slv1_add;
8226 int32_t ret;
8227
8228 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8229 if (ret == 0)
8230 {
8231 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
8232 slv1_add.r_1 = 1;
8233 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
8234 }
8235 if (ret == 0)
8236 {
8237 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_SUBADD,
8238 &(val->slv_subadd), 1);
8239 }
8240 if (ret == 0)
8241 {
8242 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV1_CONFIG,
8243 (uint8_t *)&slv1_config, 1);
8244 }
8245 if (ret == 0)
8246 {
8247 slv1_config.slave1_numop = val->slv_len;
8248 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV1_CONFIG,
8249 (uint8_t *)&slv1_config, 1);
8250 }
8251 if (ret == 0)
8252 {
8253 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8254 }
8255 return ret;
8256 }
8257
8258 /**
8259 * @brief Configure slave 2 for perform a write/read.[get]
8260 *
8261 * @param ctx Read / write interface definitions.(ptr)
8262 * @param val Structure that contain
8263 * - uint8_t slv_add; 8 bit i2c device address
8264 * - uint8_t slv_subadd; 8 bit register device address
8265 * - uint8_t slv_len; num of bit to read
8266 * @retval Interface status (MANDATORY: return 0 -> no Error).
8267 *
8268 */
asm330lhhx_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,asm330lhhx_sh_cfg_read_t * val)8269 int32_t asm330lhhx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
8270 asm330lhhx_sh_cfg_read_t *val)
8271 {
8272 asm330lhhx_slv2_config_t slv2_config;
8273 asm330lhhx_slv2_add_t slv2_add;
8274 int32_t ret;
8275
8276 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8277
8278 if (ret == 0)
8279 {
8280 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
8281 slv2_add.r_2 = 1;
8282 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_ADD,
8283 (uint8_t *)&slv2_add, 1);
8284 }
8285 if (ret == 0)
8286 {
8287 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_SUBADD,
8288 (uint8_t *) & (val->slv_subadd), 1);
8289 }
8290 if (ret == 0)
8291 {
8292 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV2_CONFIG,
8293 (uint8_t *)&slv2_config, 1);
8294 }
8295 if (ret == 0)
8296 {
8297 slv2_config.slave2_numop = val->slv_len;
8298 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV2_CONFIG,
8299 (uint8_t *)&slv2_config, 1);
8300 }
8301 if (ret == 0)
8302 {
8303 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8304 }
8305 return ret;
8306 }
8307
8308 /**
8309 * @brief Configure slave 3 for perform a write/read.[get]
8310 *
8311 * @param ctx Read / write interface definitions.(ptr)
8312 * @param val Structure that contain
8313 * - uint8_t slv_add; 8 bit i2c device address
8314 * - uint8_t slv_subadd; 8 bit register device address
8315 * - uint8_t slv_len; num of bit to read
8316 * @retval Interface status (MANDATORY: return 0 -> no Error).
8317 *
8318 */
asm330lhhx_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,asm330lhhx_sh_cfg_read_t * val)8319 int32_t asm330lhhx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
8320 asm330lhhx_sh_cfg_read_t *val)
8321 {
8322 asm330lhhx_slv3_config_t slv3_config;
8323 asm330lhhx_slv3_add_t slv3_add;
8324 int32_t ret;
8325
8326 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8327
8328 if (ret == 0)
8329 {
8330 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
8331 slv3_add.r_3 = 1;
8332 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_ADD,
8333 (uint8_t *)&slv3_add, 1);
8334 }
8335 if (ret == 0)
8336 {
8337 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_SUBADD,
8338 &(val->slv_subadd), 1);
8339 }
8340 if (ret == 0)
8341 {
8342 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_SLV3_CONFIG,
8343 (uint8_t *)&slv3_config, 1);
8344 }
8345 if (ret == 0)
8346 {
8347 slv3_config.slave3_numop = val->slv_len;
8348 ret = asm330lhhx_write_reg(ctx, ASM330LHHX_SLV3_CONFIG,
8349 (uint8_t *)&slv3_config, 1);
8350 }
8351 if (ret == 0)
8352 {
8353 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8354 }
8355 return ret;
8356 }
8357
8358 /**
8359 * @brief Sensor hub source register.[get]
8360 *
8361 * @param ctx Read / write interface definitions.(ptr)
8362 * @param val Registers from STATUS_MASTER
8363 * @retval Interface status (MANDATORY: return 0 -> no Error).
8364 *
8365 */
asm330lhhx_sh_status_get(const stmdev_ctx_t * ctx,asm330lhhx_status_master_t * val)8366 int32_t asm330lhhx_sh_status_get(const stmdev_ctx_t *ctx,
8367 asm330lhhx_status_master_t *val)
8368 {
8369 int32_t ret;
8370
8371 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_SENSOR_HUB_BANK);
8372
8373 if (ret == 0)
8374 {
8375 ret = asm330lhhx_read_reg(ctx, ASM330LHHX_STATUS_MASTER, (uint8_t *)val, 1);
8376 }
8377 if (ret == 0)
8378 {
8379 ret = asm330lhhx_mem_bank_set(ctx, ASM330LHHX_USER_BANK);
8380 }
8381 return ret;
8382 }
8383
8384 /**
8385 * @}
8386 *
8387 */
8388
8389 /**
8390 * @}
8391 *
8392 */
8393
8394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8395
