1 /* 2 ****************************************************************************** 3 * @file asm330lhh_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * asm330lhh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ASM330LHH_REGS_H 23 #define ASM330LHH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ASM330LHH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ASM330LHH Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ASM330LHH_I2C_ADD_L 0xD5U 173 #define ASM330LHH_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ASM330LHH_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define ASM330LHH_PIN_CTRL 0x02U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t sdo_pu_en : 1; 189 uint8_t not_used_02 : 1; 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t not_used_02 : 1; 192 uint8_t sdo_pu_en : 1; 193 uint8_t not_used_01 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } asm330lhh_pin_ctrl_t; 196 197 #define ASM330LHH_FIFO_CTRL1 0x07U 198 typedef struct 199 { 200 uint8_t wtm : 8; 201 } asm330lhh_fifo_ctrl1_t; 202 203 #define ASM330LHH_FIFO_CTRL2 0x08U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t wtm : 1; 208 uint8_t not_used_01 : 3; 209 uint8_t odrchg_en : 1; 210 uint8_t not_used_02 : 2; 211 uint8_t stop_on_wtm : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t stop_on_wtm : 1; 214 uint8_t not_used_02 : 2; 215 uint8_t odrchg_en : 1; 216 uint8_t not_used_01 : 3; 217 uint8_t wtm : 1; 218 #endif /* DRV_BYTE_ORDER */ 219 } asm330lhh_fifo_ctrl2_t; 220 221 #define ASM330LHH_FIFO_CTRL3 0x09U 222 typedef struct 223 { 224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 225 uint8_t bdr_xl : 4; 226 uint8_t bdr_gy : 4; 227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 228 uint8_t bdr_gy : 4; 229 uint8_t bdr_xl : 4; 230 #endif /* DRV_BYTE_ORDER */ 231 } asm330lhh_fifo_ctrl3_t; 232 233 #define ASM330LHH_FIFO_CTRL4 0x0AU 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t fifo_mode : 3; 238 uint8_t not_used_01 : 1; 239 uint8_t odr_t_batch : 2; 240 uint8_t dec_ts_batch : 2; 241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 242 uint8_t dec_ts_batch : 2; 243 uint8_t odr_t_batch : 2; 244 uint8_t not_used_01 : 1; 245 uint8_t fifo_mode : 3; 246 #endif /* DRV_BYTE_ORDER */ 247 } asm330lhh_fifo_ctrl4_t; 248 249 #define ASM330LHH_COUNTER_BDR_REG1 0x0BU 250 typedef struct 251 { 252 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 253 uint8_t cnt_bdr_th : 2; 254 uint8_t not_used_01 : 3; 255 uint8_t trig_counter_bdr : 1; 256 uint8_t rst_counter_bdr : 1; 257 uint8_t dataready_pulsed : 1; 258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 259 uint8_t dataready_pulsed : 1; 260 uint8_t rst_counter_bdr : 1; 261 uint8_t trig_counter_bdr : 1; 262 uint8_t not_used_01 : 3; 263 uint8_t cnt_bdr_th : 2; 264 #endif /* DRV_BYTE_ORDER */ 265 } asm330lhh_counter_bdr_reg1_t; 266 267 #define ASM330LHH_COUNTER_BDR_REG2 0x0CU 268 typedef struct 269 { 270 uint8_t cnt_bdr_th : 8; 271 } asm330lhh_counter_bdr_reg2_t; 272 273 #define ASM330LHH_INT1_CTRL 0x0DU 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t int1_drdy_xl : 1; 278 uint8_t int1_drdy_g : 1; 279 uint8_t int1_boot : 1; 280 uint8_t int1_fifo_th : 1; 281 uint8_t int1_fifo_ovr : 1; 282 uint8_t int1_fifo_full : 1; 283 uint8_t int1_cnt_bdr : 1; 284 uint8_t den_drdy_flag : 1; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t den_drdy_flag : 1; 287 uint8_t int1_cnt_bdr : 1; 288 uint8_t int1_fifo_full : 1; 289 uint8_t int1_fifo_ovr : 1; 290 uint8_t int1_fifo_th : 1; 291 uint8_t int1_boot : 1; 292 uint8_t int1_drdy_g : 1; 293 uint8_t int1_drdy_xl : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 } asm330lhh_int1_ctrl_t; 296 297 #define ASM330LHH_INT2_CTRL 0x0EU 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t int2_drdy_xl : 1; 302 uint8_t int2_drdy_g : 1; 303 uint8_t int2_drdy_temp : 1; 304 uint8_t int2_fifo_th : 1; 305 uint8_t int2_fifo_ovr : 1; 306 uint8_t int2_fifo_full : 1; 307 uint8_t int2_cnt_bdr : 1; 308 uint8_t not_used_01 : 1; 309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 310 uint8_t not_used_01 : 1; 311 uint8_t int2_cnt_bdr : 1; 312 uint8_t int2_fifo_full : 1; 313 uint8_t int2_fifo_ovr : 1; 314 uint8_t int2_fifo_th : 1; 315 uint8_t int2_drdy_temp : 1; 316 uint8_t int2_drdy_g : 1; 317 uint8_t int2_drdy_xl : 1; 318 #endif /* DRV_BYTE_ORDER */ 319 } asm330lhh_int2_ctrl_t; 320 321 #define ASM330LHH_WHO_AM_I 0x0FU 322 323 #define ASM330LHH_CTRL1_XL 0x10U 324 typedef struct 325 { 326 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 327 uint8_t not_used_01 : 1; 328 uint8_t lpf2_xl_en : 1; 329 uint8_t fs_xl : 2; 330 uint8_t odr_xl : 4; 331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 332 uint8_t odr_xl : 4; 333 uint8_t fs_xl : 2; 334 uint8_t lpf2_xl_en : 1; 335 uint8_t not_used_01 : 1; 336 #endif /* DRV_BYTE_ORDER */ 337 } asm330lhh_ctrl1_xl_t; 338 339 #define ASM330LHH_CTRL2_G 0x11U 340 typedef struct 341 { 342 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 343 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 344 uint8_t odr_g : 4; 345 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 346 uint8_t odr_g : 4; 347 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 348 #endif /* DRV_BYTE_ORDER */ 349 } asm330lhh_ctrl2_g_t; 350 351 #define ASM330LHH_CTRL3_C 0x12U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t sw_reset : 1; 356 uint8_t not_used_01 : 1; 357 uint8_t if_inc : 1; 358 uint8_t sim : 1; 359 uint8_t pp_od : 1; 360 uint8_t h_lactive : 1; 361 uint8_t bdu : 1; 362 uint8_t boot : 1; 363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 364 uint8_t boot : 1; 365 uint8_t bdu : 1; 366 uint8_t h_lactive : 1; 367 uint8_t pp_od : 1; 368 uint8_t sim : 1; 369 uint8_t if_inc : 1; 370 uint8_t not_used_01 : 1; 371 uint8_t sw_reset : 1; 372 #endif /* DRV_BYTE_ORDER */ 373 } asm330lhh_ctrl3_c_t; 374 375 #define ASM330LHH_CTRL4_C 0x13U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t not_used_01 : 1; 380 uint8_t lpf1_sel_g : 1; 381 uint8_t i2c_disable : 1; 382 uint8_t drdy_mask : 1; 383 uint8_t not_used_02 : 1; 384 uint8_t int2_on_int1 : 1; 385 uint8_t sleep_g : 1; 386 uint8_t not_used_03 : 1; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t not_used_03 : 1; 389 uint8_t sleep_g : 1; 390 uint8_t int2_on_int1 : 1; 391 uint8_t not_used_02 : 1; 392 uint8_t drdy_mask : 1; 393 uint8_t i2c_disable : 1; 394 uint8_t lpf1_sel_g : 1; 395 uint8_t not_used_01 : 1; 396 #endif /* DRV_BYTE_ORDER */ 397 } asm330lhh_ctrl4_c_t; 398 399 #define ASM330LHH_CTRL5_C 0x14U 400 typedef struct 401 { 402 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 403 uint8_t st_xl : 2; 404 uint8_t st_g : 2; 405 uint8_t not_used_01 : 1; 406 uint8_t rounding : 2; 407 uint8_t not_used_02 : 1; 408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 409 uint8_t not_used_02 : 1; 410 uint8_t rounding : 2; 411 uint8_t not_used_01 : 1; 412 uint8_t st_g : 2; 413 uint8_t st_xl : 2; 414 #endif /* DRV_BYTE_ORDER */ 415 } asm330lhh_ctrl5_c_t; 416 417 #define ASM330LHH_CTRL6_C 0x15U 418 typedef struct 419 { 420 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 421 uint8_t ftype : 3; 422 uint8_t usr_off_w : 1; 423 uint8_t not_used_01 : 1; 424 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 427 uint8_t not_used_01 : 1; 428 uint8_t usr_off_w : 1; 429 uint8_t ftype : 3; 430 #endif /* DRV_BYTE_ORDER */ 431 } asm330lhh_ctrl6_c_t; 432 433 #define ASM330LHH_CTRL7_G 0x16U 434 typedef struct 435 { 436 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 437 uint8_t not_used_00 : 1; 438 uint8_t usr_off_on_out : 1; 439 uint8_t not_used_01 : 2; 440 uint8_t hpm_g : 2; 441 uint8_t hp_en_g : 1; 442 uint8_t not_used_02 : 1; 443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 444 uint8_t not_used_02 : 1; 445 uint8_t hp_en_g : 1; 446 uint8_t hpm_g : 2; 447 uint8_t not_used_01 : 2; 448 uint8_t usr_off_on_out : 1; 449 uint8_t not_used_00 : 1; 450 #endif /* DRV_BYTE_ORDER */ 451 } asm330lhh_ctrl7_g_t; 452 453 #define ASM330LHH_CTRL8_XL 0x17U 454 typedef struct 455 { 456 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 457 uint8_t low_pass_on_6d : 1; 458 uint8_t not_used_01 : 1; 459 uint8_t hp_slope_xl_en : 1; 460 uint8_t fastsettl_mode_xl : 1; 461 uint8_t hp_ref_mode_xl : 1; 462 uint8_t hpcf_xl : 3; 463 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 464 uint8_t hpcf_xl : 3; 465 uint8_t hp_ref_mode_xl : 1; 466 uint8_t fastsettl_mode_xl : 1; 467 uint8_t hp_slope_xl_en : 1; 468 uint8_t not_used_01 : 1; 469 uint8_t low_pass_on_6d : 1; 470 #endif /* DRV_BYTE_ORDER */ 471 } asm330lhh_ctrl8_xl_t; 472 473 #define ASM330LHH_CTRL9_XL 0x18U 474 typedef struct 475 { 476 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 477 uint8_t not_used_01 : 1; 478 uint8_t device_conf : 1; 479 uint8_t den_lh : 1; 480 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 481 uint8_t den_z : 1; 482 uint8_t den_y : 1; 483 uint8_t den_x : 1; 484 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 485 uint8_t den_x : 1; 486 uint8_t den_y : 1; 487 uint8_t den_z : 1; 488 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 489 uint8_t den_lh : 1; 490 uint8_t device_conf : 1; 491 uint8_t not_used_01 : 1; 492 #endif /* DRV_BYTE_ORDER */ 493 } asm330lhh_ctrl9_xl_t; 494 495 #define ASM330LHH_CTRL10_C 0x19U 496 typedef struct 497 { 498 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 499 uint8_t not_used_01 : 5; 500 uint8_t timestamp_en : 1; 501 uint8_t not_used_02 : 2; 502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 503 uint8_t not_used_02 : 2; 504 uint8_t timestamp_en : 1; 505 uint8_t not_used_01 : 5; 506 #endif /* DRV_BYTE_ORDER */ 507 } asm330lhh_ctrl10_c_t; 508 509 #define ASM330LHH_ALL_INT_SRC 0x1AU 510 typedef struct 511 { 512 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 513 uint8_t ff_ia : 1; 514 uint8_t wu_ia : 1; 515 uint8_t not_used_00 : 2; 516 uint8_t d6d_ia : 1; 517 uint8_t sleep_change_ia : 1; 518 uint8_t not_used_01 : 1; 519 uint8_t timestamp_endcount : 1; 520 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 521 uint8_t timestamp_endcount : 1; 522 uint8_t not_used_01 : 1; 523 uint8_t sleep_change_ia : 1; 524 uint8_t d6d_ia : 1; 525 uint8_t not_used_00 : 2; 526 uint8_t wu_ia : 1; 527 uint8_t ff_ia : 1; 528 #endif /* DRV_BYTE_ORDER */ 529 } asm330lhh_all_int_src_t; 530 531 #define ASM330LHH_WAKE_UP_SRC 0x1BU 532 typedef struct 533 { 534 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 535 uint8_t z_wu : 1; 536 uint8_t y_wu : 1; 537 uint8_t x_wu : 1; 538 uint8_t wu_ia : 1; 539 uint8_t sleep_state : 1; 540 uint8_t ff_ia : 1; 541 uint8_t sleep_change_ia : 1; 542 uint8_t not_used_01 : 1; 543 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 544 uint8_t not_used_01 : 1; 545 uint8_t sleep_change_ia : 1; 546 uint8_t ff_ia : 1; 547 uint8_t sleep_state : 1; 548 uint8_t wu_ia : 1; 549 uint8_t x_wu : 1; 550 uint8_t y_wu : 1; 551 uint8_t z_wu : 1; 552 #endif /* DRV_BYTE_ORDER */ 553 } asm330lhh_wake_up_src_t; 554 555 #define ASM330LHH_D6D_SRC 0x1DU 556 typedef struct 557 { 558 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 559 uint8_t xl : 1; 560 uint8_t xh : 1; 561 uint8_t yl : 1; 562 uint8_t yh : 1; 563 uint8_t zl : 1; 564 uint8_t zh : 1; 565 uint8_t d6d_ia : 1; 566 uint8_t den_drdy : 1; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t den_drdy : 1; 569 uint8_t d6d_ia : 1; 570 uint8_t zh : 1; 571 uint8_t zl : 1; 572 uint8_t yh : 1; 573 uint8_t yl : 1; 574 uint8_t xh : 1; 575 uint8_t xl : 1; 576 #endif /* DRV_BYTE_ORDER */ 577 } asm330lhh_d6d_src_t; 578 579 #define ASM330LHH_STATUS_REG 0x1EU 580 typedef struct 581 { 582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 583 uint8_t xlda : 1; 584 uint8_t gda : 1; 585 uint8_t tda : 1; 586 uint8_t not_used_01 : 5; 587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 588 uint8_t not_used_01 : 5; 589 uint8_t tda : 1; 590 uint8_t gda : 1; 591 uint8_t xlda : 1; 592 #endif /* DRV_BYTE_ORDER */ 593 } asm330lhh_status_reg_t; 594 595 #define ASM330LHH_OUT_TEMP_L 0x20U 596 #define ASM330LHH_OUT_TEMP_H 0x21U 597 #define ASM330LHH_OUTX_L_G 0x22U 598 #define ASM330LHH_OUTX_H_G 0x23U 599 #define ASM330LHH_OUTY_L_G 0x24U 600 #define ASM330LHH_OUTY_H_G 0x25U 601 #define ASM330LHH_OUTZ_L_G 0x26U 602 #define ASM330LHH_OUTZ_H_G 0x27U 603 #define ASM330LHH_OUTX_L_A 0x28U 604 #define ASM330LHH_OUTX_H_A 0x29U 605 #define ASM330LHH_OUTY_L_A 0x2AU 606 #define ASM330LHH_OUTY_H_A 0x2BU 607 #define ASM330LHH_OUTZ_L_A 0x2CU 608 #define ASM330LHH_OUTZ_H_A 0x2DU 609 610 #define ASM330LHH_FIFO_STATUS1 0x3AU 611 typedef struct 612 { 613 uint8_t diff_fifo : 8; 614 } asm330lhh_fifo_status1_t; 615 616 #define ASM330LHH_FIFO_STATUS2 0x3BU 617 typedef struct 618 { 619 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 620 uint8_t diff_fifo : 2; 621 uint8_t not_used_01 : 1; 622 uint8_t over_run_latched : 1; 623 uint8_t counter_bdr_ia : 1; 624 uint8_t fifo_full_ia : 1; 625 uint8_t fifo_ovr_ia : 1; 626 uint8_t fifo_wtm_ia : 1; 627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 628 uint8_t fifo_wtm_ia : 1; 629 uint8_t fifo_ovr_ia : 1; 630 uint8_t fifo_full_ia : 1; 631 uint8_t counter_bdr_ia : 1; 632 uint8_t over_run_latched : 1; 633 uint8_t not_used_01 : 1; 634 uint8_t diff_fifo : 2; 635 #endif /* DRV_BYTE_ORDER */ 636 } asm330lhh_fifo_status2_t; 637 638 #define ASM330LHH_TIMESTAMP0 0x40U 639 #define ASM330LHH_TIMESTAMP1 0x41U 640 #define ASM330LHH_TIMESTAMP2 0x42U 641 #define ASM330LHH_TIMESTAMP3 0x43U 642 #define ASM330LHH_INT_CFG0 0x56U 643 typedef struct 644 { 645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 646 uint8_t lir : 1; 647 uint8_t not_used_01 : 3; 648 uint8_t slope_fds : 1; 649 uint8_t sleep_status_on_int : 1; 650 uint8_t int_clr_on_read : 1; 651 uint8_t not_used_02 : 1; 652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 653 uint8_t not_used_02 : 1; 654 uint8_t int_clr_on_read : 1; 655 uint8_t sleep_status_on_int : 1; 656 uint8_t slope_fds : 1; 657 uint8_t not_used_01 : 3; 658 uint8_t lir : 1; 659 #endif /* DRV_BYTE_ORDER */ 660 } asm330lhh_int_cfg0_t; 661 662 #define ASM330LHH_INT_CFG1 0x58U 663 typedef struct 664 { 665 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 666 uint8_t not_used_01 : 5; 667 uint8_t inact_en : 2; 668 uint8_t interrupts_enable : 1; 669 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 670 uint8_t interrupts_enable : 1; 671 uint8_t inact_en : 2; 672 uint8_t not_used_01 : 5; 673 #endif /* DRV_BYTE_ORDER */ 674 } asm330lhh_int_cfg1_t; 675 676 #define ASM330LHH_THS_6D 0x59U 677 typedef struct 678 { 679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 680 uint8_t not_used_01 : 5; 681 uint8_t sixd_ths : 2; 682 uint8_t d4d_en : 1; 683 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 684 uint8_t d4d_en : 1; 685 uint8_t sixd_ths : 2; 686 uint8_t not_used_01 : 5; 687 #endif /* DRV_BYTE_ORDER */ 688 } asm330lhh_ths_6d_t; 689 690 #define ASM330LHH_WAKE_UP_THS 0x5BU 691 typedef struct 692 { 693 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 694 uint8_t wk_ths : 6; 695 uint8_t usr_off_on_wu : 1; 696 uint8_t not_used_01 : 1; 697 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 698 uint8_t not_used_01 : 1; 699 uint8_t usr_off_on_wu : 1; 700 uint8_t wk_ths : 6; 701 #endif /* DRV_BYTE_ORDER */ 702 } asm330lhh_wake_up_ths_t; 703 704 #define ASM330LHH_WAKE_UP_DUR 0x5CU 705 typedef struct 706 { 707 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 708 uint8_t sleep_dur : 4; 709 uint8_t wake_ths_w : 1; 710 uint8_t wake_dur : 2; 711 uint8_t ff_dur : 1; 712 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 713 uint8_t ff_dur : 1; 714 uint8_t wake_dur : 2; 715 uint8_t wake_ths_w : 1; 716 uint8_t sleep_dur : 4; 717 #endif /* DRV_BYTE_ORDER */ 718 } asm330lhh_wake_up_dur_t; 719 720 #define ASM330LHH_FREE_FALL 0x5DU 721 typedef struct 722 { 723 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 724 uint8_t ff_ths : 3; 725 uint8_t ff_dur : 5; 726 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 727 uint8_t ff_dur : 5; 728 uint8_t ff_ths : 3; 729 #endif /* DRV_BYTE_ORDER */ 730 } asm330lhh_free_fall_t; 731 732 #define ASM330LHH_MD1_CFG 0x5EU 733 typedef struct 734 { 735 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 736 uint8_t not_used_00 : 2; 737 uint8_t int1_6d : 1; 738 uint8_t not_used_01 : 1; 739 uint8_t int1_ff : 1; 740 uint8_t int1_wu : 1; 741 uint8_t not_used_02 : 1; 742 uint8_t int1_sleep_change : 1; 743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 744 uint8_t int1_sleep_change : 1; 745 uint8_t not_used_02 : 1; 746 uint8_t int1_wu : 1; 747 uint8_t int1_ff : 1; 748 uint8_t not_used_01 : 1; 749 uint8_t int1_6d : 1; 750 uint8_t not_used_00 : 2; 751 #endif /* DRV_BYTE_ORDER */ 752 } asm330lhh_md1_cfg_t; 753 754 #define ASM330LHH_MD2_CFG 0x5FU 755 typedef struct 756 { 757 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 758 uint8_t int2_timestamp : 1; 759 uint8_t int2_emb_func : 1; 760 uint8_t int2_6d : 1; 761 uint8_t not_used_01 : 1; 762 uint8_t int2_ff : 1; 763 uint8_t int2_wu : 1; 764 uint8_t not_used_02 : 1; 765 uint8_t int2_sleep_change : 1; 766 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 767 uint8_t int2_sleep_change : 1; 768 uint8_t not_used_02 : 1; 769 uint8_t int2_wu : 1; 770 uint8_t int2_ff : 1; 771 uint8_t not_used_01 : 1; 772 uint8_t int2_6d : 1; 773 uint8_t int2_emb_func : 1; 774 uint8_t int2_timestamp : 1; 775 #endif /* DRV_BYTE_ORDER */ 776 } asm330lhh_md2_cfg_t; 777 778 #define ASM330LHH_INTERNAL_FREQ_FINE 0x63U 779 typedef struct 780 { 781 uint8_t freq_fine : 8; 782 } asm330lhh_internal_freq_fine_t; 783 784 #define ASM330LHH_X_OFS_USR 0x73U 785 #define ASM330LHH_Y_OFS_USR 0x74U 786 #define ASM330LHH_Z_OFS_USR 0x75U 787 #define ASM330LHH_FIFO_DATA_OUT_TAG 0x78U 788 typedef struct 789 { 790 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 791 uint8_t tag_parity : 1; 792 uint8_t tag_cnt : 2; 793 uint8_t tag_sensor : 5; 794 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 795 uint8_t tag_sensor : 5; 796 uint8_t tag_cnt : 2; 797 uint8_t tag_parity : 1; 798 #endif /* DRV_BYTE_ORDER */ 799 } asm330lhh_fifo_data_out_tag_t; 800 801 #define ASM330LHH_FIFO_DATA_OUT_X_L 0x79U 802 #define ASM330LHH_FIFO_DATA_OUT_X_H 0x7AU 803 #define ASM330LHH_FIFO_DATA_OUT_Y_L 0x7BU 804 #define ASM330LHH_FIFO_DATA_OUT_Y_H 0x7CU 805 #define ASM330LHH_FIFO_DATA_OUT_Z_L 0x7DU 806 #define ASM330LHH_FIFO_DATA_OUT_Z_H 0x7EU 807 808 /** 809 * @defgroup ASM330LHH_Register_Union 810 * @brief This union group all the registers that has a bit-field 811 * description. 812 * This union is useful but not need by the driver. 813 * 814 * REMOVING this union you are compliant with: 815 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 816 * 817 * @{ 818 * 819 */ 820 typedef union 821 { 822 asm330lhh_pin_ctrl_t pin_ctrl; 823 asm330lhh_fifo_ctrl1_t fifo_ctrl1; 824 asm330lhh_fifo_ctrl2_t fifo_ctrl2; 825 asm330lhh_fifo_ctrl3_t fifo_ctrl3; 826 asm330lhh_fifo_ctrl4_t fifo_ctrl4; 827 asm330lhh_counter_bdr_reg1_t counter_bdr_reg1; 828 asm330lhh_counter_bdr_reg2_t counter_bdr_reg2; 829 asm330lhh_int1_ctrl_t int1_ctrl; 830 asm330lhh_int2_ctrl_t int2_ctrl; 831 asm330lhh_ctrl1_xl_t ctrl1_xl; 832 asm330lhh_ctrl2_g_t ctrl2_g; 833 asm330lhh_ctrl3_c_t ctrl3_c; 834 asm330lhh_ctrl4_c_t ctrl4_c; 835 asm330lhh_ctrl5_c_t ctrl5_c; 836 asm330lhh_ctrl6_c_t ctrl6_c; 837 asm330lhh_ctrl7_g_t ctrl7_g; 838 asm330lhh_ctrl8_xl_t ctrl8_xl; 839 asm330lhh_ctrl9_xl_t ctrl9_xl; 840 asm330lhh_ctrl10_c_t ctrl10_c; 841 asm330lhh_all_int_src_t all_int_src; 842 asm330lhh_wake_up_src_t wake_up_src; 843 asm330lhh_d6d_src_t d6d_src; 844 asm330lhh_status_reg_t status_reg; 845 asm330lhh_fifo_status1_t fifo_status1; 846 asm330lhh_fifo_status2_t fifo_status2; 847 asm330lhh_int_cfg0_t int_cfg0; 848 asm330lhh_int_cfg1_t int_cfg1; 849 asm330lhh_ths_6d_t ths_6d; 850 asm330lhh_wake_up_ths_t wake_up_ths; 851 asm330lhh_wake_up_dur_t wake_up_dur; 852 asm330lhh_free_fall_t free_fall; 853 asm330lhh_md1_cfg_t md1_cfg; 854 asm330lhh_md2_cfg_t md2_cfg; 855 asm330lhh_internal_freq_fine_t internal_freq_fine; 856 asm330lhh_fifo_data_out_tag_t fifo_data_out_tag; 857 bitwise_t bitwise; 858 uint8_t byte; 859 } asm330lhh_reg_t; 860 861 /** 862 * @} 863 * 864 */ 865 866 #ifndef __weak 867 #define __weak __attribute__((weak)) 868 #endif /* __weak */ 869 870 /* 871 * These are the basic platform dependent I/O routines to read 872 * and write device registers connected on a standard bus. 873 * The driver keeps offering a default implementation based on function 874 * pointers to read/write routines for backward compatibility. 875 * The __weak directive allows the final application to overwrite 876 * them with a custom implementation. 877 */ 878 879 int32_t asm330lhh_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 880 uint16_t len); 881 int32_t asm330lhh_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 882 uint16_t len); 883 884 float_t asm330lhh_from_fs2g_to_mg(int16_t lsb); 885 float_t asm330lhh_from_fs4g_to_mg(int16_t lsb); 886 float_t asm330lhh_from_fs8g_to_mg(int16_t lsb); 887 float_t asm330lhh_from_fs16g_to_mg(int16_t lsb); 888 float_t asm330lhh_from_fs125dps_to_mdps(int16_t lsb); 889 float_t asm330lhh_from_fs250dps_to_mdps(int16_t lsb); 890 float_t asm330lhh_from_fs500dps_to_mdps(int16_t lsb); 891 float_t asm330lhh_from_fs1000dps_to_mdps(int16_t lsb); 892 float_t asm330lhh_from_fs2000dps_to_mdps(int16_t lsb); 893 float_t asm330lhh_from_fs4000dps_to_mdps(int16_t lsb); 894 float_t asm330lhh_from_lsb_to_celsius(int16_t lsb); 895 float_t asm330lhh_from_lsb_to_nsec(int32_t lsb); 896 897 typedef enum 898 { 899 ASM330LHH_2g = 0, 900 ASM330LHH_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHH_2g */ 901 ASM330LHH_4g = 2, 902 ASM330LHH_8g = 3, 903 } asm330lhh_fs_xl_t; 904 int32_t asm330lhh_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_xl_t val); 905 int32_t asm330lhh_xl_full_scale_get(const stmdev_ctx_t *ctx, 906 asm330lhh_fs_xl_t *val); 907 908 typedef enum 909 { 910 ASM330LHH_XL_ODR_OFF = 0, 911 ASM330LHH_XL_ODR_12Hz5 = 1, 912 ASM330LHH_XL_ODR_26Hz = 2, 913 ASM330LHH_XL_ODR_52Hz = 3, 914 ASM330LHH_XL_ODR_104Hz = 4, 915 ASM330LHH_XL_ODR_208Hz = 5, 916 ASM330LHH_XL_ODR_417Hz = 6, 917 ASM330LHH_XL_ODR_833Hz = 7, 918 ASM330LHH_XL_ODR_1667Hz = 8, 919 ASM330LHH_XL_ODR_3333Hz = 9, 920 ASM330LHH_XL_ODR_6667Hz = 10, 921 } asm330lhh_odr_xl_t; 922 int32_t asm330lhh_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhh_odr_xl_t val); 923 int32_t asm330lhh_xl_data_rate_get(const stmdev_ctx_t *ctx, 924 asm330lhh_odr_xl_t *val); 925 926 typedef enum 927 { 928 ASM330LHH_125dps = 2, 929 ASM330LHH_250dps = 0, 930 ASM330LHH_500dps = 4, 931 ASM330LHH_1000dps = 8, 932 ASM330LHH_2000dps = 12, 933 ASM330LHH_4000dps = 1, 934 } asm330lhh_fs_g_t; 935 int32_t asm330lhh_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t val); 936 int32_t asm330lhh_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhh_fs_g_t *val); 937 938 typedef enum 939 { 940 ASM330LHH_GY_ODR_OFF = 0, 941 ASM330LHH_GY_ODR_12Hz5 = 1, 942 ASM330LHH_GY_ODR_26Hz = 2, 943 ASM330LHH_GY_ODR_52Hz = 3, 944 ASM330LHH_GY_ODR_104Hz = 4, 945 ASM330LHH_GY_ODR_208Hz = 5, 946 ASM330LHH_GY_ODR_417Hz = 6, 947 ASM330LHH_GY_ODR_833Hz = 7, 948 ASM330LHH_GY_ODR_1667Hz = 8, 949 ASM330LHH_GY_ODR_3333Hz = 9, 950 ASM330LHH_GY_ODR_6667Hz = 10, 951 } asm330lhh_odr_g_t; 952 int32_t asm330lhh_gy_data_rate_set(const stmdev_ctx_t *ctx, 953 asm330lhh_odr_g_t val); 954 int32_t asm330lhh_gy_data_rate_get(const stmdev_ctx_t *ctx, 955 asm330lhh_odr_g_t *val); 956 957 int32_t asm330lhh_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 958 int32_t asm330lhh_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 959 960 typedef enum 961 { 962 ASM330LHH_LSb_1mg = 0, 963 ASM330LHH_LSb_16mg = 1, 964 } asm330lhh_usr_off_w_t; 965 int32_t asm330lhh_xl_offset_weight_set(const stmdev_ctx_t *ctx, 966 asm330lhh_usr_off_w_t val); 967 int32_t asm330lhh_xl_offset_weight_get(const stmdev_ctx_t *ctx, 968 asm330lhh_usr_off_w_t *val); 969 970 typedef struct 971 { 972 asm330lhh_all_int_src_t all_int_src; 973 asm330lhh_wake_up_src_t wake_up_src; 974 asm330lhh_d6d_src_t d6d_src; 975 asm330lhh_status_reg_t status_reg; 976 } asm330lhh_all_sources_t; 977 int32_t asm330lhh_all_sources_get(const stmdev_ctx_t *ctx, 978 asm330lhh_all_sources_t *val); 979 980 int32_t asm330lhh_status_reg_get(const stmdev_ctx_t *ctx, 981 asm330lhh_status_reg_t *val); 982 983 int32_t asm330lhh_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 984 985 int32_t asm330lhh_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 986 987 int32_t asm330lhh_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 988 989 int32_t asm330lhh_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 990 int32_t asm330lhh_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 991 992 int32_t asm330lhh_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 993 int32_t asm330lhh_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 994 995 int32_t asm330lhh_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 996 int32_t asm330lhh_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 997 998 int32_t asm330lhh_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 999 int32_t asm330lhh_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1000 1001 int32_t asm330lhh_timestamp_rst(const stmdev_ctx_t *ctx); 1002 1003 int32_t asm330lhh_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 1004 int32_t asm330lhh_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 1005 1006 int32_t asm330lhh_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 1007 1008 typedef enum 1009 { 1010 ASM330LHH_NO_ROUND = 0, 1011 ASM330LHH_ROUND_XL = 1, 1012 ASM330LHH_ROUND_GY = 2, 1013 ASM330LHH_ROUND_GY_XL = 3, 1014 } asm330lhh_rounding_t; 1015 int32_t asm330lhh_rounding_mode_set(const stmdev_ctx_t *ctx, 1016 asm330lhh_rounding_t val); 1017 int32_t asm330lhh_rounding_mode_get(const stmdev_ctx_t *ctx, 1018 asm330lhh_rounding_t *val); 1019 1020 int32_t asm330lhh_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1021 1022 int32_t asm330lhh_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1023 1024 int32_t asm330lhh_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1025 1026 int32_t asm330lhh_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 1027 1028 int32_t asm330lhh_device_conf_set(const stmdev_ctx_t *ctx, uint8_t val); 1029 int32_t asm330lhh_device_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); 1030 1031 int32_t asm330lhh_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 1032 int32_t asm330lhh_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 1033 1034 typedef enum 1035 { 1036 ASM330LHH_DRDY_LATCHED = 0, 1037 ASM330LHH_DRDY_PULSED = 1, 1038 } asm330lhh_dataready_pulsed_t; 1039 int32_t asm330lhh_data_ready_mode_set(const stmdev_ctx_t *ctx, 1040 asm330lhh_dataready_pulsed_t val); 1041 int32_t asm330lhh_data_ready_mode_get(const stmdev_ctx_t *ctx, 1042 asm330lhh_dataready_pulsed_t *val); 1043 1044 int32_t asm330lhh_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1045 1046 int32_t asm330lhh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1047 int32_t asm330lhh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1048 1049 int32_t asm330lhh_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 1050 int32_t asm330lhh_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 1051 1052 int32_t asm330lhh_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1053 int32_t asm330lhh_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1054 1055 typedef enum 1056 { 1057 ASM330LHH_XL_ST_DISABLE = 0, 1058 ASM330LHH_XL_ST_POSITIVE = 1, 1059 ASM330LHH_XL_ST_NEGATIVE = 2, 1060 } asm330lhh_st_xl_t; 1061 int32_t asm330lhh_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t val); 1062 int32_t asm330lhh_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_xl_t *val); 1063 1064 typedef enum 1065 { 1066 ASM330LHH_GY_ST_DISABLE = 0, 1067 ASM330LHH_GY_ST_POSITIVE = 1, 1068 ASM330LHH_GY_ST_NEGATIVE = 3, 1069 } asm330lhh_st_g_t; 1070 int32_t asm330lhh_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhh_st_g_t val); 1071 int32_t asm330lhh_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhh_st_g_t *val); 1072 1073 int32_t asm330lhh_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 1074 int32_t asm330lhh_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 1075 1076 int32_t asm330lhh_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 1077 int32_t asm330lhh_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 1078 1079 int32_t asm330lhh_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 1080 int32_t asm330lhh_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 1081 1082 typedef enum 1083 { 1084 ASM330LHH_ULTRA_LIGHT = 0, 1085 ASM330LHH_VERY_LIGHT = 1, 1086 ASM330LHH_LIGHT = 2, 1087 ASM330LHH_MEDIUM = 3, 1088 ASM330LHH_STRONG = 4, 1089 ASM330LHH_VERY_STRONG = 5, 1090 ASM330LHH_AGGRESSIVE = 6, 1091 ASM330LHH_XTREME = 7, 1092 } asm330lhh_ftype_t; 1093 int32_t asm330lhh_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 1094 asm330lhh_ftype_t val); 1095 int32_t asm330lhh_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 1096 asm330lhh_ftype_t *val); 1097 1098 int32_t asm330lhh_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 1099 int32_t asm330lhh_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 1100 1101 typedef enum 1102 { 1103 ASM330LHH_HP_PATH_DISABLE_ON_OUT = 0x00, 1104 ASM330LHH_SLOPE_ODR_DIV_4 = 0x10, 1105 ASM330LHH_HP_ODR_DIV_10 = 0x11, 1106 ASM330LHH_HP_ODR_DIV_20 = 0x12, 1107 ASM330LHH_HP_ODR_DIV_45 = 0x13, 1108 ASM330LHH_HP_ODR_DIV_100 = 0x14, 1109 ASM330LHH_HP_ODR_DIV_200 = 0x15, 1110 ASM330LHH_HP_ODR_DIV_400 = 0x16, 1111 ASM330LHH_HP_ODR_DIV_800 = 0x17, 1112 ASM330LHH_HP_REF_MD_ODR_DIV_10 = 0x31, 1113 ASM330LHH_HP_REF_MD_ODR_DIV_20 = 0x32, 1114 ASM330LHH_HP_REF_MD_ODR_DIV_45 = 0x33, 1115 ASM330LHH_HP_REF_MD_ODR_DIV_100 = 0x34, 1116 ASM330LHH_HP_REF_MD_ODR_DIV_200 = 0x35, 1117 ASM330LHH_HP_REF_MD_ODR_DIV_400 = 0x36, 1118 ASM330LHH_HP_REF_MD_ODR_DIV_800 = 0x37, 1119 ASM330LHH_LP_ODR_DIV_10 = 0x01, 1120 ASM330LHH_LP_ODR_DIV_20 = 0x02, 1121 ASM330LHH_LP_ODR_DIV_45 = 0x03, 1122 ASM330LHH_LP_ODR_DIV_100 = 0x04, 1123 ASM330LHH_LP_ODR_DIV_200 = 0x05, 1124 ASM330LHH_LP_ODR_DIV_400 = 0x06, 1125 ASM330LHH_LP_ODR_DIV_800 = 0x07, 1126 } asm330lhh_hp_slope_xl_en_t; 1127 int32_t asm330lhh_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 1128 asm330lhh_hp_slope_xl_en_t val); 1129 int32_t asm330lhh_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 1130 asm330lhh_hp_slope_xl_en_t *val); 1131 1132 int32_t asm330lhh_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 1133 int32_t asm330lhh_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 1134 1135 typedef enum 1136 { 1137 ASM330LHH_USE_SLOPE = 0, 1138 ASM330LHH_USE_HPF = 1, 1139 } asm330lhh_slope_fds_t; 1140 int32_t asm330lhh_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 1141 asm330lhh_slope_fds_t val); 1142 int32_t asm330lhh_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 1143 asm330lhh_slope_fds_t *val); 1144 1145 typedef enum 1146 { 1147 ASM330LHH_HP_FILTER_NONE = 0x00, 1148 ASM330LHH_HP_FILTER_16mHz = 0x80, 1149 ASM330LHH_HP_FILTER_65mHz = 0x81, 1150 ASM330LHH_HP_FILTER_260mHz = 0x82, 1151 ASM330LHH_HP_FILTER_1Hz04 = 0x83, 1152 } asm330lhh_hpm_g_t; 1153 int32_t asm330lhh_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 1154 asm330lhh_hpm_g_t val); 1155 int32_t asm330lhh_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 1156 asm330lhh_hpm_g_t *val); 1157 1158 typedef enum 1159 { 1160 ASM330LHH_PULL_UP_DISC = 0, 1161 ASM330LHH_PULL_UP_CONNECT = 1, 1162 } asm330lhh_sdo_pu_en_t; 1163 int32_t asm330lhh_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 1164 asm330lhh_sdo_pu_en_t val); 1165 int32_t asm330lhh_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 1166 asm330lhh_sdo_pu_en_t *val); 1167 1168 typedef enum 1169 { 1170 ASM330LHH_SPI_4_WIRE = 0, 1171 ASM330LHH_SPI_3_WIRE = 1, 1172 } asm330lhh_sim_t; 1173 int32_t asm330lhh_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhh_sim_t val); 1174 int32_t asm330lhh_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhh_sim_t *val); 1175 1176 typedef enum 1177 { 1178 ASM330LHH_I2C_ENABLE = 0, 1179 ASM330LHH_I2C_DISABLE = 1, 1180 } asm330lhh_i2c_disable_t; 1181 int32_t asm330lhh_i2c_interface_set(const stmdev_ctx_t *ctx, 1182 asm330lhh_i2c_disable_t val); 1183 int32_t asm330lhh_i2c_interface_get(const stmdev_ctx_t *ctx, 1184 asm330lhh_i2c_disable_t *val); 1185 1186 typedef struct 1187 { 1188 asm330lhh_int1_ctrl_t int1_ctrl; 1189 asm330lhh_md1_cfg_t md1_cfg; 1190 } asm330lhh_pin_int1_route_t; 1191 int32_t asm330lhh_pin_int1_route_set(const stmdev_ctx_t *ctx, 1192 asm330lhh_pin_int1_route_t *val); 1193 int32_t asm330lhh_pin_int1_route_get(const stmdev_ctx_t *ctx, 1194 asm330lhh_pin_int1_route_t *val); 1195 1196 typedef struct 1197 { 1198 asm330lhh_int2_ctrl_t int2_ctrl; 1199 asm330lhh_md2_cfg_t md2_cfg; 1200 } asm330lhh_pin_int2_route_t; 1201 int32_t asm330lhh_pin_int2_route_set(const stmdev_ctx_t *ctx, 1202 asm330lhh_pin_int2_route_t *val); 1203 int32_t asm330lhh_pin_int2_route_get(const stmdev_ctx_t *ctx, 1204 asm330lhh_pin_int2_route_t *val); 1205 1206 typedef enum 1207 { 1208 ASM330LHH_PUSH_PULL = 0, 1209 ASM330LHH_OPEN_DRAIN = 1, 1210 } asm330lhh_pp_od_t; 1211 int32_t asm330lhh_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t val); 1212 int32_t asm330lhh_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhh_pp_od_t *val); 1213 1214 typedef enum 1215 { 1216 ASM330LHH_ACTIVE_HIGH = 0, 1217 ASM330LHH_ACTIVE_LOW = 1, 1218 } asm330lhh_h_lactive_t; 1219 int32_t asm330lhh_pin_polarity_set(const stmdev_ctx_t *ctx, 1220 asm330lhh_h_lactive_t val); 1221 int32_t asm330lhh_pin_polarity_get(const stmdev_ctx_t *ctx, 1222 asm330lhh_h_lactive_t *val); 1223 1224 int32_t asm330lhh_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 1225 int32_t asm330lhh_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 1226 1227 typedef enum 1228 { 1229 ASM330LHH_ALL_INT_PULSED = 0, 1230 ASM330LHH_BASE_LATCHED_EMB_PULSED = 1, 1231 ASM330LHH_BASE_PULSED_EMB_LATCHED = 2, 1232 ASM330LHH_ALL_INT_LATCHED = 3, 1233 } asm330lhh_lir_t; 1234 int32_t asm330lhh_int_notification_set(const stmdev_ctx_t *ctx, 1235 asm330lhh_lir_t val); 1236 int32_t asm330lhh_int_notification_get(const stmdev_ctx_t *ctx, 1237 asm330lhh_lir_t *val); 1238 1239 typedef enum 1240 { 1241 ASM330LHH_LSb_FS_DIV_64 = 0, 1242 ASM330LHH_LSb_FS_DIV_256 = 1, 1243 } asm330lhh_wake_ths_w_t; 1244 int32_t asm330lhh_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 1245 asm330lhh_wake_ths_w_t val); 1246 int32_t asm330lhh_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 1247 asm330lhh_wake_ths_w_t *val); 1248 1249 int32_t asm330lhh_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1250 int32_t asm330lhh_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1251 1252 int32_t asm330lhh_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 1253 uint8_t val); 1254 int32_t asm330lhh_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 1255 uint8_t *val); 1256 1257 int32_t asm330lhh_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1258 int32_t asm330lhh_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1259 1260 int32_t asm330lhh_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1261 int32_t asm330lhh_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1262 1263 typedef enum 1264 { 1265 ASM330LHH_DRIVE_SLEEP_CHG_EVENT = 0, 1266 ASM330LHH_DRIVE_SLEEP_STATUS = 1, 1267 } asm330lhh_sleep_status_on_int_t; 1268 int32_t asm330lhh_act_pin_notification_set(const stmdev_ctx_t *ctx, 1269 asm330lhh_sleep_status_on_int_t val); 1270 int32_t asm330lhh_act_pin_notification_get(const stmdev_ctx_t *ctx, 1271 asm330lhh_sleep_status_on_int_t *val); 1272 1273 typedef enum 1274 { 1275 ASM330LHH_XL_AND_GY_NOT_AFFECTED = 0, 1276 ASM330LHH_XL_12Hz5_GY_NOT_AFFECTED = 1, 1277 ASM330LHH_XL_12Hz5_GY_SLEEP = 2, 1278 ASM330LHH_XL_12Hz5_GY_PD = 3, 1279 } asm330lhh_inact_en_t; 1280 int32_t asm330lhh_act_mode_set(const stmdev_ctx_t *ctx, 1281 asm330lhh_inact_en_t val); 1282 int32_t asm330lhh_act_mode_get(const stmdev_ctx_t *ctx, 1283 asm330lhh_inact_en_t *val); 1284 1285 int32_t asm330lhh_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1286 int32_t asm330lhh_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1287 1288 typedef enum 1289 { 1290 ASM330LHH_DEG_80 = 0, 1291 ASM330LHH_DEG_70 = 1, 1292 ASM330LHH_DEG_60 = 2, 1293 ASM330LHH_DEG_50 = 3, 1294 } asm330lhh_sixd_ths_t; 1295 int32_t asm330lhh_6d_threshold_set(const stmdev_ctx_t *ctx, 1296 asm330lhh_sixd_ths_t val); 1297 int32_t asm330lhh_6d_threshold_get(const stmdev_ctx_t *ctx, 1298 asm330lhh_sixd_ths_t *val); 1299 1300 int32_t asm330lhh_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 1301 int32_t asm330lhh_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 1302 1303 typedef enum 1304 { 1305 ASM330LHH_FF_TSH_156mg = 0, 1306 ASM330LHH_FF_TSH_219mg = 1, 1307 ASM330LHH_FF_TSH_250mg = 2, 1308 ASM330LHH_FF_TSH_312mg = 3, 1309 ASM330LHH_FF_TSH_344mg = 4, 1310 ASM330LHH_FF_TSH_406mg = 5, 1311 ASM330LHH_FF_TSH_469mg = 6, 1312 ASM330LHH_FF_TSH_500mg = 7, 1313 } asm330lhh_ff_ths_t; 1314 int32_t asm330lhh_ff_threshold_set(const stmdev_ctx_t *ctx, 1315 asm330lhh_ff_ths_t val); 1316 int32_t asm330lhh_ff_threshold_get(const stmdev_ctx_t *ctx, 1317 asm330lhh_ff_ths_t *val); 1318 1319 int32_t asm330lhh_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1320 int32_t asm330lhh_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1321 1322 int32_t asm330lhh_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 1323 int32_t asm330lhh_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 1324 1325 int32_t asm330lhh_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 1326 uint8_t val); 1327 int32_t asm330lhh_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 1328 uint8_t *val); 1329 1330 int32_t asm330lhh_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 1331 int32_t asm330lhh_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 1332 1333 typedef enum 1334 { 1335 ASM330LHH_XL_NOT_BATCHED = 0, 1336 ASM330LHH_XL_BATCHED_AT_12Hz5 = 1, 1337 ASM330LHH_XL_BATCHED_AT_26Hz = 2, 1338 ASM330LHH_XL_BATCHED_AT_52Hz = 3, 1339 ASM330LHH_XL_BATCHED_AT_104Hz = 4, 1340 ASM330LHH_XL_BATCHED_AT_208Hz = 5, 1341 ASM330LHH_XL_BATCHED_AT_417Hz = 6, 1342 ASM330LHH_XL_BATCHED_AT_833Hz = 7, 1343 ASM330LHH_XL_BATCHED_AT_1667Hz = 8, 1344 ASM330LHH_XL_BATCHED_AT_3333Hz = 9, 1345 ASM330LHH_XL_BATCHED_AT_6667Hz = 10, 1346 } asm330lhh_bdr_xl_t; 1347 int32_t asm330lhh_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 1348 asm330lhh_bdr_xl_t val); 1349 int32_t asm330lhh_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 1350 asm330lhh_bdr_xl_t *val); 1351 1352 typedef enum 1353 { 1354 ASM330LHH_GY_NOT_BATCHED = 0, 1355 ASM330LHH_GY_BATCHED_AT_12Hz5 = 1, 1356 ASM330LHH_GY_BATCHED_AT_26Hz = 2, 1357 ASM330LHH_GY_BATCHED_AT_52Hz = 3, 1358 ASM330LHH_GY_BATCHED_AT_104Hz = 4, 1359 ASM330LHH_GY_BATCHED_AT_208Hz = 5, 1360 ASM330LHH_GY_BATCHED_AT_417Hz = 6, 1361 ASM330LHH_GY_BATCHED_AT_833Hz = 7, 1362 ASM330LHH_GY_BATCHED_AT_1667Hz = 8, 1363 ASM330LHH_GY_BATCHED_AT_3333Hz = 9, 1364 ASM330LHH_GY_BATCHED_AT_6667Hz = 10, 1365 ASM330LHH_GY_BATCHED_AT_6Hz5 = 11, 1366 } asm330lhh_bdr_gy_t; 1367 int32_t asm330lhh_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 1368 asm330lhh_bdr_gy_t val); 1369 int32_t asm330lhh_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 1370 asm330lhh_bdr_gy_t *val); 1371 1372 typedef enum 1373 { 1374 ASM330LHH_BYPASS_MODE = 0, 1375 ASM330LHH_FIFO_MODE = 1, 1376 ASM330LHH_STREAM_TO_FIFO_MODE = 3, 1377 ASM330LHH_BYPASS_TO_STREAM_MODE = 4, 1378 ASM330LHH_STREAM_MODE = 6, 1379 ASM330LHH_BYPASS_TO_FIFO_MODE = 7, 1380 } asm330lhh_fifo_mode_t; 1381 int32_t asm330lhh_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhh_fifo_mode_t val); 1382 int32_t asm330lhh_fifo_mode_get(const stmdev_ctx_t *ctx, 1383 asm330lhh_fifo_mode_t *val); 1384 1385 typedef enum 1386 { 1387 ASM330LHH_TEMP_NOT_BATCHED = 0, 1388 ASM330LHH_TEMP_BATCHED_AT_52Hz = 1, 1389 ASM330LHH_TEMP_BATCHED_AT_12Hz5 = 2, 1390 ASM330LHH_TEMP_BATCHED_AT_1Hz6 = 3, 1391 } asm330lhh_odr_t_batch_t; 1392 int32_t asm330lhh_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 1393 asm330lhh_odr_t_batch_t val); 1394 int32_t asm330lhh_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 1395 asm330lhh_odr_t_batch_t *val); 1396 1397 typedef enum 1398 { 1399 ASM330LHH_NO_DECIMATION = 0, 1400 ASM330LHH_DEC_1 = 1, 1401 ASM330LHH_DEC_8 = 2, 1402 ASM330LHH_DEC_32 = 3, 1403 } asm330lhh_dec_ts_batch_t; 1404 int32_t asm330lhh_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 1405 asm330lhh_dec_ts_batch_t val); 1406 int32_t asm330lhh_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 1407 asm330lhh_dec_ts_batch_t *val); 1408 1409 typedef enum 1410 { 1411 ASM330LHH_XL_BATCH_EVENT = 0, 1412 ASM330LHH_GYRO_BATCH_EVENT = 1, 1413 } asm330lhh_trig_counter_bdr_t; 1414 int32_t asm330lhh_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 1415 asm330lhh_trig_counter_bdr_t val); 1416 int32_t asm330lhh_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 1417 asm330lhh_trig_counter_bdr_t *val); 1418 1419 int32_t asm330lhh_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); 1420 int32_t asm330lhh_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); 1421 1422 int32_t asm330lhh_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 1423 uint16_t val); 1424 int32_t asm330lhh_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 1425 uint16_t *val); 1426 1427 int32_t asm330lhh_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 1428 1429 int32_t asm330lhh_fifo_status_get(const stmdev_ctx_t *ctx, 1430 asm330lhh_fifo_status2_t *val); 1431 1432 int32_t asm330lhh_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1433 1434 int32_t asm330lhh_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1435 1436 int32_t asm330lhh_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 1437 1438 typedef enum 1439 { 1440 ASM330LHH_GYRO_NC_TAG = 0x01, 1441 ASM330LHH_XL_NC_TAG = 0x02, 1442 ASM330LHH_TEMPERATURE_TAG = 0x03, 1443 ASM330LHH_TIMESTAMP_TAG = 0x04, 1444 ASM330LHH_CFG_CHANGE_TAG = 0x05, 1445 } asm330lhh_fifo_tag_t; 1446 int32_t asm330lhh_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 1447 asm330lhh_fifo_tag_t *val); 1448 1449 typedef enum 1450 { 1451 ASM330LHH_DEN_DISABLE = 0, 1452 ASM330LHH_LEVEL_FIFO = 6, 1453 ASM330LHH_LEVEL_LETCHED = 3, 1454 ASM330LHH_LEVEL_TRIGGER = 2, 1455 ASM330LHH_EDGE_TRIGGER = 4, 1456 } asm330lhh_den_mode_t; 1457 int32_t asm330lhh_den_mode_set(const stmdev_ctx_t *ctx, 1458 asm330lhh_den_mode_t val); 1459 int32_t asm330lhh_den_mode_get(const stmdev_ctx_t *ctx, 1460 asm330lhh_den_mode_t *val); 1461 1462 typedef enum 1463 { 1464 ASM330LHH_DEN_ACT_LOW = 0, 1465 ASM330LHH_DEN_ACT_HIGH = 1, 1466 } asm330lhh_den_lh_t; 1467 int32_t asm330lhh_den_polarity_set(const stmdev_ctx_t *ctx, 1468 asm330lhh_den_lh_t val); 1469 int32_t asm330lhh_den_polarity_get(const stmdev_ctx_t *ctx, 1470 asm330lhh_den_lh_t *val); 1471 1472 typedef enum 1473 { 1474 ASM330LHH_STAMP_IN_GY_DATA = 0, 1475 ASM330LHH_STAMP_IN_XL_DATA = 1, 1476 ASM330LHH_STAMP_IN_GY_XL_DATA = 2, 1477 } asm330lhh_den_xl_g_t; 1478 int32_t asm330lhh_den_enable_set(const stmdev_ctx_t *ctx, 1479 asm330lhh_den_xl_g_t val); 1480 int32_t asm330lhh_den_enable_get(const stmdev_ctx_t *ctx, 1481 asm330lhh_den_xl_g_t *val); 1482 1483 int32_t asm330lhh_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 1484 int32_t asm330lhh_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 1485 1486 int32_t asm330lhh_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 1487 int32_t asm330lhh_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 1488 1489 int32_t asm330lhh_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 1490 int32_t asm330lhh_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 1491 1492 /** 1493 *@} 1494 * 1495 */ 1496 1497 #ifdef __cplusplus 1498 } 1499 #endif 1500 1501 #endif /* ASM330LHH_REGS_H */ 1502 1503 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1504
