1 /*
2 ******************************************************************************
3 * @file asm330lhb_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ASM330LHB driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "asm330lhb_reg.h"
21
22 /**
23 * @defgroup ASM330LHB
24 * @brief This file provides a set of functions needed to drive the
25 * asm330lhb enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ASM330LHB_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
asm330lhb_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak asm330lhb_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53 ret = ctx->read_reg(ctx->handle, reg, data, len);
54 return ret;
55 }
56
57 /**
58 * @brief Write generic device register
59 *
60 * @param ctx read / write interface definitions(ptr)
61 * @param reg register to write
62 * @param data pointer to data to write in register reg(ptr)
63 * @param len number of consecutive register to write
64 * @retval interface status (MANDATORY: return 0 -> no Error)
65 *
66 */
asm330lhb_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)67 int32_t __weak asm330lhb_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
68 uint16_t len)
69 {
70 int32_t ret;
71 ret = ctx->write_reg(ctx->handle, reg, data, len);
72 return ret;
73 }
74
75 /**
76 * @}
77 *
78 */
79
80 /**
81 * @defgroup ASM330LHB_Sensitivity
82 * @brief These functions convert raw-data into engineering units.
83 * @{
84 *
85 */
86
asm330lhb_from_fs2g_to_mg(int16_t lsb)87 float_t asm330lhb_from_fs2g_to_mg(int16_t lsb)
88 {
89 return ((float_t)lsb * 0.061f);
90 }
91
asm330lhb_from_fs4g_to_mg(int16_t lsb)92 float_t asm330lhb_from_fs4g_to_mg(int16_t lsb)
93 {
94 return ((float_t)lsb * 0.122f);
95 }
96
asm330lhb_from_fs8g_to_mg(int16_t lsb)97 float_t asm330lhb_from_fs8g_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb * 0.244f);
100 }
101
asm330lhb_from_fs16g_to_mg(int16_t lsb)102 float_t asm330lhb_from_fs16g_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb * 0.488f);
105 }
106
asm330lhb_from_fs125dps_to_mdps(int16_t lsb)107 float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb)
108 {
109 return ((float_t)lsb * 4.375f);
110 }
111
asm330lhb_from_fs250dps_to_mdps(int16_t lsb)112 float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb)
113 {
114 return ((float_t)lsb * 8.75f);
115 }
116
asm330lhb_from_fs500dps_to_mdps(int16_t lsb)117 float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb)
118 {
119 return ((float_t)lsb * 17.50f);
120 }
121
asm330lhb_from_fs1000dps_to_mdps(int16_t lsb)122 float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb)
123 {
124 return ((float_t)lsb * 35.0f);
125 }
126
asm330lhb_from_fs2000dps_to_mdps(int16_t lsb)127 float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb)
128 {
129 return ((float_t)lsb * 70.0f);
130 }
131
asm330lhb_from_fs4000dps_to_mdps(int16_t lsb)132 float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb)
133 {
134 return ((float_t)lsb * 140.0f);
135 }
136
asm330lhb_from_lsb_to_celsius(int16_t lsb)137 float_t asm330lhb_from_lsb_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 256.0f) + 25.0f);
140 }
141
asm330lhb_from_lsb_to_nsec(int32_t lsb)142 float_t asm330lhb_from_lsb_to_nsec(int32_t lsb)
143 {
144 return ((float_t)lsb * 25000.0f);
145 }
146
147 /**
148 * @}
149 *
150 */
151
152 /**
153 * @defgroup LSM9DS1_Data_generation
154 * @brief This section groups all the functions concerning data
155 * generation
156 * @{
157 *
158 */
159
160 /**
161 * @brief Accelerometer full-scale selection[set]
162 *
163 * @param ctx Read / write interface definitions.(ptr)
164 * @param val Change the values of fs_xl in reg CTRL1_XL
165 * @retval Interface status (MANDATORY: return 0 -> no Error).
166 *
167 */
asm330lhb_xl_full_scale_set(stmdev_ctx_t * ctx,asm330lhb_fs_xl_t val)168 int32_t asm330lhb_xl_full_scale_set(stmdev_ctx_t *ctx,
169 asm330lhb_fs_xl_t val)
170 {
171 asm330lhb_ctrl1_xl_t ctrl1_xl;
172 int32_t ret;
173
174 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
175 if (ret == 0)
176 {
177 ctrl1_xl.fs_xl = (uint8_t)val;
178 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
179 (uint8_t *)&ctrl1_xl, 1);
180 }
181 return ret;
182 }
183
184 /**
185 * @brief Accelerometer full-scale selection.[get]
186 *
187 * @param ctx Read / write interface definitions.(ptr)
188 * @param val Get the values of fs_xl in reg CTRL1_XL
189 * @retval Interface status (MANDATORY: return 0 -> no Error).
190 *
191 */
asm330lhb_xl_full_scale_get(stmdev_ctx_t * ctx,asm330lhb_fs_xl_t * val)192 int32_t asm330lhb_xl_full_scale_get(stmdev_ctx_t *ctx,
193 asm330lhb_fs_xl_t *val)
194 {
195 asm330lhb_ctrl1_xl_t ctrl1_xl;
196 int32_t ret;
197
198 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
199 switch (ctrl1_xl.fs_xl)
200 {
201 case ASM330LHB_2g:
202 *val = ASM330LHB_2g;
203 break;
204 case ASM330LHB_16g:
205 *val = ASM330LHB_16g;
206 break;
207 case ASM330LHB_4g:
208 *val = ASM330LHB_4g;
209 break;
210 case ASM330LHB_8g:
211 *val = ASM330LHB_8g;
212 break;
213 default:
214 *val = ASM330LHB_2g;
215 break;
216 }
217 return ret;
218 }
219
220 /**
221 * @brief Accelerometer UI data rate selection.[set]
222 *
223 * @param ctx Read / write interface definitions.(ptr)
224 * @param val Change the values of odr_xl in reg CTRL1_XL
225 * @retval Interface status (MANDATORY: return 0 -> no Error).
226 *
227 */
asm330lhb_xl_data_rate_set(stmdev_ctx_t * ctx,asm330lhb_odr_xl_t val)228 int32_t asm330lhb_xl_data_rate_set(stmdev_ctx_t *ctx,
229 asm330lhb_odr_xl_t val)
230 {
231 asm330lhb_odr_xl_t odr_xl = val;
232 asm330lhb_emb_fsm_enable_t fsm_enable;
233 asm330lhb_fsm_odr_t fsm_odr;
234 asm330lhb_ctrl1_xl_t ctrl1_xl;
235 asm330lhb_mlc_odr_t mlc_odr;
236 uint8_t mlc_enable;
237 int32_t ret;
238
239 /* Check the Finite State Machine data rate constraints */
240 ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable);
241 if (ret == 0)
242 {
243 if ((fsm_enable.fsm_enable_a.fsm1_en |
244 fsm_enable.fsm_enable_a.fsm2_en |
245 fsm_enable.fsm_enable_a.fsm3_en |
246 fsm_enable.fsm_enable_a.fsm4_en |
247 fsm_enable.fsm_enable_a.fsm5_en |
248 fsm_enable.fsm_enable_a.fsm6_en |
249 fsm_enable.fsm_enable_a.fsm7_en |
250 fsm_enable.fsm_enable_a.fsm8_en |
251 fsm_enable.fsm_enable_b.fsm9_en |
252 fsm_enable.fsm_enable_b.fsm10_en |
253 fsm_enable.fsm_enable_b.fsm11_en |
254 fsm_enable.fsm_enable_b.fsm12_en |
255 fsm_enable.fsm_enable_b.fsm13_en |
256 fsm_enable.fsm_enable_b.fsm14_en |
257 fsm_enable.fsm_enable_b.fsm15_en |
258 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
259 {
260
261 ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr);
262 if (ret == 0)
263 {
264 switch (fsm_odr)
265 {
266 case ASM330LHB_ODR_FSM_12Hz5:
267
268 if (val == ASM330LHB_XL_ODR_OFF)
269 {
270 odr_xl = ASM330LHB_XL_ODR_12Hz5;
271
272 }
273 else
274 {
275 odr_xl = val;
276 }
277 break;
278 case ASM330LHB_ODR_FSM_26Hz:
279
280 if (val == ASM330LHB_XL_ODR_OFF)
281 {
282 odr_xl = ASM330LHB_XL_ODR_26Hz;
283
284 }
285 else if (val == ASM330LHB_XL_ODR_12Hz5)
286 {
287 odr_xl = ASM330LHB_XL_ODR_26Hz;
288
289 }
290 else
291 {
292 odr_xl = val;
293 }
294 break;
295 case ASM330LHB_ODR_FSM_52Hz:
296
297 if (val == ASM330LHB_XL_ODR_OFF)
298 {
299 odr_xl = ASM330LHB_XL_ODR_52Hz;
300
301 }
302 else if (val == ASM330LHB_XL_ODR_12Hz5)
303 {
304 odr_xl = ASM330LHB_XL_ODR_52Hz;
305
306 }
307 else if (val == ASM330LHB_XL_ODR_26Hz)
308 {
309 odr_xl = ASM330LHB_XL_ODR_52Hz;
310
311 }
312 else
313 {
314 odr_xl = val;
315 }
316 break;
317 case ASM330LHB_ODR_FSM_104Hz:
318
319 if (val == ASM330LHB_XL_ODR_OFF)
320 {
321 odr_xl = ASM330LHB_XL_ODR_104Hz;
322
323 }
324 else if (val == ASM330LHB_XL_ODR_12Hz5)
325 {
326 odr_xl = ASM330LHB_XL_ODR_104Hz;
327
328 }
329 else if (val == ASM330LHB_XL_ODR_26Hz)
330 {
331 odr_xl = ASM330LHB_XL_ODR_104Hz;
332
333 }
334 else if (val == ASM330LHB_XL_ODR_52Hz)
335 {
336 odr_xl = ASM330LHB_XL_ODR_104Hz;
337
338 }
339 else
340 {
341 odr_xl = val;
342 }
343 break;
344 default:
345 odr_xl = val;
346 break;
347 }
348 }
349 }
350 }
351
352 /* Check the Machine Learning Core data rate constraints */
353 mlc_enable = PROPERTY_DISABLE;
354 if (ret == 0)
355 {
356 ret = asm330lhb_mlc_get(ctx, &mlc_enable);
357 if (mlc_enable == PROPERTY_ENABLE)
358 {
359
360 ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr);
361 if (ret == 0)
362 {
363 switch (mlc_odr)
364 {
365 case ASM330LHB_ODR_PRGS_12Hz5:
366
367 if (val == ASM330LHB_XL_ODR_OFF)
368 {
369 odr_xl = ASM330LHB_XL_ODR_12Hz5;
370
371 }
372 else
373 {
374 odr_xl = val;
375 }
376 break;
377 case ASM330LHB_ODR_PRGS_26Hz:
378 if (val == ASM330LHB_XL_ODR_OFF)
379 {
380 odr_xl = ASM330LHB_XL_ODR_26Hz;
381
382 }
383 else if (val == ASM330LHB_XL_ODR_12Hz5)
384 {
385 odr_xl = ASM330LHB_XL_ODR_26Hz;
386
387 }
388 else
389 {
390 odr_xl = val;
391 }
392 break;
393 case ASM330LHB_ODR_PRGS_52Hz:
394
395 if (val == ASM330LHB_XL_ODR_OFF)
396 {
397 odr_xl = ASM330LHB_XL_ODR_52Hz;
398
399 }
400 else if (val == ASM330LHB_XL_ODR_12Hz5)
401 {
402 odr_xl = ASM330LHB_XL_ODR_52Hz;
403
404 }
405 else if (val == ASM330LHB_XL_ODR_26Hz)
406 {
407 odr_xl = ASM330LHB_XL_ODR_52Hz;
408
409 }
410 else
411 {
412 odr_xl = val;
413 }
414 break;
415 case ASM330LHB_ODR_PRGS_104Hz:
416 if (val == ASM330LHB_XL_ODR_OFF)
417 {
418 odr_xl = ASM330LHB_XL_ODR_104Hz;
419
420 }
421 else if (val == ASM330LHB_XL_ODR_12Hz5)
422 {
423 odr_xl = ASM330LHB_XL_ODR_104Hz;
424
425 }
426 else if (val == ASM330LHB_XL_ODR_26Hz)
427 {
428 odr_xl = ASM330LHB_XL_ODR_104Hz;
429
430 }
431 else if (val == ASM330LHB_XL_ODR_52Hz)
432 {
433 odr_xl = ASM330LHB_XL_ODR_104Hz;
434
435 }
436 else
437 {
438 odr_xl = val;
439 }
440 break;
441 default:
442 odr_xl = val;
443 break;
444 }
445 }
446 }
447 }
448
449 if (ret == 0)
450 {
451 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
452 }
453 if (ret == 0)
454 {
455 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
456 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
457 (uint8_t *)&ctrl1_xl, 1);
458 }
459 return ret;
460 }
461
462 /**
463 * @brief Accelerometer UI data rate selection.[get]
464 *
465 * @param ctx Read / write interface definitions.(ptr)
466 * @param val Get the values of odr_xl in reg CTRL1_XL
467 * @retval Interface status (MANDATORY: return 0 -> no Error).
468 *
469 */
asm330lhb_xl_data_rate_get(stmdev_ctx_t * ctx,asm330lhb_odr_xl_t * val)470 int32_t asm330lhb_xl_data_rate_get(stmdev_ctx_t *ctx,
471 asm330lhb_odr_xl_t *val)
472 {
473 asm330lhb_ctrl1_xl_t ctrl1_xl;
474 int32_t ret;
475
476 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
477 switch (ctrl1_xl.odr_xl)
478 {
479 case ASM330LHB_XL_ODR_OFF:
480 *val = ASM330LHB_XL_ODR_OFF;
481 break;
482 case ASM330LHB_XL_ODR_12Hz5:
483 *val = ASM330LHB_XL_ODR_12Hz5;
484 break;
485 case ASM330LHB_XL_ODR_26Hz:
486 *val = ASM330LHB_XL_ODR_26Hz;
487 break;
488 case ASM330LHB_XL_ODR_52Hz:
489 *val = ASM330LHB_XL_ODR_52Hz;
490 break;
491 case ASM330LHB_XL_ODR_104Hz:
492 *val = ASM330LHB_XL_ODR_104Hz;
493 break;
494 case ASM330LHB_XL_ODR_208Hz:
495 *val = ASM330LHB_XL_ODR_208Hz;
496 break;
497 case ASM330LHB_XL_ODR_417Hz:
498 *val = ASM330LHB_XL_ODR_417Hz;
499 break;
500 case ASM330LHB_XL_ODR_833Hz:
501 *val = ASM330LHB_XL_ODR_833Hz;
502 break;
503 case ASM330LHB_XL_ODR_1667Hz:
504 *val = ASM330LHB_XL_ODR_1667Hz;
505 break;
506 case ASM330LHB_XL_ODR_1Hz6:
507 *val = ASM330LHB_XL_ODR_1Hz6;
508 break;
509 default:
510 *val = ASM330LHB_XL_ODR_OFF;
511 break;
512 }
513 return ret;
514 }
515
516 /**
517 * @brief Gyroscope UI chain full-scale selection.[set]
518 *
519 * @param ctx Read / write interface definitions.(ptr)
520 * @param val Change the values of fs_g in reg CTRL2_G
521 * @retval Interface status (MANDATORY: return 0 -> no Error).
522 *
523 */
asm330lhb_gy_full_scale_set(stmdev_ctx_t * ctx,asm330lhb_fs_g_t val)524 int32_t asm330lhb_gy_full_scale_set(stmdev_ctx_t *ctx,
525 asm330lhb_fs_g_t val)
526 {
527 asm330lhb_ctrl2_g_t ctrl2_g;
528 int32_t ret;
529
530 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
531 if (ret == 0)
532 {
533 ctrl2_g.fs_g = (uint8_t)val;
534 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
535 }
536 return ret;
537 }
538
539 /**
540 * @brief Gyroscope UI chain full-scale selection.[get]
541 *
542 * @param ctx Read / write interface definitions.(ptr)
543 * @param val Get the values of fs_g in reg CTRL2_G
544 * @retval Interface status (MANDATORY: return 0 -> no Error).
545 *
546 */
asm330lhb_gy_full_scale_get(stmdev_ctx_t * ctx,asm330lhb_fs_g_t * val)547 int32_t asm330lhb_gy_full_scale_get(stmdev_ctx_t *ctx,
548 asm330lhb_fs_g_t *val)
549 {
550 asm330lhb_ctrl2_g_t ctrl2_g;
551 int32_t ret;
552
553 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
554 switch (ctrl2_g.fs_g)
555 {
556 case ASM330LHB_125dps:
557 *val = ASM330LHB_125dps;
558 break;
559 case ASM330LHB_250dps:
560 *val = ASM330LHB_250dps;
561 break;
562 case ASM330LHB_500dps:
563 *val = ASM330LHB_500dps;
564 break;
565 case ASM330LHB_1000dps:
566 *val = ASM330LHB_1000dps;
567 break;
568 case ASM330LHB_2000dps:
569 *val = ASM330LHB_2000dps;
570 break;
571 case ASM330LHB_4000dps:
572 *val = ASM330LHB_4000dps;
573 break;
574 default:
575 *val = ASM330LHB_125dps;
576 break;
577 }
578 return ret;
579 }
580
581 /**
582 * @brief Gyroscope data rate.[set]
583 *
584 * @param ctx Read / write interface definitions.(ptr)
585 * @param val Change the values of odr_g in reg CTRL2_G
586 * @retval Interface status (MANDATORY: return 0 -> no Error).
587 *
588 */
asm330lhb_gy_data_rate_set(stmdev_ctx_t * ctx,asm330lhb_odr_g_t val)589 int32_t asm330lhb_gy_data_rate_set(stmdev_ctx_t *ctx,
590 asm330lhb_odr_g_t val)
591 {
592 asm330lhb_odr_g_t odr_gy = val;
593 asm330lhb_emb_fsm_enable_t fsm_enable;
594 asm330lhb_fsm_odr_t fsm_odr;
595 asm330lhb_ctrl2_g_t ctrl2_g;
596 asm330lhb_mlc_odr_t mlc_odr;
597 uint8_t mlc_enable;
598 int32_t ret;
599
600 /* Check the Finite State Machine data rate constraints */
601 ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable);
602 if (ret == 0)
603 {
604 if ((fsm_enable.fsm_enable_a.fsm1_en |
605 fsm_enable.fsm_enable_a.fsm2_en |
606 fsm_enable.fsm_enable_a.fsm3_en |
607 fsm_enable.fsm_enable_a.fsm4_en |
608 fsm_enable.fsm_enable_a.fsm5_en |
609 fsm_enable.fsm_enable_a.fsm6_en |
610 fsm_enable.fsm_enable_a.fsm7_en |
611 fsm_enable.fsm_enable_a.fsm8_en |
612 fsm_enable.fsm_enable_b.fsm9_en |
613 fsm_enable.fsm_enable_b.fsm10_en |
614 fsm_enable.fsm_enable_b.fsm11_en |
615 fsm_enable.fsm_enable_b.fsm12_en |
616 fsm_enable.fsm_enable_b.fsm13_en |
617 fsm_enable.fsm_enable_b.fsm14_en |
618 fsm_enable.fsm_enable_b.fsm15_en |
619 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
620 {
621
622 ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr);
623 if (ret == 0)
624 {
625 switch (fsm_odr)
626 {
627 case ASM330LHB_ODR_FSM_12Hz5:
628
629 if (val == ASM330LHB_GY_ODR_OFF)
630 {
631 odr_gy = ASM330LHB_GY_ODR_12Hz5;
632
633 }
634 else
635 {
636 odr_gy = val;
637 }
638 break;
639 case ASM330LHB_ODR_FSM_26Hz:
640
641 if (val == ASM330LHB_GY_ODR_OFF)
642 {
643 odr_gy = ASM330LHB_GY_ODR_26Hz;
644
645 }
646 else if (val == ASM330LHB_GY_ODR_12Hz5)
647 {
648 odr_gy = ASM330LHB_GY_ODR_26Hz;
649
650 }
651 else
652 {
653 odr_gy = val;
654 }
655 break;
656 case ASM330LHB_ODR_FSM_52Hz:
657
658 if (val == ASM330LHB_GY_ODR_OFF)
659 {
660 odr_gy = ASM330LHB_GY_ODR_52Hz;
661
662 }
663 else if (val == ASM330LHB_GY_ODR_12Hz5)
664 {
665 odr_gy = ASM330LHB_GY_ODR_52Hz;
666
667 }
668 else if (val == ASM330LHB_GY_ODR_26Hz)
669 {
670 odr_gy = ASM330LHB_GY_ODR_52Hz;
671
672 }
673 else
674 {
675 odr_gy = val;
676 }
677 break;
678 case ASM330LHB_ODR_FSM_104Hz:
679
680 if (val == ASM330LHB_GY_ODR_OFF)
681 {
682 odr_gy = ASM330LHB_GY_ODR_104Hz;
683
684 }
685 else if (val == ASM330LHB_GY_ODR_12Hz5)
686 {
687 odr_gy = ASM330LHB_GY_ODR_104Hz;
688
689 }
690 else if (val == ASM330LHB_GY_ODR_26Hz)
691 {
692 odr_gy = ASM330LHB_GY_ODR_104Hz;
693
694 }
695 else if (val == ASM330LHB_GY_ODR_52Hz)
696 {
697 odr_gy = ASM330LHB_GY_ODR_104Hz;
698
699 }
700 else
701 {
702 odr_gy = val;
703 }
704 break;
705 default:
706 odr_gy = val;
707 break;
708 }
709 }
710 }
711 }
712
713 /* Check the Machine Learning Core data rate constraints */
714 mlc_enable = PROPERTY_DISABLE;
715 if (ret == 0)
716 {
717 ret = asm330lhb_mlc_get(ctx, &mlc_enable);
718 if (mlc_enable == PROPERTY_ENABLE)
719 {
720
721 ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr);
722 if (ret == 0)
723 {
724 switch (mlc_odr)
725 {
726 case ASM330LHB_ODR_PRGS_12Hz5:
727
728 if (val == ASM330LHB_GY_ODR_OFF)
729 {
730 odr_gy = ASM330LHB_GY_ODR_12Hz5;
731
732 }
733 else
734 {
735 odr_gy = val;
736 }
737 break;
738 case ASM330LHB_ODR_PRGS_26Hz:
739
740 if (val == ASM330LHB_GY_ODR_OFF)
741 {
742 odr_gy = ASM330LHB_GY_ODR_26Hz;
743
744 }
745 else if (val == ASM330LHB_GY_ODR_12Hz5)
746 {
747 odr_gy = ASM330LHB_GY_ODR_26Hz;
748
749 }
750 else
751 {
752 odr_gy = val;
753 }
754 break;
755 case ASM330LHB_ODR_PRGS_52Hz:
756
757 if (val == ASM330LHB_GY_ODR_OFF)
758 {
759 odr_gy = ASM330LHB_GY_ODR_52Hz;
760
761 }
762 else if (val == ASM330LHB_GY_ODR_12Hz5)
763 {
764 odr_gy = ASM330LHB_GY_ODR_52Hz;
765
766 }
767 else if (val == ASM330LHB_GY_ODR_26Hz)
768 {
769 odr_gy = ASM330LHB_GY_ODR_52Hz;
770
771 }
772 else
773 {
774 odr_gy = val;
775 }
776 break;
777 case ASM330LHB_ODR_PRGS_104Hz:
778
779 if (val == ASM330LHB_GY_ODR_OFF)
780 {
781 odr_gy = ASM330LHB_GY_ODR_104Hz;
782
783 }
784 else if (val == ASM330LHB_GY_ODR_12Hz5)
785 {
786 odr_gy = ASM330LHB_GY_ODR_104Hz;
787
788 }
789 else if (val == ASM330LHB_GY_ODR_26Hz)
790 {
791 odr_gy = ASM330LHB_GY_ODR_104Hz;
792
793 }
794 else if (val == ASM330LHB_GY_ODR_52Hz)
795 {
796 odr_gy = ASM330LHB_GY_ODR_104Hz;
797
798 }
799 else
800 {
801 odr_gy = val;
802 }
803 break;
804 default:
805 odr_gy = val;
806 break;
807 }
808 }
809 }
810 }
811
812 if (ret == 0)
813 {
814 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
815 }
816 if (ret == 0)
817 {
818 ctrl2_g.odr_g = (uint8_t)odr_gy;
819 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
820 }
821 return ret;
822 }
823
824 /**
825 * @brief Gyroscope data rate.[get]
826 *
827 * @param ctx Read / write interface definitions.(ptr)
828 * @param val Get the values of odr_g in reg CTRL2_G
829 * @retval Interface status (MANDATORY: return 0 -> no Error).
830 *
831 */
asm330lhb_gy_data_rate_get(stmdev_ctx_t * ctx,asm330lhb_odr_g_t * val)832 int32_t asm330lhb_gy_data_rate_get(stmdev_ctx_t *ctx,
833 asm330lhb_odr_g_t *val)
834 {
835 asm330lhb_ctrl2_g_t ctrl2_g;
836 int32_t ret;
837
838 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
839 switch (ctrl2_g.odr_g)
840 {
841 case ASM330LHB_GY_ODR_OFF:
842 *val = ASM330LHB_GY_ODR_OFF;
843 break;
844 case ASM330LHB_GY_ODR_12Hz5:
845 *val = ASM330LHB_GY_ODR_12Hz5;
846 break;
847 case ASM330LHB_GY_ODR_26Hz:
848 *val = ASM330LHB_GY_ODR_26Hz;
849 break;
850 case ASM330LHB_GY_ODR_52Hz:
851 *val = ASM330LHB_GY_ODR_52Hz;
852 break;
853 case ASM330LHB_GY_ODR_104Hz:
854 *val = ASM330LHB_GY_ODR_104Hz;
855 break;
856 case ASM330LHB_GY_ODR_208Hz:
857 *val = ASM330LHB_GY_ODR_208Hz;
858 break;
859 case ASM330LHB_GY_ODR_417Hz:
860 *val = ASM330LHB_GY_ODR_417Hz;
861 break;
862 case ASM330LHB_GY_ODR_833Hz:
863 *val = ASM330LHB_GY_ODR_833Hz;
864 break;
865 case ASM330LHB_GY_ODR_1667Hz:
866 *val = ASM330LHB_GY_ODR_1667Hz;
867 break;
868 default:
869 *val = ASM330LHB_GY_ODR_OFF;
870 break;
871 }
872 return ret;
873 }
874
875 /**
876 * @brief Block data update.[set]
877 *
878 * @param ctx Read / write interface definitions.(ptr)
879 * @param val Change the values of bdu in reg CTRL3_C
880 * @retval Interface status (MANDATORY: return 0 -> no Error).
881 *
882 */
asm330lhb_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)883 int32_t asm330lhb_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
884 {
885 asm330lhb_ctrl3_c_t ctrl3_c;
886 int32_t ret;
887
888 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
889 if (ret == 0)
890 {
891 ctrl3_c.bdu = (uint8_t)val;
892 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
893 }
894 return ret;
895 }
896
897 /**
898 * @brief Block data update.[get]
899 *
900 * @param ctx Read / write interface definitions.(ptr)
901 * @param val Change the values of bdu in reg CTRL3_C
902 * @retval Interface status (MANDATORY: return 0 -> no Error).
903 *
904 */
asm330lhb_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)905 int32_t asm330lhb_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
906 {
907 asm330lhb_ctrl3_c_t ctrl3_c;
908 int32_t ret;
909
910 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
911 *val = ctrl3_c.bdu;
912
913 return ret;
914 }
915
916 /**
917 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
918 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
919 *
920 * @param ctx Read / write interface definitions.(ptr)
921 * @param val Change the values of usr_off_w in reg CTRL6_C
922 * @retval Interface status (MANDATORY: return 0 -> no Error).
923 *
924 */
asm330lhb_xl_offset_weight_set(stmdev_ctx_t * ctx,asm330lhb_usr_off_w_t val)925 int32_t asm330lhb_xl_offset_weight_set(stmdev_ctx_t *ctx,
926 asm330lhb_usr_off_w_t val)
927 {
928 asm330lhb_ctrl6_c_t ctrl6_c;
929 int32_t ret;
930
931 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
932 if (ret == 0)
933 {
934 ctrl6_c.usr_off_w = (uint8_t)val;
935 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
936 }
937 return ret;
938 }
939
940 /**
941 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
942 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
943 *
944 * @param ctx Read / write interface definitions.(ptr)
945 * @param val Get the values of usr_off_w in reg CTRL6_C
946 * @retval Interface status (MANDATORY: return 0 -> no Error).
947 *
948 */
asm330lhb_xl_offset_weight_get(stmdev_ctx_t * ctx,asm330lhb_usr_off_w_t * val)949 int32_t asm330lhb_xl_offset_weight_get(stmdev_ctx_t *ctx,
950 asm330lhb_usr_off_w_t *val)
951 {
952 asm330lhb_ctrl6_c_t ctrl6_c;
953 int32_t ret;
954
955 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
956
957 switch (ctrl6_c.usr_off_w)
958 {
959 case ASM330LHB_LSb_1mg:
960 *val = ASM330LHB_LSb_1mg;
961 break;
962 case ASM330LHB_LSb_16mg:
963 *val = ASM330LHB_LSb_16mg;
964 break;
965 default:
966 *val = ASM330LHB_LSb_1mg;
967 break;
968 }
969 return ret;
970 }
971
972 /**
973 * @brief Accelerometer power mode.[set]
974 *
975 * @param ctx Read / write interface definitions.(ptr)
976 * @param val Change the values of xl_hm_mode in reg CTRL6_C
977 * @retval Interface status (MANDATORY: return 0 -> no Error).
978 *
979 */
asm330lhb_xl_power_mode_set(stmdev_ctx_t * ctx,asm330lhb_xl_hm_mode_t val)980 int32_t asm330lhb_xl_power_mode_set(stmdev_ctx_t *ctx,
981 asm330lhb_xl_hm_mode_t val)
982 {
983 asm330lhb_ctrl6_c_t ctrl6_c;
984 int32_t ret;
985
986 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
987 if (ret == 0)
988 {
989 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
990 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
991 }
992 return ret;
993 }
994
995 /**
996 * @brief Accelerometer power mode[get]
997 *
998 * @param ctx Read / write interface definitions.(ptr)
999 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1000 * @retval Interface status (MANDATORY: return 0 -> no Error).
1001 *
1002 */
asm330lhb_xl_power_mode_get(stmdev_ctx_t * ctx,asm330lhb_xl_hm_mode_t * val)1003 int32_t asm330lhb_xl_power_mode_get(stmdev_ctx_t *ctx,
1004 asm330lhb_xl_hm_mode_t *val)
1005 {
1006 asm330lhb_ctrl6_c_t ctrl6_c;
1007 int32_t ret;
1008
1009 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1010 switch (ctrl6_c.xl_hm_mode)
1011 {
1012 case ASM330LHB_HIGH_PERFORMANCE_MD:
1013 *val = ASM330LHB_HIGH_PERFORMANCE_MD;
1014 break;
1015 case ASM330LHB_LOW_NORMAL_POWER_MD:
1016 *val = ASM330LHB_LOW_NORMAL_POWER_MD;
1017 break;
1018 default:
1019 *val = ASM330LHB_HIGH_PERFORMANCE_MD;
1020 break;
1021 }
1022 return ret;
1023 }
1024
1025 /**
1026 * @brief Operating mode for gyroscope.[set]
1027 *
1028 * @param ctx Read / write interface definitions.(ptr)
1029 * @param val Change the values of g_hm_mode in reg CTRL7_G
1030 * @retval Interface status (MANDATORY: return 0 -> no Error).
1031 *
1032 */
asm330lhb_gy_power_mode_set(stmdev_ctx_t * ctx,asm330lhb_g_hm_mode_t val)1033 int32_t asm330lhb_gy_power_mode_set(stmdev_ctx_t *ctx,
1034 asm330lhb_g_hm_mode_t val)
1035 {
1036 asm330lhb_ctrl7_g_t ctrl7_g;
1037 int32_t ret;
1038
1039 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1040 if (ret == 0)
1041 {
1042 ctrl7_g.g_hm_mode = (uint8_t)val;
1043 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1044 }
1045 return ret;
1046 }
1047
1048 /**
1049 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1050 *
1051 * @param ctx Read / write interface definitions.(ptr)
1052 * @param val Get the values of g_hm_mode in reg CTRL7_G
1053 * @retval Interface status (MANDATORY: return 0 -> no Error).
1054 *
1055 */
asm330lhb_gy_power_mode_get(stmdev_ctx_t * ctx,asm330lhb_g_hm_mode_t * val)1056 int32_t asm330lhb_gy_power_mode_get(stmdev_ctx_t *ctx,
1057 asm330lhb_g_hm_mode_t *val)
1058 {
1059 asm330lhb_ctrl7_g_t ctrl7_g;
1060 int32_t ret;
1061
1062 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1063 switch (ctrl7_g.g_hm_mode)
1064 {
1065 case ASM330LHB_GY_HIGH_PERFORMANCE:
1066 *val = ASM330LHB_GY_HIGH_PERFORMANCE;
1067 break;
1068 case ASM330LHB_GY_NORMAL:
1069 *val = ASM330LHB_GY_NORMAL;
1070 break;
1071 default:
1072 *val = ASM330LHB_GY_HIGH_PERFORMANCE;
1073 break;
1074 }
1075 return ret;
1076 }
1077
1078 /**
1079 * @brief Read all the interrupt flag of the device.
1080 *[get]
1081 * @param ctx Read / write interface definitions.(ptr)
1082 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1083 * TAP_SRC; D6D_SRC; STATUS_REG;
1084 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1085 * @retval Interface status (MANDATORY: return 0 -> no Error).
1086 *
1087 */
asm330lhb_all_sources_get(stmdev_ctx_t * ctx,asm330lhb_all_sources_t * val)1088 int32_t asm330lhb_all_sources_get(stmdev_ctx_t *ctx,
1089 asm330lhb_all_sources_t *val)
1090 {
1091 int32_t ret;
1092
1093 ret = asm330lhb_read_reg(ctx, ASM330LHB_ALL_INT_SRC,
1094 (uint8_t *)&val->all_int_src, 1);
1095 if (ret == 0)
1096 {
1097 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_SRC,
1098 (uint8_t *)&val->wake_up_src, 1);
1099 }
1100 if (ret == 0)
1101 {
1102 ret = asm330lhb_read_reg(ctx, ASM330LHB_D6D_SRC,
1103 (uint8_t *)&val->d6d_src, 1);
1104 }
1105 if (ret == 0)
1106 {
1107 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1108 (uint8_t *)&val->status_reg, 1);
1109 }
1110 if (ret == 0)
1111 {
1112 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1113 }
1114 if (ret == 0)
1115 {
1116 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS,
1117 (uint8_t *)&val->emb_func_status, 1);
1118 }
1119 if (ret == 0)
1120 {
1121 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A,
1122 (uint8_t *)&val->fsm_status_a, 1);
1123 }
1124 if (ret == 0)
1125 {
1126 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B,
1127 (uint8_t *)&val->fsm_status_b, 1);
1128 }
1129 if (ret == 0)
1130 {
1131 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS,
1132 (uint8_t *)&val->mlc_status, 1);
1133 }
1134 if (ret == 0)
1135 {
1136 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1137 }
1138
1139 return ret;
1140 }
1141
1142 /**
1143 * @brief The STATUS_REG register is read by the primary interface.[get]
1144 *
1145 * @param ctx Read / write interface definitions.(ptr)
1146 * @param val Get register STATUS_REG
1147 * @retval Interface status (MANDATORY: return 0 -> no Error).
1148 *
1149 */
asm330lhb_status_reg_get(stmdev_ctx_t * ctx,asm330lhb_status_reg_t * val)1150 int32_t asm330lhb_status_reg_get(stmdev_ctx_t *ctx,
1151 asm330lhb_status_reg_t *val)
1152 {
1153 int32_t ret;
1154 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *) val, 1);
1155 return ret;
1156 }
1157
1158 /**
1159 * @brief Accelerometer new data available.[get]
1160 *
1161 * @param ctx Read / write interface definitions.(ptr)
1162 * @param val Get the values of xlda in reg STATUS_REG
1163 * @retval Interface status (MANDATORY: return 0 -> no Error).
1164 *
1165 */
asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1166 int32_t asm330lhb_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1167 {
1168 asm330lhb_status_reg_t status_reg;
1169 int32_t ret;
1170
1171 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1172 (uint8_t *)&status_reg, 1);
1173 *val = status_reg.xlda;
1174
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Gyroscope new data available.[get]
1180 *
1181 * @param ctx Read / write interface definitions.(ptr)
1182 * @param val Get the values of gda in reg STATUS_REG
1183 * @retval Interface status (MANDATORY: return 0 -> no Error).
1184 *
1185 */
asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1186 int32_t asm330lhb_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1187 {
1188 asm330lhb_status_reg_t status_reg;
1189 int32_t ret;
1190
1191 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1192 (uint8_t *)&status_reg, 1);
1193 *val = status_reg.gda;
1194
1195 return ret;
1196 }
1197
1198 /**
1199 * @brief Temperature new data available.[get]
1200 *
1201 * @param ctx Read / write interface definitions.(ptr)
1202 * @param val Get the values of tda in reg STATUS_REG
1203 * @retval Interface status (MANDATORY: return 0 -> no Error).
1204 *
1205 */
asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1206 int32_t asm330lhb_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1207 {
1208 asm330lhb_status_reg_t status_reg;
1209 int32_t ret;
1210
1211 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1212 (uint8_t *)&status_reg, 1);
1213 *val = status_reg.tda;
1214
1215 return ret;
1216 }
1217
1218 /**
1219 * @brief Device boot status.[get]
1220 *
1221 * @param ctx Read / write interface definitions.(ptr)
1222 * @param val Get the device boot status in reg STATUS_REG.
1223 * 0: OK, 1: FAIL
1224 * @retval Interface status (MANDATORY: return 0 -> no Error).
1225 *
1226 */
asm330lhb_boot_device_status_get(stmdev_ctx_t * ctx,uint8_t * val)1227 int32_t asm330lhb_boot_device_status_get(stmdev_ctx_t *ctx, uint8_t *val)
1228 {
1229 asm330lhb_status_reg_t status_reg;
1230 int32_t ret;
1231
1232 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1233 (uint8_t *)&status_reg, 1);
1234 *val = status_reg.boot_check_fail;
1235
1236 return ret;
1237 }
1238
1239 /**
1240 * @brief Accelerometer X-axis user offset correction expressed in two’s
1241 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1242 * The value must be in the range [-127 127].[set]
1243 *
1244 * @param ctx Read / write interface definitions.(ptr)
1245 * @param buff Buffer that contains data to write
1246 * @retval Interface status (MANDATORY: return 0 -> no Error).
1247 *
1248 */
asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)1249 int32_t asm330lhb_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
1250 {
1251 int32_t ret;
1252 ret = asm330lhb_write_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1);
1253 return ret;
1254 }
1255
1256 /**
1257 * @brief Accelerometer X-axis user offset correction expressed in two’s
1258 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1259 * The value must be in the range [-127 127].[get]
1260 *
1261 * @param ctx Read / write interface definitions.(ptr)
1262 * @param buff Buffer that stores data read
1263 * @retval Interface status (MANDATORY: return 0 -> no Error).
1264 *
1265 */
asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)1266 int32_t asm330lhb_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
1267 {
1268 int32_t ret;
1269 ret = asm330lhb_read_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1);
1270 return ret;
1271 }
1272
1273 /**
1274 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1275 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1276 * The value must be in the range [-127 127].[set]
1277 *
1278 * @param ctx Read / write interface definitions.(ptr)
1279 * @param buff Buffer that contains data to write
1280 * @retval Interface status (MANDATORY: return 0 -> no Error).
1281 *
1282 */
asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)1283 int32_t asm330lhb_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
1284 {
1285 int32_t ret;
1286 ret = asm330lhb_write_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1);
1287 return ret;
1288 }
1289
1290 /**
1291 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1292 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1293 * The value must be in the range [-127 127].[get]
1294 *
1295 * @param ctx Read / write interface definitions.(ptr)
1296 * @param buff Buffer that stores data read
1297 * @retval Interface status (MANDATORY: return 0 -> no Error).
1298 *
1299 */
asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)1300 int32_t asm330lhb_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
1301 {
1302 int32_t ret;
1303 ret = asm330lhb_read_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1);
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1309 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1310 * The value must be in the range [-127 127].[set]
1311 *
1312 * @param ctx Read / write interface definitions.(ptr)
1313 * @param buff Buffer that contains data to write
1314 * @retval Interface status (MANDATORY: return 0 -> no Error).
1315 *
1316 */
asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1317 int32_t asm330lhb_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
1318 {
1319 int32_t ret;
1320 ret = asm330lhb_write_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1);
1321 return ret;
1322 }
1323
1324 /**
1325 * @brief Accelerometer X-axis user offset correction expressed in two’s
1326 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1327 * The value must be in the range [-127 127].[get]
1328 *
1329 * @param ctx Read / write interface definitions.(ptr)
1330 * @param buff Buffer that stores data read
1331 * @retval Interface status (MANDATORY: return 0 -> no Error).
1332 *
1333 */
asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1334 int32_t asm330lhb_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
1335 {
1336 int32_t ret;
1337 ret = asm330lhb_read_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1);
1338 return ret;
1339 }
1340
1341 /**
1342 * @brief Enables user offset on out.[set]
1343 *
1344 * @param ctx Read / write interface definitions.(ptr)
1345 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1346 * @retval Interface status (MANDATORY: return 0 -> no Error).
1347 *
1348 */
asm330lhb_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1349 int32_t asm330lhb_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1350 {
1351 asm330lhb_ctrl7_g_t ctrl7_g;
1352 int32_t ret;
1353
1354 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1355 if (ret == 0)
1356 {
1357 ctrl7_g.usr_off_on_out = (uint8_t)val;
1358 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1359 }
1360 return ret;
1361 }
1362
1363 /**
1364 * @brief Get user offset on out flag.[get]
1365 *
1366 * @param ctx Read / write interface definitions.(ptr)
1367 * @param val Get values of usr_off_on_out in reg CTRL7_G
1368 * @retval Interface status (MANDATORY: return 0 -> no Error).
1369 *
1370 */
asm330lhb_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1371 int32_t asm330lhb_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1372 {
1373 asm330lhb_ctrl7_g_t ctrl7_g;
1374 int32_t ret;
1375
1376 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1377 *val = ctrl7_g.usr_off_on_out;
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @}
1384 *
1385 */
1386
1387 /**
1388 * @defgroup ASM330LHB_Timestamp
1389 * @brief This section groups all the functions that manage the
1390 * timestamp generation.
1391 * @{
1392 *
1393 */
1394
1395 /**
1396 * @brief Reset timestamp counter.[set]
1397 *
1398 * @param ctx Read / write interface definitions.(ptr)
1399 * @retval Interface status (MANDATORY: return 0 -> no Error).
1400 *
1401 */
asm330lhb_timestamp_rst(stmdev_ctx_t * ctx)1402 int32_t asm330lhb_timestamp_rst(stmdev_ctx_t *ctx)
1403 {
1404 uint8_t rst_val = 0xAA;
1405
1406 return asm330lhb_write_reg(ctx, ASM330LHB_TIMESTAMP2, &rst_val, 1);
1407 }
1408
1409 /**
1410 * @brief Enables timestamp counter.[set]
1411 *
1412 * @param ctx Read / write interface definitions.(ptr)
1413 * @param val Change the values of timestamp_en in reg CTRL10_C
1414 * @retval Interface status (MANDATORY: return 0 -> no Error).
1415 *
1416 */
asm330lhb_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1417 int32_t asm330lhb_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1418 {
1419 asm330lhb_ctrl10_c_t ctrl10_c;
1420 int32_t ret;
1421
1422 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1423 if (ret == 0)
1424 {
1425 ctrl10_c.timestamp_en = (uint8_t)val;
1426 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL10_C,
1427 (uint8_t *)&ctrl10_c, 1);
1428 }
1429 return ret;
1430 }
1431
1432 /**
1433 * @brief Enables timestamp counter.[get]
1434 *
1435 * @param ctx Read / write interface definitions.(ptr)
1436 * @param val Change the values of timestamp_en in reg CTRL10_C
1437 * @retval Interface status (MANDATORY: return 0 -> no Error).
1438 *
1439 */
asm330lhb_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1440 int32_t asm330lhb_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1441 {
1442 asm330lhb_ctrl10_c_t ctrl10_c;
1443 int32_t ret;
1444
1445 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1446 *val = ctrl10_c.timestamp_en;
1447
1448 return ret;
1449 }
1450
1451 /**
1452 * @brief Timestamp first data output register (r).
1453 * The value is expressed as a 32-bit word and the bit resolution
1454 * is 25 μs.[get]
1455 *
1456 * @param ctx Read / write interface definitions.(ptr)
1457 * @param buff Buffer that stores data read
1458 * @retval Interface status (MANDATORY: return 0 -> no Error).
1459 *
1460 */
asm330lhb_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1461 int32_t asm330lhb_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1462 {
1463 uint8_t buff[4];
1464 int32_t ret;
1465
1466 ret = asm330lhb_read_reg(ctx, ASM330LHB_TIMESTAMP0, buff, 4);
1467 *val = buff[3];
1468 *val = (*val * 256U) + buff[2];
1469 *val = (*val * 256U) + buff[1];
1470 *val = (*val * 256U) + buff[0];
1471
1472 return ret;
1473 }
1474
1475 /**
1476 * @}
1477 *
1478 */
1479
1480 /**
1481 * @defgroup ASM330LHB_Data output
1482 * @brief This section groups all the data output functions.
1483 * @{
1484 *
1485 */
1486
1487 /**
1488 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1489 *
1490 * @param ctx Read / write interface definitions.(ptr)
1491 * @param val Change the values of rounding in reg CTRL5_C
1492 * @retval Interface status (MANDATORY: return 0 -> no Error).
1493 *
1494 */
asm330lhb_rounding_mode_set(stmdev_ctx_t * ctx,asm330lhb_rounding_t val)1495 int32_t asm330lhb_rounding_mode_set(stmdev_ctx_t *ctx,
1496 asm330lhb_rounding_t val)
1497 {
1498 asm330lhb_ctrl5_c_t ctrl5_c;
1499 int32_t ret;
1500
1501 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1502 if (ret == 0)
1503 {
1504 ctrl5_c.rounding = (uint8_t)val;
1505 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1506 }
1507 return ret;
1508 }
1509
1510 /**
1511 * @brief Gyroscope UI chain full-scale selection.[get]
1512 *
1513 * @param ctx Read / write interface definitions.(ptr)
1514 * @param val Get the values of rounding in reg CTRL5_C
1515 * @retval Interface status (MANDATORY: return 0 -> no Error).
1516 *
1517 */
asm330lhb_rounding_mode_get(stmdev_ctx_t * ctx,asm330lhb_rounding_t * val)1518 int32_t asm330lhb_rounding_mode_get(stmdev_ctx_t *ctx,
1519 asm330lhb_rounding_t *val)
1520 {
1521 asm330lhb_ctrl5_c_t ctrl5_c;
1522 int32_t ret;
1523
1524 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1525 switch (ctrl5_c.rounding)
1526 {
1527 case ASM330LHB_NO_ROUND:
1528 *val = ASM330LHB_NO_ROUND;
1529 break;
1530 case ASM330LHB_ROUND_XL:
1531 *val = ASM330LHB_ROUND_XL;
1532 break;
1533 case ASM330LHB_ROUND_GY:
1534 *val = ASM330LHB_ROUND_GY;
1535 break;
1536 case ASM330LHB_ROUND_GY_XL:
1537 *val = ASM330LHB_ROUND_GY_XL;
1538 break;
1539 default:
1540 *val = ASM330LHB_NO_ROUND;
1541 break;
1542 }
1543 return ret;
1544 }
1545
1546 /**
1547 * @brief Temperature data output register (r).
1548 * L and H registers together express a 16-bit word in two’s
1549 * complement.[get]
1550 *
1551 * @param ctx Read / write interface definitions.(ptr)
1552 * @param buff Buffer that stores data read
1553 * @retval Interface status (MANDATORY: return 0 -> no Error).
1554 *
1555 */
asm330lhb_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1556 int32_t asm330lhb_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1557 {
1558 uint8_t buff[2];
1559 int32_t ret;
1560
1561 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUT_TEMP_L, buff, 2);
1562 *val = (int16_t)buff[1];
1563 *val = (*val * 256) + (int16_t)buff[0];
1564
1565 return ret;
1566 }
1567
1568 /**
1569 * @brief Angular rate sensor. The value is expressed as a 16-bit
1570 * word in two’s complement.[get]
1571 *
1572 * @param ctx Read / write interface definitions.(ptr)
1573 * @param buff Buffer that stores data read
1574 * @retval Interface status (MANDATORY: return 0 -> no Error).
1575 *
1576 */
asm330lhb_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1577 int32_t asm330lhb_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1578 {
1579 uint8_t buff[6];
1580 int32_t ret;
1581 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_G, buff, 6);
1582
1583 val[0] = (int16_t)buff[1];
1584 val[0] = (val[0] * 256) + (int16_t)buff[0];
1585 val[1] = (int16_t)buff[3];
1586 val[1] = (val[1] * 256) + (int16_t)buff[2];
1587 val[2] = (int16_t)buff[5];
1588 val[2] = (val[2] * 256) + (int16_t)buff[4];
1589
1590 return ret;
1591 }
1592
1593 /**
1594 * @brief Linear acceleration output register. The value is expressed as a
1595 * 16-bit word in two’s complement.[get]
1596 *
1597 * @param ctx Read / write interface definitions.(ptr)
1598 * @param buff Buffer that stores data read
1599 * @retval Interface status (MANDATORY: return 0 -> no Error).
1600 *
1601 */
asm330lhb_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1602 int32_t asm330lhb_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1603 {
1604 uint8_t buff[6];
1605 int32_t ret;
1606 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_A, buff, 6);
1607
1608 val[0] = (int16_t)buff[1];
1609 val[0] = (val[0] * 256) + (int16_t)buff[0];
1610 val[1] = (int16_t)buff[3];
1611 val[1] = (val[1] * 256) + (int16_t)buff[2];
1612 val[2] = (int16_t)buff[5];
1613 val[2] = (val[2] * 256) + (int16_t)buff[4];
1614
1615 return ret;
1616 }
1617
1618 /**
1619 * @brief FIFO data output.[get]
1620 *
1621 * @param ctx Read / write interface definitions.(ptr)
1622 * @param buff Buffer that stores data read
1623 * @retval Interface status (MANDATORY: return 0 -> no Error).
1624 *
1625 */
asm330lhb_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * val)1626 int32_t asm330lhb_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val)
1627 {
1628 int32_t ret;
1629 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_X_L, val, 6);
1630 return ret;
1631 }
1632
1633 /**
1634 * @}
1635 *
1636 */
1637
1638 /**
1639 * @defgroup ASM330LHB_common
1640 * @brief This section groups common useful functions.
1641 * @{
1642 *
1643 */
1644
1645 /**
1646 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1647 * with respect to the typical.[set]
1648 * Step: 0.15%. 8-bit format, 2's complement.
1649 *
1650 * @param ctx Read / write interface definitions.(ptr)
1651 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1652 * @retval Interface status (MANDATORY: return 0 -> no Error).
1653 *
1654 */
asm330lhb_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1655 int32_t asm330lhb_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1656 {
1657 asm330lhb_internal_freq_fine_t internal_freq_fine;
1658 int32_t ret;
1659
1660 ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1661 (uint8_t *)&internal_freq_fine, 1);
1662 if (ret == 0)
1663 {
1664 internal_freq_fine.freq_fine = (uint8_t)val;
1665 ret = asm330lhb_write_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1666 (uint8_t *)&internal_freq_fine, 1);
1667 }
1668 return ret;
1669 }
1670
1671 /**
1672 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1673 * with respect to the typical.[get]
1674 * Step: 0.15%. 8-bit format, 2's complement.
1675 *
1676 * @param ctx Read / write interface definitions.(ptr)
1677 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1678 * @retval Interface status (MANDATORY: return 0 -> no Error).
1679 *
1680 */
asm330lhb_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1681 int32_t asm330lhb_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1682 {
1683 asm330lhb_internal_freq_fine_t internal_freq_fine;
1684 int32_t ret;
1685
1686 ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1687 (uint8_t *)&internal_freq_fine, 1);
1688 *val = internal_freq_fine.freq_fine;
1689
1690 return ret;
1691 }
1692
1693 /**
1694 * @brief Enable access to the embedded functions/sensor hub configuration
1695 * registers.[set]
1696 *
1697 * @param ctx Read / write interface definitions.(ptr)
1698 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1699 * @retval Interface status (MANDATORY: return 0 -> no Error).
1700 *
1701 */
asm330lhb_mem_bank_set(stmdev_ctx_t * ctx,asm330lhb_reg_access_t val)1702 int32_t asm330lhb_mem_bank_set(stmdev_ctx_t *ctx,
1703 asm330lhb_reg_access_t val)
1704 {
1705 asm330lhb_func_cfg_access_t func_cfg_access;
1706 int32_t ret;
1707
1708 ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1709 (uint8_t *)&func_cfg_access, 1);
1710 if (ret == 0)
1711 {
1712 func_cfg_access.reg_access = (uint8_t)val;
1713 ret = asm330lhb_write_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1714 (uint8_t *)&func_cfg_access, 1);
1715 }
1716 return ret;
1717 }
1718
1719 /**
1720 * @brief Enable access to the embedded functions/sensor hub configuration
1721 * registers.[get]
1722 *
1723 * @param ctx Read / write interface definitions.(ptr)
1724 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1725 * @retval Interface status (MANDATORY: return 0 -> no Error).
1726 *
1727 */
asm330lhb_mem_bank_get(stmdev_ctx_t * ctx,asm330lhb_reg_access_t * val)1728 int32_t asm330lhb_mem_bank_get(stmdev_ctx_t *ctx,
1729 asm330lhb_reg_access_t *val)
1730 {
1731 asm330lhb_func_cfg_access_t func_cfg_access;
1732 int32_t ret;
1733
1734 ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1735 (uint8_t *)&func_cfg_access, 1);
1736 switch (func_cfg_access.reg_access)
1737 {
1738 case ASM330LHB_USER_BANK:
1739 *val = ASM330LHB_USER_BANK;
1740 break;
1741 case ASM330LHB_EMBEDDED_FUNC_BANK:
1742 *val = ASM330LHB_EMBEDDED_FUNC_BANK;
1743 break;
1744 default:
1745 *val = ASM330LHB_USER_BANK;
1746 break;
1747 }
1748 return ret;
1749 }
1750
1751 /**
1752 * @brief Write a line(byte) in a page.[set]
1753 *
1754 * @param ctx Read / write interface definitions.(ptr)
1755 * @param add Page line address
1756 * @param val Value to write
1757 * @retval Interface status (MANDATORY: return 0 -> no Error).
1758 *
1759 */
asm330lhb_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1760 int32_t asm330lhb_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
1761 uint8_t *val)
1762 {
1763 asm330lhb_page_rw_t page_rw;
1764 asm330lhb_page_sel_t page_sel;
1765 asm330lhb_page_address_t page_address;
1766 int32_t ret;
1767
1768 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1769 if (ret == 0)
1770 {
1771 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1772 }
1773 if (ret == 0)
1774 {
1775 page_rw.page_rw = 0x02U; /* page_write enable */
1776 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1777 }
1778 if (ret == 0)
1779 {
1780 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1781 }
1782 if (ret == 0)
1783 {
1784 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1785 page_sel.not_used_01 = 1;
1786 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1787 (uint8_t *)&page_sel, 1);
1788 }
1789 if (ret == 0)
1790 {
1791 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1792 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1793 (uint8_t *)&page_address, 1);
1794 }
1795 if (ret == 0)
1796 {
1797 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, val, 1);
1798 }
1799 if (ret == 0)
1800 {
1801 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1802 }
1803 if (ret == 0)
1804 {
1805 page_rw.page_rw = 0x00; /* page_write disable */
1806 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1807 }
1808 if (ret == 0)
1809 {
1810 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1811 }
1812 return ret;
1813 }
1814
1815 /**
1816 * @brief Write buffer in a page.[set]
1817 *
1818 * @param ctx Read / write interface definitions.(ptr)
1819 * @param buf Page line address.(ptr)
1820 * @param val Value to write.
1821 * @param len buffer lenght.
1822 * @retval Interface status (MANDATORY: return 0 -> no Error).
1823 *
1824 */
asm330lhb_ln_pg_write(stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1825 int32_t asm330lhb_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
1826 uint8_t *buf, uint8_t len)
1827 {
1828 asm330lhb_page_rw_t page_rw;
1829 asm330lhb_page_sel_t page_sel;
1830 asm330lhb_page_address_t page_address;
1831 int32_t ret;
1832 uint8_t msb, lsb;
1833 uint8_t i ;
1834
1835 msb = (uint8_t)(add / 256U);
1836 lsb = (uint8_t)(add - (msb * 256U));
1837
1838 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1839 if (ret == 0)
1840 {
1841 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1842 }
1843 if (ret == 0)
1844 {
1845 page_rw.page_rw = 0x02U; /* page_write enable*/
1846 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1847 }
1848 if (ret == 0)
1849 {
1850 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1851 }
1852 if (ret == 0)
1853 {
1854 page_sel.page_sel = msb;
1855 page_sel.not_used_01 = 1;
1856 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1857 (uint8_t *)&page_sel, 1);
1858 }
1859 if (ret == 0)
1860 {
1861 page_address.page_addr = lsb;
1862 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1863 (uint8_t *)&page_address, 1);
1864 }
1865 for (i = 0; i < len; i++)
1866 {
1867 if (ret == 0)
1868 {
1869 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, &buf[i], 1);
1870 if (ret == 0)
1871 {
1872 /* Check if page wrap */
1873 if (lsb == 0x00U)
1874 {
1875 msb++;
1876 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
1877 (uint8_t *)&page_sel, 1);
1878 }
1879 lsb++;
1880 }
1881 if (ret == 0)
1882 {
1883 page_sel.page_sel = msb;
1884 page_sel.not_used_01 = 1;
1885 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1886 (uint8_t *)&page_sel, 1);
1887 }
1888 }
1889 }
1890
1891 if (ret == 0)
1892 {
1893 page_sel.page_sel = 0;
1894 page_sel.not_used_01 = 1;
1895 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1896 (uint8_t *)&page_sel, 1);
1897 }
1898 if (ret == 0)
1899 {
1900 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1901 }
1902 if (ret == 0)
1903 {
1904 page_rw.page_rw = 0x00U; /* page_write disable */
1905 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1906 }
1907 if (ret == 0)
1908 {
1909 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1910 }
1911 return ret;
1912 }
1913
1914 /**
1915 * @brief Read a line(byte) in a page.[get]
1916 *
1917 * @param ctx Read / write interface definitions.(ptr)
1918 * @param add Page line address.
1919 * @param val Read value.(ptr)
1920 * @retval Interface status (MANDATORY: return 0 -> no Error).
1921 *
1922 */
asm330lhb_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1923 int32_t asm330lhb_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
1924 uint8_t *val)
1925 {
1926 asm330lhb_page_rw_t page_rw;
1927 asm330lhb_page_sel_t page_sel;
1928 asm330lhb_page_address_t page_address;
1929 int32_t ret;
1930
1931 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1932 if (ret == 0)
1933 {
1934 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1935 }
1936 if (ret == 0)
1937 {
1938 page_rw.page_rw = 0x01U; /* page_read enable*/
1939 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1940 }
1941 if (ret == 0)
1942 {
1943 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1944 }
1945 if (ret == 0)
1946 {
1947 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1948 page_sel.not_used_01 = 1;
1949 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1950 (uint8_t *)&page_sel, 1);
1951 }
1952 if (ret == 0)
1953 {
1954 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1955 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1956 (uint8_t *)&page_address, 1);
1957 }
1958 if (ret == 0)
1959 {
1960 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_VALUE, val, 2);
1961 }
1962 if (ret == 0)
1963 {
1964 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1965 }
1966 if (ret == 0)
1967 {
1968 page_rw.page_rw = 0x00U; /* page_read disable */
1969 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1970 }
1971 if (ret == 0)
1972 {
1973 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1974 }
1975 return ret;
1976 }
1977
1978 /**
1979 * @brief Data-ready pulsed / letched mode.[set]
1980 *
1981 * @param ctx Read / write interface definitions.(ptr)
1982 * @param val Change the values of dataready_pulsed in
1983 * reg COUNTER_BDR_REG1
1984 * @retval Interface status (MANDATORY: return 0 -> no Error).
1985 *
1986 */
asm330lhb_data_ready_mode_set(stmdev_ctx_t * ctx,asm330lhb_dataready_pulsed_t val)1987 int32_t asm330lhb_data_ready_mode_set(stmdev_ctx_t *ctx,
1988 asm330lhb_dataready_pulsed_t val)
1989 {
1990 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
1991 int32_t ret;
1992
1993 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
1994 (uint8_t *)&counter_bdr_reg1, 1);
1995 if (ret == 0)
1996 {
1997 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
1998 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
1999 (uint8_t *)&counter_bdr_reg1, 1);
2000 }
2001 return ret;
2002 }
2003
2004 /**
2005 * @brief Data-ready pulsed / letched mode.[get]
2006 *
2007 * @param ctx Read / write interface definitions.(ptr)
2008 * @param val Get the values of dataready_pulsed in
2009 * reg COUNTER_BDR_REG1
2010 * @retval Interface status (MANDATORY: return 0 -> no Error).
2011 *
2012 */
asm330lhb_data_ready_mode_get(stmdev_ctx_t * ctx,asm330lhb_dataready_pulsed_t * val)2013 int32_t asm330lhb_data_ready_mode_get(stmdev_ctx_t *ctx,
2014 asm330lhb_dataready_pulsed_t *val)
2015 {
2016 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
2017 int32_t ret;
2018
2019 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
2020 (uint8_t *)&counter_bdr_reg1, 1);
2021 switch (counter_bdr_reg1.dataready_pulsed)
2022 {
2023 case ASM330LHB_DRDY_LATCHED:
2024 *val = ASM330LHB_DRDY_LATCHED;
2025 break;
2026 case ASM330LHB_DRDY_PULSED:
2027 *val = ASM330LHB_DRDY_PULSED;
2028 break;
2029 default:
2030 *val = ASM330LHB_DRDY_LATCHED;
2031 break;
2032 }
2033 return ret;
2034 }
2035
2036 /**
2037 * @brief Device Who am I.[get]
2038 *
2039 * @param ctx Read / write interface definitions.(ptr)
2040 * @param buff Buffer that stores data read
2041 * @retval Interface status (MANDATORY: return 0 -> no Error).
2042 *
2043 */
asm330lhb_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)2044 int32_t asm330lhb_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
2045 {
2046 int32_t ret;
2047 ret = asm330lhb_read_reg(ctx, ASM330LHB_WHO_AM_I, buff, 1);
2048 return ret;
2049 }
2050
2051 /**
2052 * @brief Software reset. Restore the default values in user registers.[set]
2053 *
2054 * @param ctx Read / write interface definitions.(ptr)
2055 * @param val Change the values of sw_reset in reg CTRL3_C
2056 * @retval Interface status (MANDATORY: return 0 -> no Error).
2057 *
2058 */
asm330lhb_reset_set(stmdev_ctx_t * ctx,uint8_t val)2059 int32_t asm330lhb_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2060 {
2061 asm330lhb_ctrl3_c_t ctrl3_c;
2062 int32_t ret;
2063
2064 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2065 if (ret == 0)
2066 {
2067 ctrl3_c.sw_reset = (uint8_t)val;
2068 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2069 }
2070 return ret;
2071 }
2072
2073 /**
2074 * @brief Software reset. Restore the default values in user registers.[get]
2075 *
2076 * @param ctx Read / write interface definitions.(ptr)
2077 * @param val Change the values of sw_reset in reg CTRL3_C
2078 * @retval Interface status (MANDATORY: return 0 -> no Error).
2079 *
2080 */
asm330lhb_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2081 int32_t asm330lhb_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2082 {
2083 asm330lhb_ctrl3_c_t ctrl3_c;
2084 int32_t ret;
2085
2086 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2087 *val = ctrl3_c.sw_reset;
2088
2089 return ret;
2090 }
2091
2092 /**
2093 * @brief Register address automatically incremented during a multiple byte
2094 * access with a serial interface.[set]
2095 *
2096 * @param ctx Read / write interface definitions.(ptr)
2097 * @param val Change the values of if_inc in reg CTRL3_C
2098 * @retval Interface status (MANDATORY: return 0 -> no Error).
2099 *
2100 */
asm330lhb_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)2101 int32_t asm330lhb_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
2102 {
2103 asm330lhb_ctrl3_c_t ctrl3_c;
2104 int32_t ret;
2105
2106 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2107 if (ret == 0)
2108 {
2109 ctrl3_c.if_inc = (uint8_t)val;
2110 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2111 }
2112 return ret;
2113 }
2114
2115 /**
2116 * @brief Register address automatically incremented during a multiple byte
2117 * access with a serial interface.[get]
2118 *
2119 * @param ctx Read / write interface definitions.(ptr)
2120 * @param val Change the values of if_inc in reg CTRL3_C
2121 * @retval Interface status (MANDATORY: return 0 -> no Error).
2122 *
2123 */
asm330lhb_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)2124 int32_t asm330lhb_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
2125 {
2126 asm330lhb_ctrl3_c_t ctrl3_c;
2127 int32_t ret;
2128
2129 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2130 *val = ctrl3_c.if_inc;
2131
2132 return ret;
2133 }
2134
2135 /**
2136 * @brief Reboot memory content. Reload the calibration parameters.[set]
2137 *
2138 * @param ctx Read / write interface definitions.(ptr)
2139 * @param val Change the values of boot in reg CTRL3_C
2140 * @retval Interface status (MANDATORY: return 0 -> no Error).
2141 *
2142 */
asm330lhb_boot_set(stmdev_ctx_t * ctx,uint8_t val)2143 int32_t asm330lhb_boot_set(stmdev_ctx_t *ctx, uint8_t val)
2144 {
2145 asm330lhb_ctrl3_c_t ctrl3_c;
2146 int32_t ret;
2147
2148 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2149 if (ret == 0)
2150 {
2151 ctrl3_c.boot = (uint8_t)val;
2152 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2153 }
2154 return ret;
2155 }
2156
2157 /**
2158 * @brief Reboot memory content. Reload the calibration parameters.[get]
2159 *
2160 * @param ctx Read / write interface definitions.(ptr)
2161 * @param val Change the values of boot in reg CTRL3_C
2162 * @retval Interface status (MANDATORY: return 0 -> no Error).
2163 *
2164 */
asm330lhb_boot_get(stmdev_ctx_t * ctx,uint8_t * val)2165 int32_t asm330lhb_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
2166 {
2167 asm330lhb_ctrl3_c_t ctrl3_c;
2168 int32_t ret;
2169
2170 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2171 *val = ctrl3_c.boot;
2172
2173 return ret;
2174 }
2175
2176
2177
2178 /**
2179 * @brief Linear acceleration sensor self-test enable.[set]
2180 *
2181 * @param ctx Read / write interface definitions.(ptr)
2182 * @param val Change the values of st_xl in reg CTRL5_C
2183 * @retval Interface status (MANDATORY: return 0 -> no Error).
2184 *
2185 */
asm330lhb_xl_self_test_set(stmdev_ctx_t * ctx,asm330lhb_st_xl_t val)2186 int32_t asm330lhb_xl_self_test_set(stmdev_ctx_t *ctx,
2187 asm330lhb_st_xl_t val)
2188 {
2189 asm330lhb_ctrl5_c_t ctrl5_c;
2190 int32_t ret;
2191
2192 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2193 if (ret == 0)
2194 {
2195 ctrl5_c.st_xl = (uint8_t)val;
2196 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2197 }
2198 return ret;
2199 }
2200
2201 /**
2202 * @brief Linear acceleration sensor self-test enable.[get]
2203 *
2204 * @param ctx Read / write interface definitions.(ptr)
2205 * @param val Get the values of st_xl in reg CTRL5_C
2206 * @retval Interface status (MANDATORY: return 0 -> no Error).
2207 *
2208 */
asm330lhb_xl_self_test_get(stmdev_ctx_t * ctx,asm330lhb_st_xl_t * val)2209 int32_t asm330lhb_xl_self_test_get(stmdev_ctx_t *ctx,
2210 asm330lhb_st_xl_t *val)
2211 {
2212 asm330lhb_ctrl5_c_t ctrl5_c;
2213 int32_t ret;
2214
2215 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2216
2217 switch (ctrl5_c.st_xl)
2218 {
2219 case ASM330LHB_XL_ST_DISABLE:
2220 *val = ASM330LHB_XL_ST_DISABLE;
2221 break;
2222 case ASM330LHB_XL_ST_POSITIVE:
2223 *val = ASM330LHB_XL_ST_POSITIVE;
2224 break;
2225 case ASM330LHB_XL_ST_NEGATIVE:
2226 *val = ASM330LHB_XL_ST_NEGATIVE;
2227 break;
2228 default:
2229 *val = ASM330LHB_XL_ST_DISABLE;
2230 break;
2231 }
2232 return ret;
2233 }
2234
2235 /**
2236 * @brief Angular rate sensor self-test enable.[set]
2237 *
2238 * @param ctx Read / write interface definitions.(ptr)
2239 * @param val Change the values of st_g in reg CTRL5_C
2240 * @retval Interface status (MANDATORY: return 0 -> no Error).
2241 *
2242 */
asm330lhb_gy_self_test_set(stmdev_ctx_t * ctx,asm330lhb_st_g_t val)2243 int32_t asm330lhb_gy_self_test_set(stmdev_ctx_t *ctx,
2244 asm330lhb_st_g_t val)
2245 {
2246 asm330lhb_ctrl5_c_t ctrl5_c;
2247 int32_t ret;
2248
2249 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2250 if (ret == 0)
2251 {
2252 ctrl5_c.st_g = (uint8_t)val;
2253 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2254 }
2255 return ret;
2256 }
2257
2258 /**
2259 * @brief Angular rate sensor self-test enable.[get]
2260 *
2261 * @param ctx Read / write interface definitions.(ptr)
2262 * @param val Get the values of st_g in reg CTRL5_C
2263 * @retval Interface status (MANDATORY: return 0 -> no Error).
2264 *
2265 */
asm330lhb_gy_self_test_get(stmdev_ctx_t * ctx,asm330lhb_st_g_t * val)2266 int32_t asm330lhb_gy_self_test_get(stmdev_ctx_t *ctx,
2267 asm330lhb_st_g_t *val)
2268 {
2269 asm330lhb_ctrl5_c_t ctrl5_c;
2270 int32_t ret;
2271
2272 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2273
2274 switch (ctrl5_c.st_g)
2275 {
2276 case ASM330LHB_GY_ST_DISABLE:
2277 *val = ASM330LHB_GY_ST_DISABLE;
2278 break;
2279 case ASM330LHB_GY_ST_POSITIVE:
2280 *val = ASM330LHB_GY_ST_POSITIVE;
2281 break;
2282 case ASM330LHB_GY_ST_NEGATIVE:
2283 *val = ASM330LHB_GY_ST_NEGATIVE;
2284 break;
2285 default:
2286 *val = ASM330LHB_GY_ST_DISABLE;
2287 break;
2288 }
2289 return ret;
2290 }
2291
2292 /**
2293 * @}
2294 *
2295 */
2296
2297 /**
2298 * @defgroup ASM330LHB_filters
2299 * @brief This section group all the functions concerning the
2300 * filters configuration
2301 * @{
2302 *
2303 */
2304
2305 /**
2306 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2307 *
2308 * @param ctx Read / write interface definitions.(ptr)
2309 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2310 * @retval Interface status (MANDATORY: return 0 -> no Error).
2311 *
2312 */
asm330lhb_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2313 int32_t asm330lhb_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2314 {
2315 asm330lhb_ctrl1_xl_t ctrl1_xl;
2316 int32_t ret;
2317
2318 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2319 if (ret == 0)
2320 {
2321 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2322 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
2323 (uint8_t *)&ctrl1_xl, 1);
2324 }
2325 return ret;
2326 }
2327
2328 /**
2329 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2330 *
2331 * @param ctx Read / write interface definitions.(ptr)
2332 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2333 * @retval Interface status (MANDATORY: return 0 -> no Error).
2334 *
2335 */
asm330lhb_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2336 int32_t asm330lhb_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2337 {
2338 asm330lhb_ctrl1_xl_t ctrl1_xl;
2339 int32_t ret;
2340
2341 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2342 *val = ctrl1_xl.lpf2_xl_en;
2343
2344 return ret;
2345 }
2346
2347 /**
2348 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2349 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2350 *
2351 * @param ctx Read / write interface definitions.(ptr)
2352 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2353 * @retval Interface status (MANDATORY: return 0 -> no Error).
2354 *
2355 */
asm330lhb_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2356 int32_t asm330lhb_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2357 {
2358 asm330lhb_ctrl4_c_t ctrl4_c;
2359 int32_t ret;
2360
2361 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2362 if (ret == 0)
2363 {
2364 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2365 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2366 }
2367 return ret;
2368 }
2369
2370 /**
2371 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2372 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2373 *
2374 * @param ctx Read / write interface definitions.(ptr)
2375 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2376 * @retval Interface status (MANDATORY: return 0 -> no Error).
2377 *
2378 */
asm330lhb_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2379 int32_t asm330lhb_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2380 {
2381 asm330lhb_ctrl4_c_t ctrl4_c;
2382 int32_t ret;
2383
2384 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2385 *val = ctrl4_c.lpf1_sel_g;
2386
2387 return ret;
2388 }
2389
2390 /**
2391 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2392 * (XL and Gyro independently masked).[set]
2393 *
2394 * @param ctx Read / write interface definitions.(ptr)
2395 * @param val Change the values of drdy_mask in reg CTRL4_C
2396 * @retval Interface status (MANDATORY: return 0 -> no Error).
2397 *
2398 */
asm330lhb_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2399 int32_t asm330lhb_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val)
2400 {
2401 asm330lhb_ctrl4_c_t ctrl4_c;
2402 int32_t ret;
2403
2404 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2405 if (ret == 0)
2406 {
2407 ctrl4_c.drdy_mask = (uint8_t)val;
2408 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2409 }
2410 return ret;
2411 }
2412
2413 /**
2414 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2415 * (XL and Gyro independently masked).[get]
2416 *
2417 * @param ctx Read / write interface definitions.(ptr)
2418 * @param val Change the values of drdy_mask in reg CTRL4_C
2419 * @retval Interface status (MANDATORY: return 0 -> no Error).
2420 *
2421 */
asm330lhb_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2422 int32_t asm330lhb_filter_settling_mask_get(stmdev_ctx_t *ctx,
2423 uint8_t *val)
2424 {
2425 asm330lhb_ctrl4_c_t ctrl4_c;
2426 int32_t ret;
2427
2428 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2429 *val = ctrl4_c.drdy_mask;
2430
2431 return ret;
2432 }
2433
2434 /**
2435 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2436 *
2437 * @param ctx Read / write interface definitions.(ptr)
2438 * @param val Change the values of ftype in reg CTRL6_C
2439 * @retval Interface status (MANDATORY: return 0 -> no Error).
2440 *
2441 */
asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,asm330lhb_ftype_t val)2442 int32_t asm330lhb_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2443 asm330lhb_ftype_t val)
2444 {
2445 asm330lhb_ctrl6_c_t ctrl6_c;
2446 int32_t ret;
2447
2448 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2449 if (ret == 0)
2450 {
2451 ctrl6_c.ftype = (uint8_t)val;
2452 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2453 }
2454 return ret;
2455 }
2456
2457 /**
2458 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2459 *
2460 * @param ctx Read / write interface definitions.(ptr)
2461 * @param val Get the values of ftype in reg CTRL6_C
2462 * @retval Interface status (MANDATORY: return 0 -> no Error).
2463 *
2464 */
asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,asm330lhb_ftype_t * val)2465 int32_t asm330lhb_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2466 asm330lhb_ftype_t *val)
2467 {
2468 asm330lhb_ctrl6_c_t ctrl6_c;
2469 int32_t ret;
2470
2471 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2472
2473 switch (ctrl6_c.ftype)
2474 {
2475 case ASM330LHB_ULTRA_LIGHT:
2476 *val = ASM330LHB_ULTRA_LIGHT;
2477 break;
2478 case ASM330LHB_VERY_LIGHT:
2479 *val = ASM330LHB_VERY_LIGHT;
2480 break;
2481 case ASM330LHB_LIGHT:
2482 *val = ASM330LHB_LIGHT;
2483 break;
2484 case ASM330LHB_MEDIUM:
2485 *val = ASM330LHB_MEDIUM;
2486 break;
2487 case ASM330LHB_STRONG:
2488 *val = ASM330LHB_STRONG;
2489 break;
2490 case ASM330LHB_VERY_STRONG:
2491 *val = ASM330LHB_VERY_STRONG;
2492 break;
2493 case ASM330LHB_AGGRESSIVE:
2494 *val = ASM330LHB_AGGRESSIVE;
2495 break;
2496 case ASM330LHB_XTREME:
2497 *val = ASM330LHB_XTREME;
2498 break;
2499 default:
2500 *val = ASM330LHB_ULTRA_LIGHT;
2501 break;
2502 }
2503 return ret;
2504 }
2505
2506 /**
2507 * @brief Low pass filter 2 on 6D function selection.[set]
2508 *
2509 * @param ctx Read / write interface definitions.(ptr)
2510 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2511 * @retval Interface status (MANDATORY: return 0 -> no Error).
2512 *
2513 */
asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2514 int32_t asm330lhb_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2515 {
2516 asm330lhb_ctrl8_xl_t ctrl8_xl;
2517 int32_t ret;
2518
2519 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2520 if (ret == 0)
2521 {
2522 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2523 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2524 (uint8_t *)&ctrl8_xl, 1);
2525 }
2526 return ret;
2527 }
2528
2529 /**
2530 * @brief Low pass filter 2 on 6D function selection.[get]
2531 *
2532 * @param ctx Read / write interface definitions.(ptr)
2533 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2534 * @retval Interface status (MANDATORY: return 0 -> no Error).
2535 *
2536 */
asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2537 int32_t asm330lhb_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2538 {
2539 asm330lhb_ctrl8_xl_t ctrl8_xl;
2540 int32_t ret;
2541
2542 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2543 *val = ctrl8_xl.low_pass_on_6d;
2544
2545 return ret;
2546 }
2547
2548 /**
2549 * @brief Accelerometer slope filter / high-pass filter selection
2550 * on output.[set]
2551 *
2552 * @param ctx Read / write interface definitions.(ptr)
2553 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2554 * @retval Interface status (MANDATORY: return 0 -> no Error).
2555 *
2556 */
asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,asm330lhb_hp_slope_xl_en_t val)2557 int32_t asm330lhb_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2558 asm330lhb_hp_slope_xl_en_t val)
2559 {
2560 asm330lhb_ctrl8_xl_t ctrl8_xl;
2561 int32_t ret;
2562
2563 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2564 if (ret == 0)
2565 {
2566 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2567 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2568 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2569 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2570 (uint8_t *)&ctrl8_xl, 1);
2571 }
2572 return ret;
2573 }
2574
2575 /**
2576 * @brief Accelerometer slope filter / high-pass filter selection on
2577 * output.[get]
2578 *
2579 * @param ctx Read / write interface definitions.(ptr)
2580 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2581 * @retval Interface status (MANDATORY: return 0 -> no Error).
2582 *
2583 */
asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,asm330lhb_hp_slope_xl_en_t * val)2584 int32_t asm330lhb_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2585 asm330lhb_hp_slope_xl_en_t *val)
2586 {
2587 asm330lhb_ctrl8_xl_t ctrl8_xl;
2588 int32_t ret;
2589
2590 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2591 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) +
2592 ctrl8_xl.hpcf_xl))
2593 {
2594 case ASM330LHB_HP_PATH_DISABLE_ON_OUT:
2595 *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT;
2596 break;
2597 case ASM330LHB_SLOPE_ODR_DIV_4:
2598 *val = ASM330LHB_SLOPE_ODR_DIV_4;
2599 break;
2600 case ASM330LHB_HP_ODR_DIV_10:
2601 *val = ASM330LHB_HP_ODR_DIV_10;
2602 break;
2603 case ASM330LHB_HP_ODR_DIV_20:
2604 *val = ASM330LHB_HP_ODR_DIV_20;
2605 break;
2606 case ASM330LHB_HP_ODR_DIV_45:
2607 *val = ASM330LHB_HP_ODR_DIV_45;
2608 break;
2609 case ASM330LHB_HP_ODR_DIV_100:
2610 *val = ASM330LHB_HP_ODR_DIV_100;
2611 break;
2612 case ASM330LHB_HP_ODR_DIV_200:
2613 *val = ASM330LHB_HP_ODR_DIV_200;
2614 break;
2615 case ASM330LHB_HP_ODR_DIV_400:
2616 *val = ASM330LHB_HP_ODR_DIV_400;
2617 break;
2618 case ASM330LHB_HP_ODR_DIV_800:
2619 *val = ASM330LHB_HP_ODR_DIV_800;
2620 break;
2621 case ASM330LHB_HP_REF_MD_ODR_DIV_10:
2622 *val = ASM330LHB_HP_REF_MD_ODR_DIV_10;
2623 break;
2624 case ASM330LHB_HP_REF_MD_ODR_DIV_20:
2625 *val = ASM330LHB_HP_REF_MD_ODR_DIV_20;
2626 break;
2627 case ASM330LHB_HP_REF_MD_ODR_DIV_45:
2628 *val = ASM330LHB_HP_REF_MD_ODR_DIV_45;
2629 break;
2630 case ASM330LHB_HP_REF_MD_ODR_DIV_100:
2631 *val = ASM330LHB_HP_REF_MD_ODR_DIV_100;
2632 break;
2633 case ASM330LHB_HP_REF_MD_ODR_DIV_200:
2634 *val = ASM330LHB_HP_REF_MD_ODR_DIV_200;
2635 break;
2636 case ASM330LHB_HP_REF_MD_ODR_DIV_400:
2637 *val = ASM330LHB_HP_REF_MD_ODR_DIV_400;
2638 break;
2639 case ASM330LHB_HP_REF_MD_ODR_DIV_800:
2640 *val = ASM330LHB_HP_REF_MD_ODR_DIV_800;
2641 break;
2642 case ASM330LHB_LP_ODR_DIV_10:
2643 *val = ASM330LHB_LP_ODR_DIV_10;
2644 break;
2645 case ASM330LHB_LP_ODR_DIV_20:
2646 *val = ASM330LHB_LP_ODR_DIV_20;
2647 break;
2648 case ASM330LHB_LP_ODR_DIV_45:
2649 *val = ASM330LHB_LP_ODR_DIV_45;
2650 break;
2651 case ASM330LHB_LP_ODR_DIV_100:
2652 *val = ASM330LHB_LP_ODR_DIV_100;
2653 break;
2654 case ASM330LHB_LP_ODR_DIV_200:
2655 *val = ASM330LHB_LP_ODR_DIV_200;
2656 break;
2657 case ASM330LHB_LP_ODR_DIV_400:
2658 *val = ASM330LHB_LP_ODR_DIV_400;
2659 break;
2660 case ASM330LHB_LP_ODR_DIV_800:
2661 *val = ASM330LHB_LP_ODR_DIV_800;
2662 break;
2663 default:
2664 *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT;
2665 break;
2666 }
2667 return ret;
2668 }
2669
2670 /**
2671 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2672 * The filter sets the second samples after writing this bit.
2673 * Active only during device exit from powerdown mode.[set]
2674 *
2675 * @param ctx Read / write interface definitions.(ptr)
2676 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2677 * @retval Interface status (MANDATORY: return 0 -> no Error).
2678 *
2679 */
asm330lhb_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2680 int32_t asm330lhb_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2681 {
2682 asm330lhb_ctrl8_xl_t ctrl8_xl;
2683 int32_t ret;
2684
2685 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2686 if (ret == 0)
2687 {
2688 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2689 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2690 (uint8_t *)&ctrl8_xl, 1);
2691 }
2692 return ret;
2693 }
2694
2695 /**
2696 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2697 * The filter sets the second samples after writing
2698 * this bit. Active only during device exit from powerdown mode.[get]
2699 *
2700 * @param ctx Read / write interface definitions.(ptr)
2701 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2702 * @retval Interface status (MANDATORY: return 0 -> no Error).
2703 *
2704 */
asm330lhb_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2705 int32_t asm330lhb_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
2706 {
2707 asm330lhb_ctrl8_xl_t ctrl8_xl;
2708 int32_t ret;
2709
2710 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2711 *val = ctrl8_xl.fastsettl_mode_xl;
2712
2713 return ret;
2714 }
2715
2716 /**
2717 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2718 * functions.[set]
2719 *
2720 * @param ctx Read / write interface definitions.(ptr)
2721 * @param val Change the values of slope_fds in reg INT_CFG0
2722 * @retval Interface status (MANDATORY: return 0 -> no Error).
2723 *
2724 */
asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t * ctx,asm330lhb_slope_fds_t val)2725 int32_t asm330lhb_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
2726 asm330lhb_slope_fds_t val)
2727 {
2728 asm330lhb_int_cfg0_t int_cfg0;
2729 int32_t ret;
2730
2731 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2732 if (ret == 0)
2733 {
2734 int_cfg0.slope_fds = (uint8_t)val;
2735 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
2736 (uint8_t *)&int_cfg0, 1);
2737 }
2738 return ret;
2739 }
2740
2741 /**
2742 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2743 * functions.[get]
2744 *
2745 * @param ctx Read / write interface definitions.(ptr)
2746 * @param val Get the values of slope_fds in reg INT_CFG0
2747 * @retval Interface status (MANDATORY: return 0 -> no Error).
2748 *
2749 */
asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t * ctx,asm330lhb_slope_fds_t * val)2750 int32_t asm330lhb_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
2751 asm330lhb_slope_fds_t *val)
2752 {
2753 asm330lhb_int_cfg0_t int_cfg0;
2754 int32_t ret;
2755
2756 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2757 switch (int_cfg0.slope_fds)
2758 {
2759 case ASM330LHB_USE_SLOPE:
2760 *val = ASM330LHB_USE_SLOPE;
2761 break;
2762 case ASM330LHB_USE_HPF:
2763 *val = ASM330LHB_USE_HPF;
2764 break;
2765 default:
2766 *val = ASM330LHB_USE_SLOPE;
2767 break;
2768 }
2769 return ret;
2770 }
2771
2772 /**
2773 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2774 * only if the gyro is in HP mode.[set]
2775 *
2776 * @param ctx Read / write interface definitions.(ptr)
2777 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2778 * @retval Interface status (MANDATORY: return 0 -> no Error).
2779 *
2780 */
asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t * ctx,asm330lhb_hpm_g_t val)2781 int32_t asm330lhb_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
2782 asm330lhb_hpm_g_t val)
2783 {
2784 asm330lhb_ctrl7_g_t ctrl7_g;
2785 int32_t ret;
2786
2787 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2788 if (ret == 0)
2789 {
2790 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2791 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2792 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2793 }
2794 return ret;
2795 }
2796
2797 /**
2798 * @brief Enables gyroscope digital high-pass filter. The filter is
2799 * enabled only if the gyro is in HP mode.[get]
2800 *
2801 * @param ctx Read / write interface definitions.(ptr)
2802 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2803 * @retval Interface status (MANDATORY: return 0 -> no Error).
2804 *
2805 */
asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t * ctx,asm330lhb_hpm_g_t * val)2806 int32_t asm330lhb_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
2807 asm330lhb_hpm_g_t *val)
2808 {
2809 asm330lhb_ctrl7_g_t ctrl7_g;
2810 int32_t ret;
2811
2812 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2813
2814 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
2815 {
2816 case ASM330LHB_HP_FILTER_NONE:
2817 *val = ASM330LHB_HP_FILTER_NONE;
2818 break;
2819 case ASM330LHB_HP_FILTER_16mHz:
2820 *val = ASM330LHB_HP_FILTER_16mHz;
2821 break;
2822 case ASM330LHB_HP_FILTER_65mHz:
2823 *val = ASM330LHB_HP_FILTER_65mHz;
2824 break;
2825 case ASM330LHB_HP_FILTER_260mHz:
2826 *val = ASM330LHB_HP_FILTER_260mHz;
2827 break;
2828 case ASM330LHB_HP_FILTER_1Hz04:
2829 *val = ASM330LHB_HP_FILTER_1Hz04;
2830 break;
2831 default:
2832 *val = ASM330LHB_HP_FILTER_NONE;
2833 break;
2834 }
2835 return ret;
2836 }
2837
2838 /**
2839 * @}
2840 *
2841 */
2842
2843 /**
2844 * @defgroup ASM330LHB_ serial_interface
2845 * @brief This section groups all the functions concerning main
2846 * serial interface management (not auxiliary)
2847 * @{
2848 *
2849 */
2850
2851 /**
2852 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2853 *
2854 * @param ctx Read / write interface definitions.(ptr)
2855 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
2856 * @retval Interface status (MANDATORY: return 0 -> no Error).
2857 *
2858 */
asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t * ctx,asm330lhb_sdo_pu_en_t val)2859 int32_t asm330lhb_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
2860 asm330lhb_sdo_pu_en_t val)
2861 {
2862 asm330lhb_pin_ctrl_t pin_ctrl;
2863 int32_t ret;
2864
2865 ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2866 if (ret == 0)
2867 {
2868 pin_ctrl.sdo_pu_en = (uint8_t)val;
2869 ret = asm330lhb_write_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2870 }
2871 return ret;
2872 }
2873
2874 /**
2875 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2876 *
2877 * @param ctx Read / write interface definitions.(ptr)
2878 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2879 * @retval Interface status (MANDATORY: return 0 -> no Error).
2880 *
2881 */
asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t * ctx,asm330lhb_sdo_pu_en_t * val)2882 int32_t asm330lhb_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
2883 asm330lhb_sdo_pu_en_t *val)
2884 {
2885 asm330lhb_pin_ctrl_t pin_ctrl;
2886 int32_t ret;
2887
2888 ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2889
2890 switch (pin_ctrl.sdo_pu_en)
2891 {
2892 case ASM330LHB_PULL_UP_DISC:
2893 *val = ASM330LHB_PULL_UP_DISC;
2894 break;
2895 case ASM330LHB_PULL_UP_CONNECT:
2896 *val = ASM330LHB_PULL_UP_CONNECT;
2897 break;
2898 default:
2899 *val = ASM330LHB_PULL_UP_DISC;
2900 break;
2901 }
2902 return ret;
2903 }
2904
2905 /**
2906 * @brief Connect/Disconnect INT1 pull-down.[set]
2907 *
2908 * @param ctx Read / write interface definitions.(ptr)
2909 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
2910 * @retval Interface status (MANDATORY: return 0 -> no Error).
2911 *
2912 */
asm330lhb_int1_mode_set(stmdev_ctx_t * ctx,asm330lhb_pd_dis_int1_t val)2913 int32_t asm330lhb_int1_mode_set(stmdev_ctx_t *ctx,
2914 asm330lhb_pd_dis_int1_t val)
2915 {
2916 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
2917 int32_t ret;
2918
2919 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2920 if (ret == 0)
2921 {
2922 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
2923 ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB,
2924 (uint8_t *)&i3c_bus_avb, 1);
2925 }
2926 return ret;
2927 }
2928
2929 /**
2930 * @brief Connect/Disconnect INT1 pull-down.[get]
2931 *
2932 * @param ctx Read / write interface definitions.(ptr)
2933 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
2934 * @retval Interface status (MANDATORY: return 0 -> no Error).
2935 *
2936 */
asm330lhb_int1_mode_get(stmdev_ctx_t * ctx,asm330lhb_pd_dis_int1_t * val)2937 int32_t asm330lhb_int1_mode_get(stmdev_ctx_t *ctx,
2938 asm330lhb_pd_dis_int1_t *val)
2939 {
2940 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
2941 int32_t ret;
2942
2943 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2944
2945 switch (i3c_bus_avb.pd_dis_int1)
2946 {
2947 case ASM330LHB_PULL_DOWN_CONNECT:
2948 *val = ASM330LHB_PULL_DOWN_CONNECT;
2949 break;
2950 case ASM330LHB_PULL_DOWN_DISC:
2951 *val = ASM330LHB_PULL_DOWN_DISC;
2952 break;
2953 default:
2954 *val = ASM330LHB_PULL_DOWN_CONNECT;
2955 break;
2956 }
2957 return ret;
2958 }
2959
2960 /**
2961 * @brief SPI Serial Interface Mode selection.[set]
2962 *
2963 * @param ctx Read / write interface definitions.(ptr)
2964 * @param val Change the values of sim in reg CTRL3_C
2965 * @retval Interface status (MANDATORY: return 0 -> no Error).
2966 *
2967 */
asm330lhb_spi_mode_set(stmdev_ctx_t * ctx,asm330lhb_sim_t val)2968 int32_t asm330lhb_spi_mode_set(stmdev_ctx_t *ctx, asm330lhb_sim_t val)
2969 {
2970 asm330lhb_ctrl3_c_t ctrl3_c;
2971 int32_t ret;
2972
2973 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2974 if (ret == 0)
2975 {
2976 ctrl3_c.sim = (uint8_t)val;
2977 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2978 }
2979 return ret;
2980 }
2981
2982 /**
2983 * @brief SPI Serial Interface Mode selection.[get]
2984 *
2985 * @param ctx Read / write interface definitions.(ptr)
2986 * @param val Get the values of sim in reg CTRL3_C
2987 * @retval Interface status (MANDATORY: return 0 -> no Error).
2988 *
2989 */
asm330lhb_spi_mode_get(stmdev_ctx_t * ctx,asm330lhb_sim_t * val)2990 int32_t asm330lhb_spi_mode_get(stmdev_ctx_t *ctx, asm330lhb_sim_t *val)
2991 {
2992 asm330lhb_ctrl3_c_t ctrl3_c;
2993 int32_t ret;
2994
2995 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2996
2997 switch (ctrl3_c.sim)
2998 {
2999 case ASM330LHB_SPI_4_WIRE:
3000 *val = ASM330LHB_SPI_4_WIRE;
3001 break;
3002 case ASM330LHB_SPI_3_WIRE:
3003 *val = ASM330LHB_SPI_3_WIRE;
3004 break;
3005 default:
3006 *val = ASM330LHB_SPI_4_WIRE;
3007 break;
3008 }
3009 return ret;
3010 }
3011
3012 /**
3013 * @brief Disable / Enable I2C interface.[set]
3014 *
3015 * @param ctx Read / write interface definitions.(ptr)
3016 * @param val Change the values of i2c_disable in reg CTRL4_C
3017 * @retval Interface status (MANDATORY: return 0 -> no Error).
3018 *
3019 */
asm330lhb_i2c_interface_set(stmdev_ctx_t * ctx,asm330lhb_i2c_disable_t val)3020 int32_t asm330lhb_i2c_interface_set(stmdev_ctx_t *ctx,
3021 asm330lhb_i2c_disable_t val)
3022 {
3023 asm330lhb_ctrl4_c_t ctrl4_c;
3024 int32_t ret;
3025
3026 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3027 if (ret == 0)
3028 {
3029 ctrl4_c.i2c_disable = (uint8_t)val;
3030 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3031 }
3032 return ret;
3033 }
3034
3035 /**
3036 * @brief Disable / Enable I2C interface.[get]
3037 *
3038 * @param ctx Read / write interface definitions.(ptr)
3039 * @param val Get the values of i2c reg CTRL4_C
3040 * @retval Interface status (MANDATORY: return 0 -> no Error).
3041 *
3042 */
asm330lhb_i2c_interface_get(stmdev_ctx_t * ctx,asm330lhb_i2c_disable_t * val)3043 int32_t asm330lhb_i2c_interface_get(stmdev_ctx_t *ctx,
3044 asm330lhb_i2c_disable_t *val)
3045 {
3046 asm330lhb_ctrl4_c_t ctrl4_c;
3047 int32_t ret;
3048
3049 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3050
3051 switch (ctrl4_c.i2c_disable)
3052 {
3053 case ASM330LHB_I2C_ENABLE:
3054 *val = ASM330LHB_I2C_ENABLE;
3055 break;
3056 case ASM330LHB_I2C_DISABLE:
3057 *val = ASM330LHB_I2C_DISABLE;
3058 break;
3059 default:
3060 *val = ASM330LHB_I2C_ENABLE;
3061 break;
3062 }
3063 return ret;
3064 }
3065
3066 /**
3067 * @brief I3C Enable/Disable communication protocol.[set]
3068 *
3069 * @param ctx Read / write interface definitions.(ptr)
3070 * @param val Change the values of i3c_disable in reg CTRL9_XL
3071 * @retval Interface status (MANDATORY: return 0 -> no Error).
3072 *
3073 */
asm330lhb_i3c_disable_set(stmdev_ctx_t * ctx,asm330lhb_i3c_disable_t val)3074 int32_t asm330lhb_i3c_disable_set(stmdev_ctx_t *ctx,
3075 asm330lhb_i3c_disable_t val)
3076 {
3077 asm330lhb_ctrl9_xl_t ctrl9_xl;
3078 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
3079 int32_t ret;
3080
3081 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3082 if (ret == 0)
3083 {
3084 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3085 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
3086 (uint8_t *)&ctrl9_xl, 1);
3087 }
3088 if (ret == 0)
3089 {
3090 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3091 (uint8_t *)&i3c_bus_avb, 1);
3092 }
3093 if (ret == 0)
3094 {
3095 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3096 ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3097 (uint8_t *)&i3c_bus_avb, 1);
3098 }
3099 return ret;
3100 }
3101
3102 /**
3103 * @brief I3C Enable/Disable communication protocol.[get]
3104 *
3105 * @param ctx Read / write interface definitions.(ptr)
3106 * @param val Change the values of i3c_disable in reg CTRL9_XL
3107 * @retval Interface status (MANDATORY: return 0 -> no Error).
3108 *
3109 */
asm330lhb_i3c_disable_get(stmdev_ctx_t * ctx,asm330lhb_i3c_disable_t * val)3110 int32_t asm330lhb_i3c_disable_get(stmdev_ctx_t *ctx,
3111 asm330lhb_i3c_disable_t *val)
3112 {
3113 asm330lhb_ctrl9_xl_t ctrl9_xl;
3114 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
3115 int32_t ret;
3116
3117 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3118 if (ret == 0)
3119 {
3120 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3121 (uint8_t *)&i3c_bus_avb, 1);
3122 }
3123 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
3124 {
3125 case ASM330LHB_I3C_DISABLE:
3126 *val = ASM330LHB_I3C_DISABLE;
3127 break;
3128 case ASM330LHB_I3C_ENABLE_T_50us:
3129 *val = ASM330LHB_I3C_ENABLE_T_50us;
3130 break;
3131 case ASM330LHB_I3C_ENABLE_T_2us:
3132 *val = ASM330LHB_I3C_ENABLE_T_2us;
3133 break;
3134 case ASM330LHB_I3C_ENABLE_T_1ms:
3135 *val = ASM330LHB_I3C_ENABLE_T_1ms;
3136 break;
3137 case ASM330LHB_I3C_ENABLE_T_25ms:
3138 *val = ASM330LHB_I3C_ENABLE_T_25ms;
3139 break;
3140 default:
3141 *val = ASM330LHB_I3C_DISABLE;
3142 break;
3143 }
3144 return ret;
3145 }
3146
3147 /**
3148 * @}
3149 *
3150 */
3151
3152 /**
3153 * @defgroup ASM330LHB_interrupt_pins
3154 * @brief This section groups all the functions that manage
3155 * interrupt pins
3156 * @{
3157 *
3158 */
3159
3160 /**
3161 * @brief Select the signal that need to route on int1 pad.[set]
3162 *
3163 * @param ctx read / write interface definitions
3164 * @param val struct of registers: INT1_CTRL,
3165 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3166 * FSM_INT1_B
3167 *
3168 */
asm330lhb_pin_int1_route_set(stmdev_ctx_t * ctx,asm330lhb_pin_int1_route_t * val)3169 int32_t asm330lhb_pin_int1_route_set(stmdev_ctx_t *ctx,
3170 asm330lhb_pin_int1_route_t *val)
3171 {
3172 asm330lhb_pin_int2_route_t pin_int2_route;
3173 asm330lhb_int_cfg1_t int_cfg1;
3174 int32_t ret;
3175
3176 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3177 if (ret == 0)
3178 {
3179 ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1,
3180 (uint8_t *)&val->mlc_int1, 1);
3181 }
3182 if (ret == 0)
3183 {
3184 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1,
3185 (uint8_t *)&val->emb_func_int1, 1);
3186 }
3187 if (ret == 0)
3188 {
3189 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A,
3190 (uint8_t *)&val->fsm_int1_a, 1);
3191 }
3192 if (ret == 0)
3193 {
3194 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B,
3195 (uint8_t *)&val->fsm_int1_b, 1);
3196 }
3197 if (ret == 0)
3198 {
3199 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3200 }
3201
3202 if (ret == 0)
3203 {
3204 if ((val->emb_func_int1.int1_fsm_lc
3205 | val->fsm_int1_a.int1_fsm1
3206 | val->fsm_int1_a.int1_fsm2
3207 | val->fsm_int1_a.int1_fsm3
3208 | val->fsm_int1_a.int1_fsm4
3209 | val->fsm_int1_a.int1_fsm5
3210 | val->fsm_int1_a.int1_fsm6
3211 | val->fsm_int1_a.int1_fsm7
3212 | val->fsm_int1_a.int1_fsm8
3213 | val->fsm_int1_b.int1_fsm9
3214 | val->fsm_int1_b.int1_fsm10
3215 | val->fsm_int1_b.int1_fsm11
3216 | val->fsm_int1_b.int1_fsm12
3217 | val->fsm_int1_b.int1_fsm13
3218 | val->fsm_int1_b.int1_fsm14
3219 | val->fsm_int1_b.int1_fsm15
3220 | val->fsm_int1_b.int1_fsm16
3221 | val->mlc_int1.int1_mlc1
3222 | val->mlc_int1.int1_mlc2
3223 | val->mlc_int1.int1_mlc3
3224 | val->mlc_int1.int1_mlc4
3225 | val->mlc_int1.int1_mlc5
3226 | val->mlc_int1.int1_mlc6
3227 | val->mlc_int1.int1_mlc7
3228 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
3229 {
3230 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3231 }
3232 else
3233 {
3234 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3235 }
3236 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL,
3237 (uint8_t *)&val->int1_ctrl, 1);
3238 }
3239 if (ret == 0)
3240 {
3241 ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3242 }
3243 if (ret == 0)
3244 {
3245 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3246 }
3247
3248 if (ret == 0)
3249 {
3250 ret = asm330lhb_pin_int2_route_get(ctx, &pin_int2_route);
3251 }
3252 if (ret == 0)
3253 {
3254 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3255 | pin_int2_route.int2_ctrl.int2_drdy_g
3256 | pin_int2_route.int2_ctrl.int2_drdy_temp
3257 | pin_int2_route.int2_ctrl.int2_drdy_xl
3258 | pin_int2_route.int2_ctrl.int2_fifo_full
3259 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3260 | pin_int2_route.int2_ctrl.int2_fifo_th
3261 | pin_int2_route.md2_cfg.int2_6d
3262 | pin_int2_route.md2_cfg.int2_ff
3263 | pin_int2_route.md2_cfg.int2_wu
3264 | pin_int2_route.md2_cfg.int2_sleep_change
3265 | val->int1_ctrl.den_drdy_flag
3266 | val->int1_ctrl.int1_boot
3267 | val->int1_ctrl.int1_cnt_bdr
3268 | val->int1_ctrl.int1_drdy_g
3269 | val->int1_ctrl.int1_drdy_xl
3270 | val->int1_ctrl.int1_fifo_full
3271 | val->int1_ctrl.int1_fifo_ovr
3272 | val->int1_ctrl.int1_fifo_th
3273 | val->md1_cfg.int1_6d
3274 | val->md1_cfg.int1_ff
3275 | val->md1_cfg.int1_wu
3276 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3277 {
3278 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3279 }
3280 else
3281 {
3282 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3283 }
3284 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3285 }
3286 return ret;
3287 }
3288
3289 /**
3290 * @brief Select the signal that need to route on int1 pad.[get]
3291 *
3292 * @param ctx read / write interface definitions
3293 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3294 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3295 *
3296 */
asm330lhb_pin_int1_route_get(stmdev_ctx_t * ctx,asm330lhb_pin_int1_route_t * val)3297 int32_t asm330lhb_pin_int1_route_get(stmdev_ctx_t *ctx,
3298 asm330lhb_pin_int1_route_t *val)
3299 {
3300 int32_t ret;
3301
3302 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3303 if (ret == 0)
3304 {
3305 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1,
3306 (uint8_t *)&val->mlc_int1, 1);
3307 }
3308 if (ret == 0)
3309 {
3310 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1,
3311 (uint8_t *)&val->emb_func_int1, 1);
3312 }
3313 if (ret == 0)
3314 {
3315 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A,
3316 (uint8_t *)&val->fsm_int1_a, 1);
3317 }
3318 if (ret == 0)
3319 {
3320 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B,
3321 (uint8_t *)&val->fsm_int1_b, 1);
3322 }
3323 if (ret == 0)
3324 {
3325 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3326 }
3327 if (ret == 0)
3328 {
3329
3330 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL,
3331 (uint8_t *)&val->int1_ctrl, 1);
3332 }
3333 if (ret == 0)
3334 {
3335 ret = asm330lhb_read_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3336 }
3337
3338 return ret;
3339 }
3340
3341 /**
3342 * @brief Select the signal that need to route on int2 pad.[set]
3343 *
3344 * @param ctx read / write interface definitions
3345 * @param val union of registers INT2_CTRL, MD2_CFG,
3346 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3347 *
3348 */
asm330lhb_pin_int2_route_set(stmdev_ctx_t * ctx,asm330lhb_pin_int2_route_t * val)3349 int32_t asm330lhb_pin_int2_route_set(stmdev_ctx_t *ctx,
3350 asm330lhb_pin_int2_route_t *val)
3351 {
3352 asm330lhb_pin_int1_route_t pin_int1_route;
3353 asm330lhb_int_cfg1_t int_cfg1;
3354 int32_t ret;
3355
3356 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3357 if (ret == 0)
3358 {
3359 ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2,
3360 (uint8_t *)&val->mlc_int2, 1);
3361 }
3362 if (ret == 0)
3363 {
3364 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2,
3365 (uint8_t *)&val->emb_func_int2, 1);
3366 }
3367 if (ret == 0)
3368 {
3369 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A,
3370 (uint8_t *)&val->fsm_int2_a, 1);
3371 }
3372 if (ret == 0)
3373 {
3374 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B,
3375 (uint8_t *)&val->fsm_int2_b, 1);
3376 }
3377 if (ret == 0)
3378 {
3379 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3380 }
3381
3382 if (ret == 0)
3383 {
3384 if ((val->emb_func_int2.int2_fsm_lc
3385 | val->fsm_int2_a.int2_fsm1
3386 | val->fsm_int2_a.int2_fsm2
3387 | val->fsm_int2_a.int2_fsm3
3388 | val->fsm_int2_a.int2_fsm4
3389 | val->fsm_int2_a.int2_fsm5
3390 | val->fsm_int2_a.int2_fsm6
3391 | val->fsm_int2_a.int2_fsm7
3392 | val->fsm_int2_a.int2_fsm8
3393 | val->fsm_int2_b.int2_fsm9
3394 | val->fsm_int2_b.int2_fsm10
3395 | val->fsm_int2_b.int2_fsm11
3396 | val->fsm_int2_b.int2_fsm12
3397 | val->fsm_int2_b.int2_fsm13
3398 | val->fsm_int2_b.int2_fsm14
3399 | val->fsm_int2_b.int2_fsm15
3400 | val->fsm_int2_b.int2_fsm16
3401 | val->mlc_int2.int2_mlc1
3402 | val->mlc_int2.int2_mlc2
3403 | val->mlc_int2.int2_mlc3
3404 | val->mlc_int2.int2_mlc4
3405 | val->mlc_int2.int2_mlc5
3406 | val->mlc_int2.int2_mlc6
3407 | val->mlc_int2.int2_mlc7
3408 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
3409 {
3410 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3411 }
3412 else
3413 {
3414 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3415 }
3416 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL,
3417 (uint8_t *)&val->int2_ctrl, 1);
3418 }
3419 if (ret == 0)
3420 {
3421 ret = asm330lhb_write_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3422 }
3423 if (ret == 0)
3424 {
3425 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3426 }
3427
3428 if (ret == 0)
3429 {
3430 ret = asm330lhb_pin_int1_route_get(ctx, &pin_int1_route);
3431 }
3432
3433 if (ret == 0)
3434 {
3435 if ((val->int2_ctrl.int2_cnt_bdr
3436 | val->int2_ctrl.int2_drdy_g
3437 | val->int2_ctrl.int2_drdy_temp
3438 | val->int2_ctrl.int2_drdy_xl
3439 | val->int2_ctrl.int2_fifo_full
3440 | val->int2_ctrl.int2_fifo_ovr
3441 | val->int2_ctrl.int2_fifo_th
3442 | val->md2_cfg.int2_6d
3443 | val->md2_cfg.int2_ff
3444 | val->md2_cfg.int2_wu
3445 | val->md2_cfg.int2_sleep_change
3446 | pin_int1_route.int1_ctrl.den_drdy_flag
3447 | pin_int1_route.int1_ctrl.int1_boot
3448 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3449 | pin_int1_route.int1_ctrl.int1_drdy_g
3450 | pin_int1_route.int1_ctrl.int1_drdy_xl
3451 | pin_int1_route.int1_ctrl.int1_fifo_full
3452 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3453 | pin_int1_route.int1_ctrl.int1_fifo_th
3454 | pin_int1_route.md1_cfg.int1_6d
3455 | pin_int1_route.md1_cfg.int1_ff
3456 | pin_int1_route.md1_cfg.int1_wu
3457 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3458 {
3459 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3460 }
3461 else
3462 {
3463 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3464 }
3465 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3466 }
3467 return ret;
3468 }
3469
3470 /**
3471 * @brief Select the signal that need to route on int2 pad.[get]
3472 *
3473 * @param ctx read / write interface definitions
3474 * @param val union of registers INT2_CTRL, MD2_CFG,
3475 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3476 *
3477 */
asm330lhb_pin_int2_route_get(stmdev_ctx_t * ctx,asm330lhb_pin_int2_route_t * val)3478 int32_t asm330lhb_pin_int2_route_get(stmdev_ctx_t *ctx,
3479 asm330lhb_pin_int2_route_t *val)
3480 {
3481 int32_t ret;
3482
3483 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3484 if (ret == 0)
3485 {
3486 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2,
3487 (uint8_t *)&val->mlc_int2, 1);
3488 }
3489 if (ret == 0)
3490 {
3491 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2,
3492 (uint8_t *)&val->emb_func_int2, 1);
3493 }
3494 if (ret == 0)
3495 {
3496 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A,
3497 (uint8_t *)&val->fsm_int2_a, 1);
3498 }
3499 if (ret == 0)
3500 {
3501 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B,
3502 (uint8_t *)&val->fsm_int2_b, 1);
3503 }
3504 if (ret == 0)
3505 {
3506 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3507 }
3508 if (ret == 0)
3509 {
3510
3511 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL,
3512 (uint8_t *)&val->int2_ctrl, 1);
3513 }
3514 if (ret == 0)
3515 {
3516 ret = asm330lhb_read_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3517 }
3518 return ret;
3519 }
3520
3521 /**
3522 * @brief Push-pull/open drain selection on interrupt pads.[set]
3523 *
3524 * @param ctx Read / write interface definitions.(ptr)
3525 * @param val Change the values of pp_od in reg CTRL3_C
3526 * @retval Interface status (MANDATORY: return 0 -> no Error).
3527 *
3528 */
asm330lhb_pin_mode_set(stmdev_ctx_t * ctx,asm330lhb_pp_od_t val)3529 int32_t asm330lhb_pin_mode_set(stmdev_ctx_t *ctx, asm330lhb_pp_od_t val)
3530 {
3531 asm330lhb_ctrl3_c_t ctrl3_c;
3532 int32_t ret;
3533
3534 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3535 if (ret == 0)
3536 {
3537 ctrl3_c.pp_od = (uint8_t)val;
3538 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3539 }
3540 return ret;
3541 }
3542
3543 /**
3544 * @brief Push-pull/open drain selection on interrupt pads.[get]
3545 *
3546 * @param ctx Read / write interface definitions.(ptr)
3547 * @param val Get the values of pp_od in reg CTRL3_C
3548 * @retval Interface status (MANDATORY: return 0 -> no Error).
3549 *
3550 */
asm330lhb_pin_mode_get(stmdev_ctx_t * ctx,asm330lhb_pp_od_t * val)3551 int32_t asm330lhb_pin_mode_get(stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val)
3552 {
3553 asm330lhb_ctrl3_c_t ctrl3_c;
3554 int32_t ret;
3555
3556 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3557
3558 switch (ctrl3_c.pp_od)
3559 {
3560 case ASM330LHB_PUSH_PULL:
3561 *val = ASM330LHB_PUSH_PULL;
3562 break;
3563 case ASM330LHB_OPEN_DRAIN:
3564 *val = ASM330LHB_OPEN_DRAIN;
3565 break;
3566 default:
3567 *val = ASM330LHB_PUSH_PULL;
3568 break;
3569 }
3570 return ret;
3571 }
3572
3573 /**
3574 * @brief Interrupt active-high/low.[set]
3575 *
3576 * @param ctx Read / write interface definitions.(ptr)
3577 * @param val Change the values of h_lactive in reg CTRL3_C
3578 * @retval Interface status (MANDATORY: return 0 -> no Error).
3579 *
3580 */
asm330lhb_pin_polarity_set(stmdev_ctx_t * ctx,asm330lhb_h_lactive_t val)3581 int32_t asm330lhb_pin_polarity_set(stmdev_ctx_t *ctx,
3582 asm330lhb_h_lactive_t val)
3583 {
3584 asm330lhb_ctrl3_c_t ctrl3_c;
3585 int32_t ret;
3586
3587 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3588 if (ret == 0)
3589 {
3590 ctrl3_c.h_lactive = (uint8_t)val;
3591 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3592 }
3593 return ret;
3594 }
3595
3596 /**
3597 * @brief Interrupt active-high/low.[get]
3598 *
3599 * @param ctx Read / write interface definitions.(ptr)
3600 * @param val Get the values of h_lactive in reg CTRL3_C
3601 * @retval Interface status (MANDATORY: return 0 -> no Error).
3602 *
3603 */
asm330lhb_pin_polarity_get(stmdev_ctx_t * ctx,asm330lhb_h_lactive_t * val)3604 int32_t asm330lhb_pin_polarity_get(stmdev_ctx_t *ctx,
3605 asm330lhb_h_lactive_t *val)
3606 {
3607 asm330lhb_ctrl3_c_t ctrl3_c;
3608 int32_t ret;
3609
3610 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3611
3612 switch (ctrl3_c.h_lactive)
3613 {
3614 case ASM330LHB_ACTIVE_HIGH:
3615 *val = ASM330LHB_ACTIVE_HIGH;
3616 break;
3617 case ASM330LHB_ACTIVE_LOW:
3618 *val = ASM330LHB_ACTIVE_LOW;
3619 break;
3620 default:
3621 *val = ASM330LHB_ACTIVE_HIGH;
3622 break;
3623 }
3624 return ret;
3625 }
3626
3627 /**
3628 * @brief All interrupt signals become available on INT1 pin.[set]
3629 *
3630 * @param ctx Read / write interface definitions.(ptr)
3631 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3632 * @retval Interface status (MANDATORY: return 0 -> no Error).
3633 *
3634 */
asm330lhb_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)3635 int32_t asm330lhb_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
3636 {
3637 asm330lhb_ctrl4_c_t ctrl4_c;
3638 int32_t ret;
3639
3640 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3641 if (ret == 0)
3642 {
3643 ctrl4_c.int2_on_int1 = (uint8_t)val;
3644 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3645 }
3646 return ret;
3647 }
3648
3649 /**
3650 * @brief All interrupt signals become available on INT1 pin.[get]
3651 *
3652 * @param ctx Read / write interface definitions.(ptr)
3653 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3654 * @retval Interface status (MANDATORY: return 0 -> no Error).
3655 *
3656 */
asm330lhb_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)3657 int32_t asm330lhb_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
3658 {
3659 asm330lhb_ctrl4_c_t ctrl4_c;
3660 int32_t ret;
3661
3662 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3663 *val = ctrl4_c.int2_on_int1;
3664
3665 return ret;
3666 }
3667
3668 /**
3669 * @brief All interrupt signals notification mode.[set]
3670 *
3671 * @param ctx Read / write interface definitions.(ptr)
3672 * @param val Change the values of lir in reg INT_CFG0
3673 * @retval Interface status (MANDATORY: return 0 -> no Error).
3674 *
3675 */
asm330lhb_int_notification_set(stmdev_ctx_t * ctx,asm330lhb_lir_t val)3676 int32_t asm330lhb_int_notification_set(stmdev_ctx_t *ctx,
3677 asm330lhb_lir_t val)
3678 {
3679 asm330lhb_int_cfg0_t int_cfg0;
3680 asm330lhb_page_rw_t page_rw;
3681 int32_t ret;
3682
3683 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3684 if (ret == 0)
3685 {
3686 int_cfg0.lir = (uint8_t)val & 0x01U;
3687 int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3688 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
3689 (uint8_t *)&int_cfg0, 1);
3690 }
3691 if (ret == 0)
3692 {
3693 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3694 }
3695 if (ret == 0)
3696 {
3697 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3698 }
3699 if (ret == 0)
3700 {
3701 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3702 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3703 }
3704 if (ret == 0)
3705 {
3706 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3707 }
3708 return ret;
3709 }
3710
3711 /**
3712 * @brief All interrupt signals notification mode.[get]
3713 *
3714 * @param ctx Read / write interface definitions.(ptr)
3715 * @param val Get the values of lir in reg INT_CFG0
3716 * @retval Interface status (MANDATORY: return 0 -> no Error).
3717 *
3718 */
asm330lhb_int_notification_get(stmdev_ctx_t * ctx,asm330lhb_lir_t * val)3719 int32_t asm330lhb_int_notification_get(stmdev_ctx_t *ctx,
3720 asm330lhb_lir_t *val)
3721 {
3722 asm330lhb_int_cfg0_t int_cfg0;
3723 asm330lhb_page_rw_t page_rw;
3724 int32_t ret;
3725
3726 *val = ASM330LHB_ALL_INT_PULSED;
3727 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3728
3729 if (ret == 0)
3730 {
3731 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3732 }
3733 if (ret == 0)
3734 {
3735 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3736 }
3737 if (ret == 0)
3738 {
3739 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3740 }
3741 switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir)
3742 {
3743 case ASM330LHB_ALL_INT_PULSED:
3744 *val = ASM330LHB_ALL_INT_PULSED;
3745 break;
3746 case ASM330LHB_BASE_LATCHED_EMB_PULSED:
3747 *val = ASM330LHB_BASE_LATCHED_EMB_PULSED;
3748 break;
3749 case ASM330LHB_BASE_PULSED_EMB_LATCHED:
3750 *val = ASM330LHB_BASE_PULSED_EMB_LATCHED;
3751 break;
3752 case ASM330LHB_ALL_INT_LATCHED:
3753 *val = ASM330LHB_ALL_INT_LATCHED;
3754 break;
3755 default:
3756 *val = ASM330LHB_ALL_INT_PULSED;
3757 break;
3758 }
3759 return ret;
3760 }
3761
3762 /**
3763 * @}
3764 *
3765 */
3766
3767 /**
3768 * @defgroup ASM330LHB_Wake_Up_event
3769 * @brief This section groups all the functions that manage the
3770 * Wake Up event generation.
3771 * @{
3772 *
3773 */
3774
3775 /**
3776 * @brief Weight of 1 LSB of wakeup threshold.[set]
3777 * 0: 1 LSB =FS_XL / 64
3778 * 1: 1 LSB = FS_XL / 256
3779 *
3780 * @param ctx Read / write interface definitions.(ptr)
3781 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
3782 * @retval Interface status (MANDATORY: return 0 -> no Error).
3783 *
3784 */
asm330lhb_wkup_ths_weight_set(stmdev_ctx_t * ctx,asm330lhb_wake_ths_w_t val)3785 int32_t asm330lhb_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3786 asm330lhb_wake_ths_w_t val)
3787 {
3788 asm330lhb_wake_up_dur_t wake_up_dur;
3789 int32_t ret;
3790
3791 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3792 (uint8_t *)&wake_up_dur, 1);
3793 if (ret == 0)
3794 {
3795 wake_up_dur.wake_ths_w = (uint8_t)val;
3796 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3797 (uint8_t *)&wake_up_dur, 1);
3798 }
3799 return ret;
3800 }
3801
3802 /**
3803 * @brief Weight of 1 LSB of wakeup threshold.[get]
3804 * 0: 1 LSB =FS_XL / 64
3805 * 1: 1 LSB = FS_XL / 256
3806 *
3807 * @param ctx Read / write interface definitions.(ptr)
3808 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
3809 * @retval Interface status (MANDATORY: return 0 -> no Error).
3810 *
3811 */
asm330lhb_wkup_ths_weight_get(stmdev_ctx_t * ctx,asm330lhb_wake_ths_w_t * val)3812 int32_t asm330lhb_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3813 asm330lhb_wake_ths_w_t *val)
3814 {
3815 asm330lhb_wake_up_dur_t wake_up_dur;
3816 int32_t ret;
3817
3818 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3819 (uint8_t *)&wake_up_dur, 1);
3820
3821 switch (wake_up_dur.wake_ths_w)
3822 {
3823 case ASM330LHB_LSb_FS_DIV_64:
3824 *val = ASM330LHB_LSb_FS_DIV_64;
3825 break;
3826 case ASM330LHB_LSb_FS_DIV_256:
3827 *val = ASM330LHB_LSb_FS_DIV_256;
3828 break;
3829 default:
3830 *val = ASM330LHB_LSb_FS_DIV_64;
3831 break;
3832 }
3833 return ret;
3834 }
3835
3836 /**
3837 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3838 * WAKE_UP_DUR.[set]
3839 *
3840 * @param ctx Read / write interface definitions.(ptr)
3841 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3842 * @retval Interface status (MANDATORY: return 0 -> no Error).
3843 *
3844 */
asm330lhb_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3845 int32_t asm330lhb_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3846 {
3847 asm330lhb_wake_up_ths_t wake_up_ths;
3848 int32_t ret;
3849
3850 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3851 (uint8_t *)&wake_up_ths, 1);
3852 if (ret == 0)
3853 {
3854 wake_up_ths.wk_ths = (uint8_t)val;
3855 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS,
3856 (uint8_t *)&wake_up_ths, 1);
3857 }
3858 return ret;
3859 }
3860
3861 /**
3862 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3863 * WAKE_UP_DUR.[get]
3864 *
3865 * @param ctx Read / write interface definitions.(ptr)
3866 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3867 * @retval Interface status (MANDATORY: return 0 -> no Error).
3868 *
3869 */
asm330lhb_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3870 int32_t asm330lhb_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3871 {
3872 asm330lhb_wake_up_ths_t wake_up_ths;
3873 int32_t ret;
3874
3875 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3876 (uint8_t *)&wake_up_ths, 1);
3877 *val = wake_up_ths.wk_ths;
3878
3879 return ret;
3880 }
3881
3882 /**
3883 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
3884 *
3885 * @param ctx Read / write interface definitions.(ptr)
3886 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3887 * @retval Interface status (MANDATORY: return 0 -> no Error).
3888 *
3889 */
asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)3890 int32_t asm330lhb_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, uint8_t val)
3891 {
3892 asm330lhb_wake_up_ths_t wake_up_ths;
3893 int32_t ret;
3894
3895 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3896 (uint8_t *)&wake_up_ths, 1);
3897 if (ret == 0)
3898 {
3899 wake_up_ths.usr_off_on_wu = (uint8_t)val;
3900 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS,
3901 (uint8_t *)&wake_up_ths, 1);
3902 }
3903 return ret;
3904 }
3905
3906 /**
3907 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
3908 *
3909 * @param ctx Read / write interface definitions.(ptr)
3910 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3911 * @retval Interface status (MANDATORY: return 0 -> no Error).
3912 *
3913 */
asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)3914 int32_t asm330lhb_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3915 uint8_t *val)
3916 {
3917 asm330lhb_wake_up_ths_t wake_up_ths;
3918 int32_t ret;
3919
3920 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3921 (uint8_t *)&wake_up_ths, 1);
3922 *val = wake_up_ths.usr_off_on_wu;
3923
3924 return ret;
3925 }
3926
3927 /**
3928 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
3929 *
3930 * @param ctx Read / write interface definitions.(ptr)
3931 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3932 * @retval Interface status (MANDATORY: return 0 -> no Error).
3933 *
3934 */
asm330lhb_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)3935 int32_t asm330lhb_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3936 {
3937 asm330lhb_wake_up_dur_t wake_up_dur;
3938 int32_t ret;
3939
3940 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3941 (uint8_t *)&wake_up_dur, 1);
3942 if (ret == 0)
3943 {
3944 wake_up_dur.wake_dur = (uint8_t)val;
3945 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3946 (uint8_t *)&wake_up_dur, 1);
3947 }
3948 return ret;
3949 }
3950
3951 /**
3952 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3953 *
3954 * @param ctx Read / write interface definitions.(ptr)
3955 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3956 * @retval Interface status (MANDATORY: return 0 -> no Error).
3957 *
3958 */
asm330lhb_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3959 int32_t asm330lhb_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3960 {
3961 asm330lhb_wake_up_dur_t wake_up_dur;
3962 int32_t ret;
3963
3964 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3965 (uint8_t *)&wake_up_dur, 1);
3966 *val = wake_up_dur.wake_dur;
3967
3968 return ret;
3969 }
3970
3971 /**
3972 * @}
3973 *
3974 */
3975
3976 /**
3977 * @defgroup ASM330LHB_ Activity/Inactivity_detection
3978 * @brief This section groups all the functions concerning
3979 * activity/inactivity detection.
3980 * @{
3981 *
3982 */
3983
3984 /**
3985 * @brief Enables gyroscope Sleep mode.[set]
3986 *
3987 * @param ctx Read / write interface definitions.(ptr)
3988 * @param val Change the values of sleep_g in reg CTRL4_C
3989 * @retval Interface status (MANDATORY: return 0 -> no Error).
3990 *
3991 */
asm330lhb_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)3992 int32_t asm330lhb_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
3993 {
3994 asm330lhb_ctrl4_c_t ctrl4_c;
3995 int32_t ret;
3996
3997 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3998 if (ret == 0)
3999 {
4000 ctrl4_c.sleep_g = (uint8_t)val;
4001 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4002 }
4003 return ret;
4004 }
4005
4006 /**
4007 * @brief Enables gyroscope Sleep mode.[get]
4008 *
4009 * @param ctx Read / write interface definitions.(ptr)
4010 * @param val Change the values of sleep_g in reg CTRL4_C
4011 * @retval Interface status (MANDATORY: return 0 -> no Error).
4012 *
4013 */
asm330lhb_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4014 int32_t asm330lhb_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4015 {
4016 asm330lhb_ctrl4_c_t ctrl4_c;
4017 int32_t ret;
4018
4019 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4020 *val = ctrl4_c.sleep_g;
4021
4022 return ret;
4023 }
4024
4025 /**
4026 * @brief Drives the sleep status instead of sleep change on INT pins
4027 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4028 * are enabled).[set]
4029 *
4030 * @param ctx Read / write interface definitions.(ptr)
4031 * @param val Change the values of sleep_status_on_int in reg INT_CFG0
4032 * @retval Interface status (MANDATORY: return 0 -> no Error).
4033 *
4034 */
asm330lhb_act_pin_notification_set(stmdev_ctx_t * ctx,asm330lhb_sleep_status_on_int_t val)4035 int32_t asm330lhb_act_pin_notification_set(stmdev_ctx_t *ctx,
4036 asm330lhb_sleep_status_on_int_t val)
4037 {
4038 asm330lhb_int_cfg0_t int_cfg0;
4039 int32_t ret;
4040
4041 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4042 if (ret == 0)
4043 {
4044 int_cfg0. sleep_status_on_int = (uint8_t)val;
4045 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
4046 (uint8_t *)&int_cfg0, 1);
4047 }
4048 return ret;
4049 }
4050
4051 /**
4052 * @brief Drives the sleep status instead of sleep change on INT pins
4053 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4054 * are enabled).[get]
4055 *
4056 * @param ctx Read / write interface definitions.(ptr)
4057 * @param val Get the values of sleep_status_on_int in reg INT_CFG0
4058 * @retval Interface status (MANDATORY: return 0 -> no Error).
4059 *
4060 */
asm330lhb_act_pin_notification_get(stmdev_ctx_t * ctx,asm330lhb_sleep_status_on_int_t * val)4061 int32_t asm330lhb_act_pin_notification_get(stmdev_ctx_t *ctx,
4062 asm330lhb_sleep_status_on_int_t *val)
4063 {
4064 asm330lhb_int_cfg0_t int_cfg0;
4065 int32_t ret;
4066
4067 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4068 switch (int_cfg0. sleep_status_on_int)
4069 {
4070 case ASM330LHB_DRIVE_SLEEP_CHG_EVENT:
4071 *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT;
4072 break;
4073 case ASM330LHB_DRIVE_SLEEP_STATUS:
4074 *val = ASM330LHB_DRIVE_SLEEP_STATUS;
4075 break;
4076 default:
4077 *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT;
4078 break;
4079 }
4080 return ret;
4081 }
4082
4083 /**
4084 * @brief Enable inactivity function.[set]
4085 *
4086 * @param ctx Read / write interface definitions.(ptr)
4087 * @param val Change the values of inact_en in reg INT_CFG1
4088 * @retval Interface status (MANDATORY: return 0 -> no Error).
4089 *
4090 */
asm330lhb_act_mode_set(stmdev_ctx_t * ctx,asm330lhb_inact_en_t val)4091 int32_t asm330lhb_act_mode_set(stmdev_ctx_t *ctx, asm330lhb_inact_en_t val)
4092 {
4093 asm330lhb_int_cfg1_t int_cfg1;
4094 int32_t ret;
4095
4096 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4097 if (ret == 0)
4098 {
4099 int_cfg1.inact_en = (uint8_t)val;
4100 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4101 }
4102 return ret;
4103 }
4104
4105 /**
4106 * @brief Enable inactivity function.[get]
4107 *
4108 * @param ctx Read / write interface definitions.(ptr)
4109 * @param val Get the values of inact_en in reg INT_CFG1
4110 * @retval Interface status (MANDATORY: return 0 -> no Error).
4111 *
4112 */
asm330lhb_act_mode_get(stmdev_ctx_t * ctx,asm330lhb_inact_en_t * val)4113 int32_t asm330lhb_act_mode_get(stmdev_ctx_t *ctx,
4114 asm330lhb_inact_en_t *val)
4115 {
4116 asm330lhb_int_cfg1_t int_cfg1;
4117 int32_t ret;
4118
4119 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4120
4121 switch (int_cfg1.inact_en)
4122 {
4123 case ASM330LHB_XL_AND_GY_NOT_AFFECTED:
4124 *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED;
4125 break;
4126 case ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED:
4127 *val = ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED;
4128 break;
4129 case ASM330LHB_XL_12Hz5_GY_SLEEP:
4130 *val = ASM330LHB_XL_12Hz5_GY_SLEEP;
4131 break;
4132 case ASM330LHB_XL_12Hz5_GY_PD:
4133 *val = ASM330LHB_XL_12Hz5_GY_PD;
4134 break;
4135 default:
4136 *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED;
4137 break;
4138 }
4139 return ret;
4140 }
4141
4142 /**
4143 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
4144 *
4145 * @param ctx Read / write interface definitions.(ptr)
4146 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4147 * @retval Interface status (MANDATORY: return 0 -> no Error).
4148 *
4149 */
asm330lhb_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)4150 int32_t asm330lhb_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4151 {
4152 asm330lhb_wake_up_dur_t wake_up_dur;
4153 int32_t ret;
4154
4155 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4156 (uint8_t *)&wake_up_dur, 1);
4157 if (ret == 0)
4158 {
4159 wake_up_dur.sleep_dur = (uint8_t)val;
4160 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4161 (uint8_t *)&wake_up_dur, 1);
4162 }
4163 return ret;
4164 }
4165
4166 /**
4167 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
4168 *
4169 * @param ctx Read / write interface definitions.(ptr)
4170 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4171 * @retval Interface status (MANDATORY: return 0 -> no Error).
4172 *
4173 */
asm330lhb_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4174 int32_t asm330lhb_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4175 {
4176 asm330lhb_wake_up_dur_t wake_up_dur;
4177 int32_t ret;
4178
4179 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4180 (uint8_t *)&wake_up_dur, 1);
4181 *val = wake_up_dur.sleep_dur;
4182
4183 return ret;
4184 }
4185
4186 /**
4187 * @}
4188 *
4189 */
4190
4191 /**
4192 * @defgroup ASM330LHB_ Six_position_detection(6D/4D)
4193 * @brief This section groups all the functions concerning six
4194 * position detection (6D).
4195 * @{
4196 *
4197 */
4198
4199 /**
4200 * @brief Threshold for 4D/6D function.[set]
4201 *
4202 * @param ctx Read / write interface definitions.(ptr)
4203 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4204 * @retval Interface status (MANDATORY: return 0 -> no Error).
4205 *
4206 */
asm330lhb_6d_threshold_set(stmdev_ctx_t * ctx,asm330lhb_sixd_ths_t val)4207 int32_t asm330lhb_6d_threshold_set(stmdev_ctx_t *ctx,
4208 asm330lhb_sixd_ths_t val)
4209 {
4210 asm330lhb_ths_6d_t ths_6d;
4211 int32_t ret;
4212
4213 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4214 (uint8_t *)&ths_6d, 1);
4215 if (ret == 0)
4216 {
4217 ths_6d.sixd_ths = (uint8_t)val;
4218 ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D,
4219 (uint8_t *)&ths_6d, 1);
4220 }
4221 return ret;
4222 }
4223
4224 /**
4225 * @brief Threshold for 4D/6D function.[get]
4226 *
4227 * @param ctx Read / write interface definitions.(ptr)
4228 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4229 * @retval Interface status (MANDATORY: return 0 -> no Error).
4230 *
4231 */
asm330lhb_6d_threshold_get(stmdev_ctx_t * ctx,asm330lhb_sixd_ths_t * val)4232 int32_t asm330lhb_6d_threshold_get(stmdev_ctx_t *ctx,
4233 asm330lhb_sixd_ths_t *val)
4234 {
4235 asm330lhb_ths_6d_t ths_6d;
4236 int32_t ret;
4237
4238 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4239 (uint8_t *)&ths_6d, 1);
4240
4241 switch (ths_6d.sixd_ths)
4242 {
4243 case ASM330LHB_DEG_80:
4244 *val = ASM330LHB_DEG_80;
4245 break;
4246 case ASM330LHB_DEG_70:
4247 *val = ASM330LHB_DEG_70;
4248 break;
4249 case ASM330LHB_DEG_60:
4250 *val = ASM330LHB_DEG_60;
4251 break;
4252 case ASM330LHB_DEG_50:
4253 *val = ASM330LHB_DEG_50;
4254 break;
4255 default:
4256 *val = ASM330LHB_DEG_80;
4257 break;
4258 }
4259 return ret;
4260 }
4261
4262 /**
4263 * @brief 4D orientation detection enable.[set]
4264 *
4265 * @param ctx Read / write interface definitions.(ptr)
4266 * @param val Change the values of d4d_en in reg TAP_THS_6D
4267 * @retval Interface status (MANDATORY: return 0 -> no Error).
4268 *
4269 */
asm330lhb_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)4270 int32_t asm330lhb_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4271 {
4272 asm330lhb_ths_6d_t ths_6d;
4273 int32_t ret;
4274
4275 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4276 (uint8_t *)&ths_6d, 1);
4277 if (ret == 0)
4278 {
4279 ths_6d.d4d_en = (uint8_t)val;
4280 ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D,
4281 (uint8_t *)&ths_6d, 1);
4282 }
4283 return ret;
4284 }
4285
4286 /**
4287 * @brief 4D orientation detection enable.[get]
4288 *
4289 * @param ctx Read / write interface definitions.(ptr)
4290 * @param val Change the values of d4d_en in reg TAP_THS_6D
4291 * @retval Interface status (MANDATORY: return 0 -> no Error).
4292 *
4293 */
asm330lhb_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4294 int32_t asm330lhb_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4295 {
4296 asm330lhb_ths_6d_t ths_6d;
4297 int32_t ret;
4298
4299 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4300 (uint8_t *)&ths_6d, 1);
4301 *val = ths_6d.d4d_en;
4302
4303 return ret;
4304 }
4305
4306 /**
4307 * @}
4308 *
4309 */
4310
4311 /**
4312 * @defgroup ASM330LHB_free_fall
4313 * @brief This section group all the functions concerning the free
4314 * fall detection.
4315 * @{
4316 *
4317 */
4318
4319 /**
4320 * @brief Free fall threshold setting.[set]
4321 *
4322 * @param ctx Read / write interface definitions.(ptr)
4323 * @param val Change the values of ff_ths in reg FREE_FALL
4324 * @retval Interface status (MANDATORY: return 0 -> no Error).
4325 *
4326 */
asm330lhb_ff_threshold_set(stmdev_ctx_t * ctx,asm330lhb_ff_ths_t val)4327 int32_t asm330lhb_ff_threshold_set(stmdev_ctx_t *ctx,
4328 asm330lhb_ff_ths_t val)
4329 {
4330 asm330lhb_free_fall_t free_fall;
4331 int32_t ret;
4332
4333 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1);
4334 if (ret == 0)
4335 {
4336 free_fall.ff_ths = (uint8_t)val;
4337 ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL,
4338 (uint8_t *)&free_fall, 1);
4339 }
4340 return ret;
4341 }
4342
4343 /**
4344 * @brief Free fall threshold setting.[get]
4345 *
4346 * @param ctx Read / write interface definitions.(ptr)
4347 * @param val Get the values of ff_ths in reg FREE_FALL
4348 * @retval Interface status (MANDATORY: return 0 -> no Error).
4349 *
4350 */
asm330lhb_ff_threshold_get(stmdev_ctx_t * ctx,asm330lhb_ff_ths_t * val)4351 int32_t asm330lhb_ff_threshold_get(stmdev_ctx_t *ctx,
4352 asm330lhb_ff_ths_t *val)
4353 {
4354 asm330lhb_free_fall_t free_fall;
4355 int32_t ret;
4356
4357 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1);
4358
4359 switch (free_fall.ff_ths)
4360 {
4361 case ASM330LHB_FF_TSH_156mg:
4362 *val = ASM330LHB_FF_TSH_156mg;
4363 break;
4364 case ASM330LHB_FF_TSH_219mg:
4365 *val = ASM330LHB_FF_TSH_219mg;
4366 break;
4367 case ASM330LHB_FF_TSH_250mg:
4368 *val = ASM330LHB_FF_TSH_250mg;
4369 break;
4370 case ASM330LHB_FF_TSH_312mg:
4371 *val = ASM330LHB_FF_TSH_312mg;
4372 break;
4373 case ASM330LHB_FF_TSH_344mg:
4374 *val = ASM330LHB_FF_TSH_344mg;
4375 break;
4376 case ASM330LHB_FF_TSH_406mg:
4377 *val = ASM330LHB_FF_TSH_406mg;
4378 break;
4379 case ASM330LHB_FF_TSH_469mg:
4380 *val = ASM330LHB_FF_TSH_469mg;
4381 break;
4382 case ASM330LHB_FF_TSH_500mg:
4383 *val = ASM330LHB_FF_TSH_500mg;
4384 break;
4385 default:
4386 *val = ASM330LHB_FF_TSH_156mg;
4387 break;
4388 }
4389 return ret;
4390 }
4391
4392 /**
4393 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
4394 *
4395 * @param ctx Read / write interface definitions.(ptr)
4396 * @param val Change the values of ff_dur in reg FREE_FALL
4397 * @retval Interface status (MANDATORY: return 0 -> no Error).
4398 *
4399 */
asm330lhb_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)4400 int32_t asm330lhb_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4401 {
4402 asm330lhb_wake_up_dur_t wake_up_dur;
4403 asm330lhb_free_fall_t free_fall;
4404 int32_t ret;
4405
4406 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4407 (uint8_t *)&wake_up_dur, 1);
4408 if (ret == 0)
4409 {
4410 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4411 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4412 (uint8_t *)&wake_up_dur, 1);
4413 }
4414 if (ret == 0)
4415 {
4416 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL,
4417 (uint8_t *)&free_fall, 1);
4418 }
4419 if (ret == 0)
4420 {
4421 free_fall.ff_dur = val & 0x1FU;
4422 ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL,
4423 (uint8_t *)&free_fall, 1);
4424 }
4425 return ret;
4426 }
4427
4428 /**
4429 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
4430 *
4431 * @param ctx Read / write interface definitions.(ptr)
4432 * @param val Change the values of ff_dur in reg FREE_FALL
4433 * @retval Interface status (MANDATORY: return 0 -> no Error).
4434 *
4435 */
asm330lhb_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4436 int32_t asm330lhb_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4437 {
4438 asm330lhb_wake_up_dur_t wake_up_dur;
4439 asm330lhb_free_fall_t free_fall;
4440 int32_t ret;
4441
4442 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4443 (uint8_t *)&wake_up_dur, 1);
4444
4445 if (ret == 0)
4446 {
4447 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL,
4448 (uint8_t *)&free_fall, 1);
4449 }
4450 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4451
4452 return ret;
4453 }
4454
4455 /**
4456 * @}
4457 *
4458 */
4459
4460 /**
4461 * @defgroup ASM330LHB_fifo
4462 * @brief This section group all the functions concerning
4463 * the fifo usage
4464 * @{
4465 *
4466 */
4467
4468 /**
4469 * @brief FIFO watermark level selection.[set]
4470 *
4471 * @param ctx Read / write interface definitions.(ptr)
4472 * @param val Change the values of wtm in reg FIFO_CTRL1
4473 * @retval Interface status (MANDATORY: return 0 -> no Error).
4474 *
4475 */
asm330lhb_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)4476 int32_t asm330lhb_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
4477 {
4478 asm330lhb_fifo_ctrl1_t fifo_ctrl1;
4479 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4480 int32_t ret;
4481
4482 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4483 (uint8_t *)&fifo_ctrl2, 1);
4484 if (ret == 0)
4485 {
4486 fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
4487 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
4488 (uint8_t *)&fifo_ctrl2, 1);
4489 }
4490 if (ret == 0)
4491 {
4492 fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
4493 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1,
4494 (uint8_t *)&fifo_ctrl1, 1);
4495 }
4496
4497 return ret;
4498 }
4499
4500 /**
4501 * @brief FIFO watermark level selection.[get]
4502 *
4503 * @param ctx Read / write interface definitions.(ptr)
4504 * @param val Change the values of wtm in reg FIFO_CTRL1
4505 * @retval Interface status (MANDATORY: return 0 -> no Error).
4506 *
4507 */
asm330lhb_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)4508 int32_t asm330lhb_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
4509 {
4510 asm330lhb_fifo_ctrl1_t fifo_ctrl1;
4511 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4512 int32_t ret;
4513
4514 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4515 (uint8_t *)&fifo_ctrl2, 1);
4516 if (ret == 0)
4517 {
4518 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1,
4519 (uint8_t *)&fifo_ctrl1, 1);
4520 }
4521 *val = fifo_ctrl2.wtm;
4522 *val = (*val * 256U) + fifo_ctrl1.wtm;
4523 return ret;
4524 }
4525
4526 /**
4527 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4528 *
4529 * @param ctx Read / write interface definitions.(ptr)
4530 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4531 * @retval Interface status (MANDATORY: return 0 -> no Error).
4532 *
4533 */
asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)4534 int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
4535 uint8_t val)
4536 {
4537 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4538 int32_t ret;
4539
4540 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4541 (uint8_t *)&fifo_ctrl2, 1);
4542 if (ret == 0)
4543 {
4544 fifo_ctrl2.odrchg_en = (uint8_t)val;
4545 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
4546 (uint8_t *)&fifo_ctrl2, 1);
4547 }
4548
4549 return ret;
4550 }
4551
4552 /**
4553 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4554 *
4555 * @param ctx Read / write interface definitions.(ptr)
4556 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4557 * @retval Interface status (MANDATORY: return 0 -> no Error).
4558 *
4559 */
asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)4560 int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
4561 uint8_t *val)
4562 {
4563 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4564 int32_t ret;
4565
4566 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4567 (uint8_t *)&fifo_ctrl2, 1);
4568 *val = fifo_ctrl2.odrchg_en;
4569
4570 return ret;
4571 }
4572
4573 /**
4574 * @brief Sensing chain FIFO stop values memorization at threshold
4575 * level.[set]
4576 *
4577 * @param ctx Read / write interface definitions.(ptr)
4578 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4579 * @retval Interface status (MANDATORY: return 0 -> no Error).
4580 *
4581 */
asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)4582 int32_t asm330lhb_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
4583 {
4584 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4585 int32_t ret;
4586
4587 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4588 (uint8_t *)&fifo_ctrl2, 1);
4589 if (ret == 0)
4590 {
4591 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
4592 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
4593 (uint8_t *)&fifo_ctrl2, 1);
4594 }
4595 return ret;
4596 }
4597
4598 /**
4599 * @brief Sensing chain FIFO stop values memorization at threshold
4600 * level.[get]
4601 *
4602 * @param ctx Read / write interface definitions.(ptr)
4603 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4604 * @retval Interface status (MANDATORY: return 0 -> no Error).
4605 *
4606 */
asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)4607 int32_t asm330lhb_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
4608 {
4609 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4610 int32_t ret;
4611
4612 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4613 (uint8_t *)&fifo_ctrl2, 1);
4614 *val = fifo_ctrl2.stop_on_wtm;
4615
4616 return ret;
4617 }
4618
4619 /**
4620 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4621 * for accelerometer data.[set]
4622 *
4623 * @param ctx Read / write interface definitions.(ptr)
4624 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
4625 * @retval Interface status (MANDATORY: return 0 -> no Error).
4626 *
4627 */
asm330lhb_fifo_xl_batch_set(stmdev_ctx_t * ctx,asm330lhb_bdr_xl_t val)4628 int32_t asm330lhb_fifo_xl_batch_set(stmdev_ctx_t *ctx,
4629 asm330lhb_bdr_xl_t val)
4630 {
4631 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4632 int32_t ret;
4633
4634 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4635 (uint8_t *)&fifo_ctrl3, 1);
4636 if (ret == 0)
4637 {
4638 fifo_ctrl3.bdr_xl = (uint8_t)val;
4639 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3,
4640 (uint8_t *)&fifo_ctrl3, 1);
4641 }
4642 return ret;
4643 }
4644
4645 /**
4646 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4647 * for accelerometer data.[get]
4648 *
4649 * @param ctx Read / write interface definitions.(ptr)
4650 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
4651 * @retval Interface status (MANDATORY: return 0 -> no Error).
4652 *
4653 */
asm330lhb_fifo_xl_batch_get(stmdev_ctx_t * ctx,asm330lhb_bdr_xl_t * val)4654 int32_t asm330lhb_fifo_xl_batch_get(stmdev_ctx_t *ctx,
4655 asm330lhb_bdr_xl_t *val)
4656 {
4657 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4658 int32_t ret;
4659
4660 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4661 (uint8_t *)&fifo_ctrl3, 1);
4662
4663 switch (fifo_ctrl3.bdr_xl)
4664 {
4665 case ASM330LHB_XL_NOT_BATCHED:
4666 *val = ASM330LHB_XL_NOT_BATCHED;
4667 break;
4668 case ASM330LHB_XL_BATCHED_AT_12Hz5:
4669 *val = ASM330LHB_XL_BATCHED_AT_12Hz5;
4670 break;
4671 case ASM330LHB_XL_BATCHED_AT_26Hz:
4672 *val = ASM330LHB_XL_BATCHED_AT_26Hz;
4673 break;
4674 case ASM330LHB_XL_BATCHED_AT_52Hz:
4675 *val = ASM330LHB_XL_BATCHED_AT_52Hz;
4676 break;
4677 case ASM330LHB_XL_BATCHED_AT_104Hz:
4678 *val = ASM330LHB_XL_BATCHED_AT_104Hz;
4679 break;
4680 case ASM330LHB_XL_BATCHED_AT_208Hz:
4681 *val = ASM330LHB_XL_BATCHED_AT_208Hz;
4682 break;
4683 case ASM330LHB_XL_BATCHED_AT_417Hz:
4684 *val = ASM330LHB_XL_BATCHED_AT_417Hz;
4685 break;
4686 case ASM330LHB_XL_BATCHED_AT_833Hz:
4687 *val = ASM330LHB_XL_BATCHED_AT_833Hz;
4688 break;
4689 case ASM330LHB_XL_BATCHED_AT_1667Hz:
4690 *val = ASM330LHB_XL_BATCHED_AT_1667Hz;
4691 break;
4692 case ASM330LHB_XL_BATCHED_AT_1Hz6:
4693 *val = ASM330LHB_XL_BATCHED_AT_1Hz6;
4694 break;
4695 default:
4696 *val = ASM330LHB_XL_NOT_BATCHED;
4697 break;
4698 }
4699 return ret;
4700 }
4701
4702 /**
4703 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4704 * for gyroscope data.[set]
4705 *
4706 * @param ctx Read / write interface definitions.(ptr)
4707 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
4708 * @retval Interface status (MANDATORY: return 0 -> no Error).
4709 *
4710 */
asm330lhb_fifo_gy_batch_set(stmdev_ctx_t * ctx,asm330lhb_bdr_gy_t val)4711 int32_t asm330lhb_fifo_gy_batch_set(stmdev_ctx_t *ctx,
4712 asm330lhb_bdr_gy_t val)
4713 {
4714 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4715 int32_t ret;
4716
4717 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4718 (uint8_t *)&fifo_ctrl3, 1);
4719 if (ret == 0)
4720 {
4721 fifo_ctrl3.bdr_gy = (uint8_t)val;
4722 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3,
4723 (uint8_t *)&fifo_ctrl3, 1);
4724 }
4725 return ret;
4726 }
4727
4728 /**
4729 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4730 * for gyroscope data.[get]
4731 *
4732 * @param ctx Read / write interface definitions.(ptr)
4733 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
4734 * @retval Interface status (MANDATORY: return 0 -> no Error).
4735 *
4736 */
asm330lhb_fifo_gy_batch_get(stmdev_ctx_t * ctx,asm330lhb_bdr_gy_t * val)4737 int32_t asm330lhb_fifo_gy_batch_get(stmdev_ctx_t *ctx,
4738 asm330lhb_bdr_gy_t *val)
4739 {
4740 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4741 int32_t ret;
4742
4743 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4744 (uint8_t *)&fifo_ctrl3, 1);
4745
4746 switch (fifo_ctrl3.bdr_gy)
4747 {
4748 case ASM330LHB_GY_NOT_BATCHED:
4749 *val = ASM330LHB_GY_NOT_BATCHED;
4750 break;
4751 case ASM330LHB_GY_BATCHED_AT_12Hz5:
4752 *val = ASM330LHB_GY_BATCHED_AT_12Hz5;
4753 break;
4754 case ASM330LHB_GY_BATCHED_AT_26Hz:
4755 *val = ASM330LHB_GY_BATCHED_AT_26Hz;
4756 break;
4757 case ASM330LHB_GY_BATCHED_AT_52Hz:
4758 *val = ASM330LHB_GY_BATCHED_AT_52Hz;
4759 break;
4760 case ASM330LHB_GY_BATCHED_AT_104Hz:
4761 *val = ASM330LHB_GY_BATCHED_AT_104Hz;
4762 break;
4763 case ASM330LHB_GY_BATCHED_AT_208Hz:
4764 *val = ASM330LHB_GY_BATCHED_AT_208Hz;
4765 break;
4766 case ASM330LHB_GY_BATCHED_AT_417Hz:
4767 *val = ASM330LHB_GY_BATCHED_AT_417Hz;
4768 break;
4769 case ASM330LHB_GY_BATCHED_AT_833Hz:
4770 *val = ASM330LHB_GY_BATCHED_AT_833Hz;
4771 break;
4772 case ASM330LHB_GY_BATCHED_AT_1667Hz:
4773 *val = ASM330LHB_GY_BATCHED_AT_1667Hz;
4774 break;
4775 case ASM330LHB_GY_BATCHED_AT_6Hz5:
4776 *val = ASM330LHB_GY_BATCHED_AT_6Hz5;
4777 break;
4778 default:
4779 *val = ASM330LHB_GY_NOT_BATCHED;
4780 break;
4781 }
4782 return ret;
4783 }
4784
4785 /**
4786 * @brief FIFO mode selection.[set]
4787 *
4788 * @param ctx Read / write interface definitions.(ptr)
4789 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
4790 * @retval Interface status (MANDATORY: return 0 -> no Error).
4791 *
4792 */
asm330lhb_fifo_mode_set(stmdev_ctx_t * ctx,asm330lhb_fifo_mode_t val)4793 int32_t asm330lhb_fifo_mode_set(stmdev_ctx_t *ctx,
4794 asm330lhb_fifo_mode_t val)
4795 {
4796 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4797 int32_t ret;
4798
4799 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4800 (uint8_t *)&fifo_ctrl4, 1);
4801 if (ret == 0)
4802 {
4803 fifo_ctrl4.fifo_mode = (uint8_t)val;
4804 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4805 (uint8_t *)&fifo_ctrl4, 1);
4806 }
4807 return ret;
4808 }
4809
4810 /**
4811 * @brief FIFO mode selection.[get]
4812 *
4813 * @param ctx Read / write interface definitions.(ptr)
4814 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
4815 * @retval Interface status (MANDATORY: return 0 -> no Error).
4816 *
4817 */
asm330lhb_fifo_mode_get(stmdev_ctx_t * ctx,asm330lhb_fifo_mode_t * val)4818 int32_t asm330lhb_fifo_mode_get(stmdev_ctx_t *ctx,
4819 asm330lhb_fifo_mode_t *val)
4820 {
4821 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4822 int32_t ret;
4823
4824 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4825 (uint8_t *)&fifo_ctrl4, 1);
4826
4827 switch (fifo_ctrl4.fifo_mode)
4828 {
4829 case ASM330LHB_BYPASS_MODE:
4830 *val = ASM330LHB_BYPASS_MODE;
4831 break;
4832 case ASM330LHB_FIFO_MODE:
4833 *val = ASM330LHB_FIFO_MODE;
4834 break;
4835 case ASM330LHB_STREAM_TO_FIFO_MODE:
4836 *val = ASM330LHB_STREAM_TO_FIFO_MODE;
4837 break;
4838 case ASM330LHB_BYPASS_TO_STREAM_MODE:
4839 *val = ASM330LHB_BYPASS_TO_STREAM_MODE;
4840 break;
4841 case ASM330LHB_STREAM_MODE:
4842 *val = ASM330LHB_STREAM_MODE;
4843 break;
4844 case ASM330LHB_BYPASS_TO_FIFO_MODE:
4845 *val = ASM330LHB_BYPASS_TO_FIFO_MODE;
4846 break;
4847 default:
4848 *val = ASM330LHB_BYPASS_MODE;
4849 break;
4850 }
4851 return ret;
4852 }
4853
4854 /**
4855 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4856 * for temperature data.[set]
4857 *
4858 * @param ctx Read / write interface definitions.(ptr)
4859 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
4860 * @retval Interface status (MANDATORY: return 0 -> no Error).
4861 *
4862 */
asm330lhb_fifo_temp_batch_set(stmdev_ctx_t * ctx,asm330lhb_odr_t_batch_t val)4863 int32_t asm330lhb_fifo_temp_batch_set(stmdev_ctx_t *ctx,
4864 asm330lhb_odr_t_batch_t val)
4865 {
4866 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4867 int32_t ret;
4868
4869 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4870 (uint8_t *)&fifo_ctrl4, 1);
4871 if (ret == 0)
4872 {
4873 fifo_ctrl4.odr_t_batch = (uint8_t)val;
4874 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4875 (uint8_t *)&fifo_ctrl4, 1);
4876 }
4877 return ret;
4878 }
4879
4880 /**
4881 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4882 * for temperature data.[get]
4883 *
4884 * @param ctx Read / write interface definitions.(ptr)
4885 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
4886 * @retval Interface status (MANDATORY: return 0 -> no Error).
4887 *
4888 */
asm330lhb_fifo_temp_batch_get(stmdev_ctx_t * ctx,asm330lhb_odr_t_batch_t * val)4889 int32_t asm330lhb_fifo_temp_batch_get(stmdev_ctx_t *ctx,
4890 asm330lhb_odr_t_batch_t *val)
4891 {
4892 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4893 int32_t ret;
4894
4895 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4896 (uint8_t *)&fifo_ctrl4, 1);
4897
4898 switch (fifo_ctrl4.odr_t_batch)
4899 {
4900 case ASM330LHB_TEMP_NOT_BATCHED:
4901 *val = ASM330LHB_TEMP_NOT_BATCHED;
4902 break;
4903 case ASM330LHB_TEMP_BATCHED_AT_52Hz:
4904 *val = ASM330LHB_TEMP_BATCHED_AT_52Hz;
4905 break;
4906 case ASM330LHB_TEMP_BATCHED_AT_12Hz5:
4907 *val = ASM330LHB_TEMP_BATCHED_AT_12Hz5;
4908 break;
4909 case ASM330LHB_TEMP_BATCHED_AT_1Hz6:
4910 *val = ASM330LHB_TEMP_BATCHED_AT_1Hz6;
4911 break;
4912 default:
4913 *val = ASM330LHB_TEMP_NOT_BATCHED;
4914 break;
4915 }
4916 return ret;
4917 }
4918
4919 /**
4920 * @brief Selects decimation for timestamp batching in FIFO.
4921 * Writing rate will be the maximum rate between XL and
4922 * GYRO BDR divided by decimation decoder.[set]
4923 *
4924 * @param ctx Read / write interface definitions.(ptr)
4925 * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4
4926 * @retval Interface status (MANDATORY: return 0 -> no Error).
4927 *
4928 */
asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,asm330lhb_dec_ts_batch_t val)4929 int32_t asm330lhb_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
4930 asm330lhb_dec_ts_batch_t val)
4931 {
4932 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4933 int32_t ret;
4934
4935 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4936 (uint8_t *)&fifo_ctrl4, 1);
4937 if (ret == 0)
4938 {
4939 fifo_ctrl4.dec_ts_batch = (uint8_t)val;
4940 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4941 (uint8_t *)&fifo_ctrl4, 1);
4942 }
4943 return ret;
4944 }
4945
4946 /**
4947 * @brief Selects decimation for timestamp batching in FIFO.
4948 * Writing rate will be the maximum rate between XL and
4949 * GYRO BDR divided by decimation decoder.[get]
4950 *
4951 * @param ctx Read / write interface definitions.(ptr)
4952 * @param val Get the values of dec_ts_batch in reg
4953 * FIFO_CTRL4
4954 * @retval Interface status (MANDATORY: return 0 -> no Error).
4955 *
4956 */
asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,asm330lhb_dec_ts_batch_t * val)4957 int32_t asm330lhb_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
4958 asm330lhb_dec_ts_batch_t *val)
4959 {
4960 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4961 int32_t ret;
4962
4963 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4964 (uint8_t *)&fifo_ctrl4, 1);
4965
4966 switch (fifo_ctrl4.dec_ts_batch)
4967 {
4968 case ASM330LHB_NO_DECIMATION:
4969 *val = ASM330LHB_NO_DECIMATION;
4970 break;
4971 case ASM330LHB_DEC_1:
4972 *val = ASM330LHB_DEC_1;
4973 break;
4974 case ASM330LHB_DEC_8:
4975 *val = ASM330LHB_DEC_8;
4976 break;
4977 case ASM330LHB_DEC_32:
4978 *val = ASM330LHB_DEC_32;
4979 break;
4980 default:
4981 *val = ASM330LHB_NO_DECIMATION;
4982 break;
4983 }
4984 return ret;
4985 }
4986
4987 /**
4988 * @brief Selects the trigger for the internal counter of batching events
4989 * between XL and gyro.[set]
4990 *
4991 * @param ctx Read / write interface definitions.(ptr)
4992 * @param val Change the values of trig_counter_bdr in
4993 * reg COUNTER_BDR_REG1
4994 * @retval Interface status (MANDATORY: return 0 -> no Error).
4995 *
4996 */
asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,asm330lhb_trig_counter_bdr_t val)4997 int32_t asm330lhb_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
4998 asm330lhb_trig_counter_bdr_t val)
4999 {
5000 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5001 int32_t ret;
5002
5003 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5004 (uint8_t *)&counter_bdr_reg1, 1);
5005 if (ret == 0)
5006 {
5007 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
5008 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5009 (uint8_t *)&counter_bdr_reg1, 1);
5010 }
5011 return ret;
5012 }
5013
5014 /**
5015 * @brief Selects the trigger for the internal counter of batching events
5016 * between XL and gyro.[get]
5017 *
5018 * @param ctx Read / write interface definitions.(ptr)
5019 * @param val Get the values of trig_counter_bdr
5020 * in reg COUNTER_BDR_REG1
5021 * @retval Interface status (MANDATORY: return 0 -> no Error).
5022 *
5023 */
asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,asm330lhb_trig_counter_bdr_t * val)5024 int32_t asm330lhb_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
5025 asm330lhb_trig_counter_bdr_t *val)
5026 {
5027 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5028 int32_t ret;
5029
5030 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5031 (uint8_t *)&counter_bdr_reg1, 1);
5032
5033 switch (counter_bdr_reg1.trig_counter_bdr)
5034 {
5035 case ASM330LHB_XL_BATCH_EVENT:
5036 *val = ASM330LHB_XL_BATCH_EVENT;
5037 break;
5038 case ASM330LHB_GYRO_BATCH_EVENT:
5039 *val = ASM330LHB_GYRO_BATCH_EVENT;
5040 break;
5041 default:
5042 *val = ASM330LHB_XL_BATCH_EVENT;
5043 break;
5044 }
5045 return ret;
5046 }
5047
5048 /**
5049 * @brief Resets the internal counter of batching events for a single sensor.
5050 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5051 *
5052 * @param ctx Read / write interface definitions.(ptr)
5053 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5054 * @retval Interface status (MANDATORY: return 0 -> no Error).
5055 *
5056 */
asm330lhb_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)5057 int32_t asm330lhb_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
5058 {
5059 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5060 int32_t ret;
5061
5062 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5063 (uint8_t *)&counter_bdr_reg1, 1);
5064 if (ret == 0)
5065 {
5066 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
5067 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5068 (uint8_t *)&counter_bdr_reg1, 1);
5069 }
5070 return ret;
5071 }
5072
5073 /**
5074 * @brief Resets the internal counter of batching events for a single sensor.
5075 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5076 *
5077 * @param ctx Read / write interface definitions.(ptr)
5078 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5079 * @retval Interface status (MANDATORY: return 0 -> no Error).
5080 *
5081 */
asm330lhb_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)5082 int32_t asm330lhb_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
5083 {
5084 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5085 int32_t ret;
5086
5087 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5088 (uint8_t *)&counter_bdr_reg1, 1);
5089 *val = counter_bdr_reg1.rst_counter_bdr;
5090
5091 return ret;
5092 }
5093
5094 /**
5095 * @brief Batch data rate counter.[set]
5096 *
5097 * @param ctx Read / write interface definitions.(ptr)
5098 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5099 * and COUNTER_BDR_REG1.
5100 * @retval Interface status (MANDATORY: return 0 -> no Error).
5101 *
5102 */
asm330lhb_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)5103 int32_t asm330lhb_batch_counter_threshold_set(stmdev_ctx_t *ctx, uint16_t val)
5104 {
5105 asm330lhb_counter_bdr_reg2_t counter_bdr_reg1;
5106 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2;
5107 int32_t ret;
5108
5109 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5110 (uint8_t *)&counter_bdr_reg1, 1);
5111 if (ret == 0)
5112 {
5113 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
5114 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5115 (uint8_t *)&counter_bdr_reg1, 1);
5116 }
5117 if (ret == 0)
5118 {
5119 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
5120 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG2,
5121 (uint8_t *)&counter_bdr_reg2, 1);
5122 }
5123 return ret;
5124 }
5125
5126 /**
5127 * @brief Batch data rate counter.[get]
5128 *
5129 * @param ctx Read / write interface definitions.(ptr)
5130 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5131 * and COUNTER_BDR_REG1.
5132 * @retval Interface status (MANDATORY: return 0 -> no Error).
5133 *
5134 */
asm330lhb_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)5135 int32_t asm330lhb_batch_counter_threshold_get(stmdev_ctx_t *ctx,
5136 uint16_t *val)
5137 {
5138 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5139 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2;
5140 int32_t ret;
5141
5142 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5143 (uint8_t *)&counter_bdr_reg1, 1);
5144 if (ret == 0)
5145 {
5146 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2,
5147 (uint8_t *)&counter_bdr_reg2, 1);
5148 }
5149
5150 *val = counter_bdr_reg1.cnt_bdr_th;
5151 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
5152 return ret;
5153 }
5154
5155 /**
5156 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
5157 *
5158 * @param ctx Read / write interface definitions.(ptr)
5159 * @param val Change the values of diff_fifo in reg FIFO_STATUS1
5160 * @retval Interface status (MANDATORY: return 0 -> no Error).
5161 *
5162 */
asm330lhb_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)5163 int32_t asm330lhb_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
5164 {
5165 asm330lhb_fifo_status1_t fifo_status1;
5166 asm330lhb_fifo_status2_t fifo_status2;
5167 int32_t ret;
5168
5169 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1,
5170 (uint8_t *)&fifo_status1, 1);
5171 if (ret == 0)
5172 {
5173 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
5174 (uint8_t *)&fifo_status2, 1);
5175
5176 *val = fifo_status2.diff_fifo;
5177 *val = (*val * 256U) + fifo_status1.diff_fifo;
5178 }
5179 return ret;
5180 }
5181
5182 /**
5183 * @brief Smart FIFO status.[get]
5184 *
5185 * @param ctx Read / write interface definitions.(ptr)
5186 * @param val Registers FIFO_STATUS2
5187 * @retval Interface status (MANDATORY: return 0 -> no Error).
5188 *
5189 */
asm330lhb_fifo_status_get(stmdev_ctx_t * ctx,asm330lhb_fifo_status2_t * val)5190 int32_t asm330lhb_fifo_status_get(stmdev_ctx_t *ctx,
5191 asm330lhb_fifo_status2_t *val)
5192 {
5193 int32_t ret;
5194 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2, (uint8_t *)val, 1);
5195 return ret;
5196 }
5197
5198 /**
5199 * @brief Smart FIFO full status.[get]
5200 *
5201 * @param ctx Read / write interface definitions.(ptr)
5202 * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2
5203 * @retval Interface status (MANDATORY: return 0 -> no Error).
5204 *
5205 */
asm330lhb_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)5206 int32_t asm330lhb_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
5207 {
5208 asm330lhb_fifo_status2_t fifo_status2;
5209 int32_t ret;
5210
5211 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
5212 (uint8_t *)&fifo_status2, 1);
5213 *val = fifo_status2.fifo_full_ia;
5214
5215 return ret;
5216 }
5217
5218 /**
5219 * @brief FIFO overrun status.[get]
5220 *
5221 * @param ctx Read / write interface definitions.(ptr)
5222 * @param val Change the values of fifo_over_run_latched in
5223 * reg FIFO_STATUS2
5224 * @retval Interface status (MANDATORY: return 0 -> no Error).
5225 *
5226 */
asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)5227 int32_t asm330lhb_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
5228 {
5229 asm330lhb_fifo_status2_t fifo_status2;
5230 int32_t ret;
5231
5232 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
5233 (uint8_t *)&fifo_status2, 1);
5234 *val = fifo_status2. fifo_ovr_ia;
5235
5236 return ret;
5237 }
5238
5239 /**
5240 * @brief FIFO watermark status.[get]
5241 *
5242 * @param ctx Read / write interface definitions.(ptr)
5243 * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2
5244 * @retval Interface status (MANDATORY: return 0 -> no Error).
5245 *
5246 */
asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)5247 int32_t asm330lhb_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
5248 {
5249 asm330lhb_fifo_status2_t fifo_status2;
5250 int32_t ret;
5251
5252 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS2,
5253 (uint8_t *)&fifo_status2, 1);
5254 *val = fifo_status2.fifo_wtm_ia;
5255
5256 return ret;
5257 }
5258
5259 /**
5260 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
5261 *
5262 * @param ctx Read / write interface definitions.(ptr)
5263 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
5264 * @retval Interface status (MANDATORY: return 0 -> no Error).
5265 *
5266 */
asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t * ctx,asm330lhb_fifo_tag_t * val)5267 int32_t asm330lhb_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
5268 asm330lhb_fifo_tag_t *val)
5269 {
5270 asm330lhb_fifo_data_out_tag_t fifo_data_out_tag;
5271 int32_t ret;
5272
5273 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_TAG,
5274 (uint8_t *)&fifo_data_out_tag, 1);
5275
5276 switch (fifo_data_out_tag.tag_sensor)
5277 {
5278 case ASM330LHB_GYRO_NC_TAG:
5279 *val = ASM330LHB_GYRO_NC_TAG;
5280 break;
5281 case ASM330LHB_XL_NC_TAG:
5282 *val = ASM330LHB_XL_NC_TAG;
5283 break;
5284 case ASM330LHB_TEMPERATURE_TAG:
5285 *val = ASM330LHB_TEMPERATURE_TAG;
5286 break;
5287 case ASM330LHB_TIMESTAMP_TAG:
5288 *val = ASM330LHB_TIMESTAMP_TAG;
5289 break;
5290 case ASM330LHB_CFG_CHANGE_TAG:
5291 *val = ASM330LHB_CFG_CHANGE_TAG;
5292 break;
5293 default:
5294 *val = ASM330LHB_XL_NC_TAG;
5295 break;
5296 }
5297 return ret;
5298 }
5299
5300 /**
5301 * @}
5302 *
5303 */
5304
5305 /**
5306 * @defgroup ASM330LHB_DEN_functionality
5307 * @brief This section groups all the functions concerning
5308 * DEN functionality.
5309 * @{
5310 *
5311 */
5312
5313 /**
5314 * @brief DEN functionality marking mode.[set]
5315 *
5316 * @param ctx Read / write interface definitions.(ptr)
5317 * @param val Change the values of den_mode in reg CTRL6_C
5318 * @retval Interface status (MANDATORY: return 0 -> no Error).
5319 *
5320 */
asm330lhb_den_mode_set(stmdev_ctx_t * ctx,asm330lhb_den_mode_t val)5321 int32_t asm330lhb_den_mode_set(stmdev_ctx_t *ctx, asm330lhb_den_mode_t val)
5322 {
5323 asm330lhb_ctrl6_c_t ctrl6_c;
5324 int32_t ret;
5325
5326 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5327 if (ret == 0)
5328 {
5329 ctrl6_c.den_mode = (uint8_t)val;
5330 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5331 }
5332 return ret;
5333 }
5334
5335 /**
5336 * @brief DEN functionality marking mode.[get]
5337 *
5338 * @param ctx Read / write interface definitions.(ptr)
5339 * @param val Get the values of den_mode in reg CTRL6_C
5340 * @retval Interface status (MANDATORY: return 0 -> no Error).
5341 *
5342 */
asm330lhb_den_mode_get(stmdev_ctx_t * ctx,asm330lhb_den_mode_t * val)5343 int32_t asm330lhb_den_mode_get(stmdev_ctx_t *ctx,
5344 asm330lhb_den_mode_t *val)
5345 {
5346 asm330lhb_ctrl6_c_t ctrl6_c;
5347 int32_t ret;
5348
5349 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5350
5351 switch (ctrl6_c.den_mode)
5352 {
5353 case ASM330LHB_DEN_DISABLE:
5354 *val = ASM330LHB_DEN_DISABLE;
5355 break;
5356 case ASM330LHB_LEVEL_FIFO:
5357 *val = ASM330LHB_LEVEL_FIFO;
5358 break;
5359 case ASM330LHB_LEVEL_LETCHED:
5360 *val = ASM330LHB_LEVEL_LETCHED;
5361 break;
5362 case ASM330LHB_LEVEL_TRIGGER:
5363 *val = ASM330LHB_LEVEL_TRIGGER;
5364 break;
5365 case ASM330LHB_EDGE_TRIGGER:
5366 *val = ASM330LHB_EDGE_TRIGGER;
5367 break;
5368 default:
5369 *val = ASM330LHB_DEN_DISABLE;
5370 break;
5371 }
5372 return ret;
5373 }
5374
5375 /**
5376 * @brief DEN active level configuration.[set]
5377 *
5378 * @param ctx Read / write interface definitions.(ptr)
5379 * @param val Change the values of den_lh in reg CTRL9_XL
5380 * @retval Interface status (MANDATORY: return 0 -> no Error).
5381 *
5382 */
asm330lhb_den_polarity_set(stmdev_ctx_t * ctx,asm330lhb_den_lh_t val)5383 int32_t asm330lhb_den_polarity_set(stmdev_ctx_t *ctx,
5384 asm330lhb_den_lh_t val)
5385 {
5386 asm330lhb_ctrl9_xl_t ctrl9_xl;
5387 int32_t ret;
5388
5389 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5390 if (ret == 0)
5391 {
5392 ctrl9_xl.den_lh = (uint8_t)val;
5393 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5394 (uint8_t *)&ctrl9_xl, 1);
5395 }
5396 return ret;
5397 }
5398
5399 /**
5400 * @brief DEN active level configuration.[get]
5401 *
5402 * @param ctx Read / write interface definitions.(ptr)
5403 * @param val Get the values of den_lh in reg CTRL9_XL
5404 * @retval Interface status (MANDATORY: return 0 -> no Error).
5405 *
5406 */
asm330lhb_den_polarity_get(stmdev_ctx_t * ctx,asm330lhb_den_lh_t * val)5407 int32_t asm330lhb_den_polarity_get(stmdev_ctx_t *ctx,
5408 asm330lhb_den_lh_t *val)
5409 {
5410 asm330lhb_ctrl9_xl_t ctrl9_xl;
5411 int32_t ret;
5412
5413 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5414
5415 switch (ctrl9_xl.den_lh)
5416 {
5417 case ASM330LHB_DEN_ACT_LOW:
5418 *val = ASM330LHB_DEN_ACT_LOW;
5419 break;
5420 case ASM330LHB_DEN_ACT_HIGH:
5421 *val = ASM330LHB_DEN_ACT_HIGH;
5422 break;
5423 default:
5424 *val = ASM330LHB_DEN_ACT_LOW;
5425 break;
5426 }
5427 return ret;
5428 }
5429
5430 /**
5431 * @brief DEN configuration.[set]
5432 *
5433 * @param ctx Read / write interface definitions.(ptr)
5434 * @param val Change the values of den_xl_g in reg CTRL9_XL
5435 * @retval Interface status (MANDATORY: return 0 -> no Error).
5436 *
5437 */
asm330lhb_den_enable_set(stmdev_ctx_t * ctx,asm330lhb_den_xl_g_t val)5438 int32_t asm330lhb_den_enable_set(stmdev_ctx_t *ctx,
5439 asm330lhb_den_xl_g_t val)
5440 {
5441 asm330lhb_ctrl9_xl_t ctrl9_xl;
5442 int32_t ret;
5443
5444 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5445 if (ret == 0)
5446 {
5447 ctrl9_xl.den_xl_g = (uint8_t)val;
5448 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5449 (uint8_t *)&ctrl9_xl, 1);
5450 }
5451 return ret;
5452 }
5453
5454 /**
5455 * @brief DEN configuration.[get]
5456 *
5457 * @param ctx Read / write interface definitions.(ptr)
5458 * @param val Get the values of den_xl_g in reg CTRL9_XL
5459 * @retval Interface status (MANDATORY: return 0 -> no Error).
5460 *
5461 */
asm330lhb_den_enable_get(stmdev_ctx_t * ctx,asm330lhb_den_xl_g_t * val)5462 int32_t asm330lhb_den_enable_get(stmdev_ctx_t *ctx,
5463 asm330lhb_den_xl_g_t *val)
5464 {
5465 asm330lhb_ctrl9_xl_t ctrl9_xl;
5466 int32_t ret;
5467
5468 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5469
5470 switch (ctrl9_xl.den_xl_g)
5471 {
5472 case ASM330LHB_STAMP_IN_GY_DATA:
5473 *val = ASM330LHB_STAMP_IN_GY_DATA;
5474 break;
5475 case ASM330LHB_STAMP_IN_XL_DATA:
5476 *val = ASM330LHB_STAMP_IN_XL_DATA;
5477 break;
5478 case ASM330LHB_STAMP_IN_GY_XL_DATA:
5479 *val = ASM330LHB_STAMP_IN_GY_XL_DATA;
5480 break;
5481 default:
5482 *val = ASM330LHB_STAMP_IN_GY_DATA;
5483 break;
5484 }
5485 return ret;
5486 }
5487
5488 /**
5489 * @brief DEN value stored in LSB of X-axis.[set]
5490 *
5491 * @param ctx Read / write interface definitions.(ptr)
5492 * @param val Change the values of den_z in reg CTRL9_XL
5493 * @retval Interface status (MANDATORY: return 0 -> no Error).
5494 *
5495 */
asm330lhb_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)5496 int32_t asm330lhb_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
5497 {
5498 asm330lhb_ctrl9_xl_t ctrl9_xl;
5499 int32_t ret;
5500
5501 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5502 if (ret == 0)
5503 {
5504 ctrl9_xl.den_z = (uint8_t)val;
5505 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5506 (uint8_t *)&ctrl9_xl, 1);
5507 }
5508 return ret;
5509 }
5510
5511 /**
5512 * @brief DEN value stored in LSB of X-axis.[get]
5513 *
5514 * @param ctx Read / write interface definitions.(ptr)
5515 * @param val Change the values of den_z in reg CTRL9_XL
5516 * @retval Interface status (MANDATORY: return 0 -> no Error).
5517 *
5518 */
asm330lhb_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)5519 int32_t asm330lhb_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5520 {
5521 asm330lhb_ctrl9_xl_t ctrl9_xl;
5522 int32_t ret;
5523
5524 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5525 *val = ctrl9_xl.den_z;
5526
5527 return ret;
5528 }
5529
5530 /**
5531 * @brief DEN value stored in LSB of Y-axis.[set]
5532 *
5533 * @param ctx Read / write interface definitions.(ptr)
5534 * @param val Change the values of den_y in reg CTRL9_XL
5535 * @retval Interface status (MANDATORY: return 0 -> no Error).
5536 *
5537 */
asm330lhb_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)5538 int32_t asm330lhb_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
5539 {
5540 asm330lhb_ctrl9_xl_t ctrl9_xl;
5541 int32_t ret;
5542
5543 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5544 if (ret == 0)
5545 {
5546 ctrl9_xl.den_y = (uint8_t)val;
5547 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5548 (uint8_t *)&ctrl9_xl, 1);
5549 }
5550 return ret;
5551 }
5552
5553 /**
5554 * @brief DEN value stored in LSB of Y-axis.[get]
5555 *
5556 * @param ctx Read / write interface definitions.(ptr)
5557 * @param val Change the values of den_y in reg CTRL9_XL
5558 * @retval Interface status (MANDATORY: return 0 -> no Error).
5559 *
5560 */
asm330lhb_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)5561 int32_t asm330lhb_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
5562 {
5563 asm330lhb_ctrl9_xl_t ctrl9_xl;
5564 int32_t ret;
5565
5566 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5567 *val = ctrl9_xl.den_y;
5568
5569 return ret;
5570 }
5571
5572 /**
5573 * @brief DEN value stored in LSB of Z-axis.[set]
5574 *
5575 * @param ctx Read / write interface definitions.(ptr)
5576 * @param val Change the values of den_x in reg CTRL9_XL
5577 * @retval Interface status (MANDATORY: return 0 -> no Error).
5578 *
5579 */
asm330lhb_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)5580 int32_t asm330lhb_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
5581 {
5582 asm330lhb_ctrl9_xl_t ctrl9_xl;
5583 int32_t ret;
5584
5585 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5586 if (ret == 0)
5587 {
5588 ctrl9_xl.den_x = (uint8_t)val;
5589 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5590 }
5591 return ret;
5592 }
5593
5594 /**
5595 * @brief DEN value stored in LSB of Z-axis.[get]
5596 *
5597 * @param ctx Read / write interface definitions.(ptr)
5598 * @param val Change the values of den_x in reg CTRL9_XL
5599 * @retval Interface status (MANDATORY: return 0 -> no Error).
5600 *
5601 */
asm330lhb_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)5602 int32_t asm330lhb_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
5603 {
5604 asm330lhb_ctrl9_xl_t ctrl9_xl;
5605 int32_t ret;
5606
5607 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5608 *val = ctrl9_xl.den_x;
5609
5610 return ret;
5611 }
5612
5613 /**
5614 * @}
5615 *
5616 */
5617
5618 /**
5619 * @defgroup ASM330LHB_finite_state_machine
5620 * @brief This section groups all the functions that manage the
5621 * state_machine.
5622 * @{
5623 *
5624 */
5625
5626 /**
5627 * @brief FSM status register[get]
5628 *
5629 * @param ctx read / write interface definitions
5630 * @param val register ASM330LHB_FSM_STATUS_A_MAINPAGE,
5631 * ASM330LHB_FSM_STATUS_B_MAINPAGE
5632 *
5633 */
asm330lhb_fsm_status_get(stmdev_ctx_t * ctx,asm330lhb_fsm_status_t * val)5634 int32_t asm330lhb_fsm_status_get(stmdev_ctx_t *ctx,
5635 asm330lhb_fsm_status_t *val)
5636 {
5637 asm330lhb_fsm_status_a_mainpage_t status_a;
5638 asm330lhb_fsm_status_b_mainpage_t status_b;
5639 int32_t ret;
5640
5641 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A_MAINPAGE,
5642 (uint8_t *)&status_a, 1);
5643 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE,
5644 (uint8_t *)&status_b, 1);
5645
5646 val->fsm1 = status_a.is_fsm1;
5647 val->fsm2 = status_a.is_fsm2;
5648 val->fsm3 = status_a.is_fsm3;
5649 val->fsm4 = status_a.is_fsm4;
5650 val->fsm5 = status_a.is_fsm5;
5651 val->fsm6 = status_a.is_fsm6;
5652 val->fsm7 = status_a.is_fsm7;
5653 val->fsm8 = status_a.is_fsm8;
5654 val->fsm9 = status_b.is_fsm9;
5655 val->fsm10 = status_b.is_fsm10;
5656 val->fsm11 = status_b.is_fsm11;
5657 val->fsm12 = status_b.is_fsm12;
5658 val->fsm13 = status_b.is_fsm13;
5659 val->fsm14 = status_b.is_fsm14;
5660 val->fsm15 = status_b.is_fsm15;
5661 val->fsm16 = status_b.is_fsm16;
5662 return ret;
5663 }
5664
5665 /**
5666 * @brief prgsens_out: [get] Output value of all FSMs.
5667 *
5668 * @param ctx_t *ctx: read / write interface definitions
5669 * @param uint8_t * : buffer that stores data read
5670 *
5671 */
asm330lhb_fsm_out_get(stmdev_ctx_t * ctx,uint8_t * buff)5672 int32_t asm330lhb_fsm_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
5673 {
5674 int32_t ret;
5675 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5676 if (ret == 0)
5677 {
5678 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_OUTS1, buff, 16);
5679 }
5680 if (ret == 0)
5681 {
5682 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5683 }
5684 return ret;
5685 }
5686
5687 /**
5688 * @brief Interrupt status bit for FSM long counter timeout interrupt
5689 * event.[get]
5690 *
5691 * @param ctx Read / write interface definitions.(ptr)
5692 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
5693 * @retval Interface status (MANDATORY: return 0 -> no Error).
5694 *
5695 */
asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)5696 int32_t asm330lhb_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
5697 uint8_t *val)
5698 {
5699 asm330lhb_emb_func_status_t emb_func_status;
5700 int32_t ret;
5701
5702 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5703 if (ret == 0)
5704 {
5705 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS,
5706 (uint8_t *)&emb_func_status, 1);
5707 }
5708 if (ret == 0)
5709 {
5710 *val = emb_func_status.is_fsm_lc;
5711 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5712 }
5713 return ret;
5714 }
5715
asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t * ctx,uint8_t val)5716 int32_t asm330lhb_emb_func_clk_dis_set(stmdev_ctx_t *ctx, uint8_t val)
5717 {
5718 asm330lhb_page_sel_t page_sel;
5719 int32_t ret;
5720
5721 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5722 if (ret == 0)
5723 {
5724 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
5725 (uint8_t *)&page_sel, 1);
5726
5727 page_sel.emb_func_clk_dis = val;
5728 }
5729
5730 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5731
5732 return ret;
5733 }
5734
asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t * ctx,uint8_t * val)5735 int32_t asm330lhb_emb_func_clk_dis_get(stmdev_ctx_t *ctx, uint8_t *val)
5736 {
5737 asm330lhb_page_sel_t page_sel;
5738 int32_t ret;
5739
5740 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5741 if (ret == 0)
5742 {
5743 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
5744 (uint8_t *)&page_sel, 1);
5745
5746 *val = page_sel.emb_func_clk_dis;
5747 }
5748
5749 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5750
5751 return ret;
5752 }
5753
5754 /**
5755 * @brief Embedded final state machine functions mode.[set]
5756 *
5757 * @param ctx Read / write interface definitions.(ptr)
5758 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
5759 * @retval Interface status (MANDATORY: return 0 -> no Error).
5760 *
5761 */
asm330lhb_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)5762 int32_t asm330lhb_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
5763 {
5764 int32_t ret;
5765 asm330lhb_emb_func_en_b_t emb_func_en_b;
5766
5767 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5768
5769 if (ret == 0)
5770 {
5771 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5772 (uint8_t *)&emb_func_en_b, 1);
5773 }
5774 if (ret == 0)
5775 {
5776 emb_func_en_b.fsm_en = (uint8_t)val;
5777 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5778 (uint8_t *)&emb_func_en_b, 1);
5779 }
5780 if (ret == 0)
5781 {
5782 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5783 }
5784 return ret;
5785 }
5786
5787 /**
5788 * @brief Embedded final state machine functions mode.[get]
5789 *
5790 * @param ctx Read / write interface definitions.(ptr)
5791 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
5792 * @retval Interface status (MANDATORY: return 0 -> no Error).
5793 *
5794 */
asm330lhb_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)5795 int32_t asm330lhb_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
5796 {
5797 int32_t ret;
5798 asm330lhb_emb_func_en_b_t emb_func_en_b;
5799
5800 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5801 if (ret == 0)
5802 {
5803 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5804 (uint8_t *)&emb_func_en_b, 1);
5805 }
5806 if (ret == 0)
5807 {
5808 *val = emb_func_en_b.fsm_en;
5809 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5810 (uint8_t *)&emb_func_en_b, 1);
5811 }
5812 if (ret == 0)
5813 {
5814 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5815 }
5816 return ret;
5817 }
5818
5819 /**
5820 * @brief Embedded final state machine functions mode.[set]
5821 *
5822 * @param ctx Read / write interface definitions.(ptr)
5823 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5824 * @retval Interface status (MANDATORY: return 0 -> no Error).
5825 *
5826 */
asm330lhb_fsm_enable_set(stmdev_ctx_t * ctx,asm330lhb_emb_fsm_enable_t * val)5827 int32_t asm330lhb_fsm_enable_set(stmdev_ctx_t *ctx,
5828 asm330lhb_emb_fsm_enable_t *val)
5829 {
5830 asm330lhb_emb_func_en_b_t emb_func_en_b;
5831 int32_t ret;
5832
5833 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5834 if (ret == 0)
5835 {
5836 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_A,
5837 (uint8_t *)&val->fsm_enable_a, 1);
5838 }
5839 if (ret == 0)
5840 {
5841 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_B,
5842 (uint8_t *)&val->fsm_enable_b, 1);
5843 }
5844 if (ret == 0)
5845 {
5846 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5847 (uint8_t *)&emb_func_en_b, 1);
5848 }
5849 if (ret == 0)
5850 {
5851 if ((val->fsm_enable_a.fsm1_en |
5852 val->fsm_enable_a.fsm2_en |
5853 val->fsm_enable_a.fsm3_en |
5854 val->fsm_enable_a.fsm4_en |
5855 val->fsm_enable_a.fsm5_en |
5856 val->fsm_enable_a.fsm6_en |
5857 val->fsm_enable_a.fsm7_en |
5858 val->fsm_enable_a.fsm8_en |
5859 val->fsm_enable_b.fsm9_en |
5860 val->fsm_enable_b.fsm10_en |
5861 val->fsm_enable_b.fsm11_en |
5862 val->fsm_enable_b.fsm12_en |
5863 val->fsm_enable_b.fsm13_en |
5864 val->fsm_enable_b.fsm14_en |
5865 val->fsm_enable_b.fsm15_en |
5866 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
5867 {
5868 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
5869 }
5870 else
5871 {
5872 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
5873 }
5874 }
5875 if (ret == 0)
5876 {
5877 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5878 (uint8_t *)&emb_func_en_b, 1);
5879 }
5880 if (ret == 0)
5881 {
5882 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5883 }
5884 return ret;
5885 }
5886
5887 /**
5888 * @brief Embedded final state machine functions mode.[get]
5889 *
5890 * @param ctx Read / write interface definitions.(ptr)
5891 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5892 * @retval Interface status (MANDATORY: return 0 -> no Error).
5893 *
5894 */
asm330lhb_fsm_enable_get(stmdev_ctx_t * ctx,asm330lhb_emb_fsm_enable_t * val)5895 int32_t asm330lhb_fsm_enable_get(stmdev_ctx_t *ctx,
5896 asm330lhb_emb_fsm_enable_t *val)
5897 {
5898 int32_t ret;
5899
5900 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5901 if (ret == 0)
5902 {
5903 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_A,
5904 (uint8_t *)&val->fsm_enable_a, 1);
5905 }
5906 if (ret == 0)
5907 {
5908 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_B,
5909 (uint8_t *)&val->fsm_enable_b, 1);
5910 }
5911 if (ret == 0)
5912 {
5913 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5914 }
5915 return ret;
5916 }
5917
5918 /**
5919 * @brief FSM long counter status register. Long counter value is an
5920 * unsigned integer value (16-bit format).[set]
5921 *
5922 * @param ctx Read / write interface definitions.(ptr)
5923 * @param buff Buffer that contains data to write
5924 * @retval Interface status (MANDATORY: return 0 -> no Error).
5925 *
5926 */
asm330lhb_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)5927 int32_t asm330lhb_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
5928 {
5929 uint8_t buff[2];
5930 int32_t ret;
5931
5932 buff[1] = (uint8_t)(val / 256U);
5933 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5934
5935 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5936 if (ret == 0)
5937 {
5938 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2);
5939 }
5940 if (ret == 0)
5941 {
5942 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5943 }
5944 return ret;
5945 }
5946
5947 /**
5948 * @brief FSM long counter status register. Long counter value is an
5949 * unsigned integer value (16-bit format).[get]
5950 *
5951 * @param ctx Read / write interface definitions.(ptr)
5952 * @param buff Buffer that stores data read
5953 * @retval Interface status (MANDATORY: return 0 -> no Error).
5954 *
5955 */
asm330lhb_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)5956 int32_t asm330lhb_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
5957 {
5958 uint8_t buff[2];
5959 int32_t ret;
5960
5961 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5962 if (ret == 0)
5963 {
5964 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2);
5965 *val = buff[1];
5966 *val = (*val * 256U) + buff[0];
5967 }
5968 if (ret == 0)
5969 {
5970 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5971 }
5972 return ret;
5973 }
5974
5975 /**
5976 * @brief Clear FSM long counter value.[set]
5977 *
5978 * @param ctx Read / write interface definitions.(ptr)
5979 * @param val Change the values of fsm_lc_clr in reg
5980 * FSM_LONG_COUNTER_CLEAR
5981 * @retval Interface status (MANDATORY: return 0 -> no Error).
5982 *
5983 */
asm330lhb_long_clr_set(stmdev_ctx_t * ctx,asm330lhb_fsm_lc_clr_t val)5984 int32_t asm330lhb_long_clr_set(stmdev_ctx_t *ctx,
5985 asm330lhb_fsm_lc_clr_t val)
5986 {
5987 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear;
5988 int32_t ret;
5989
5990 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5991 if (ret == 0)
5992 {
5993 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
5994 (uint8_t *)&fsm_long_counter_clear, 1);
5995 }
5996 if (ret == 0)
5997 {
5998 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
5999 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
6000 (uint8_t *)&fsm_long_counter_clear, 1);
6001 }
6002 if (ret == 0)
6003 {
6004 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6005 }
6006 return ret;
6007 }
6008
6009 /**
6010 * @brief Clear FSM long counter value.[get]
6011 *
6012 * @param ctx Read / write interface definitions.(ptr)
6013 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
6014 * @retval Interface status (MANDATORY: return 0 -> no Error).
6015 *
6016 */
asm330lhb_long_clr_get(stmdev_ctx_t * ctx,asm330lhb_fsm_lc_clr_t * val)6017 int32_t asm330lhb_long_clr_get(stmdev_ctx_t *ctx,
6018 asm330lhb_fsm_lc_clr_t *val)
6019 {
6020 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear;
6021 int32_t ret;
6022
6023 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6024
6025 if (ret == 0)
6026 {
6027 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
6028 (uint8_t *)&fsm_long_counter_clear, 1);
6029 }
6030 if (ret == 0)
6031 {
6032 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6033 }
6034 switch (fsm_long_counter_clear.fsm_lc_clr)
6035 {
6036 case ASM330LHB_LC_NORMAL:
6037 *val = ASM330LHB_LC_NORMAL;
6038 break;
6039 case ASM330LHB_LC_CLEAR:
6040 *val = ASM330LHB_LC_CLEAR;
6041 break;
6042 case ASM330LHB_LC_CLEAR_DONE:
6043 *val = ASM330LHB_LC_CLEAR_DONE;
6044 break;
6045 default:
6046 *val = ASM330LHB_LC_NORMAL;
6047 break;
6048 }
6049 return ret;
6050 }
6051
6052 /**
6053 * @brief Finite State Machine ODR configuration.[set]
6054 *
6055 * @param ctx Read / write interface definitions.(ptr)
6056 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6057 * @retval Interface status (MANDATORY: return 0 -> no Error).
6058 *
6059 */
asm330lhb_fsm_data_rate_set(stmdev_ctx_t * ctx,asm330lhb_fsm_odr_t val)6060 int32_t asm330lhb_fsm_data_rate_set(stmdev_ctx_t *ctx,
6061 asm330lhb_fsm_odr_t val)
6062 {
6063 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6064 int32_t ret;
6065
6066 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6067
6068 if (ret == 0)
6069 {
6070 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6071 (uint8_t *)&emb_func_odr_cfg_b, 1);
6072 }
6073 if (ret == 0)
6074 {
6075 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
6076 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
6077 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
6078 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6079 (uint8_t *)&emb_func_odr_cfg_b, 1);
6080 }
6081 if (ret == 0)
6082 {
6083 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6084 }
6085 return ret;
6086 }
6087
6088 /**
6089 * @brief Finite State Machine ODR configuration.[get]
6090 *
6091 * @param ctx Read / write interface definitions.(ptr)
6092 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6093 * @retval Interface status (MANDATORY: return 0 -> no Error).
6094 *
6095 */
asm330lhb_fsm_data_rate_get(stmdev_ctx_t * ctx,asm330lhb_fsm_odr_t * val)6096 int32_t asm330lhb_fsm_data_rate_get(stmdev_ctx_t *ctx,
6097 asm330lhb_fsm_odr_t *val)
6098 {
6099 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6100 int32_t ret;
6101
6102 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6103
6104 if (ret == 0)
6105 {
6106 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6107 (uint8_t *)&emb_func_odr_cfg_b, 1);
6108 }
6109 if (ret == 0)
6110 {
6111 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6112 }
6113 switch (emb_func_odr_cfg_b.fsm_odr)
6114 {
6115 case ASM330LHB_ODR_FSM_12Hz5:
6116 *val = ASM330LHB_ODR_FSM_12Hz5;
6117 break;
6118 case ASM330LHB_ODR_FSM_26Hz:
6119 *val = ASM330LHB_ODR_FSM_26Hz;
6120 break;
6121 case ASM330LHB_ODR_FSM_52Hz:
6122 *val = ASM330LHB_ODR_FSM_52Hz;
6123 break;
6124 case ASM330LHB_ODR_FSM_104Hz:
6125 *val = ASM330LHB_ODR_FSM_104Hz;
6126 break;
6127 default:
6128 *val = ASM330LHB_ODR_FSM_12Hz5;
6129 break;
6130 }
6131 return ret;
6132 }
6133
6134 /**
6135 * @brief FSM initialization request.[set]
6136 *
6137 * @param ctx Read / write interface definitions.(ptr)
6138 * @param val Change the values of fsm_init in reg FSM_INIT
6139 * @retval Interface status (MANDATORY: return 0 -> no Error).
6140 *
6141 */
asm330lhb_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)6142 int32_t asm330lhb_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
6143 {
6144 asm330lhb_emb_func_init_b_t emb_func_init_b;
6145 int32_t ret;
6146
6147 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6148
6149 if (ret == 0)
6150 {
6151 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6152 (uint8_t *)&emb_func_init_b, 1);
6153 }
6154 if (ret == 0)
6155 {
6156 emb_func_init_b.fsm_init = (uint8_t)val;
6157 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6158 (uint8_t *)&emb_func_init_b, 1);
6159 }
6160 if (ret == 0)
6161 {
6162 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6163 }
6164 return ret;
6165 }
6166
6167 /**
6168 * @brief FSM initialization request.[get]
6169 *
6170 * @param ctx Read / write interface definitions.(ptr)
6171 * @param val Change the values of fsm_init in reg FSM_INIT
6172 * @retval Interface status (MANDATORY: return 0 -> no Error).
6173 *
6174 */
asm330lhb_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)6175 int32_t asm330lhb_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
6176 {
6177 asm330lhb_emb_func_init_b_t emb_func_init_b;
6178 int32_t ret;
6179
6180 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6181 if (ret == 0)
6182 {
6183 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6184 (uint8_t *)&emb_func_init_b, 1);
6185 }
6186 if (ret == 0)
6187 {
6188 *val = emb_func_init_b.fsm_init;
6189 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6190 }
6191 return ret;
6192 }
6193
6194 /**
6195 * @brief FSM long counter timeout register (r/w). The long counter
6196 * timeout value is an unsigned integer value (16-bit format).
6197 * When the long counter value reached this value, the FSM
6198 * generates an interrupt.[set]
6199 *
6200 * @param ctx Read / write interface definitions.(ptr)
6201 * @param buff Buffer that contains data to write
6202 * @retval Interface status (MANDATORY: return 0 -> no Error).
6203 *
6204 */
asm330lhb_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)6205 int32_t asm330lhb_long_cnt_int_value_set(stmdev_ctx_t *ctx, uint16_t val)
6206 {
6207 uint8_t buff[2];
6208 int32_t ret;
6209
6210 buff[1] = (uint8_t)(val / 256U);
6211 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6212 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]);
6213
6214 if (ret == 0)
6215 {
6216 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H,
6217 &buff[1]);
6218 }
6219 return ret;
6220 }
6221
6222 /**
6223 * @brief FSM long counter timeout register (r/w). The long counter
6224 * timeout value is an unsigned integer value (16-bit format).
6225 * When the long counter value reached this value, the FSM generates
6226 * an interrupt.[get]
6227 *
6228 * @param ctx Read / write interface definitions.(ptr)
6229 * @param buff Buffer that stores data read
6230 * @retval Interface status (MANDATORY: return 0 -> no Error).
6231 *
6232 */
asm330lhb_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)6233 int32_t asm330lhb_long_cnt_int_value_get(stmdev_ctx_t *ctx, uint16_t *val)
6234 {
6235 uint8_t buff[2];
6236 int32_t ret;
6237
6238 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]);
6239
6240 if (ret == 0)
6241 {
6242 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H,
6243 &buff[1]);
6244 *val = buff[1];
6245 *val = (*val * 256U) + buff[0];
6246 }
6247 return ret;
6248 }
6249
6250 /**
6251 * @brief FSM number of programs register.[set]
6252 *
6253 * @param ctx Read / write interface definitions.(ptr)
6254 * @param buff Buffer that contains data to write
6255 * @retval Interface status (MANDATORY: return 0 -> no Error).
6256 *
6257 */
asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)6258 int32_t asm330lhb_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t *buff)
6259 {
6260 int32_t ret;
6261
6262 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff);
6263
6264 if (ret == 0)
6265 {
6266 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS + 0x01U,
6267 buff);
6268 }
6269 return ret;
6270 }
6271
6272 /**
6273 * @brief FSM number of programs register.[get]
6274 *
6275 * @param ctx Read / write interface definitions.(ptr)
6276 * @param buff Buffer that stores data read
6277 * @retval Interface status (MANDATORY: return 0 -> no Error).
6278 *
6279 */
asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)6280 int32_t asm330lhb_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *buff)
6281 {
6282 int32_t ret;
6283
6284 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff);
6285
6286 return ret;
6287 }
6288
6289 /**
6290 * @brief FSM start address register (r/w). First available address is
6291 * 0x033C.[set]
6292 *
6293 * @param ctx Read / write interface definitions.(ptr)
6294 * @param buff Buffer that contains data to write
6295 * @retval Interface status (MANDATORY: return 0 -> no Error).
6296 *
6297 */
asm330lhb_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)6298 int32_t asm330lhb_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
6299 {
6300 uint8_t buff[2];
6301 int32_t ret;
6302
6303 buff[1] = (uint8_t)(val / 256U);
6304 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6305
6306 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]);
6307 if (ret == 0)
6308 {
6309 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]);
6310 }
6311 return ret;
6312 }
6313
6314 /**
6315 * @brief FSM start address register (r/w). First available address
6316 * is 0x033C.[get]
6317 *
6318 * @param ctx Read / write interface definitions.(ptr)
6319 * @param buff Buffer that stores data read
6320 * @retval Interface status (MANDATORY: return 0 -> no Error).
6321 *
6322 */
asm330lhb_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)6323 int32_t asm330lhb_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
6324 {
6325 uint8_t buff[2];
6326 int32_t ret;
6327
6328 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]);
6329 if (ret == 0)
6330 {
6331 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]);
6332 *val = buff[1];
6333 *val = (*val * 256U) + buff[0];
6334 }
6335 return ret;
6336 }
6337
6338 /**
6339 * @}
6340 *
6341 */
6342
6343 /**
6344 * @addtogroup Machine Learning Core
6345 * @brief This section group all the functions concerning the
6346 * usage of Machine Learning Core
6347 * @{
6348 *
6349 */
6350
6351 /**
6352 * @brief Enable Machine Learning Core.[set]
6353 *
6354 * @param ctx read / write interface definitions
6355 * @param val change the values of mlc_en in
6356 * reg EMB_FUNC_EN_B and mlc_init
6357 * in EMB_FUNC_INIT_B
6358 *
6359 */
asm330lhb_mlc_set(stmdev_ctx_t * ctx,uint8_t val)6360 int32_t asm330lhb_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
6361 {
6362 asm330lhb_emb_func_en_b_t reg;
6363 int32_t ret;
6364
6365 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6366 if (ret == 0)
6367 {
6368 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6369 }
6370 if (ret == 0)
6371 {
6372 reg.mlc_en = val;
6373 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6374 }
6375 if ((val != PROPERTY_DISABLE) && (ret == 0))
6376 {
6377 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6378 (uint8_t *)®, 1);
6379 if (ret == 0)
6380 {
6381 reg.mlc_en = val;
6382 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6383 (uint8_t *)®, 1);
6384 }
6385 }
6386 if (ret == 0)
6387 {
6388 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6389 }
6390 return ret;
6391 }
6392
6393 /**
6394 * @brief Enable Machine Learning Core.[get]
6395 *
6396 * @param ctx read / write interface definitions
6397 * @param val Get the values of mlc_en in
6398 * reg EMB_FUNC_EN_B
6399 *
6400 */
asm330lhb_mlc_get(stmdev_ctx_t * ctx,uint8_t * val)6401 int32_t asm330lhb_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
6402 {
6403 asm330lhb_emb_func_en_b_t reg;
6404 int32_t ret;
6405
6406 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6407 if (ret == 0)
6408 {
6409 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6410 }
6411 if (ret == 0)
6412 {
6413 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6414 *val = reg.mlc_en;
6415 }
6416 return ret;
6417 }
6418
6419 /**
6420 * @brief Machine Learning Core status register[get]
6421 *
6422 * @param ctx read / write interface definitions
6423 * @param val register MLC_STATUS_MAINPAGE
6424 *
6425 */
asm330lhb_mlc_status_get(stmdev_ctx_t * ctx,asm330lhb_mlc_status_mainpage_t * val)6426 int32_t asm330lhb_mlc_status_get(stmdev_ctx_t *ctx,
6427 asm330lhb_mlc_status_mainpage_t *val)
6428 {
6429 return asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS_MAINPAGE,
6430 (uint8_t *) val, 1);
6431 }
6432
6433 /**
6434 * @brief Machine Learning Core data rate selection.[set]
6435 *
6436 * @param ctx read / write interface definitions
6437 * @param val get the values of mlc_odr in
6438 * reg EMB_FUNC_ODR_CFG_C
6439 *
6440 */
asm330lhb_mlc_data_rate_set(stmdev_ctx_t * ctx,asm330lhb_mlc_odr_t val)6441 int32_t asm330lhb_mlc_data_rate_set(stmdev_ctx_t *ctx,
6442 asm330lhb_mlc_odr_t val)
6443 {
6444 asm330lhb_emb_func_odr_cfg_c_t reg;
6445 int32_t ret;
6446
6447 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6448 if (ret == 0)
6449 {
6450 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6451 (uint8_t *)®, 1);
6452 }
6453 if (ret == 0)
6454 {
6455 reg.mlc_odr = (uint8_t)val;
6456 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6457 (uint8_t *)®, 1);
6458 }
6459 if (ret == 0)
6460 {
6461 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6462 }
6463
6464 return ret;
6465 }
6466
6467 /**
6468 * @brief Machine Learning Core data rate selection.[get]
6469 *
6470 * @param ctx read / write interface definitions
6471 * @param val change the values of mlc_odr in
6472 * reg EMB_FUNC_ODR_CFG_C
6473 *
6474 */
asm330lhb_mlc_data_rate_get(stmdev_ctx_t * ctx,asm330lhb_mlc_odr_t * val)6475 int32_t asm330lhb_mlc_data_rate_get(stmdev_ctx_t *ctx,
6476 asm330lhb_mlc_odr_t *val)
6477 {
6478 asm330lhb_emb_func_odr_cfg_c_t reg;
6479 int32_t ret;
6480
6481 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6482 if (ret == 0)
6483 {
6484 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6485 (uint8_t *)®, 1);
6486 }
6487 if (ret == 0)
6488 {
6489 switch (reg.mlc_odr)
6490 {
6491 case ASM330LHB_ODR_PRGS_12Hz5:
6492 *val = ASM330LHB_ODR_PRGS_12Hz5;
6493 break;
6494 case ASM330LHB_ODR_PRGS_26Hz:
6495 *val = ASM330LHB_ODR_PRGS_26Hz;
6496 break;
6497 case ASM330LHB_ODR_PRGS_52Hz:
6498 *val = ASM330LHB_ODR_PRGS_52Hz;
6499 break;
6500 case ASM330LHB_ODR_PRGS_104Hz:
6501 *val = ASM330LHB_ODR_PRGS_104Hz;
6502 break;
6503 default:
6504 *val = ASM330LHB_ODR_PRGS_12Hz5;
6505 break;
6506 }
6507 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6508 }
6509 return ret;
6510 }
6511
6512 /**
6513 * @brief MLC initialization request.[set]
6514 *
6515 * @param ctx Read / write interface definitions.(ptr)
6516 * @param val Change the values of mlc_init
6517 * @retval Interface status (MANDATORY: return 0 -> no Error).
6518 *
6519 */
asm330lhb_mlc_init_set(stmdev_ctx_t * ctx,uint8_t val)6520 int32_t asm330lhb_mlc_init_set(stmdev_ctx_t *ctx, uint8_t val)
6521 {
6522 asm330lhb_emb_func_init_b_t emb_func_init_b;
6523 int32_t ret;
6524
6525 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6526
6527 if (ret == 0)
6528 {
6529 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6530 (uint8_t *)&emb_func_init_b, 1);
6531 }
6532 if (ret == 0)
6533 {
6534 emb_func_init_b.mlc_init = (uint8_t)val;
6535 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6536 (uint8_t *)&emb_func_init_b, 1);
6537 }
6538
6539 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6540
6541 return ret;
6542 }
6543
6544 /**
6545 * @brief MLC initialization request.[get]
6546 *
6547 * @param ctx Read / write interface definitions.(ptr)
6548 * @param val Get the values of mlc_init
6549 * @retval Interface status (MANDATORY: return 0 -> no Error).
6550 *
6551 */
asm330lhb_mlc_init_get(stmdev_ctx_t * ctx,uint8_t * val)6552 int32_t asm330lhb_mlc_init_get(stmdev_ctx_t *ctx, uint8_t *val)
6553 {
6554 asm330lhb_emb_func_init_b_t emb_func_init_b;
6555 int32_t ret;
6556
6557 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6558 if (ret == 0)
6559 {
6560 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6561 (uint8_t *)&emb_func_init_b, 1);
6562 }
6563 if (ret == 0)
6564 {
6565 *val = emb_func_init_b.mlc_init;
6566 }
6567
6568 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6569
6570 return ret;
6571 }
6572
6573 /**
6574 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
6575 *
6576 * @param ctx_t *ctx: read / write interface definitions
6577 * @param uint8_t * : buffer that stores data read
6578 *
6579 */
asm330lhb_mlc_out_get(stmdev_ctx_t * ctx,uint8_t * buff)6580 int32_t asm330lhb_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
6581 {
6582 int32_t ret;
6583 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6584 if (ret == 0)
6585 {
6586 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC0_SRC, buff, 8);
6587 }
6588 if (ret == 0)
6589 {
6590 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6591 }
6592 return ret;
6593 }
6594
6595 /**
6596 * @}
6597 *
6598 */
6599
6600 /**
6601 * @}
6602 *
6603 */
6604
6605 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6606
