1 /* 2 ****************************************************************************** 3 * @file asm330lhb_reg.h 4 * @author Sensor Solutions Software Team 5 * @brief This file contains all the functions prototypes for the 6 * asm330lhb_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ASM330LHB_REGS_H 23 #define ASM330LHB_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ASM330LHB 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ASM330LHB Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define ASM330LHB_I2C_ADD_L 0xD5U 173 #define ASM330LHB_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define ASM330LHB_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define ASM330LHB_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 7; 188 uint8_t reg_access : 1; /* func_cfg_access */ 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t reg_access : 1; /* func_cfg_access */ 191 uint8_t not_used_01 : 7; 192 #endif /* DRV_BYTE_ORDER */ 193 } asm330lhb_func_cfg_access_t; 194 195 #define ASM330LHB_PIN_CTRL 0x02U 196 typedef struct 197 { 198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 199 uint8_t not_used_01 : 6; 200 uint8_t sdo_pu_en : 1; 201 uint8_t not_used_02 : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t not_used_02 : 1; 204 uint8_t sdo_pu_en : 1; 205 uint8_t not_used_01 : 6; 206 #endif /* DRV_BYTE_ORDER */ 207 } asm330lhb_pin_ctrl_t; 208 209 #define ASM330LHB_FIFO_CTRL1 0x07U 210 typedef struct 211 { 212 uint8_t wtm : 8; 213 } asm330lhb_fifo_ctrl1_t; 214 215 #define ASM330LHB_FIFO_CTRL2 0x08U 216 typedef struct 217 { 218 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 219 uint8_t wtm : 1; 220 uint8_t not_used_01 : 3; 221 uint8_t odrchg_en : 1; 222 uint8_t not_used_02 : 2; 223 uint8_t stop_on_wtm : 1; 224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 225 uint8_t stop_on_wtm : 1; 226 uint8_t not_used_02 : 2; 227 uint8_t odrchg_en : 1; 228 uint8_t not_used_01 : 3; 229 uint8_t wtm : 1; 230 #endif /* DRV_BYTE_ORDER */ 231 } asm330lhb_fifo_ctrl2_t; 232 233 #define ASM330LHB_FIFO_CTRL3 0x09U 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t bdr_xl : 4; 238 uint8_t bdr_gy : 4; 239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 240 uint8_t bdr_gy : 4; 241 uint8_t bdr_xl : 4; 242 #endif /* DRV_BYTE_ORDER */ 243 } asm330lhb_fifo_ctrl3_t; 244 245 #define ASM330LHB_FIFO_CTRL4 0x0AU 246 typedef struct 247 { 248 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 249 uint8_t fifo_mode : 3; 250 uint8_t not_used_01 : 1; 251 uint8_t odr_t_batch : 2; 252 uint8_t dec_ts_batch : 2; 253 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 254 uint8_t dec_ts_batch : 2; 255 uint8_t odr_t_batch : 2; 256 uint8_t not_used_01 : 1; 257 uint8_t fifo_mode : 3; 258 #endif /* DRV_BYTE_ORDER */ 259 } asm330lhb_fifo_ctrl4_t; 260 261 #define ASM330LHB_COUNTER_BDR_REG1 0x0BU 262 typedef struct 263 { 264 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 265 uint8_t cnt_bdr_th : 3; 266 uint8_t not_used_01 : 2; 267 uint8_t trig_counter_bdr : 1; 268 uint8_t rst_counter_bdr : 1; 269 uint8_t dataready_pulsed : 1; 270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 271 uint8_t dataready_pulsed : 1; 272 uint8_t rst_counter_bdr : 1; 273 uint8_t trig_counter_bdr : 1; 274 uint8_t not_used_01 : 2; 275 uint8_t cnt_bdr_th : 3; 276 #endif /* DRV_BYTE_ORDER */ 277 } asm330lhb_counter_bdr_reg1_t; 278 279 #define ASM330LHB_COUNTER_BDR_REG2 0x0CU 280 typedef struct 281 { 282 uint8_t cnt_bdr_th : 8; 283 } asm330lhb_counter_bdr_reg2_t; 284 285 #define ASM330LHB_INT1_CTRL 0x0DU 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t int1_drdy_xl : 1; 290 uint8_t int1_drdy_g : 1; 291 uint8_t int1_boot : 1; 292 uint8_t int1_fifo_th : 1; 293 uint8_t int1_fifo_ovr : 1; 294 uint8_t int1_fifo_full : 1; 295 uint8_t int1_cnt_bdr : 1; 296 uint8_t den_drdy_flag : 1; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t den_drdy_flag : 1; 299 uint8_t int1_cnt_bdr : 1; 300 uint8_t int1_fifo_full : 1; 301 uint8_t int1_fifo_ovr : 1; 302 uint8_t int1_fifo_th : 1; 303 uint8_t int1_boot : 1; 304 uint8_t int1_drdy_g : 1; 305 uint8_t int1_drdy_xl : 1; 306 #endif /* DRV_BYTE_ORDER */ 307 } asm330lhb_int1_ctrl_t; 308 309 #define ASM330LHB_INT2_CTRL 0x0EU 310 typedef struct 311 { 312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 313 uint8_t int2_drdy_xl : 1; 314 uint8_t int2_drdy_g : 1; 315 uint8_t int2_drdy_temp : 1; 316 uint8_t int2_fifo_th : 1; 317 uint8_t int2_fifo_ovr : 1; 318 uint8_t int2_fifo_full : 1; 319 uint8_t int2_cnt_bdr : 1; 320 uint8_t not_used_01 : 1; 321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 322 uint8_t not_used_01 : 1; 323 uint8_t int2_cnt_bdr : 1; 324 uint8_t int2_fifo_full : 1; 325 uint8_t int2_fifo_ovr : 1; 326 uint8_t int2_fifo_th : 1; 327 uint8_t int2_drdy_temp : 1; 328 uint8_t int2_drdy_g : 1; 329 uint8_t int2_drdy_xl : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } asm330lhb_int2_ctrl_t; 332 333 #define ASM330LHB_WHO_AM_I 0x0FU 334 335 #define ASM330LHB_CTRL1_XL 0x10U 336 typedef struct 337 { 338 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 339 uint8_t not_used_01 : 1; 340 uint8_t lpf2_xl_en : 1; 341 uint8_t fs_xl : 2; 342 uint8_t odr_xl : 4; 343 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 344 uint8_t odr_xl : 4; 345 uint8_t fs_xl : 2; 346 uint8_t lpf2_xl_en : 1; 347 uint8_t not_used_01 : 1; 348 #endif /* DRV_BYTE_ORDER */ 349 } asm330lhb_ctrl1_xl_t; 350 351 #define ASM330LHB_CTRL2_G 0x11U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 356 uint8_t odr_g : 4; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t odr_g : 4; 359 uint8_t fs_g : 4; /* fs_4000 + fs_125 + fs_g */ 360 #endif /* DRV_BYTE_ORDER */ 361 } asm330lhb_ctrl2_g_t; 362 363 #define ASM330LHB_CTRL3_C 0x12U 364 typedef struct 365 { 366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 367 uint8_t sw_reset : 1; 368 uint8_t not_used_01 : 1; 369 uint8_t if_inc : 1; 370 uint8_t sim : 1; 371 uint8_t pp_od : 1; 372 uint8_t h_lactive : 1; 373 uint8_t bdu : 1; 374 uint8_t boot : 1; 375 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 376 uint8_t boot : 1; 377 uint8_t bdu : 1; 378 uint8_t h_lactive : 1; 379 uint8_t pp_od : 1; 380 uint8_t sim : 1; 381 uint8_t if_inc : 1; 382 uint8_t not_used_01 : 1; 383 uint8_t sw_reset : 1; 384 #endif /* DRV_BYTE_ORDER */ 385 } asm330lhb_ctrl3_c_t; 386 387 #define ASM330LHB_CTRL4_C 0x13U 388 typedef struct 389 { 390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 391 uint8_t not_used_01 : 1; 392 uint8_t lpf1_sel_g : 1; 393 uint8_t i2c_disable : 1; 394 uint8_t drdy_mask : 1; 395 uint8_t not_used_02 : 1; 396 uint8_t int2_on_int1 : 1; 397 uint8_t sleep_g : 1; 398 uint8_t not_used_03 : 1; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t not_used_03 : 1; 401 uint8_t sleep_g : 1; 402 uint8_t int2_on_int1 : 1; 403 uint8_t not_used_02 : 1; 404 uint8_t drdy_mask : 1; 405 uint8_t i2c_disable : 1; 406 uint8_t lpf1_sel_g : 1; 407 uint8_t not_used_01 : 1; 408 #endif /* DRV_BYTE_ORDER */ 409 } asm330lhb_ctrl4_c_t; 410 411 #define ASM330LHB_CTRL5_C 0x14U 412 typedef struct 413 { 414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 415 uint8_t st_xl : 2; 416 uint8_t st_g : 2; 417 uint8_t not_used_01 : 1; 418 uint8_t rounding : 2; 419 uint8_t not_used_02 : 1; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t not_used_02 : 1; 422 uint8_t rounding : 2; 423 uint8_t not_used_01 : 1; 424 uint8_t st_g : 2; 425 uint8_t st_xl : 2; 426 #endif /* DRV_BYTE_ORDER */ 427 } asm330lhb_ctrl5_c_t; 428 429 #define ASM330LHB_CTRL6_C 0x15U 430 typedef struct 431 { 432 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 433 uint8_t ftype : 3; 434 uint8_t usr_off_w : 1; 435 uint8_t xl_hm_mode : 1; 436 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 438 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 439 uint8_t xl_hm_mode : 1; 440 uint8_t usr_off_w : 1; 441 uint8_t ftype : 3; 442 #endif /* DRV_BYTE_ORDER */ 443 } asm330lhb_ctrl6_c_t; 444 445 #define ASM330LHB_CTRL7_G 0x16U 446 typedef struct 447 { 448 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 449 uint8_t not_used_00 : 1; 450 uint8_t usr_off_on_out : 1; 451 uint8_t not_used_01 : 2; 452 uint8_t hpm_g : 2; 453 uint8_t hp_en_g : 1; 454 uint8_t g_hm_mode : 1; 455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 456 uint8_t g_hm_mode : 1; 457 uint8_t hp_en_g : 1; 458 uint8_t hpm_g : 2; 459 uint8_t not_used_01 : 2; 460 uint8_t usr_off_on_out : 1; 461 uint8_t not_used_00 : 1; 462 #endif /* DRV_BYTE_ORDER */ 463 } asm330lhb_ctrl7_g_t; 464 465 #define ASM330LHB_CTRL8_XL 0x17U 466 typedef struct 467 { 468 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 469 uint8_t low_pass_on_6d : 1; 470 uint8_t not_used_01 : 1; 471 uint8_t hp_slope_xl_en : 1; 472 uint8_t fastsettl_mode_xl : 1; 473 uint8_t hp_ref_mode_xl : 1; 474 uint8_t hpcf_xl : 3; 475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 476 uint8_t hpcf_xl : 3; 477 uint8_t hp_ref_mode_xl : 1; 478 uint8_t fastsettl_mode_xl : 1; 479 uint8_t hp_slope_xl_en : 1; 480 uint8_t not_used_01 : 1; 481 uint8_t low_pass_on_6d : 1; 482 #endif /* DRV_BYTE_ORDER */ 483 } asm330lhb_ctrl8_xl_t; 484 485 #define ASM330LHB_CTRL9_XL 0x18U 486 typedef struct 487 { 488 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 489 uint8_t not_used_01 : 1; 490 uint8_t i3c_disable : 1; 491 uint8_t den_lh : 1; 492 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 493 uint8_t den_z : 1; 494 uint8_t den_y : 1; 495 uint8_t den_x : 1; 496 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 497 uint8_t den_x : 1; 498 uint8_t den_y : 1; 499 uint8_t den_z : 1; 500 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 501 uint8_t den_lh : 1; 502 uint8_t i3c_disable : 1; 503 uint8_t not_used_01 : 1; 504 #endif /* DRV_BYTE_ORDER */ 505 } asm330lhb_ctrl9_xl_t; 506 507 #define ASM330LHB_CTRL10_C 0x19U 508 typedef struct 509 { 510 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 511 uint8_t not_used_01 : 5; 512 uint8_t timestamp_en : 1; 513 uint8_t not_used_02 : 2; 514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 515 uint8_t not_used_02 : 2; 516 uint8_t timestamp_en : 1; 517 uint8_t not_used_01 : 5; 518 #endif /* DRV_BYTE_ORDER */ 519 } asm330lhb_ctrl10_c_t; 520 521 #define ASM330LHB_ALL_INT_SRC 0x1AU 522 typedef struct 523 { 524 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 525 uint8_t ff_ia : 1; 526 uint8_t wu_ia : 1; 527 uint8_t not_used_00 : 2; 528 uint8_t d6d_ia : 1; 529 uint8_t sleep_change_ia : 1; 530 uint8_t not_used_01 : 1; 531 uint8_t timestamp_endcount : 1; 532 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 533 uint8_t timestamp_endcount : 1; 534 uint8_t not_used_01 : 1; 535 uint8_t sleep_change_ia : 1; 536 uint8_t d6d_ia : 1; 537 uint8_t not_used_00 : 2; 538 uint8_t wu_ia : 1; 539 uint8_t ff_ia : 1; 540 #endif /* DRV_BYTE_ORDER */ 541 } asm330lhb_all_int_src_t; 542 543 #define ASM330LHB_WAKE_UP_SRC 0x1BU 544 typedef struct 545 { 546 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 547 uint8_t z_wu : 1; 548 uint8_t y_wu : 1; 549 uint8_t x_wu : 1; 550 uint8_t wu_ia : 1; 551 uint8_t sleep_state : 1; 552 uint8_t ff_ia : 1; 553 uint8_t sleep_change_ia : 1; 554 uint8_t not_used_01 : 1; 555 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 556 uint8_t not_used_01 : 1; 557 uint8_t sleep_change_ia : 1; 558 uint8_t ff_ia : 1; 559 uint8_t sleep_state : 1; 560 uint8_t wu_ia : 1; 561 uint8_t x_wu : 1; 562 uint8_t y_wu : 1; 563 uint8_t z_wu : 1; 564 #endif /* DRV_BYTE_ORDER */ 565 } asm330lhb_wake_up_src_t; 566 567 #define ASM330LHB_D6D_SRC 0x1DU 568 typedef struct 569 { 570 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 571 uint8_t xl : 1; 572 uint8_t xh : 1; 573 uint8_t yl : 1; 574 uint8_t yh : 1; 575 uint8_t zl : 1; 576 uint8_t zh : 1; 577 uint8_t d6d_ia : 1; 578 uint8_t den_drdy : 1; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t den_drdy : 1; 581 uint8_t d6d_ia : 1; 582 uint8_t zh : 1; 583 uint8_t zl : 1; 584 uint8_t yh : 1; 585 uint8_t yl : 1; 586 uint8_t xh : 1; 587 uint8_t xl : 1; 588 #endif /* DRV_BYTE_ORDER */ 589 } asm330lhb_d6d_src_t; 590 591 #define ASM330LHB_STATUS_REG 0x1EU 592 typedef struct 593 { 594 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 595 uint8_t xlda : 1; 596 uint8_t gda : 1; 597 uint8_t tda : 1; 598 uint8_t boot_check_fail : 1; 599 uint8_t not_used_01 : 4; 600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 601 uint8_t not_used_01 : 4; 602 uint8_t boot_check_fail : 1; 603 uint8_t tda : 1; 604 uint8_t gda : 1; 605 uint8_t xlda : 1; 606 #endif /* DRV_BYTE_ORDER */ 607 } asm330lhb_status_reg_t; 608 609 #define ASM330LHB_OUT_TEMP_L 0x20U 610 #define ASM330LHB_OUT_TEMP_H 0x21U 611 #define ASM330LHB_OUTX_L_G 0x22U 612 #define ASM330LHB_OUTX_H_G 0x23U 613 #define ASM330LHB_OUTY_L_G 0x24U 614 #define ASM330LHB_OUTY_H_G 0x25U 615 #define ASM330LHB_OUTZ_L_G 0x26U 616 #define ASM330LHB_OUTZ_H_G 0x27U 617 #define ASM330LHB_OUTX_L_A 0x28U 618 #define ASM330LHB_OUTX_H_A 0x29U 619 #define ASM330LHB_OUTY_L_A 0x2AU 620 #define ASM330LHB_OUTY_H_A 0x2BU 621 #define ASM330LHB_OUTZ_L_A 0x2CU 622 #define ASM330LHB_OUTZ_H_A 0x2DU 623 #define ASM330LHB_EMB_FUNC_STATUS_MAINPAGE 0x35U 624 typedef struct 625 { 626 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 627 uint8_t not_used_01 : 7; 628 uint8_t is_fsm_lc : 1; 629 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 630 uint8_t is_fsm_lc : 1; 631 uint8_t not_used_01 : 7; 632 #endif /* DRV_BYTE_ORDER */ 633 } asm330lhb_emb_func_status_mainpage_t; 634 635 #define ASM330LHB_FSM_STATUS_A_MAINPAGE 0x36U 636 typedef struct 637 { 638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 639 uint8_t is_fsm1 : 1; 640 uint8_t is_fsm2 : 1; 641 uint8_t is_fsm3 : 1; 642 uint8_t is_fsm4 : 1; 643 uint8_t is_fsm5 : 1; 644 uint8_t is_fsm6 : 1; 645 uint8_t is_fsm7 : 1; 646 uint8_t is_fsm8 : 1; 647 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 648 uint8_t is_fsm8 : 1; 649 uint8_t is_fsm7 : 1; 650 uint8_t is_fsm6 : 1; 651 uint8_t is_fsm5 : 1; 652 uint8_t is_fsm4 : 1; 653 uint8_t is_fsm3 : 1; 654 uint8_t is_fsm2 : 1; 655 uint8_t is_fsm1 : 1; 656 #endif /* DRV_BYTE_ORDER */ 657 } asm330lhb_fsm_status_a_mainpage_t; 658 659 #define ASM330LHB_FSM_STATUS_B_MAINPAGE 0x37U 660 typedef struct 661 { 662 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 663 uint8_t is_fsm9 : 1; 664 uint8_t is_fsm10 : 1; 665 uint8_t is_fsm11 : 1; 666 uint8_t is_fsm12 : 1; 667 uint8_t is_fsm13 : 1; 668 uint8_t is_fsm14 : 1; 669 uint8_t is_fsm15 : 1; 670 uint8_t is_fsm16 : 1; 671 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 672 uint8_t is_fsm16 : 1; 673 uint8_t is_fsm15 : 1; 674 uint8_t is_fsm14 : 1; 675 uint8_t is_fsm13 : 1; 676 uint8_t is_fsm12 : 1; 677 uint8_t is_fsm11 : 1; 678 uint8_t is_fsm10 : 1; 679 uint8_t is_fsm9 : 1; 680 #endif /* DRV_BYTE_ORDER */ 681 } asm330lhb_fsm_status_b_mainpage_t; 682 683 #define ASM330LHB_MLC_STATUS_MAINPAGE 0x38U 684 typedef struct 685 { 686 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 687 uint8_t is_mlc1 : 1; 688 uint8_t is_mlc2 : 1; 689 uint8_t is_mlc3 : 1; 690 uint8_t is_mlc4 : 1; 691 uint8_t is_mlc5 : 1; 692 uint8_t is_mlc6 : 1; 693 uint8_t is_mlc7 : 1; 694 uint8_t is_mlc8 : 1; 695 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 696 uint8_t is_mlc8 : 1; 697 uint8_t is_mlc7 : 1; 698 uint8_t is_mlc6 : 1; 699 uint8_t is_mlc5 : 1; 700 uint8_t is_mlc4 : 1; 701 uint8_t is_mlc3 : 1; 702 uint8_t is_mlc2 : 1; 703 uint8_t is_mlc1 : 1; 704 #endif /* DRV_BYTE_ORDER */ 705 } asm330lhb_mlc_status_mainpage_t; 706 707 #define ASM330LHB_FIFO_STATUS1 0x3AU 708 typedef struct 709 { 710 uint8_t diff_fifo : 8; 711 } asm330lhb_fifo_status1_t; 712 713 #define ASM330LHB_FIFO_STATUS2 0x3BU 714 typedef struct 715 { 716 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 717 uint8_t diff_fifo : 2; 718 uint8_t not_used_01 : 1; 719 uint8_t over_run_latched : 1; 720 uint8_t counter_bdr_ia : 1; 721 uint8_t fifo_full_ia : 1; 722 uint8_t fifo_ovr_ia : 1; 723 uint8_t fifo_wtm_ia : 1; 724 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 725 uint8_t fifo_wtm_ia : 1; 726 uint8_t fifo_ovr_ia : 1; 727 uint8_t fifo_full_ia : 1; 728 uint8_t counter_bdr_ia : 1; 729 uint8_t over_run_latched : 1; 730 uint8_t not_used_01 : 1; 731 uint8_t diff_fifo : 2; 732 #endif /* DRV_BYTE_ORDER */ 733 } asm330lhb_fifo_status2_t; 734 735 #define ASM330LHB_TIMESTAMP0 0x40U 736 #define ASM330LHB_TIMESTAMP1 0x41U 737 #define ASM330LHB_TIMESTAMP2 0x42U 738 #define ASM330LHB_TIMESTAMP3 0x43U 739 #define ASM330LHB_INT_CFG0 0x56U 740 typedef struct 741 { 742 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 743 uint8_t lir : 1; 744 uint8_t not_used_01 : 3; 745 uint8_t slope_fds : 1; 746 uint8_t sleep_status_on_int : 1; 747 uint8_t int_clr_on_read : 1; 748 uint8_t not_used_02 : 1; 749 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 750 uint8_t not_used_02 : 1; 751 uint8_t int_clr_on_read : 1; 752 uint8_t sleep_status_on_int : 1; 753 uint8_t slope_fds : 1; 754 uint8_t not_used_01 : 3; 755 uint8_t lir : 1; 756 #endif /* DRV_BYTE_ORDER */ 757 } asm330lhb_int_cfg0_t; 758 759 #define ASM330LHB_INT_CFG1 0x58U 760 typedef struct 761 { 762 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 763 uint8_t not_used_01 : 5; 764 uint8_t inact_en : 2; 765 uint8_t interrupts_enable : 1; 766 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 767 uint8_t interrupts_enable : 1; 768 uint8_t inact_en : 2; 769 uint8_t not_used_01 : 5; 770 #endif /* DRV_BYTE_ORDER */ 771 } asm330lhb_int_cfg1_t; 772 773 #define ASM330LHB_THS_6D 0x59U 774 typedef struct 775 { 776 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 777 uint8_t not_used_01 : 5; 778 uint8_t sixd_ths : 2; 779 uint8_t d4d_en : 1; 780 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 781 uint8_t d4d_en : 1; 782 uint8_t sixd_ths : 2; 783 uint8_t not_used_01 : 5; 784 #endif /* DRV_BYTE_ORDER */ 785 } asm330lhb_ths_6d_t; 786 787 #define ASM330LHB_WAKE_UP_THS 0x5BU 788 typedef struct 789 { 790 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 791 uint8_t wk_ths : 6; 792 uint8_t usr_off_on_wu : 1; 793 uint8_t not_used_01 : 1; 794 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 795 uint8_t not_used_01 : 1; 796 uint8_t usr_off_on_wu : 1; 797 uint8_t wk_ths : 6; 798 #endif /* DRV_BYTE_ORDER */ 799 } asm330lhb_wake_up_ths_t; 800 801 #define ASM330LHB_WAKE_UP_DUR 0x5CU 802 typedef struct 803 { 804 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 805 uint8_t sleep_dur : 4; 806 uint8_t wake_ths_w : 1; 807 uint8_t wake_dur : 2; 808 uint8_t ff_dur : 1; 809 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 810 uint8_t ff_dur : 1; 811 uint8_t wake_dur : 2; 812 uint8_t wake_ths_w : 1; 813 uint8_t sleep_dur : 4; 814 #endif /* DRV_BYTE_ORDER */ 815 } asm330lhb_wake_up_dur_t; 816 817 #define ASM330LHB_FREE_FALL 0x5DU 818 typedef struct 819 { 820 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 821 uint8_t ff_ths : 3; 822 uint8_t ff_dur : 5; 823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 824 uint8_t ff_dur : 5; 825 uint8_t ff_ths : 3; 826 #endif /* DRV_BYTE_ORDER */ 827 } asm330lhb_free_fall_t; 828 829 #define ASM330LHB_MD1_CFG 0x5EU 830 typedef struct 831 { 832 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 833 uint8_t not_used_00 : 1; 834 uint8_t int1_emb_func : 1; 835 uint8_t int1_6d : 1; 836 uint8_t not_used_01 : 1; 837 uint8_t int1_ff : 1; 838 uint8_t int1_wu : 1; 839 uint8_t not_used_02 : 1; 840 uint8_t int1_sleep_change : 1; 841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 842 uint8_t int1_sleep_change : 1; 843 uint8_t not_used_02 : 1; 844 uint8_t int1_wu : 1; 845 uint8_t int1_ff : 1; 846 uint8_t not_used_01 : 1; 847 uint8_t int1_6d : 1; 848 uint8_t int1_emb_func : 1; 849 uint8_t not_used_00 : 1; 850 #endif /* DRV_BYTE_ORDER */ 851 } asm330lhb_md1_cfg_t; 852 853 #define ASM330LHB_MD2_CFG 0x5FU 854 typedef struct 855 { 856 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 857 uint8_t int2_timestamp : 1; 858 uint8_t int2_emb_func : 1; 859 uint8_t int2_6d : 1; 860 uint8_t not_used_01 : 1; 861 uint8_t int2_ff : 1; 862 uint8_t int2_wu : 1; 863 uint8_t not_used_02 : 1; 864 uint8_t int2_sleep_change : 1; 865 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 866 uint8_t int2_sleep_change : 1; 867 uint8_t not_used_02 : 1; 868 uint8_t int2_wu : 1; 869 uint8_t int2_ff : 1; 870 uint8_t not_used_01 : 1; 871 uint8_t int2_6d : 1; 872 uint8_t int2_emb_func : 1; 873 uint8_t int2_timestamp : 1; 874 #endif /* DRV_BYTE_ORDER */ 875 } asm330lhb_md2_cfg_t; 876 877 #define ASM330LHB_I3C_BUS_AVB 0x62U 878 typedef struct 879 { 880 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 881 uint8_t pd_dis_int1 : 1; 882 uint8_t not_used_01 : 2; 883 uint8_t i3c_bus_avb_sel : 2; 884 uint8_t not_used_02 : 3; 885 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 886 uint8_t not_used_02 : 3; 887 uint8_t i3c_bus_avb_sel : 2; 888 uint8_t not_used_01 : 2; 889 uint8_t pd_dis_int1 : 1; 890 #endif /* DRV_BYTE_ORDER */ 891 } asm330lhb_i3c_bus_avb_t; 892 893 #define ASM330LHB_INTERNAL_FREQ_FINE 0x63U 894 typedef struct 895 { 896 uint8_t freq_fine : 8; 897 } asm330lhb_internal_freq_fine_t; 898 899 #define ASM330LHB_X_OFS_USR 0x73U 900 #define ASM330LHB_Y_OFS_USR 0x74U 901 #define ASM330LHB_Z_OFS_USR 0x75U 902 #define ASM330LHB_FIFO_DATA_OUT_TAG 0x78U 903 typedef struct 904 { 905 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 906 uint8_t tag_parity : 1; 907 uint8_t tag_cnt : 2; 908 uint8_t tag_sensor : 5; 909 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 910 uint8_t tag_sensor : 5; 911 uint8_t tag_cnt : 2; 912 uint8_t tag_parity : 1; 913 #endif /* DRV_BYTE_ORDER */ 914 } asm330lhb_fifo_data_out_tag_t; 915 916 #define ASM330LHB_FIFO_DATA_OUT_X_L 0x79U 917 #define ASM330LHB_FIFO_DATA_OUT_X_H 0x7AU 918 #define ASM330LHB_FIFO_DATA_OUT_Y_L 0x7BU 919 #define ASM330LHB_FIFO_DATA_OUT_Y_H 0x7CU 920 #define ASM330LHB_FIFO_DATA_OUT_Z_L 0x7DU 921 #define ASM330LHB_FIFO_DATA_OUT_Z_H 0x7EU 922 923 #define ASM330LHB_PAGE_SEL 0x02U 924 typedef struct 925 { 926 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 927 uint8_t not_used_01 : 1; 928 uint8_t emb_func_clk_dis : 1; 929 uint8_t not_used_02 : 2; 930 uint8_t page_sel : 4; 931 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 932 uint8_t page_sel : 4; 933 uint8_t not_used_02 : 2; 934 uint8_t emb_func_clk_dis : 1; 935 uint8_t not_used_01 : 1; 936 #endif /* DRV_BYTE_ORDER */ 937 } asm330lhb_page_sel_t; 938 939 #define ASM330LHB_EMB_FUNC_EN_B 0x05U 940 typedef struct 941 { 942 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 943 uint8_t fsm_en : 1; 944 uint8_t not_used_01 : 3; 945 uint8_t mlc_en : 1; 946 uint8_t not_used_02 : 3; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t not_used_02 : 3; 949 uint8_t mlc_en : 1; 950 uint8_t not_used_01 : 3; 951 uint8_t fsm_en : 1; 952 #endif /* DRV_BYTE_ORDER */ 953 } asm330lhb_emb_func_en_b_t; 954 955 #define ASM330LHB_PAGE_ADDRESS 0x08U 956 typedef struct 957 { 958 uint8_t page_addr : 8; 959 } asm330lhb_page_address_t; 960 961 #define ASM330LHB_PAGE_VALUE 0x09U 962 typedef struct 963 { 964 uint8_t page_value : 8; 965 } asm330lhb_page_value_t; 966 967 #define ASM330LHB_EMB_FUNC_INT1 0x0AU 968 typedef struct 969 { 970 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 971 uint8_t not_used_01 : 7; 972 uint8_t int1_fsm_lc : 1; 973 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 974 uint8_t int1_fsm_lc : 1; 975 uint8_t not_used_01 : 7; 976 #endif /* DRV_BYTE_ORDER */ 977 } asm330lhb_emb_func_int1_t; 978 979 #define ASM330LHB_FSM_INT1_A 0x0BU 980 typedef struct 981 { 982 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 983 uint8_t int1_fsm1 : 1; 984 uint8_t int1_fsm2 : 1; 985 uint8_t int1_fsm3 : 1; 986 uint8_t int1_fsm4 : 1; 987 uint8_t int1_fsm5 : 1; 988 uint8_t int1_fsm6 : 1; 989 uint8_t int1_fsm7 : 1; 990 uint8_t int1_fsm8 : 1; 991 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 992 uint8_t int1_fsm8 : 1; 993 uint8_t int1_fsm7 : 1; 994 uint8_t int1_fsm6 : 1; 995 uint8_t int1_fsm5 : 1; 996 uint8_t int1_fsm4 : 1; 997 uint8_t int1_fsm3 : 1; 998 uint8_t int1_fsm2 : 1; 999 uint8_t int1_fsm1 : 1; 1000 #endif /* DRV_BYTE_ORDER */ 1001 } asm330lhb_fsm_int1_a_t; 1002 1003 #define ASM330LHB_FSM_INT1_B 0x0CU 1004 typedef struct 1005 { 1006 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1007 uint8_t int1_fsm9 : 1; 1008 uint8_t int1_fsm10 : 1; 1009 uint8_t int1_fsm11 : 1; 1010 uint8_t int1_fsm12 : 1; 1011 uint8_t int1_fsm13 : 1; 1012 uint8_t int1_fsm14 : 1; 1013 uint8_t int1_fsm15 : 1; 1014 uint8_t int1_fsm16 : 1; 1015 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1016 uint8_t int1_fsm16 : 1; 1017 uint8_t int1_fsm15 : 1; 1018 uint8_t int1_fsm14 : 1; 1019 uint8_t int1_fsm13 : 1; 1020 uint8_t int1_fsm12 : 1; 1021 uint8_t int1_fsm11 : 1; 1022 uint8_t int1_fsm10 : 1; 1023 uint8_t int1_fsm9 : 1; 1024 #endif /* DRV_BYTE_ORDER */ 1025 } asm330lhb_fsm_int1_b_t; 1026 1027 #define ASM330LHB_MLC_INT1 0x0DU 1028 typedef struct 1029 { 1030 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1031 uint8_t int1_mlc1 : 1; 1032 uint8_t int1_mlc2 : 1; 1033 uint8_t int1_mlc3 : 1; 1034 uint8_t int1_mlc4 : 1; 1035 uint8_t int1_mlc5 : 1; 1036 uint8_t int1_mlc6 : 1; 1037 uint8_t int1_mlc7 : 1; 1038 uint8_t int1_mlc8 : 1; 1039 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1040 uint8_t int1_mlc8 : 1; 1041 uint8_t int1_mlc7 : 1; 1042 uint8_t int1_mlc6 : 1; 1043 uint8_t int1_mlc5 : 1; 1044 uint8_t int1_mlc4 : 1; 1045 uint8_t int1_mlc3 : 1; 1046 uint8_t int1_mlc2 : 1; 1047 uint8_t int1_mlc1 : 1; 1048 #endif /* DRV_BYTE_ORDER */ 1049 } asm330lhb_mlc_int1_t; 1050 1051 #define ASM330LHB_EMB_FUNC_INT2 0x0EU 1052 typedef struct 1053 { 1054 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1055 uint8_t not_used_01 : 7; 1056 uint8_t int2_fsm_lc : 1; 1057 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1058 uint8_t int2_fsm_lc : 1; 1059 uint8_t not_used_01 : 7; 1060 #endif /* DRV_BYTE_ORDER */ 1061 } asm330lhb_emb_func_int2_t; 1062 1063 #define ASM330LHB_FSM_INT2_A 0x0FU 1064 typedef struct 1065 { 1066 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1067 uint8_t int2_fsm1 : 1; 1068 uint8_t int2_fsm2 : 1; 1069 uint8_t int2_fsm3 : 1; 1070 uint8_t int2_fsm4 : 1; 1071 uint8_t int2_fsm5 : 1; 1072 uint8_t int2_fsm6 : 1; 1073 uint8_t int2_fsm7 : 1; 1074 uint8_t int2_fsm8 : 1; 1075 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1076 uint8_t int2_fsm8 : 1; 1077 uint8_t int2_fsm7 : 1; 1078 uint8_t int2_fsm6 : 1; 1079 uint8_t int2_fsm5 : 1; 1080 uint8_t int2_fsm4 : 1; 1081 uint8_t int2_fsm3 : 1; 1082 uint8_t int2_fsm2 : 1; 1083 uint8_t int2_fsm1 : 1; 1084 #endif /* DRV_BYTE_ORDER */ 1085 } asm330lhb_fsm_int2_a_t; 1086 1087 #define ASM330LHB_FSM_INT2_B 0x10U 1088 typedef struct 1089 { 1090 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1091 uint8_t int2_fsm9 : 1; 1092 uint8_t int2_fsm10 : 1; 1093 uint8_t int2_fsm11 : 1; 1094 uint8_t int2_fsm12 : 1; 1095 uint8_t int2_fsm13 : 1; 1096 uint8_t int2_fsm14 : 1; 1097 uint8_t int2_fsm15 : 1; 1098 uint8_t int2_fsm16 : 1; 1099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1100 uint8_t int2_fsm16 : 1; 1101 uint8_t int2_fsm15 : 1; 1102 uint8_t int2_fsm14 : 1; 1103 uint8_t int2_fsm13 : 1; 1104 uint8_t int2_fsm12 : 1; 1105 uint8_t int2_fsm11 : 1; 1106 uint8_t int2_fsm10 : 1; 1107 uint8_t int2_fsm9 : 1; 1108 #endif /* DRV_BYTE_ORDER */ 1109 } asm330lhb_fsm_int2_b_t; 1110 1111 #define ASM330LHB_MLC_INT2 0x11U 1112 typedef struct 1113 { 1114 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1115 uint8_t int2_mlc1 : 1; 1116 uint8_t int2_mlc2 : 1; 1117 uint8_t int2_mlc3 : 1; 1118 uint8_t int2_mlc4 : 1; 1119 uint8_t int2_mlc5 : 1; 1120 uint8_t int2_mlc6 : 1; 1121 uint8_t int2_mlc7 : 1; 1122 uint8_t int2_mlc8 : 1; 1123 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1124 uint8_t int2_mlc8 : 1; 1125 uint8_t int2_mlc7 : 1; 1126 uint8_t int2_mlc6 : 1; 1127 uint8_t int2_mlc5 : 1; 1128 uint8_t int2_mlc4 : 1; 1129 uint8_t int2_mlc3 : 1; 1130 uint8_t int2_mlc2 : 1; 1131 uint8_t int2_mlc1 : 1; 1132 #endif /* DRV_BYTE_ORDER */ 1133 } asm330lhb_mlc_int2_t; 1134 1135 #define ASM330LHB_EMB_FUNC_STATUS 0x12U 1136 typedef struct 1137 { 1138 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1139 uint8_t not_used_01 : 7; 1140 uint8_t is_fsm_lc : 1; 1141 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1142 uint8_t is_fsm_lc : 1; 1143 uint8_t not_used_01 : 7; 1144 #endif /* DRV_BYTE_ORDER */ 1145 } asm330lhb_emb_func_status_t; 1146 1147 #define ASM330LHB_FSM_STATUS_A 0x13U 1148 typedef struct 1149 { 1150 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1151 uint8_t is_fsm1 : 1; 1152 uint8_t is_fsm2 : 1; 1153 uint8_t is_fsm3 : 1; 1154 uint8_t is_fsm4 : 1; 1155 uint8_t is_fsm5 : 1; 1156 uint8_t is_fsm6 : 1; 1157 uint8_t is_fsm7 : 1; 1158 uint8_t is_fsm8 : 1; 1159 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1160 uint8_t is_fsm8 : 1; 1161 uint8_t is_fsm7 : 1; 1162 uint8_t is_fsm6 : 1; 1163 uint8_t is_fsm5 : 1; 1164 uint8_t is_fsm4 : 1; 1165 uint8_t is_fsm3 : 1; 1166 uint8_t is_fsm2 : 1; 1167 uint8_t is_fsm1 : 1; 1168 #endif /* DRV_BYTE_ORDER */ 1169 } asm330lhb_fsm_status_a_t; 1170 1171 #define ASM330LHB_FSM_STATUS_B 0x14U 1172 typedef struct 1173 { 1174 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1175 uint8_t is_fsm9 : 1; 1176 uint8_t is_fsm10 : 1; 1177 uint8_t is_fsm11 : 1; 1178 uint8_t is_fsm12 : 1; 1179 uint8_t is_fsm13 : 1; 1180 uint8_t is_fsm14 : 1; 1181 uint8_t is_fsm15 : 1; 1182 uint8_t is_fsm16 : 1; 1183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1184 uint8_t is_fsm16 : 1; 1185 uint8_t is_fsm15 : 1; 1186 uint8_t is_fsm14 : 1; 1187 uint8_t is_fsm13 : 1; 1188 uint8_t is_fsm12 : 1; 1189 uint8_t is_fsm11 : 1; 1190 uint8_t is_fsm10 : 1; 1191 uint8_t is_fsm9 : 1; 1192 #endif /* DRV_BYTE_ORDER */ 1193 } asm330lhb_fsm_status_b_t; 1194 1195 #define ASM330LHB_MLC_STATUS 0x15U 1196 typedef struct 1197 { 1198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1199 uint8_t is_mlc1 : 1; 1200 uint8_t is_mlc2 : 1; 1201 uint8_t is_mlc3 : 1; 1202 uint8_t is_mlc4 : 1; 1203 uint8_t is_mlc5 : 1; 1204 uint8_t is_mlc6 : 1; 1205 uint8_t is_mlc7 : 1; 1206 uint8_t is_mlc8 : 1; 1207 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1208 uint8_t is_mlc8 : 1; 1209 uint8_t is_mlc7 : 1; 1210 uint8_t is_mlc6 : 1; 1211 uint8_t is_mlc5 : 1; 1212 uint8_t is_mlc4 : 1; 1213 uint8_t is_mlc3 : 1; 1214 uint8_t is_mlc2 : 1; 1215 uint8_t is_mlc1 : 1; 1216 #endif /* DRV_BYTE_ORDER */ 1217 } asm330lhb_mlc_status_t; 1218 1219 #define ASM330LHB_PAGE_RW 0x17U 1220 typedef struct 1221 { 1222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1223 uint8_t not_used_01 : 5; 1224 uint8_t page_rw : 2; /* page_write + page_read */ 1225 uint8_t emb_func_lir : 1; 1226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1227 uint8_t emb_func_lir : 1; 1228 uint8_t page_rw : 2; /* page_write + page_read */ 1229 uint8_t not_used_01 : 5; 1230 #endif /* DRV_BYTE_ORDER */ 1231 } asm330lhb_page_rw_t; 1232 1233 #define ASM330LHB_FSM_ENABLE_A 0x46U 1234 typedef struct 1235 { 1236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1237 uint8_t fsm1_en : 1; 1238 uint8_t fsm2_en : 1; 1239 uint8_t fsm3_en : 1; 1240 uint8_t fsm4_en : 1; 1241 uint8_t fsm5_en : 1; 1242 uint8_t fsm6_en : 1; 1243 uint8_t fsm7_en : 1; 1244 uint8_t fsm8_en : 1; 1245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1246 uint8_t fsm8_en : 1; 1247 uint8_t fsm7_en : 1; 1248 uint8_t fsm6_en : 1; 1249 uint8_t fsm5_en : 1; 1250 uint8_t fsm4_en : 1; 1251 uint8_t fsm3_en : 1; 1252 uint8_t fsm2_en : 1; 1253 uint8_t fsm1_en : 1; 1254 #endif /* DRV_BYTE_ORDER */ 1255 } asm330lhb_fsm_enable_a_t; 1256 1257 #define ASM330LHB_FSM_ENABLE_B 0x47U 1258 typedef struct 1259 { 1260 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1261 uint8_t fsm9_en : 1; 1262 uint8_t fsm10_en : 1; 1263 uint8_t fsm11_en : 1; 1264 uint8_t fsm12_en : 1; 1265 uint8_t fsm13_en : 1; 1266 uint8_t fsm14_en : 1; 1267 uint8_t fsm15_en : 1; 1268 uint8_t fsm16_en : 1; 1269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1270 uint8_t fsm16_en : 1; 1271 uint8_t fsm15_en : 1; 1272 uint8_t fsm14_en : 1; 1273 uint8_t fsm13_en : 1; 1274 uint8_t fsm12_en : 1; 1275 uint8_t fsm11_en : 1; 1276 uint8_t fsm10_en : 1; 1277 uint8_t fsm9_en : 1; 1278 #endif /* DRV_BYTE_ORDER */ 1279 } asm330lhb_fsm_enable_b_t; 1280 1281 #define ASM330LHB_FSM_LONG_COUNTER_L 0x48U 1282 #define ASM330LHB_FSM_LONG_COUNTER_H 0x49U 1283 #define ASM330LHB_FSM_LONG_COUNTER_CLEAR 0x4AU 1284 typedef struct 1285 { 1286 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1287 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1288 uint8_t not_used_01 : 6; 1289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1290 uint8_t not_used_01 : 6; 1291 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 1292 #endif /* DRV_BYTE_ORDER */ 1293 } asm330lhb_fsm_long_counter_clear_t; 1294 1295 #define ASM330LHB_FSM_OUTS1 0x4CU 1296 typedef struct 1297 { 1298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1299 uint8_t n_v : 1; 1300 uint8_t p_v : 1; 1301 uint8_t n_z : 1; 1302 uint8_t p_z : 1; 1303 uint8_t n_y : 1; 1304 uint8_t p_y : 1; 1305 uint8_t n_x : 1; 1306 uint8_t p_x : 1; 1307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1308 uint8_t p_x : 1; 1309 uint8_t n_x : 1; 1310 uint8_t p_y : 1; 1311 uint8_t n_y : 1; 1312 uint8_t p_z : 1; 1313 uint8_t n_z : 1; 1314 uint8_t p_v : 1; 1315 uint8_t n_v : 1; 1316 #endif /* DRV_BYTE_ORDER */ 1317 } asm330lhb_fsm_outs1_t; 1318 1319 #define ASM330LHB_FSM_OUTS2 0x4DU 1320 typedef struct 1321 { 1322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1323 uint8_t n_v : 1; 1324 uint8_t p_v : 1; 1325 uint8_t n_z : 1; 1326 uint8_t p_z : 1; 1327 uint8_t n_y : 1; 1328 uint8_t p_y : 1; 1329 uint8_t n_x : 1; 1330 uint8_t p_x : 1; 1331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1332 uint8_t p_x : 1; 1333 uint8_t n_x : 1; 1334 uint8_t p_y : 1; 1335 uint8_t n_y : 1; 1336 uint8_t p_z : 1; 1337 uint8_t n_z : 1; 1338 uint8_t p_v : 1; 1339 uint8_t n_v : 1; 1340 #endif /* DRV_BYTE_ORDER */ 1341 } asm330lhb_fsm_outs2_t; 1342 1343 #define ASM330LHB_FSM_OUTS3 0x4EU 1344 typedef struct 1345 { 1346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1347 uint8_t n_v : 1; 1348 uint8_t p_v : 1; 1349 uint8_t n_z : 1; 1350 uint8_t p_z : 1; 1351 uint8_t n_y : 1; 1352 uint8_t p_y : 1; 1353 uint8_t n_x : 1; 1354 uint8_t p_x : 1; 1355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1356 uint8_t p_x : 1; 1357 uint8_t n_x : 1; 1358 uint8_t p_y : 1; 1359 uint8_t n_y : 1; 1360 uint8_t p_z : 1; 1361 uint8_t n_z : 1; 1362 uint8_t p_v : 1; 1363 uint8_t n_v : 1; 1364 #endif /* DRV_BYTE_ORDER */ 1365 } asm330lhb_fsm_outs3_t; 1366 1367 #define ASM330LHB_FSM_OUTS4 0x4FU 1368 typedef struct 1369 { 1370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1371 uint8_t n_v : 1; 1372 uint8_t p_v : 1; 1373 uint8_t n_z : 1; 1374 uint8_t p_z : 1; 1375 uint8_t n_y : 1; 1376 uint8_t p_y : 1; 1377 uint8_t n_x : 1; 1378 uint8_t p_x : 1; 1379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1380 uint8_t p_x : 1; 1381 uint8_t n_x : 1; 1382 uint8_t p_y : 1; 1383 uint8_t n_y : 1; 1384 uint8_t p_z : 1; 1385 uint8_t n_z : 1; 1386 uint8_t p_v : 1; 1387 uint8_t n_v : 1; 1388 #endif /* DRV_BYTE_ORDER */ 1389 } asm330lhb_fsm_outs4_t; 1390 1391 #define ASM330LHB_FSM_OUTS5 0x50U 1392 typedef struct 1393 { 1394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1395 uint8_t n_v : 1; 1396 uint8_t p_v : 1; 1397 uint8_t n_z : 1; 1398 uint8_t p_z : 1; 1399 uint8_t n_y : 1; 1400 uint8_t p_y : 1; 1401 uint8_t n_x : 1; 1402 uint8_t p_x : 1; 1403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1404 uint8_t p_x : 1; 1405 uint8_t n_x : 1; 1406 uint8_t p_y : 1; 1407 uint8_t n_y : 1; 1408 uint8_t p_z : 1; 1409 uint8_t n_z : 1; 1410 uint8_t p_v : 1; 1411 uint8_t n_v : 1; 1412 #endif /* DRV_BYTE_ORDER */ 1413 } asm330lhb_fsm_outs5_t; 1414 1415 #define ASM330LHB_FSM_OUTS6 0x51U 1416 typedef struct 1417 { 1418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1419 uint8_t n_v : 1; 1420 uint8_t p_v : 1; 1421 uint8_t n_z : 1; 1422 uint8_t p_z : 1; 1423 uint8_t n_y : 1; 1424 uint8_t p_y : 1; 1425 uint8_t n_x : 1; 1426 uint8_t p_x : 1; 1427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1428 uint8_t p_x : 1; 1429 uint8_t n_x : 1; 1430 uint8_t p_y : 1; 1431 uint8_t n_y : 1; 1432 uint8_t p_z : 1; 1433 uint8_t n_z : 1; 1434 uint8_t p_v : 1; 1435 uint8_t n_v : 1; 1436 #endif /* DRV_BYTE_ORDER */ 1437 } asm330lhb_fsm_outs6_t; 1438 1439 #define ASM330LHB_FSM_OUTS7 0x52U 1440 typedef struct 1441 { 1442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1443 uint8_t n_v : 1; 1444 uint8_t p_v : 1; 1445 uint8_t n_z : 1; 1446 uint8_t p_z : 1; 1447 uint8_t n_y : 1; 1448 uint8_t p_y : 1; 1449 uint8_t n_x : 1; 1450 uint8_t p_x : 1; 1451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1452 uint8_t p_x : 1; 1453 uint8_t n_x : 1; 1454 uint8_t p_y : 1; 1455 uint8_t n_y : 1; 1456 uint8_t p_z : 1; 1457 uint8_t n_z : 1; 1458 uint8_t p_v : 1; 1459 uint8_t n_v : 1; 1460 #endif /* DRV_BYTE_ORDER */ 1461 } asm330lhb_fsm_outs7_t; 1462 1463 #define ASM330LHB_FSM_OUTS8 0x53U 1464 typedef struct 1465 { 1466 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1467 uint8_t n_v : 1; 1468 uint8_t p_v : 1; 1469 uint8_t n_z : 1; 1470 uint8_t p_z : 1; 1471 uint8_t n_y : 1; 1472 uint8_t p_y : 1; 1473 uint8_t n_x : 1; 1474 uint8_t p_x : 1; 1475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1476 uint8_t p_x : 1; 1477 uint8_t n_x : 1; 1478 uint8_t p_y : 1; 1479 uint8_t n_y : 1; 1480 uint8_t p_z : 1; 1481 uint8_t n_z : 1; 1482 uint8_t p_v : 1; 1483 uint8_t n_v : 1; 1484 #endif /* DRV_BYTE_ORDER */ 1485 } asm330lhb_fsm_outs8_t; 1486 1487 #define ASM330LHB_FSM_OUTS9 0x54U 1488 typedef struct 1489 { 1490 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1491 uint8_t n_v : 1; 1492 uint8_t p_v : 1; 1493 uint8_t n_z : 1; 1494 uint8_t p_z : 1; 1495 uint8_t n_y : 1; 1496 uint8_t p_y : 1; 1497 uint8_t n_x : 1; 1498 uint8_t p_x : 1; 1499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1500 uint8_t p_x : 1; 1501 uint8_t n_x : 1; 1502 uint8_t p_y : 1; 1503 uint8_t n_y : 1; 1504 uint8_t p_z : 1; 1505 uint8_t n_z : 1; 1506 uint8_t p_v : 1; 1507 uint8_t n_v : 1; 1508 #endif /* DRV_BYTE_ORDER */ 1509 } asm330lhb_fsm_outs9_t; 1510 1511 #define ASM330LHB_FSM_OUTS10 0x55U 1512 typedef struct 1513 { 1514 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1515 uint8_t n_v : 1; 1516 uint8_t p_v : 1; 1517 uint8_t n_z : 1; 1518 uint8_t p_z : 1; 1519 uint8_t n_y : 1; 1520 uint8_t p_y : 1; 1521 uint8_t n_x : 1; 1522 uint8_t p_x : 1; 1523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1524 uint8_t p_x : 1; 1525 uint8_t n_x : 1; 1526 uint8_t p_y : 1; 1527 uint8_t n_y : 1; 1528 uint8_t p_z : 1; 1529 uint8_t n_z : 1; 1530 uint8_t p_v : 1; 1531 uint8_t n_v : 1; 1532 #endif /* DRV_BYTE_ORDER */ 1533 } asm330lhb_fsm_outs10_t; 1534 1535 #define ASM330LHB_FSM_OUTS11 0x56U 1536 typedef struct 1537 { 1538 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1539 uint8_t n_v : 1; 1540 uint8_t p_v : 1; 1541 uint8_t n_z : 1; 1542 uint8_t p_z : 1; 1543 uint8_t n_y : 1; 1544 uint8_t p_y : 1; 1545 uint8_t n_x : 1; 1546 uint8_t p_x : 1; 1547 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1548 uint8_t p_x : 1; 1549 uint8_t n_x : 1; 1550 uint8_t p_y : 1; 1551 uint8_t n_y : 1; 1552 uint8_t p_z : 1; 1553 uint8_t n_z : 1; 1554 uint8_t p_v : 1; 1555 uint8_t n_v : 1; 1556 #endif /* DRV_BYTE_ORDER */ 1557 } asm330lhb_fsm_outs11_t; 1558 1559 #define ASM330LHB_FSM_OUTS12 0x57U 1560 typedef struct 1561 { 1562 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1563 uint8_t n_v : 1; 1564 uint8_t p_v : 1; 1565 uint8_t n_z : 1; 1566 uint8_t p_z : 1; 1567 uint8_t n_y : 1; 1568 uint8_t p_y : 1; 1569 uint8_t n_x : 1; 1570 uint8_t p_x : 1; 1571 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1572 uint8_t p_x : 1; 1573 uint8_t n_x : 1; 1574 uint8_t p_y : 1; 1575 uint8_t n_y : 1; 1576 uint8_t p_z : 1; 1577 uint8_t n_z : 1; 1578 uint8_t p_v : 1; 1579 uint8_t n_v : 1; 1580 #endif /* DRV_BYTE_ORDER */ 1581 } asm330lhb_fsm_outs12_t; 1582 1583 #define ASM330LHB_FSM_OUTS13 0x58U 1584 typedef struct 1585 { 1586 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1587 uint8_t n_v : 1; 1588 uint8_t p_v : 1; 1589 uint8_t n_z : 1; 1590 uint8_t p_z : 1; 1591 uint8_t n_y : 1; 1592 uint8_t p_y : 1; 1593 uint8_t n_x : 1; 1594 uint8_t p_x : 1; 1595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1596 uint8_t p_x : 1; 1597 uint8_t n_x : 1; 1598 uint8_t p_y : 1; 1599 uint8_t n_y : 1; 1600 uint8_t p_z : 1; 1601 uint8_t n_z : 1; 1602 uint8_t p_v : 1; 1603 uint8_t n_v : 1; 1604 #endif /* DRV_BYTE_ORDER */ 1605 } asm330lhb_fsm_outs13_t; 1606 1607 #define ASM330LHB_FSM_OUTS14 0x59U 1608 typedef struct 1609 { 1610 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1611 uint8_t n_v : 1; 1612 uint8_t p_v : 1; 1613 uint8_t n_z : 1; 1614 uint8_t p_z : 1; 1615 uint8_t n_y : 1; 1616 uint8_t p_y : 1; 1617 uint8_t n_x : 1; 1618 uint8_t p_x : 1; 1619 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1620 uint8_t p_x : 1; 1621 uint8_t n_x : 1; 1622 uint8_t p_y : 1; 1623 uint8_t n_y : 1; 1624 uint8_t p_z : 1; 1625 uint8_t n_z : 1; 1626 uint8_t p_v : 1; 1627 uint8_t n_v : 1; 1628 #endif /* DRV_BYTE_ORDER */ 1629 } asm330lhb_fsm_outs14_t; 1630 1631 #define ASM330LHB_FSM_OUTS15 0x5AU 1632 typedef struct 1633 { 1634 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1635 uint8_t n_v : 1; 1636 uint8_t p_v : 1; 1637 uint8_t n_z : 1; 1638 uint8_t p_z : 1; 1639 uint8_t n_y : 1; 1640 uint8_t p_y : 1; 1641 uint8_t n_x : 1; 1642 uint8_t p_x : 1; 1643 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1644 uint8_t p_x : 1; 1645 uint8_t n_x : 1; 1646 uint8_t p_y : 1; 1647 uint8_t n_y : 1; 1648 uint8_t p_z : 1; 1649 uint8_t n_z : 1; 1650 uint8_t p_v : 1; 1651 uint8_t n_v : 1; 1652 #endif /* DRV_BYTE_ORDER */ 1653 } asm330lhb_fsm_outs15_t; 1654 1655 #define ASM330LHB_FSM_OUTS16 0x5BU 1656 typedef struct 1657 { 1658 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1659 uint8_t n_v : 1; 1660 uint8_t p_v : 1; 1661 uint8_t n_z : 1; 1662 uint8_t p_z : 1; 1663 uint8_t n_y : 1; 1664 uint8_t p_y : 1; 1665 uint8_t n_x : 1; 1666 uint8_t p_x : 1; 1667 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1668 uint8_t p_x : 1; 1669 uint8_t n_x : 1; 1670 uint8_t p_y : 1; 1671 uint8_t n_y : 1; 1672 uint8_t p_z : 1; 1673 uint8_t n_z : 1; 1674 uint8_t p_v : 1; 1675 uint8_t n_v : 1; 1676 #endif /* DRV_BYTE_ORDER */ 1677 } asm330lhb_fsm_outs16_t; 1678 1679 #define ASM330LHB_EMB_FUNC_ODR_CFG_B 0x5FU 1680 typedef struct 1681 { 1682 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1683 uint8_t not_used_01 : 3; 1684 uint8_t fsm_odr : 2; 1685 uint8_t not_used_02 : 3; 1686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1687 uint8_t not_used_02 : 3; 1688 uint8_t fsm_odr : 2; 1689 uint8_t not_used_01 : 3; 1690 #endif /* DRV_BYTE_ORDER */ 1691 } asm330lhb_emb_func_odr_cfg_b_t; 1692 1693 #define ASM330LHB_EMB_FUNC_ODR_CFG_C 0x60U 1694 typedef struct 1695 { 1696 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1697 uint8_t not_used_01 : 4; 1698 uint8_t mlc_odr : 2; 1699 uint8_t not_used_02 : 2; 1700 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1701 uint8_t not_used_02 : 2; 1702 uint8_t mlc_odr : 2; 1703 uint8_t not_used_01 : 4; 1704 #endif /* DRV_BYTE_ORDER */ 1705 } asm330lhb_emb_func_odr_cfg_c_t; 1706 1707 #define ASM330LHB_EMB_FUNC_INIT_B 0x67U 1708 typedef struct 1709 { 1710 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1711 uint8_t fsm_init : 1; 1712 uint8_t not_used_01 : 3; 1713 uint8_t mlc_init : 1; 1714 uint8_t not_used_02 : 3; 1715 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1716 uint8_t not_used_02 : 3; 1717 uint8_t mlc_init : 1; 1718 uint8_t not_used_01 : 3; 1719 uint8_t fsm_init : 1; 1720 #endif /* DRV_BYTE_ORDER */ 1721 } asm330lhb_emb_func_init_b_t; 1722 1723 #define ASM330LHB_MLC0_SRC 0x70U 1724 #define ASM330LHB_MLC1_SRC 0x71U 1725 #define ASM330LHB_MLC2_SRC 0x72U 1726 #define ASM330LHB_MLC3_SRC 0x73U 1727 #define ASM330LHB_MLC4_SRC 0x74U 1728 #define ASM330LHB_MLC5_SRC 0x75U 1729 #define ASM330LHB_MLC6_SRC 0x76U 1730 #define ASM330LHB_MLC7_SRC 0x77U 1731 1732 #define ASM330LHB_FSM_LC_TIMEOUT_L 0x17AU 1733 #define ASM330LHB_FSM_LC_TIMEOUT_H 0x17BU 1734 #define ASM330LHB_FSM_PROGRAMS 0x17CU 1735 #define ASM330LHB_FSM_START_ADD_L 0x17EU 1736 #define ASM330LHB_FSM_START_ADD_H 0x17FU 1737 1738 /** 1739 * @defgroup ASM330LHB_Register_Union 1740 * @brief This union group all the registers that has a bit-field 1741 * description. 1742 * This union is useful but not need by the driver. 1743 * 1744 * REMOVING this union you are compliant with: 1745 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 1746 * 1747 * @{ 1748 * 1749 */ 1750 typedef union 1751 { 1752 asm330lhb_func_cfg_access_t func_cfg_access; 1753 asm330lhb_pin_ctrl_t pin_ctrl; 1754 asm330lhb_fifo_ctrl1_t fifo_ctrl1; 1755 asm330lhb_fifo_ctrl2_t fifo_ctrl2; 1756 asm330lhb_fifo_ctrl3_t fifo_ctrl3; 1757 asm330lhb_fifo_ctrl4_t fifo_ctrl4; 1758 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1; 1759 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2; 1760 asm330lhb_int1_ctrl_t int1_ctrl; 1761 asm330lhb_int2_ctrl_t int2_ctrl; 1762 asm330lhb_ctrl1_xl_t ctrl1_xl; 1763 asm330lhb_ctrl2_g_t ctrl2_g; 1764 asm330lhb_ctrl3_c_t ctrl3_c; 1765 asm330lhb_ctrl4_c_t ctrl4_c; 1766 asm330lhb_ctrl5_c_t ctrl5_c; 1767 asm330lhb_ctrl6_c_t ctrl6_c; 1768 asm330lhb_ctrl7_g_t ctrl7_g; 1769 asm330lhb_ctrl8_xl_t ctrl8_xl; 1770 asm330lhb_ctrl9_xl_t ctrl9_xl; 1771 asm330lhb_ctrl10_c_t ctrl10_c; 1772 asm330lhb_all_int_src_t all_int_src; 1773 asm330lhb_wake_up_src_t wake_up_src; 1774 asm330lhb_d6d_src_t d6d_src; 1775 asm330lhb_status_reg_t status_reg; 1776 asm330lhb_fifo_status1_t fifo_status1; 1777 asm330lhb_fifo_status2_t fifo_status2; 1778 asm330lhb_int_cfg0_t int_cfg0; 1779 asm330lhb_int_cfg1_t int_cfg1; 1780 asm330lhb_ths_6d_t ths_6d; 1781 asm330lhb_wake_up_ths_t wake_up_ths; 1782 asm330lhb_wake_up_dur_t wake_up_dur; 1783 asm330lhb_free_fall_t free_fall; 1784 asm330lhb_md1_cfg_t md1_cfg; 1785 asm330lhb_md2_cfg_t md2_cfg; 1786 asm330lhb_i3c_bus_avb_t i3c_bus_avb; 1787 asm330lhb_internal_freq_fine_t internal_freq_fine; 1788 asm330lhb_fifo_data_out_tag_t fifo_data_out_tag; 1789 asm330lhb_page_sel_t page_sel; 1790 asm330lhb_emb_func_en_b_t emb_func_en_b; 1791 asm330lhb_page_address_t page_address; 1792 asm330lhb_page_value_t page_value; 1793 asm330lhb_emb_func_int1_t emb_func_int1; 1794 asm330lhb_fsm_int1_a_t fsm_int1_a; 1795 asm330lhb_fsm_int1_b_t fsm_int1_b; 1796 asm330lhb_mlc_int1_t mlc_int1; 1797 asm330lhb_emb_func_int2_t emb_func_int2; 1798 asm330lhb_fsm_int2_a_t fsm_int2_a; 1799 asm330lhb_fsm_int2_b_t fsm_int2_b; 1800 asm330lhb_mlc_int2_t mlc_int2; 1801 asm330lhb_emb_func_status_t emb_func_status; 1802 asm330lhb_fsm_status_a_t fsm_status_a; 1803 asm330lhb_fsm_status_b_t fsm_status_b; 1804 asm330lhb_mlc_status_mainpage_t mlc_status_mainpage; 1805 asm330lhb_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 1806 asm330lhb_page_rw_t page_rw; 1807 asm330lhb_fsm_enable_a_t fsm_enable_a; 1808 asm330lhb_fsm_enable_b_t fsm_enable_b; 1809 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear; 1810 asm330lhb_fsm_outs1_t fsm_outs1; 1811 asm330lhb_fsm_outs2_t fsm_outs2; 1812 asm330lhb_fsm_outs3_t fsm_outs3; 1813 asm330lhb_fsm_outs4_t fsm_outs4; 1814 asm330lhb_fsm_outs5_t fsm_outs5; 1815 asm330lhb_fsm_outs6_t fsm_outs6; 1816 asm330lhb_fsm_outs7_t fsm_outs7; 1817 asm330lhb_fsm_outs8_t fsm_outs8; 1818 asm330lhb_fsm_outs9_t fsm_outs9; 1819 asm330lhb_fsm_outs10_t fsm_outs10; 1820 asm330lhb_fsm_outs11_t fsm_outs11; 1821 asm330lhb_fsm_outs12_t fsm_outs12; 1822 asm330lhb_fsm_outs13_t fsm_outs13; 1823 asm330lhb_fsm_outs14_t fsm_outs14; 1824 asm330lhb_fsm_outs15_t fsm_outs15; 1825 asm330lhb_fsm_outs16_t fsm_outs16; 1826 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 1827 asm330lhb_emb_func_init_b_t emb_func_init_b; 1828 bitwise_t bitwise; 1829 uint8_t byte; 1830 } asm330lhb_reg_t; 1831 1832 /** 1833 * @} 1834 * 1835 */ 1836 1837 #ifndef __weak 1838 #define __weak __attribute__((weak)) 1839 #endif /* __weak */ 1840 1841 /* 1842 * These are the basic platform dependent I/O routines to read 1843 * and write device registers connected on a standard bus. 1844 * The driver keeps offering a default implementation based on function 1845 * pointers to read/write routines for backward compatibility. 1846 * The __weak directive allows the final application to overwrite 1847 * them with a custom implementation. 1848 */ 1849 1850 int32_t asm330lhb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 1851 uint16_t len); 1852 int32_t asm330lhb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 1853 uint16_t len); 1854 1855 float_t asm330lhb_from_fs2g_to_mg(int16_t lsb); 1856 float_t asm330lhb_from_fs4g_to_mg(int16_t lsb); 1857 float_t asm330lhb_from_fs8g_to_mg(int16_t lsb); 1858 float_t asm330lhb_from_fs16g_to_mg(int16_t lsb); 1859 float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb); 1860 float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb); 1861 float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb); 1862 float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb); 1863 float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb); 1864 float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb); 1865 float_t asm330lhb_from_lsb_to_celsius(int16_t lsb); 1866 float_t asm330lhb_from_lsb_to_nsec(int32_t lsb); 1867 1868 typedef enum 1869 { 1870 ASM330LHB_2g = 0, 1871 ASM330LHB_16g = 1, /* if XL_FS_MODE = '1' -> ASM330LHB_2g */ 1872 ASM330LHB_4g = 2, 1873 ASM330LHB_8g = 3, 1874 } asm330lhb_fs_xl_t; 1875 int32_t asm330lhb_xl_full_scale_set(const stmdev_ctx_t *ctx, asm330lhb_fs_xl_t val); 1876 int32_t asm330lhb_xl_full_scale_get(const stmdev_ctx_t *ctx, 1877 asm330lhb_fs_xl_t *val); 1878 1879 typedef enum 1880 { 1881 ASM330LHB_XL_ODR_OFF = 0, 1882 ASM330LHB_XL_ODR_12Hz5 = 1, 1883 ASM330LHB_XL_ODR_26Hz = 2, 1884 ASM330LHB_XL_ODR_52Hz = 3, 1885 ASM330LHB_XL_ODR_104Hz = 4, 1886 ASM330LHB_XL_ODR_208Hz = 5, 1887 ASM330LHB_XL_ODR_417Hz = 6, 1888 ASM330LHB_XL_ODR_833Hz = 7, 1889 ASM330LHB_XL_ODR_1667Hz = 8, 1890 ASM330LHB_XL_ODR_1Hz6 = 11, /* (low power only) */ 1891 } asm330lhb_odr_xl_t; 1892 int32_t asm330lhb_xl_data_rate_set(const stmdev_ctx_t *ctx, asm330lhb_odr_xl_t val); 1893 int32_t asm330lhb_xl_data_rate_get(const stmdev_ctx_t *ctx, 1894 asm330lhb_odr_xl_t *val); 1895 1896 typedef enum 1897 { 1898 ASM330LHB_125dps = 2, 1899 ASM330LHB_250dps = 0, 1900 ASM330LHB_500dps = 4, 1901 ASM330LHB_1000dps = 8, 1902 ASM330LHB_2000dps = 12, 1903 ASM330LHB_4000dps = 1, 1904 } asm330lhb_fs_g_t; 1905 int32_t asm330lhb_gy_full_scale_set(const stmdev_ctx_t *ctx, asm330lhb_fs_g_t val); 1906 int32_t asm330lhb_gy_full_scale_get(const stmdev_ctx_t *ctx, asm330lhb_fs_g_t *val); 1907 1908 typedef enum 1909 { 1910 ASM330LHB_GY_ODR_OFF = 0, 1911 ASM330LHB_GY_ODR_12Hz5 = 1, 1912 ASM330LHB_GY_ODR_26Hz = 2, 1913 ASM330LHB_GY_ODR_52Hz = 3, 1914 ASM330LHB_GY_ODR_104Hz = 4, 1915 ASM330LHB_GY_ODR_208Hz = 5, 1916 ASM330LHB_GY_ODR_417Hz = 6, 1917 ASM330LHB_GY_ODR_833Hz = 7, 1918 ASM330LHB_GY_ODR_1667Hz = 8, 1919 } asm330lhb_odr_g_t; 1920 int32_t asm330lhb_gy_data_rate_set(const stmdev_ctx_t *ctx, 1921 asm330lhb_odr_g_t val); 1922 int32_t asm330lhb_gy_data_rate_get(const stmdev_ctx_t *ctx, 1923 asm330lhb_odr_g_t *val); 1924 1925 int32_t asm330lhb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 1926 int32_t asm330lhb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 1927 1928 typedef enum 1929 { 1930 ASM330LHB_LSb_1mg = 0, 1931 ASM330LHB_LSb_16mg = 1, 1932 } asm330lhb_usr_off_w_t; 1933 int32_t asm330lhb_xl_offset_weight_set(const stmdev_ctx_t *ctx, 1934 asm330lhb_usr_off_w_t val); 1935 int32_t asm330lhb_xl_offset_weight_get(const stmdev_ctx_t *ctx, 1936 asm330lhb_usr_off_w_t *val); 1937 1938 typedef enum 1939 { 1940 ASM330LHB_HIGH_PERFORMANCE_MD = 0, 1941 ASM330LHB_LOW_NORMAL_POWER_MD = 1, 1942 } asm330lhb_xl_hm_mode_t; 1943 int32_t asm330lhb_xl_power_mode_set(const stmdev_ctx_t *ctx, 1944 asm330lhb_xl_hm_mode_t val); 1945 int32_t asm330lhb_xl_power_mode_get(const stmdev_ctx_t *ctx, 1946 asm330lhb_xl_hm_mode_t *val); 1947 1948 typedef enum 1949 { 1950 ASM330LHB_GY_HIGH_PERFORMANCE = 0, 1951 ASM330LHB_GY_NORMAL = 1, 1952 } asm330lhb_g_hm_mode_t; 1953 int32_t asm330lhb_gy_power_mode_set(const stmdev_ctx_t *ctx, 1954 asm330lhb_g_hm_mode_t val); 1955 int32_t asm330lhb_gy_power_mode_get(const stmdev_ctx_t *ctx, 1956 asm330lhb_g_hm_mode_t *val); 1957 1958 typedef struct 1959 { 1960 asm330lhb_all_int_src_t all_int_src; 1961 asm330lhb_wake_up_src_t wake_up_src; 1962 asm330lhb_d6d_src_t d6d_src; 1963 asm330lhb_status_reg_t status_reg; 1964 asm330lhb_emb_func_status_t emb_func_status; 1965 asm330lhb_fsm_status_a_t fsm_status_a; 1966 asm330lhb_fsm_status_b_t fsm_status_b; 1967 asm330lhb_mlc_status_mainpage_t mlc_status; 1968 } asm330lhb_all_sources_t; 1969 int32_t asm330lhb_all_sources_get(const stmdev_ctx_t *ctx, 1970 asm330lhb_all_sources_t *val); 1971 1972 int32_t asm330lhb_status_reg_get(const stmdev_ctx_t *ctx, 1973 asm330lhb_status_reg_t *val); 1974 1975 int32_t asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 1976 1977 int32_t asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 1978 1979 int32_t asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 1980 1981 int32_t asm330lhb_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val); 1982 1983 int32_t asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1984 int32_t asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1985 1986 int32_t asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1987 int32_t asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1988 1989 int32_t asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff); 1990 int32_t asm330lhb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1991 1992 int32_t asm330lhb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val); 1993 int32_t asm330lhb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1994 1995 int32_t asm330lhb_timestamp_rst(const stmdev_ctx_t *ctx); 1996 1997 int32_t asm330lhb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 1998 int32_t asm330lhb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 1999 2000 int32_t asm330lhb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2001 2002 typedef enum 2003 { 2004 ASM330LHB_NO_ROUND = 0, 2005 ASM330LHB_ROUND_XL = 1, 2006 ASM330LHB_ROUND_GY = 2, 2007 ASM330LHB_ROUND_GY_XL = 3, 2008 } asm330lhb_rounding_t; 2009 int32_t asm330lhb_rounding_mode_set(const stmdev_ctx_t *ctx, 2010 asm330lhb_rounding_t val); 2011 int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx, 2012 asm330lhb_rounding_t *val); 2013 2014 int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2015 2016 int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2017 2018 int32_t asm330lhb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2019 2020 int32_t asm330lhb_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val); 2021 2022 int32_t asm330lhb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val); 2023 int32_t asm330lhb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val); 2024 2025 typedef enum 2026 { 2027 ASM330LHB_USER_BANK = 0, 2028 ASM330LHB_EMBEDDED_FUNC_BANK = 1, 2029 } asm330lhb_reg_access_t; 2030 int32_t asm330lhb_mem_bank_set(const stmdev_ctx_t *ctx, asm330lhb_reg_access_t val); 2031 int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx, 2032 asm330lhb_reg_access_t *val); 2033 2034 int32_t asm330lhb_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, 2035 uint8_t *val); 2036 int32_t asm330lhb_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2037 uint8_t *buf, uint8_t len); 2038 int32_t asm330lhb_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add, 2039 uint8_t *val); 2040 int32_t asm330lhb_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2041 uint8_t *val); 2042 2043 typedef enum 2044 { 2045 ASM330LHB_DRDY_LATCHED = 0, 2046 ASM330LHB_DRDY_PULSED = 1, 2047 } asm330lhb_dataready_pulsed_t; 2048 int32_t asm330lhb_data_ready_mode_set(const stmdev_ctx_t *ctx, 2049 asm330lhb_dataready_pulsed_t val); 2050 int32_t asm330lhb_data_ready_mode_get(const stmdev_ctx_t *ctx, 2051 asm330lhb_dataready_pulsed_t *val); 2052 2053 int32_t asm330lhb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2054 2055 int32_t asm330lhb_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 2056 int32_t asm330lhb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 2057 2058 int32_t asm330lhb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2059 int32_t asm330lhb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 2060 2061 int32_t asm330lhb_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 2062 int32_t asm330lhb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 2063 2064 typedef enum 2065 { 2066 ASM330LHB_XL_ST_DISABLE = 0, 2067 ASM330LHB_XL_ST_POSITIVE = 1, 2068 ASM330LHB_XL_ST_NEGATIVE = 2, 2069 } asm330lhb_st_xl_t; 2070 int32_t asm330lhb_xl_self_test_set(const stmdev_ctx_t *ctx, asm330lhb_st_xl_t val); 2071 int32_t asm330lhb_xl_self_test_get(const stmdev_ctx_t *ctx, asm330lhb_st_xl_t *val); 2072 2073 typedef enum 2074 { 2075 ASM330LHB_GY_ST_DISABLE = 0, 2076 ASM330LHB_GY_ST_POSITIVE = 1, 2077 ASM330LHB_GY_ST_NEGATIVE = 3, 2078 } asm330lhb_st_g_t; 2079 int32_t asm330lhb_gy_self_test_set(const stmdev_ctx_t *ctx, asm330lhb_st_g_t val); 2080 int32_t asm330lhb_gy_self_test_get(const stmdev_ctx_t *ctx, asm330lhb_st_g_t *val); 2081 2082 int32_t asm330lhb_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 2083 int32_t asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 2084 2085 int32_t asm330lhb_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 2086 int32_t asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2087 2088 int32_t asm330lhb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 2089 int32_t asm330lhb_filter_settling_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 2090 2091 typedef enum 2092 { 2093 ASM330LHB_ULTRA_LIGHT = 0, 2094 ASM330LHB_VERY_LIGHT = 1, 2095 ASM330LHB_LIGHT = 2, 2096 ASM330LHB_MEDIUM = 3, 2097 ASM330LHB_STRONG = 4, 2098 ASM330LHB_VERY_STRONG = 5, 2099 ASM330LHB_AGGRESSIVE = 6, 2100 ASM330LHB_XTREME = 7, 2101 } asm330lhb_ftype_t; 2102 int32_t asm330lhb_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2103 asm330lhb_ftype_t val); 2104 int32_t asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2105 asm330lhb_ftype_t *val); 2106 2107 int32_t asm330lhb_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val); 2108 int32_t asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val); 2109 2110 typedef enum 2111 { 2112 ASM330LHB_HP_PATH_DISABLE_ON_OUT = 0x00, 2113 ASM330LHB_SLOPE_ODR_DIV_4 = 0x10, 2114 ASM330LHB_HP_ODR_DIV_10 = 0x11, 2115 ASM330LHB_HP_ODR_DIV_20 = 0x12, 2116 ASM330LHB_HP_ODR_DIV_45 = 0x13, 2117 ASM330LHB_HP_ODR_DIV_100 = 0x14, 2118 ASM330LHB_HP_ODR_DIV_200 = 0x15, 2119 ASM330LHB_HP_ODR_DIV_400 = 0x16, 2120 ASM330LHB_HP_ODR_DIV_800 = 0x17, 2121 ASM330LHB_HP_REF_MD_ODR_DIV_10 = 0x31, 2122 ASM330LHB_HP_REF_MD_ODR_DIV_20 = 0x32, 2123 ASM330LHB_HP_REF_MD_ODR_DIV_45 = 0x33, 2124 ASM330LHB_HP_REF_MD_ODR_DIV_100 = 0x34, 2125 ASM330LHB_HP_REF_MD_ODR_DIV_200 = 0x35, 2126 ASM330LHB_HP_REF_MD_ODR_DIV_400 = 0x36, 2127 ASM330LHB_HP_REF_MD_ODR_DIV_800 = 0x37, 2128 ASM330LHB_LP_ODR_DIV_10 = 0x01, 2129 ASM330LHB_LP_ODR_DIV_20 = 0x02, 2130 ASM330LHB_LP_ODR_DIV_45 = 0x03, 2131 ASM330LHB_LP_ODR_DIV_100 = 0x04, 2132 ASM330LHB_LP_ODR_DIV_200 = 0x05, 2133 ASM330LHB_LP_ODR_DIV_400 = 0x06, 2134 ASM330LHB_LP_ODR_DIV_800 = 0x07, 2135 } asm330lhb_hp_slope_xl_en_t; 2136 int32_t asm330lhb_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx, 2137 asm330lhb_hp_slope_xl_en_t val); 2138 int32_t asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx, 2139 asm330lhb_hp_slope_xl_en_t *val); 2140 2141 int32_t asm330lhb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 2142 int32_t asm330lhb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 2143 2144 typedef enum 2145 { 2146 ASM330LHB_USE_SLOPE = 0, 2147 ASM330LHB_USE_HPF = 1, 2148 } asm330lhb_slope_fds_t; 2149 int32_t asm330lhb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx, 2150 asm330lhb_slope_fds_t val); 2151 int32_t asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx, 2152 asm330lhb_slope_fds_t *val); 2153 2154 typedef enum 2155 { 2156 ASM330LHB_HP_FILTER_NONE = 0x00, 2157 ASM330LHB_HP_FILTER_16mHz = 0x80, 2158 ASM330LHB_HP_FILTER_65mHz = 0x81, 2159 ASM330LHB_HP_FILTER_260mHz = 0x82, 2160 ASM330LHB_HP_FILTER_1Hz04 = 0x83, 2161 } asm330lhb_hpm_g_t; 2162 int32_t asm330lhb_gy_hp_path_internal_set(const stmdev_ctx_t *ctx, 2163 asm330lhb_hpm_g_t val); 2164 int32_t asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t *ctx, 2165 asm330lhb_hpm_g_t *val); 2166 2167 typedef enum 2168 { 2169 ASM330LHB_PULL_UP_DISC = 0, 2170 ASM330LHB_PULL_UP_CONNECT = 1, 2171 } asm330lhb_sdo_pu_en_t; 2172 int32_t asm330lhb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx, 2173 asm330lhb_sdo_pu_en_t val); 2174 int32_t asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx, 2175 asm330lhb_sdo_pu_en_t *val); 2176 2177 typedef enum 2178 { 2179 ASM330LHB_PULL_DOWN_CONNECT = 0, 2180 ASM330LHB_PULL_DOWN_DISC = 1, 2181 } asm330lhb_pd_dis_int1_t; 2182 int32_t asm330lhb_int1_mode_set(const stmdev_ctx_t *ctx, 2183 asm330lhb_pd_dis_int1_t val); 2184 int32_t asm330lhb_int1_mode_get(const stmdev_ctx_t *ctx, 2185 asm330lhb_pd_dis_int1_t *val); 2186 2187 typedef enum 2188 { 2189 ASM330LHB_SPI_4_WIRE = 0, 2190 ASM330LHB_SPI_3_WIRE = 1, 2191 } asm330lhb_sim_t; 2192 int32_t asm330lhb_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhb_sim_t val); 2193 int32_t asm330lhb_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhb_sim_t *val); 2194 2195 typedef enum 2196 { 2197 ASM330LHB_I2C_ENABLE = 0, 2198 ASM330LHB_I2C_DISABLE = 1, 2199 } asm330lhb_i2c_disable_t; 2200 int32_t asm330lhb_i2c_interface_set(const stmdev_ctx_t *ctx, 2201 asm330lhb_i2c_disable_t val); 2202 int32_t asm330lhb_i2c_interface_get(const stmdev_ctx_t *ctx, 2203 asm330lhb_i2c_disable_t *val); 2204 2205 typedef enum 2206 { 2207 ASM330LHB_I3C_DISABLE = 0x80, 2208 ASM330LHB_I3C_ENABLE_T_50us = 0x00, 2209 ASM330LHB_I3C_ENABLE_T_2us = 0x01, 2210 ASM330LHB_I3C_ENABLE_T_1ms = 0x02, 2211 ASM330LHB_I3C_ENABLE_T_25ms = 0x03, 2212 } asm330lhb_i3c_disable_t; 2213 int32_t asm330lhb_i3c_disable_set(const stmdev_ctx_t *ctx, 2214 asm330lhb_i3c_disable_t val); 2215 int32_t asm330lhb_i3c_disable_get(const stmdev_ctx_t *ctx, 2216 asm330lhb_i3c_disable_t *val); 2217 2218 typedef struct 2219 { 2220 asm330lhb_int1_ctrl_t int1_ctrl; 2221 asm330lhb_md1_cfg_t md1_cfg; 2222 asm330lhb_emb_func_int1_t emb_func_int1; 2223 asm330lhb_fsm_int1_a_t fsm_int1_a; 2224 asm330lhb_fsm_int1_b_t fsm_int1_b; 2225 asm330lhb_mlc_int1_t mlc_int1; 2226 } asm330lhb_pin_int1_route_t; 2227 int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx, 2228 asm330lhb_pin_int1_route_t *val); 2229 int32_t asm330lhb_pin_int1_route_get(const stmdev_ctx_t *ctx, 2230 asm330lhb_pin_int1_route_t *val); 2231 2232 typedef struct 2233 { 2234 asm330lhb_int2_ctrl_t int2_ctrl; 2235 asm330lhb_md2_cfg_t md2_cfg; 2236 asm330lhb_emb_func_int2_t emb_func_int2; 2237 asm330lhb_fsm_int2_a_t fsm_int2_a; 2238 asm330lhb_fsm_int2_b_t fsm_int2_b; 2239 asm330lhb_mlc_int2_t mlc_int2; 2240 } asm330lhb_pin_int2_route_t; 2241 int32_t asm330lhb_pin_int2_route_set(const stmdev_ctx_t *ctx, 2242 asm330lhb_pin_int2_route_t *val); 2243 int32_t asm330lhb_pin_int2_route_get(const stmdev_ctx_t *ctx, 2244 asm330lhb_pin_int2_route_t *val); 2245 2246 typedef enum 2247 { 2248 ASM330LHB_PUSH_PULL = 0, 2249 ASM330LHB_OPEN_DRAIN = 1, 2250 } asm330lhb_pp_od_t; 2251 int32_t asm330lhb_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t val); 2252 int32_t asm330lhb_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val); 2253 2254 typedef enum 2255 { 2256 ASM330LHB_ACTIVE_HIGH = 0, 2257 ASM330LHB_ACTIVE_LOW = 1, 2258 } asm330lhb_h_lactive_t; 2259 int32_t asm330lhb_pin_polarity_set(const stmdev_ctx_t *ctx, 2260 asm330lhb_h_lactive_t val); 2261 int32_t asm330lhb_pin_polarity_get(const stmdev_ctx_t *ctx, 2262 asm330lhb_h_lactive_t *val); 2263 2264 int32_t asm330lhb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val); 2265 int32_t asm330lhb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2266 2267 typedef enum 2268 { 2269 ASM330LHB_ALL_INT_PULSED = 0, 2270 ASM330LHB_BASE_LATCHED_EMB_PULSED = 1, 2271 ASM330LHB_BASE_PULSED_EMB_LATCHED = 2, 2272 ASM330LHB_ALL_INT_LATCHED = 3, 2273 } asm330lhb_lir_t; 2274 int32_t asm330lhb_int_notification_set(const stmdev_ctx_t *ctx, 2275 asm330lhb_lir_t val); 2276 int32_t asm330lhb_int_notification_get(const stmdev_ctx_t *ctx, 2277 asm330lhb_lir_t *val); 2278 2279 typedef enum 2280 { 2281 ASM330LHB_LSb_FS_DIV_64 = 0, 2282 ASM330LHB_LSb_FS_DIV_256 = 1, 2283 } asm330lhb_wake_ths_w_t; 2284 int32_t asm330lhb_wkup_ths_weight_set(const stmdev_ctx_t *ctx, 2285 asm330lhb_wake_ths_w_t val); 2286 int32_t asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t *ctx, 2287 asm330lhb_wake_ths_w_t *val); 2288 2289 int32_t asm330lhb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 2290 int32_t asm330lhb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 2291 2292 int32_t asm330lhb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, 2293 uint8_t val); 2294 int32_t asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx, 2295 uint8_t *val); 2296 2297 int32_t asm330lhb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2298 int32_t asm330lhb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2299 2300 int32_t asm330lhb_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2301 int32_t asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2302 2303 typedef enum 2304 { 2305 ASM330LHB_DRIVE_SLEEP_CHG_EVENT = 0, 2306 ASM330LHB_DRIVE_SLEEP_STATUS = 1, 2307 } asm330lhb_sleep_status_on_int_t; 2308 int32_t asm330lhb_act_pin_notification_set(const stmdev_ctx_t *ctx, 2309 asm330lhb_sleep_status_on_int_t val); 2310 int32_t asm330lhb_act_pin_notification_get(const stmdev_ctx_t *ctx, 2311 asm330lhb_sleep_status_on_int_t *val); 2312 2313 typedef enum 2314 { 2315 ASM330LHB_XL_AND_GY_NOT_AFFECTED = 0, 2316 ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED = 1, 2317 ASM330LHB_XL_12Hz5_GY_SLEEP = 2, 2318 ASM330LHB_XL_12Hz5_GY_PD = 3, 2319 } asm330lhb_inact_en_t; 2320 int32_t asm330lhb_act_mode_set(const stmdev_ctx_t *ctx, 2321 asm330lhb_inact_en_t val); 2322 int32_t asm330lhb_act_mode_get(const stmdev_ctx_t *ctx, 2323 asm330lhb_inact_en_t *val); 2324 2325 int32_t asm330lhb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2326 int32_t asm330lhb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2327 2328 typedef enum 2329 { 2330 ASM330LHB_DEG_80 = 0, 2331 ASM330LHB_DEG_70 = 1, 2332 ASM330LHB_DEG_60 = 2, 2333 ASM330LHB_DEG_50 = 3, 2334 } asm330lhb_sixd_ths_t; 2335 int32_t asm330lhb_6d_threshold_set(const stmdev_ctx_t *ctx, 2336 asm330lhb_sixd_ths_t val); 2337 int32_t asm330lhb_6d_threshold_get(const stmdev_ctx_t *ctx, 2338 asm330lhb_sixd_ths_t *val); 2339 2340 int32_t asm330lhb_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2341 int32_t asm330lhb_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2342 2343 typedef enum 2344 { 2345 ASM330LHB_FF_TSH_156mg = 0, 2346 ASM330LHB_FF_TSH_219mg = 1, 2347 ASM330LHB_FF_TSH_250mg = 2, 2348 ASM330LHB_FF_TSH_312mg = 3, 2349 ASM330LHB_FF_TSH_344mg = 4, 2350 ASM330LHB_FF_TSH_406mg = 5, 2351 ASM330LHB_FF_TSH_469mg = 6, 2352 ASM330LHB_FF_TSH_500mg = 7, 2353 } asm330lhb_ff_ths_t; 2354 int32_t asm330lhb_ff_threshold_set(const stmdev_ctx_t *ctx, 2355 asm330lhb_ff_ths_t val); 2356 int32_t asm330lhb_ff_threshold_get(const stmdev_ctx_t *ctx, 2357 asm330lhb_ff_ths_t *val); 2358 2359 int32_t asm330lhb_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 2360 int32_t asm330lhb_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 2361 2362 int32_t asm330lhb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val); 2363 int32_t asm330lhb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val); 2364 2365 int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 2366 uint8_t val); 2367 int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 2368 uint8_t *val); 2369 2370 int32_t asm330lhb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 2371 int32_t asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 2372 2373 typedef enum 2374 { 2375 ASM330LHB_XL_NOT_BATCHED = 0, 2376 ASM330LHB_XL_BATCHED_AT_12Hz5 = 1, 2377 ASM330LHB_XL_BATCHED_AT_26Hz = 2, 2378 ASM330LHB_XL_BATCHED_AT_52Hz = 3, 2379 ASM330LHB_XL_BATCHED_AT_104Hz = 4, 2380 ASM330LHB_XL_BATCHED_AT_208Hz = 5, 2381 ASM330LHB_XL_BATCHED_AT_417Hz = 6, 2382 ASM330LHB_XL_BATCHED_AT_833Hz = 7, 2383 ASM330LHB_XL_BATCHED_AT_1667Hz = 8, 2384 ASM330LHB_XL_BATCHED_AT_1Hz6 = 11, 2385 } asm330lhb_bdr_xl_t; 2386 int32_t asm330lhb_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 2387 asm330lhb_bdr_xl_t val); 2388 int32_t asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 2389 asm330lhb_bdr_xl_t *val); 2390 2391 typedef enum 2392 { 2393 ASM330LHB_GY_NOT_BATCHED = 0, 2394 ASM330LHB_GY_BATCHED_AT_12Hz5 = 1, 2395 ASM330LHB_GY_BATCHED_AT_26Hz = 2, 2396 ASM330LHB_GY_BATCHED_AT_52Hz = 3, 2397 ASM330LHB_GY_BATCHED_AT_104Hz = 4, 2398 ASM330LHB_GY_BATCHED_AT_208Hz = 5, 2399 ASM330LHB_GY_BATCHED_AT_417Hz = 6, 2400 ASM330LHB_GY_BATCHED_AT_833Hz = 7, 2401 ASM330LHB_GY_BATCHED_AT_1667Hz = 8, 2402 ASM330LHB_GY_BATCHED_AT_6Hz5 = 11, 2403 } asm330lhb_bdr_gy_t; 2404 int32_t asm330lhb_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 2405 asm330lhb_bdr_gy_t val); 2406 int32_t asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 2407 asm330lhb_bdr_gy_t *val); 2408 2409 typedef enum 2410 { 2411 ASM330LHB_BYPASS_MODE = 0, 2412 ASM330LHB_FIFO_MODE = 1, 2413 ASM330LHB_STREAM_TO_FIFO_MODE = 3, 2414 ASM330LHB_BYPASS_TO_STREAM_MODE = 4, 2415 ASM330LHB_STREAM_MODE = 6, 2416 ASM330LHB_BYPASS_TO_FIFO_MODE = 7, 2417 } asm330lhb_fifo_mode_t; 2418 int32_t asm330lhb_fifo_mode_set(const stmdev_ctx_t *ctx, asm330lhb_fifo_mode_t val); 2419 int32_t asm330lhb_fifo_mode_get(const stmdev_ctx_t *ctx, 2420 asm330lhb_fifo_mode_t *val); 2421 2422 typedef enum 2423 { 2424 ASM330LHB_TEMP_NOT_BATCHED = 0, 2425 ASM330LHB_TEMP_BATCHED_AT_52Hz = 1, 2426 ASM330LHB_TEMP_BATCHED_AT_12Hz5 = 2, 2427 ASM330LHB_TEMP_BATCHED_AT_1Hz6 = 3, 2428 } asm330lhb_odr_t_batch_t; 2429 int32_t asm330lhb_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 2430 asm330lhb_odr_t_batch_t val); 2431 int32_t asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 2432 asm330lhb_odr_t_batch_t *val); 2433 2434 typedef enum 2435 { 2436 ASM330LHB_NO_DECIMATION = 0, 2437 ASM330LHB_DEC_1 = 1, 2438 ASM330LHB_DEC_8 = 2, 2439 ASM330LHB_DEC_32 = 3, 2440 } asm330lhb_dec_ts_batch_t; 2441 int32_t asm330lhb_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx, 2442 asm330lhb_dec_ts_batch_t val); 2443 int32_t asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx, 2444 asm330lhb_dec_ts_batch_t *val); 2445 2446 typedef enum 2447 { 2448 ASM330LHB_XL_BATCH_EVENT = 0, 2449 ASM330LHB_GYRO_BATCH_EVENT = 1, 2450 } asm330lhb_trig_counter_bdr_t; 2451 int32_t asm330lhb_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx, 2452 asm330lhb_trig_counter_bdr_t val); 2453 int32_t asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx, 2454 asm330lhb_trig_counter_bdr_t *val); 2455 2456 int32_t asm330lhb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val); 2457 int32_t asm330lhb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val); 2458 2459 int32_t asm330lhb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 2460 uint16_t val); 2461 int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 2462 uint16_t *val); 2463 2464 int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 2465 2466 int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx, 2467 asm330lhb_fifo_status2_t *val); 2468 2469 int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2470 2471 int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2472 2473 int32_t asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2474 2475 typedef enum 2476 { 2477 ASM330LHB_GYRO_NC_TAG = 0x01, 2478 ASM330LHB_XL_NC_TAG = 0x02, 2479 ASM330LHB_TEMPERATURE_TAG = 0x03, 2480 ASM330LHB_TIMESTAMP_TAG = 0x04, 2481 ASM330LHB_CFG_CHANGE_TAG = 0x05, 2482 } asm330lhb_fifo_tag_t; 2483 int32_t asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 2484 asm330lhb_fifo_tag_t *val); 2485 2486 typedef enum 2487 { 2488 ASM330LHB_DEN_DISABLE = 0, 2489 ASM330LHB_LEVEL_FIFO = 6, 2490 ASM330LHB_LEVEL_LETCHED = 3, 2491 ASM330LHB_LEVEL_TRIGGER = 2, 2492 ASM330LHB_EDGE_TRIGGER = 4, 2493 } asm330lhb_den_mode_t; 2494 int32_t asm330lhb_den_mode_set(const stmdev_ctx_t *ctx, 2495 asm330lhb_den_mode_t val); 2496 int32_t asm330lhb_den_mode_get(const stmdev_ctx_t *ctx, 2497 asm330lhb_den_mode_t *val); 2498 2499 typedef enum 2500 { 2501 ASM330LHB_DEN_ACT_LOW = 0, 2502 ASM330LHB_DEN_ACT_HIGH = 1, 2503 } asm330lhb_den_lh_t; 2504 int32_t asm330lhb_den_polarity_set(const stmdev_ctx_t *ctx, 2505 asm330lhb_den_lh_t val); 2506 int32_t asm330lhb_den_polarity_get(const stmdev_ctx_t *ctx, 2507 asm330lhb_den_lh_t *val); 2508 2509 typedef enum 2510 { 2511 ASM330LHB_STAMP_IN_GY_DATA = 0, 2512 ASM330LHB_STAMP_IN_XL_DATA = 1, 2513 ASM330LHB_STAMP_IN_GY_XL_DATA = 2, 2514 } asm330lhb_den_xl_g_t; 2515 int32_t asm330lhb_den_enable_set(const stmdev_ctx_t *ctx, 2516 asm330lhb_den_xl_g_t val); 2517 int32_t asm330lhb_den_enable_get(const stmdev_ctx_t *ctx, 2518 asm330lhb_den_xl_g_t *val); 2519 2520 int32_t asm330lhb_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val); 2521 int32_t asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val); 2522 2523 int32_t asm330lhb_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val); 2524 int32_t asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val); 2525 2526 int32_t asm330lhb_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val); 2527 int32_t asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val); 2528 2529 int32_t asm330lhb_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 2530 int32_t asm330lhb_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 2531 2532 int32_t asm330lhb_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val); 2533 int32_t asm330lhb_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val); 2534 2535 int32_t asm330lhb_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val); 2536 int32_t asm330lhb_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val); 2537 2538 typedef enum 2539 { 2540 ASM330LHB_Z_EQ_Y = 0, 2541 ASM330LHB_Z_EQ_MIN_Y = 1, 2542 ASM330LHB_Z_EQ_X = 2, 2543 ASM330LHB_Z_EQ_MIN_X = 3, 2544 ASM330LHB_Z_EQ_MIN_Z = 4, 2545 ASM330LHB_Z_EQ_Z = 5, 2546 } asm330lhb_mag_z_axis_t; 2547 int32_t asm330lhb_mag_z_orient_set(const stmdev_ctx_t *ctx, 2548 asm330lhb_mag_z_axis_t val); 2549 int32_t asm330lhb_mag_z_orient_get(const stmdev_ctx_t *ctx, 2550 asm330lhb_mag_z_axis_t *val); 2551 2552 typedef enum 2553 { 2554 ASM330LHB_Y_EQ_Y = 0, 2555 ASM330LHB_Y_EQ_MIN_Y = 1, 2556 ASM330LHB_Y_EQ_X = 2, 2557 ASM330LHB_Y_EQ_MIN_X = 3, 2558 ASM330LHB_Y_EQ_MIN_Z = 4, 2559 ASM330LHB_Y_EQ_Z = 5, 2560 } asm330lhb_mag_y_axis_t; 2561 int32_t asm330lhb_mag_y_orient_set(const stmdev_ctx_t *ctx, 2562 asm330lhb_mag_y_axis_t val); 2563 int32_t asm330lhb_mag_y_orient_get(const stmdev_ctx_t *ctx, 2564 asm330lhb_mag_y_axis_t *val); 2565 2566 typedef enum 2567 { 2568 ASM330LHB_X_EQ_Y = 0, 2569 ASM330LHB_X_EQ_MIN_Y = 1, 2570 ASM330LHB_X_EQ_X = 2, 2571 ASM330LHB_X_EQ_MIN_X = 3, 2572 ASM330LHB_X_EQ_MIN_Z = 4, 2573 ASM330LHB_X_EQ_Z = 5, 2574 } asm330lhb_mag_x_axis_t; 2575 int32_t asm330lhb_mag_x_orient_set(const stmdev_ctx_t *ctx, 2576 asm330lhb_mag_x_axis_t val); 2577 int32_t asm330lhb_mag_x_orient_get(const stmdev_ctx_t *ctx, 2578 asm330lhb_mag_x_axis_t *val); 2579 2580 typedef struct 2581 { 2582 uint16_t fsm1 : 1; 2583 uint16_t fsm2 : 1; 2584 uint16_t fsm3 : 1; 2585 uint16_t fsm4 : 1; 2586 uint16_t fsm5 : 1; 2587 uint16_t fsm6 : 1; 2588 uint16_t fsm7 : 1; 2589 uint16_t fsm8 : 1; 2590 uint16_t fsm9 : 1; 2591 uint16_t fsm10 : 1; 2592 uint16_t fsm11 : 1; 2593 uint16_t fsm12 : 1; 2594 uint16_t fsm13 : 1; 2595 uint16_t fsm14 : 1; 2596 uint16_t fsm15 : 1; 2597 uint16_t fsm16 : 1; 2598 } asm330lhb_fsm_status_t; 2599 int32_t asm330lhb_fsm_status_get(const stmdev_ctx_t *ctx, 2600 asm330lhb_fsm_status_t *val); 2601 int32_t asm330lhb_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2602 2603 int32_t asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 2604 uint8_t *val); 2605 2606 int32_t asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val); 2607 int32_t asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val); 2608 2609 int32_t asm330lhb_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2610 int32_t asm330lhb_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2611 2612 typedef struct 2613 { 2614 asm330lhb_fsm_enable_a_t fsm_enable_a; 2615 asm330lhb_fsm_enable_b_t fsm_enable_b; 2616 } asm330lhb_emb_fsm_enable_t; 2617 int32_t asm330lhb_fsm_enable_set(const stmdev_ctx_t *ctx, 2618 asm330lhb_emb_fsm_enable_t *val); 2619 int32_t asm330lhb_fsm_enable_get(const stmdev_ctx_t *ctx, 2620 asm330lhb_emb_fsm_enable_t *val); 2621 2622 int32_t asm330lhb_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 2623 int32_t asm330lhb_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 2624 2625 typedef enum 2626 { 2627 ASM330LHB_LC_NORMAL = 0, 2628 ASM330LHB_LC_CLEAR = 1, 2629 ASM330LHB_LC_CLEAR_DONE = 2, 2630 } asm330lhb_fsm_lc_clr_t; 2631 int32_t asm330lhb_long_clr_set(const stmdev_ctx_t *ctx, 2632 asm330lhb_fsm_lc_clr_t val); 2633 int32_t asm330lhb_long_clr_get(const stmdev_ctx_t *ctx, 2634 asm330lhb_fsm_lc_clr_t *val); 2635 2636 typedef enum 2637 { 2638 ASM330LHB_ODR_FSM_12Hz5 = 0, 2639 ASM330LHB_ODR_FSM_26Hz = 1, 2640 ASM330LHB_ODR_FSM_52Hz = 2, 2641 ASM330LHB_ODR_FSM_104Hz = 3, 2642 } asm330lhb_fsm_odr_t; 2643 int32_t asm330lhb_fsm_data_rate_set(const stmdev_ctx_t *ctx, 2644 asm330lhb_fsm_odr_t val); 2645 int32_t asm330lhb_fsm_data_rate_get(const stmdev_ctx_t *ctx, 2646 asm330lhb_fsm_odr_t *val); 2647 2648 int32_t asm330lhb_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 2649 int32_t asm330lhb_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 2650 2651 int32_t asm330lhb_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val); 2652 int32_t asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val); 2653 2654 int32_t asm330lhb_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, 2655 uint8_t *buff); 2656 int32_t asm330lhb_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, 2657 uint8_t *buff); 2658 2659 int32_t asm330lhb_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); 2660 int32_t asm330lhb_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); 2661 2662 int32_t asm330lhb_mlc_set(const stmdev_ctx_t *ctx, uint8_t val); 2663 int32_t asm330lhb_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val); 2664 2665 int32_t asm330lhb_mlc_status_get(const stmdev_ctx_t *ctx, 2666 asm330lhb_mlc_status_mainpage_t *val); 2667 2668 typedef enum 2669 { 2670 ASM330LHB_ODR_PRGS_12Hz5 = 0, 2671 ASM330LHB_ODR_PRGS_26Hz = 1, 2672 ASM330LHB_ODR_PRGS_52Hz = 2, 2673 ASM330LHB_ODR_PRGS_104Hz = 3, 2674 } asm330lhb_mlc_odr_t; 2675 int32_t asm330lhb_mlc_data_rate_set(const stmdev_ctx_t *ctx, 2676 asm330lhb_mlc_odr_t val); 2677 int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx, 2678 asm330lhb_mlc_odr_t *val); 2679 2680 int32_t asm330lhb_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val); 2681 int32_t asm330lhb_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 2682 2683 int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2684 2685 int32_t asm330lhb_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val); 2686 int32_t asm330lhb_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val); 2687 2688 /** 2689 *@} 2690 * 2691 */ 2692 2693 #ifdef __cplusplus 2694 } 2695 #endif 2696 2697 #endif /* ASM330LHB_REGS_H */ 2698 2699 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2700
