1 /*
2 ******************************************************************************
3 * @file asm330lhb_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ASM330LHB driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "asm330lhb_reg.h"
21
22 /**
23 * @defgroup ASM330LHB
24 * @brief This file provides a set of functions needed to drive the
25 * asm330lhb enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup ASM330LHB_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
asm330lhb_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak asm330lhb_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
asm330lhb_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak asm330lhb_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup ASM330LHB_Sensitivity
96 * @brief These functions convert raw-data into engineering units.
97 * @{
98 *
99 */
100
asm330lhb_from_fs2g_to_mg(int16_t lsb)101 float_t asm330lhb_from_fs2g_to_mg(int16_t lsb)
102 {
103 return ((float_t)lsb * 0.061f);
104 }
105
asm330lhb_from_fs4g_to_mg(int16_t lsb)106 float_t asm330lhb_from_fs4g_to_mg(int16_t lsb)
107 {
108 return ((float_t)lsb * 0.122f);
109 }
110
asm330lhb_from_fs8g_to_mg(int16_t lsb)111 float_t asm330lhb_from_fs8g_to_mg(int16_t lsb)
112 {
113 return ((float_t)lsb * 0.244f);
114 }
115
asm330lhb_from_fs16g_to_mg(int16_t lsb)116 float_t asm330lhb_from_fs16g_to_mg(int16_t lsb)
117 {
118 return ((float_t)lsb * 0.488f);
119 }
120
asm330lhb_from_fs125dps_to_mdps(int16_t lsb)121 float_t asm330lhb_from_fs125dps_to_mdps(int16_t lsb)
122 {
123 return ((float_t)lsb * 4.375f);
124 }
125
asm330lhb_from_fs250dps_to_mdps(int16_t lsb)126 float_t asm330lhb_from_fs250dps_to_mdps(int16_t lsb)
127 {
128 return ((float_t)lsb * 8.75f);
129 }
130
asm330lhb_from_fs500dps_to_mdps(int16_t lsb)131 float_t asm330lhb_from_fs500dps_to_mdps(int16_t lsb)
132 {
133 return ((float_t)lsb * 17.50f);
134 }
135
asm330lhb_from_fs1000dps_to_mdps(int16_t lsb)136 float_t asm330lhb_from_fs1000dps_to_mdps(int16_t lsb)
137 {
138 return ((float_t)lsb * 35.0f);
139 }
140
asm330lhb_from_fs2000dps_to_mdps(int16_t lsb)141 float_t asm330lhb_from_fs2000dps_to_mdps(int16_t lsb)
142 {
143 return ((float_t)lsb * 70.0f);
144 }
145
asm330lhb_from_fs4000dps_to_mdps(int16_t lsb)146 float_t asm330lhb_from_fs4000dps_to_mdps(int16_t lsb)
147 {
148 return ((float_t)lsb * 140.0f);
149 }
150
asm330lhb_from_lsb_to_celsius(int16_t lsb)151 float_t asm330lhb_from_lsb_to_celsius(int16_t lsb)
152 {
153 return (((float_t)lsb / 256.0f) + 25.0f);
154 }
155
asm330lhb_from_lsb_to_nsec(int32_t lsb)156 float_t asm330lhb_from_lsb_to_nsec(int32_t lsb)
157 {
158 return ((float_t)lsb * 25000.0f);
159 }
160
161 /**
162 * @}
163 *
164 */
165
166 /**
167 * @defgroup LSM9DS1_Data_generation
168 * @brief This section groups all the functions concerning data
169 * generation
170 * @{
171 *
172 */
173
174 /**
175 * @brief Accelerometer full-scale selection[set]
176 *
177 * @param ctx Read / write interface definitions.(ptr)
178 * @param val Change the values of fs_xl in reg CTRL1_XL
179 * @retval Interface status (MANDATORY: return 0 -> no Error).
180 *
181 */
asm330lhb_xl_full_scale_set(const stmdev_ctx_t * ctx,asm330lhb_fs_xl_t val)182 int32_t asm330lhb_xl_full_scale_set(const stmdev_ctx_t *ctx,
183 asm330lhb_fs_xl_t val)
184 {
185 asm330lhb_ctrl1_xl_t ctrl1_xl;
186 int32_t ret;
187
188 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
189 if (ret == 0)
190 {
191 ctrl1_xl.fs_xl = (uint8_t)val;
192 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
193 (uint8_t *)&ctrl1_xl, 1);
194 }
195 return ret;
196 }
197
198 /**
199 * @brief Accelerometer full-scale selection.[get]
200 *
201 * @param ctx Read / write interface definitions.(ptr)
202 * @param val Get the values of fs_xl in reg CTRL1_XL
203 * @retval Interface status (MANDATORY: return 0 -> no Error).
204 *
205 */
asm330lhb_xl_full_scale_get(const stmdev_ctx_t * ctx,asm330lhb_fs_xl_t * val)206 int32_t asm330lhb_xl_full_scale_get(const stmdev_ctx_t *ctx,
207 asm330lhb_fs_xl_t *val)
208 {
209 asm330lhb_ctrl1_xl_t ctrl1_xl;
210 int32_t ret;
211
212 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
213 switch (ctrl1_xl.fs_xl)
214 {
215 case ASM330LHB_2g:
216 *val = ASM330LHB_2g;
217 break;
218 case ASM330LHB_16g:
219 *val = ASM330LHB_16g;
220 break;
221 case ASM330LHB_4g:
222 *val = ASM330LHB_4g;
223 break;
224 case ASM330LHB_8g:
225 *val = ASM330LHB_8g;
226 break;
227 default:
228 *val = ASM330LHB_2g;
229 break;
230 }
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer UI data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions.(ptr)
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
asm330lhb_xl_data_rate_set(const stmdev_ctx_t * ctx,asm330lhb_odr_xl_t val)242 int32_t asm330lhb_xl_data_rate_set(const stmdev_ctx_t *ctx,
243 asm330lhb_odr_xl_t val)
244 {
245 asm330lhb_odr_xl_t odr_xl = val;
246 asm330lhb_emb_fsm_enable_t fsm_enable;
247 asm330lhb_fsm_odr_t fsm_odr;
248 asm330lhb_ctrl1_xl_t ctrl1_xl;
249 asm330lhb_mlc_odr_t mlc_odr;
250 uint8_t mlc_enable;
251 int32_t ret;
252
253 /* Check the Finite State Machine data rate constraints */
254 ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable);
255 if (ret == 0)
256 {
257 if ((fsm_enable.fsm_enable_a.fsm1_en |
258 fsm_enable.fsm_enable_a.fsm2_en |
259 fsm_enable.fsm_enable_a.fsm3_en |
260 fsm_enable.fsm_enable_a.fsm4_en |
261 fsm_enable.fsm_enable_a.fsm5_en |
262 fsm_enable.fsm_enable_a.fsm6_en |
263 fsm_enable.fsm_enable_a.fsm7_en |
264 fsm_enable.fsm_enable_a.fsm8_en |
265 fsm_enable.fsm_enable_b.fsm9_en |
266 fsm_enable.fsm_enable_b.fsm10_en |
267 fsm_enable.fsm_enable_b.fsm11_en |
268 fsm_enable.fsm_enable_b.fsm12_en |
269 fsm_enable.fsm_enable_b.fsm13_en |
270 fsm_enable.fsm_enable_b.fsm14_en |
271 fsm_enable.fsm_enable_b.fsm15_en |
272 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
273 {
274
275 ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr);
276 if (ret == 0)
277 {
278 switch (fsm_odr)
279 {
280 case ASM330LHB_ODR_FSM_12Hz5:
281
282 if (val == ASM330LHB_XL_ODR_OFF)
283 {
284 odr_xl = ASM330LHB_XL_ODR_12Hz5;
285
286 }
287 else
288 {
289 odr_xl = val;
290 }
291 break;
292 case ASM330LHB_ODR_FSM_26Hz:
293
294 if (val == ASM330LHB_XL_ODR_OFF)
295 {
296 odr_xl = ASM330LHB_XL_ODR_26Hz;
297
298 }
299 else if (val == ASM330LHB_XL_ODR_12Hz5)
300 {
301 odr_xl = ASM330LHB_XL_ODR_26Hz;
302
303 }
304 else
305 {
306 odr_xl = val;
307 }
308 break;
309 case ASM330LHB_ODR_FSM_52Hz:
310
311 if (val == ASM330LHB_XL_ODR_OFF)
312 {
313 odr_xl = ASM330LHB_XL_ODR_52Hz;
314
315 }
316 else if (val == ASM330LHB_XL_ODR_12Hz5)
317 {
318 odr_xl = ASM330LHB_XL_ODR_52Hz;
319
320 }
321 else if (val == ASM330LHB_XL_ODR_26Hz)
322 {
323 odr_xl = ASM330LHB_XL_ODR_52Hz;
324
325 }
326 else
327 {
328 odr_xl = val;
329 }
330 break;
331 case ASM330LHB_ODR_FSM_104Hz:
332
333 if (val == ASM330LHB_XL_ODR_OFF)
334 {
335 odr_xl = ASM330LHB_XL_ODR_104Hz;
336
337 }
338 else if (val == ASM330LHB_XL_ODR_12Hz5)
339 {
340 odr_xl = ASM330LHB_XL_ODR_104Hz;
341
342 }
343 else if (val == ASM330LHB_XL_ODR_26Hz)
344 {
345 odr_xl = ASM330LHB_XL_ODR_104Hz;
346
347 }
348 else if (val == ASM330LHB_XL_ODR_52Hz)
349 {
350 odr_xl = ASM330LHB_XL_ODR_104Hz;
351
352 }
353 else
354 {
355 odr_xl = val;
356 }
357 break;
358 default:
359 odr_xl = val;
360 break;
361 }
362 }
363 }
364 }
365
366 /* Check the Machine Learning Core data rate constraints */
367 mlc_enable = PROPERTY_DISABLE;
368 if (ret == 0)
369 {
370 ret = asm330lhb_mlc_get(ctx, &mlc_enable);
371 if (mlc_enable == PROPERTY_ENABLE)
372 {
373
374 ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr);
375 if (ret == 0)
376 {
377 switch (mlc_odr)
378 {
379 case ASM330LHB_ODR_PRGS_12Hz5:
380
381 if (val == ASM330LHB_XL_ODR_OFF)
382 {
383 odr_xl = ASM330LHB_XL_ODR_12Hz5;
384
385 }
386 else
387 {
388 odr_xl = val;
389 }
390 break;
391 case ASM330LHB_ODR_PRGS_26Hz:
392 if (val == ASM330LHB_XL_ODR_OFF)
393 {
394 odr_xl = ASM330LHB_XL_ODR_26Hz;
395
396 }
397 else if (val == ASM330LHB_XL_ODR_12Hz5)
398 {
399 odr_xl = ASM330LHB_XL_ODR_26Hz;
400
401 }
402 else
403 {
404 odr_xl = val;
405 }
406 break;
407 case ASM330LHB_ODR_PRGS_52Hz:
408
409 if (val == ASM330LHB_XL_ODR_OFF)
410 {
411 odr_xl = ASM330LHB_XL_ODR_52Hz;
412
413 }
414 else if (val == ASM330LHB_XL_ODR_12Hz5)
415 {
416 odr_xl = ASM330LHB_XL_ODR_52Hz;
417
418 }
419 else if (val == ASM330LHB_XL_ODR_26Hz)
420 {
421 odr_xl = ASM330LHB_XL_ODR_52Hz;
422
423 }
424 else
425 {
426 odr_xl = val;
427 }
428 break;
429 case ASM330LHB_ODR_PRGS_104Hz:
430 if (val == ASM330LHB_XL_ODR_OFF)
431 {
432 odr_xl = ASM330LHB_XL_ODR_104Hz;
433
434 }
435 else if (val == ASM330LHB_XL_ODR_12Hz5)
436 {
437 odr_xl = ASM330LHB_XL_ODR_104Hz;
438
439 }
440 else if (val == ASM330LHB_XL_ODR_26Hz)
441 {
442 odr_xl = ASM330LHB_XL_ODR_104Hz;
443
444 }
445 else if (val == ASM330LHB_XL_ODR_52Hz)
446 {
447 odr_xl = ASM330LHB_XL_ODR_104Hz;
448
449 }
450 else
451 {
452 odr_xl = val;
453 }
454 break;
455 default:
456 odr_xl = val;
457 break;
458 }
459 }
460 }
461 }
462
463 if (ret == 0)
464 {
465 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
466 }
467 if (ret == 0)
468 {
469 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
470 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
471 (uint8_t *)&ctrl1_xl, 1);
472 }
473 return ret;
474 }
475
476 /**
477 * @brief Accelerometer UI data rate selection.[get]
478 *
479 * @param ctx Read / write interface definitions.(ptr)
480 * @param val Get the values of odr_xl in reg CTRL1_XL
481 * @retval Interface status (MANDATORY: return 0 -> no Error).
482 *
483 */
asm330lhb_xl_data_rate_get(const stmdev_ctx_t * ctx,asm330lhb_odr_xl_t * val)484 int32_t asm330lhb_xl_data_rate_get(const stmdev_ctx_t *ctx,
485 asm330lhb_odr_xl_t *val)
486 {
487 asm330lhb_ctrl1_xl_t ctrl1_xl;
488 int32_t ret;
489
490 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
491 switch (ctrl1_xl.odr_xl)
492 {
493 case ASM330LHB_XL_ODR_OFF:
494 *val = ASM330LHB_XL_ODR_OFF;
495 break;
496 case ASM330LHB_XL_ODR_12Hz5:
497 *val = ASM330LHB_XL_ODR_12Hz5;
498 break;
499 case ASM330LHB_XL_ODR_26Hz:
500 *val = ASM330LHB_XL_ODR_26Hz;
501 break;
502 case ASM330LHB_XL_ODR_52Hz:
503 *val = ASM330LHB_XL_ODR_52Hz;
504 break;
505 case ASM330LHB_XL_ODR_104Hz:
506 *val = ASM330LHB_XL_ODR_104Hz;
507 break;
508 case ASM330LHB_XL_ODR_208Hz:
509 *val = ASM330LHB_XL_ODR_208Hz;
510 break;
511 case ASM330LHB_XL_ODR_417Hz:
512 *val = ASM330LHB_XL_ODR_417Hz;
513 break;
514 case ASM330LHB_XL_ODR_833Hz:
515 *val = ASM330LHB_XL_ODR_833Hz;
516 break;
517 case ASM330LHB_XL_ODR_1667Hz:
518 *val = ASM330LHB_XL_ODR_1667Hz;
519 break;
520 case ASM330LHB_XL_ODR_1Hz6:
521 *val = ASM330LHB_XL_ODR_1Hz6;
522 break;
523 default:
524 *val = ASM330LHB_XL_ODR_OFF;
525 break;
526 }
527 return ret;
528 }
529
530 /**
531 * @brief Gyroscope UI chain full-scale selection.[set]
532 *
533 * @param ctx Read / write interface definitions.(ptr)
534 * @param val Change the values of fs_g in reg CTRL2_G
535 * @retval Interface status (MANDATORY: return 0 -> no Error).
536 *
537 */
asm330lhb_gy_full_scale_set(const stmdev_ctx_t * ctx,asm330lhb_fs_g_t val)538 int32_t asm330lhb_gy_full_scale_set(const stmdev_ctx_t *ctx,
539 asm330lhb_fs_g_t val)
540 {
541 asm330lhb_ctrl2_g_t ctrl2_g;
542 int32_t ret;
543
544 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
545 if (ret == 0)
546 {
547 ctrl2_g.fs_g = (uint8_t)val;
548 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
549 }
550 return ret;
551 }
552
553 /**
554 * @brief Gyroscope UI chain full-scale selection.[get]
555 *
556 * @param ctx Read / write interface definitions.(ptr)
557 * @param val Get the values of fs_g in reg CTRL2_G
558 * @retval Interface status (MANDATORY: return 0 -> no Error).
559 *
560 */
asm330lhb_gy_full_scale_get(const stmdev_ctx_t * ctx,asm330lhb_fs_g_t * val)561 int32_t asm330lhb_gy_full_scale_get(const stmdev_ctx_t *ctx,
562 asm330lhb_fs_g_t *val)
563 {
564 asm330lhb_ctrl2_g_t ctrl2_g;
565 int32_t ret;
566
567 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
568 switch (ctrl2_g.fs_g)
569 {
570 case ASM330LHB_125dps:
571 *val = ASM330LHB_125dps;
572 break;
573 case ASM330LHB_250dps:
574 *val = ASM330LHB_250dps;
575 break;
576 case ASM330LHB_500dps:
577 *val = ASM330LHB_500dps;
578 break;
579 case ASM330LHB_1000dps:
580 *val = ASM330LHB_1000dps;
581 break;
582 case ASM330LHB_2000dps:
583 *val = ASM330LHB_2000dps;
584 break;
585 case ASM330LHB_4000dps:
586 *val = ASM330LHB_4000dps;
587 break;
588 default:
589 *val = ASM330LHB_125dps;
590 break;
591 }
592 return ret;
593 }
594
595 /**
596 * @brief Gyroscope data rate.[set]
597 *
598 * @param ctx Read / write interface definitions.(ptr)
599 * @param val Change the values of odr_g in reg CTRL2_G
600 * @retval Interface status (MANDATORY: return 0 -> no Error).
601 *
602 */
asm330lhb_gy_data_rate_set(const stmdev_ctx_t * ctx,asm330lhb_odr_g_t val)603 int32_t asm330lhb_gy_data_rate_set(const stmdev_ctx_t *ctx,
604 asm330lhb_odr_g_t val)
605 {
606 asm330lhb_odr_g_t odr_gy = val;
607 asm330lhb_emb_fsm_enable_t fsm_enable;
608 asm330lhb_fsm_odr_t fsm_odr;
609 asm330lhb_ctrl2_g_t ctrl2_g;
610 asm330lhb_mlc_odr_t mlc_odr;
611 uint8_t mlc_enable;
612 int32_t ret;
613
614 /* Check the Finite State Machine data rate constraints */
615 ret = asm330lhb_fsm_enable_get(ctx, &fsm_enable);
616 if (ret == 0)
617 {
618 if ((fsm_enable.fsm_enable_a.fsm1_en |
619 fsm_enable.fsm_enable_a.fsm2_en |
620 fsm_enable.fsm_enable_a.fsm3_en |
621 fsm_enable.fsm_enable_a.fsm4_en |
622 fsm_enable.fsm_enable_a.fsm5_en |
623 fsm_enable.fsm_enable_a.fsm6_en |
624 fsm_enable.fsm_enable_a.fsm7_en |
625 fsm_enable.fsm_enable_a.fsm8_en |
626 fsm_enable.fsm_enable_b.fsm9_en |
627 fsm_enable.fsm_enable_b.fsm10_en |
628 fsm_enable.fsm_enable_b.fsm11_en |
629 fsm_enable.fsm_enable_b.fsm12_en |
630 fsm_enable.fsm_enable_b.fsm13_en |
631 fsm_enable.fsm_enable_b.fsm14_en |
632 fsm_enable.fsm_enable_b.fsm15_en |
633 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
634 {
635
636 ret = asm330lhb_fsm_data_rate_get(ctx, &fsm_odr);
637 if (ret == 0)
638 {
639 switch (fsm_odr)
640 {
641 case ASM330LHB_ODR_FSM_12Hz5:
642
643 if (val == ASM330LHB_GY_ODR_OFF)
644 {
645 odr_gy = ASM330LHB_GY_ODR_12Hz5;
646
647 }
648 else
649 {
650 odr_gy = val;
651 }
652 break;
653 case ASM330LHB_ODR_FSM_26Hz:
654
655 if (val == ASM330LHB_GY_ODR_OFF)
656 {
657 odr_gy = ASM330LHB_GY_ODR_26Hz;
658
659 }
660 else if (val == ASM330LHB_GY_ODR_12Hz5)
661 {
662 odr_gy = ASM330LHB_GY_ODR_26Hz;
663
664 }
665 else
666 {
667 odr_gy = val;
668 }
669 break;
670 case ASM330LHB_ODR_FSM_52Hz:
671
672 if (val == ASM330LHB_GY_ODR_OFF)
673 {
674 odr_gy = ASM330LHB_GY_ODR_52Hz;
675
676 }
677 else if (val == ASM330LHB_GY_ODR_12Hz5)
678 {
679 odr_gy = ASM330LHB_GY_ODR_52Hz;
680
681 }
682 else if (val == ASM330LHB_GY_ODR_26Hz)
683 {
684 odr_gy = ASM330LHB_GY_ODR_52Hz;
685
686 }
687 else
688 {
689 odr_gy = val;
690 }
691 break;
692 case ASM330LHB_ODR_FSM_104Hz:
693
694 if (val == ASM330LHB_GY_ODR_OFF)
695 {
696 odr_gy = ASM330LHB_GY_ODR_104Hz;
697
698 }
699 else if (val == ASM330LHB_GY_ODR_12Hz5)
700 {
701 odr_gy = ASM330LHB_GY_ODR_104Hz;
702
703 }
704 else if (val == ASM330LHB_GY_ODR_26Hz)
705 {
706 odr_gy = ASM330LHB_GY_ODR_104Hz;
707
708 }
709 else if (val == ASM330LHB_GY_ODR_52Hz)
710 {
711 odr_gy = ASM330LHB_GY_ODR_104Hz;
712
713 }
714 else
715 {
716 odr_gy = val;
717 }
718 break;
719 default:
720 odr_gy = val;
721 break;
722 }
723 }
724 }
725 }
726
727 /* Check the Machine Learning Core data rate constraints */
728 mlc_enable = PROPERTY_DISABLE;
729 if (ret == 0)
730 {
731 ret = asm330lhb_mlc_get(ctx, &mlc_enable);
732 if (mlc_enable == PROPERTY_ENABLE)
733 {
734
735 ret = asm330lhb_mlc_data_rate_get(ctx, &mlc_odr);
736 if (ret == 0)
737 {
738 switch (mlc_odr)
739 {
740 case ASM330LHB_ODR_PRGS_12Hz5:
741
742 if (val == ASM330LHB_GY_ODR_OFF)
743 {
744 odr_gy = ASM330LHB_GY_ODR_12Hz5;
745
746 }
747 else
748 {
749 odr_gy = val;
750 }
751 break;
752 case ASM330LHB_ODR_PRGS_26Hz:
753
754 if (val == ASM330LHB_GY_ODR_OFF)
755 {
756 odr_gy = ASM330LHB_GY_ODR_26Hz;
757
758 }
759 else if (val == ASM330LHB_GY_ODR_12Hz5)
760 {
761 odr_gy = ASM330LHB_GY_ODR_26Hz;
762
763 }
764 else
765 {
766 odr_gy = val;
767 }
768 break;
769 case ASM330LHB_ODR_PRGS_52Hz:
770
771 if (val == ASM330LHB_GY_ODR_OFF)
772 {
773 odr_gy = ASM330LHB_GY_ODR_52Hz;
774
775 }
776 else if (val == ASM330LHB_GY_ODR_12Hz5)
777 {
778 odr_gy = ASM330LHB_GY_ODR_52Hz;
779
780 }
781 else if (val == ASM330LHB_GY_ODR_26Hz)
782 {
783 odr_gy = ASM330LHB_GY_ODR_52Hz;
784
785 }
786 else
787 {
788 odr_gy = val;
789 }
790 break;
791 case ASM330LHB_ODR_PRGS_104Hz:
792
793 if (val == ASM330LHB_GY_ODR_OFF)
794 {
795 odr_gy = ASM330LHB_GY_ODR_104Hz;
796
797 }
798 else if (val == ASM330LHB_GY_ODR_12Hz5)
799 {
800 odr_gy = ASM330LHB_GY_ODR_104Hz;
801
802 }
803 else if (val == ASM330LHB_GY_ODR_26Hz)
804 {
805 odr_gy = ASM330LHB_GY_ODR_104Hz;
806
807 }
808 else if (val == ASM330LHB_GY_ODR_52Hz)
809 {
810 odr_gy = ASM330LHB_GY_ODR_104Hz;
811
812 }
813 else
814 {
815 odr_gy = val;
816 }
817 break;
818 default:
819 odr_gy = val;
820 break;
821 }
822 }
823 }
824 }
825
826 if (ret == 0)
827 {
828 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
829 }
830 if (ret == 0)
831 {
832 ctrl2_g.odr_g = (uint8_t)odr_gy;
833 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
834 }
835 return ret;
836 }
837
838 /**
839 * @brief Gyroscope data rate.[get]
840 *
841 * @param ctx Read / write interface definitions.(ptr)
842 * @param val Get the values of odr_g in reg CTRL2_G
843 * @retval Interface status (MANDATORY: return 0 -> no Error).
844 *
845 */
asm330lhb_gy_data_rate_get(const stmdev_ctx_t * ctx,asm330lhb_odr_g_t * val)846 int32_t asm330lhb_gy_data_rate_get(const stmdev_ctx_t *ctx,
847 asm330lhb_odr_g_t *val)
848 {
849 asm330lhb_ctrl2_g_t ctrl2_g;
850 int32_t ret;
851
852 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
853 switch (ctrl2_g.odr_g)
854 {
855 case ASM330LHB_GY_ODR_OFF:
856 *val = ASM330LHB_GY_ODR_OFF;
857 break;
858 case ASM330LHB_GY_ODR_12Hz5:
859 *val = ASM330LHB_GY_ODR_12Hz5;
860 break;
861 case ASM330LHB_GY_ODR_26Hz:
862 *val = ASM330LHB_GY_ODR_26Hz;
863 break;
864 case ASM330LHB_GY_ODR_52Hz:
865 *val = ASM330LHB_GY_ODR_52Hz;
866 break;
867 case ASM330LHB_GY_ODR_104Hz:
868 *val = ASM330LHB_GY_ODR_104Hz;
869 break;
870 case ASM330LHB_GY_ODR_208Hz:
871 *val = ASM330LHB_GY_ODR_208Hz;
872 break;
873 case ASM330LHB_GY_ODR_417Hz:
874 *val = ASM330LHB_GY_ODR_417Hz;
875 break;
876 case ASM330LHB_GY_ODR_833Hz:
877 *val = ASM330LHB_GY_ODR_833Hz;
878 break;
879 case ASM330LHB_GY_ODR_1667Hz:
880 *val = ASM330LHB_GY_ODR_1667Hz;
881 break;
882 default:
883 *val = ASM330LHB_GY_ODR_OFF;
884 break;
885 }
886 return ret;
887 }
888
889 /**
890 * @brief Block data update.[set]
891 *
892 * @param ctx Read / write interface definitions.(ptr)
893 * @param val Change the values of bdu in reg CTRL3_C
894 * @retval Interface status (MANDATORY: return 0 -> no Error).
895 *
896 */
asm330lhb_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)897 int32_t asm330lhb_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
898 {
899 asm330lhb_ctrl3_c_t ctrl3_c;
900 int32_t ret;
901
902 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
903 if (ret == 0)
904 {
905 ctrl3_c.bdu = (uint8_t)val;
906 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
907 }
908 return ret;
909 }
910
911 /**
912 * @brief Block data update.[get]
913 *
914 * @param ctx Read / write interface definitions.(ptr)
915 * @param val Change the values of bdu in reg CTRL3_C
916 * @retval Interface status (MANDATORY: return 0 -> no Error).
917 *
918 */
asm330lhb_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)919 int32_t asm330lhb_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
920 {
921 asm330lhb_ctrl3_c_t ctrl3_c;
922 int32_t ret;
923
924 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
925 *val = ctrl3_c.bdu;
926
927 return ret;
928 }
929
930 /**
931 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
932 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
933 *
934 * @param ctx Read / write interface definitions.(ptr)
935 * @param val Change the values of usr_off_w in reg CTRL6_C
936 * @retval Interface status (MANDATORY: return 0 -> no Error).
937 *
938 */
asm330lhb_xl_offset_weight_set(const stmdev_ctx_t * ctx,asm330lhb_usr_off_w_t val)939 int32_t asm330lhb_xl_offset_weight_set(const stmdev_ctx_t *ctx,
940 asm330lhb_usr_off_w_t val)
941 {
942 asm330lhb_ctrl6_c_t ctrl6_c;
943 int32_t ret;
944
945 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
946 if (ret == 0)
947 {
948 ctrl6_c.usr_off_w = (uint8_t)val;
949 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
950 }
951 return ret;
952 }
953
954 /**
955 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
956 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
957 *
958 * @param ctx Read / write interface definitions.(ptr)
959 * @param val Get the values of usr_off_w in reg CTRL6_C
960 * @retval Interface status (MANDATORY: return 0 -> no Error).
961 *
962 */
asm330lhb_xl_offset_weight_get(const stmdev_ctx_t * ctx,asm330lhb_usr_off_w_t * val)963 int32_t asm330lhb_xl_offset_weight_get(const stmdev_ctx_t *ctx,
964 asm330lhb_usr_off_w_t *val)
965 {
966 asm330lhb_ctrl6_c_t ctrl6_c;
967 int32_t ret;
968
969 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
970
971 switch (ctrl6_c.usr_off_w)
972 {
973 case ASM330LHB_LSb_1mg:
974 *val = ASM330LHB_LSb_1mg;
975 break;
976 case ASM330LHB_LSb_16mg:
977 *val = ASM330LHB_LSb_16mg;
978 break;
979 default:
980 *val = ASM330LHB_LSb_1mg;
981 break;
982 }
983 return ret;
984 }
985
986 /**
987 * @brief Accelerometer power mode.[set]
988 *
989 * @param ctx Read / write interface definitions.(ptr)
990 * @param val Change the values of xl_hm_mode in reg CTRL6_C
991 * @retval Interface status (MANDATORY: return 0 -> no Error).
992 *
993 */
asm330lhb_xl_power_mode_set(const stmdev_ctx_t * ctx,asm330lhb_xl_hm_mode_t val)994 int32_t asm330lhb_xl_power_mode_set(const stmdev_ctx_t *ctx,
995 asm330lhb_xl_hm_mode_t val)
996 {
997 asm330lhb_ctrl6_c_t ctrl6_c;
998 int32_t ret;
999
1000 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1001 if (ret == 0)
1002 {
1003 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1004 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1005 }
1006 return ret;
1007 }
1008
1009 /**
1010 * @brief Accelerometer power mode[get]
1011 *
1012 * @param ctx Read / write interface definitions.(ptr)
1013 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1014 * @retval Interface status (MANDATORY: return 0 -> no Error).
1015 *
1016 */
asm330lhb_xl_power_mode_get(const stmdev_ctx_t * ctx,asm330lhb_xl_hm_mode_t * val)1017 int32_t asm330lhb_xl_power_mode_get(const stmdev_ctx_t *ctx,
1018 asm330lhb_xl_hm_mode_t *val)
1019 {
1020 asm330lhb_ctrl6_c_t ctrl6_c;
1021 int32_t ret;
1022
1023 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1024 switch (ctrl6_c.xl_hm_mode)
1025 {
1026 case ASM330LHB_HIGH_PERFORMANCE_MD:
1027 *val = ASM330LHB_HIGH_PERFORMANCE_MD;
1028 break;
1029 case ASM330LHB_LOW_NORMAL_POWER_MD:
1030 *val = ASM330LHB_LOW_NORMAL_POWER_MD;
1031 break;
1032 default:
1033 *val = ASM330LHB_HIGH_PERFORMANCE_MD;
1034 break;
1035 }
1036 return ret;
1037 }
1038
1039 /**
1040 * @brief Operating mode for gyroscope.[set]
1041 *
1042 * @param ctx Read / write interface definitions.(ptr)
1043 * @param val Change the values of g_hm_mode in reg CTRL7_G
1044 * @retval Interface status (MANDATORY: return 0 -> no Error).
1045 *
1046 */
asm330lhb_gy_power_mode_set(const stmdev_ctx_t * ctx,asm330lhb_g_hm_mode_t val)1047 int32_t asm330lhb_gy_power_mode_set(const stmdev_ctx_t *ctx,
1048 asm330lhb_g_hm_mode_t val)
1049 {
1050 asm330lhb_ctrl7_g_t ctrl7_g;
1051 int32_t ret;
1052
1053 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1054 if (ret == 0)
1055 {
1056 ctrl7_g.g_hm_mode = (uint8_t)val;
1057 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1058 }
1059 return ret;
1060 }
1061
1062 /**
1063 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1064 *
1065 * @param ctx Read / write interface definitions.(ptr)
1066 * @param val Get the values of g_hm_mode in reg CTRL7_G
1067 * @retval Interface status (MANDATORY: return 0 -> no Error).
1068 *
1069 */
asm330lhb_gy_power_mode_get(const stmdev_ctx_t * ctx,asm330lhb_g_hm_mode_t * val)1070 int32_t asm330lhb_gy_power_mode_get(const stmdev_ctx_t *ctx,
1071 asm330lhb_g_hm_mode_t *val)
1072 {
1073 asm330lhb_ctrl7_g_t ctrl7_g;
1074 int32_t ret;
1075
1076 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1077 switch (ctrl7_g.g_hm_mode)
1078 {
1079 case ASM330LHB_GY_HIGH_PERFORMANCE:
1080 *val = ASM330LHB_GY_HIGH_PERFORMANCE;
1081 break;
1082 case ASM330LHB_GY_NORMAL:
1083 *val = ASM330LHB_GY_NORMAL;
1084 break;
1085 default:
1086 *val = ASM330LHB_GY_HIGH_PERFORMANCE;
1087 break;
1088 }
1089 return ret;
1090 }
1091
1092 /**
1093 * @brief Read all the interrupt flag of the device.
1094 *[get]
1095 * @param ctx Read / write interface definitions.(ptr)
1096 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1097 * TAP_SRC; D6D_SRC; STATUS_REG;
1098 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1099 * @retval Interface status (MANDATORY: return 0 -> no Error).
1100 *
1101 */
asm330lhb_all_sources_get(const stmdev_ctx_t * ctx,asm330lhb_all_sources_t * val)1102 int32_t asm330lhb_all_sources_get(const stmdev_ctx_t *ctx,
1103 asm330lhb_all_sources_t *val)
1104 {
1105 int32_t ret;
1106
1107 ret = asm330lhb_read_reg(ctx, ASM330LHB_ALL_INT_SRC,
1108 (uint8_t *)&val->all_int_src, 1);
1109 if (ret == 0)
1110 {
1111 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_SRC,
1112 (uint8_t *)&val->wake_up_src, 1);
1113 }
1114 if (ret == 0)
1115 {
1116 ret = asm330lhb_read_reg(ctx, ASM330LHB_D6D_SRC,
1117 (uint8_t *)&val->d6d_src, 1);
1118 }
1119 if (ret == 0)
1120 {
1121 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1122 (uint8_t *)&val->status_reg, 1);
1123 }
1124 if (ret == 0)
1125 {
1126 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1127 }
1128 if (ret == 0)
1129 {
1130 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS,
1131 (uint8_t *)&val->emb_func_status, 1);
1132 }
1133 if (ret == 0)
1134 {
1135 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A,
1136 (uint8_t *)&val->fsm_status_a, 1);
1137 }
1138 if (ret == 0)
1139 {
1140 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B,
1141 (uint8_t *)&val->fsm_status_b, 1);
1142 }
1143 if (ret == 0)
1144 {
1145 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS,
1146 (uint8_t *)&val->mlc_status, 1);
1147 }
1148 if (ret == 0)
1149 {
1150 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1151 }
1152
1153 return ret;
1154 }
1155
1156 /**
1157 * @brief The STATUS_REG register is read by the primary interface.[get]
1158 *
1159 * @param ctx Read / write interface definitions.(ptr)
1160 * @param val Get register STATUS_REG
1161 * @retval Interface status (MANDATORY: return 0 -> no Error).
1162 *
1163 */
asm330lhb_status_reg_get(const stmdev_ctx_t * ctx,asm330lhb_status_reg_t * val)1164 int32_t asm330lhb_status_reg_get(const stmdev_ctx_t *ctx,
1165 asm330lhb_status_reg_t *val)
1166 {
1167 int32_t ret;
1168 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG, (uint8_t *) val, 1);
1169 return ret;
1170 }
1171
1172 /**
1173 * @brief Accelerometer new data available.[get]
1174 *
1175 * @param ctx Read / write interface definitions.(ptr)
1176 * @param val Get the values of xlda in reg STATUS_REG
1177 * @retval Interface status (MANDATORY: return 0 -> no Error).
1178 *
1179 */
asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1180 int32_t asm330lhb_xl_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1181 {
1182 asm330lhb_status_reg_t status_reg;
1183 int32_t ret;
1184
1185 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1186 (uint8_t *)&status_reg, 1);
1187 *val = status_reg.xlda;
1188
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief Gyroscope new data available.[get]
1194 *
1195 * @param ctx Read / write interface definitions.(ptr)
1196 * @param val Get the values of gda in reg STATUS_REG
1197 * @retval Interface status (MANDATORY: return 0 -> no Error).
1198 *
1199 */
asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1200 int32_t asm330lhb_gy_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1201 {
1202 asm330lhb_status_reg_t status_reg;
1203 int32_t ret;
1204
1205 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1206 (uint8_t *)&status_reg, 1);
1207 *val = status_reg.gda;
1208
1209 return ret;
1210 }
1211
1212 /**
1213 * @brief Temperature new data available.[get]
1214 *
1215 * @param ctx Read / write interface definitions.(ptr)
1216 * @param val Get the values of tda in reg STATUS_REG
1217 * @retval Interface status (MANDATORY: return 0 -> no Error).
1218 *
1219 */
asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1220 int32_t asm330lhb_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1221 {
1222 asm330lhb_status_reg_t status_reg;
1223 int32_t ret;
1224
1225 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1226 (uint8_t *)&status_reg, 1);
1227 *val = status_reg.tda;
1228
1229 return ret;
1230 }
1231
1232 /**
1233 * @brief Device boot status.[get]
1234 *
1235 * @param ctx Read / write interface definitions.(ptr)
1236 * @param val Get the device boot status in reg STATUS_REG.
1237 * 0: OK, 1: FAIL
1238 * @retval Interface status (MANDATORY: return 0 -> no Error).
1239 *
1240 */
asm330lhb_boot_device_status_get(const stmdev_ctx_t * ctx,uint8_t * val)1241 int32_t asm330lhb_boot_device_status_get(const stmdev_ctx_t *ctx, uint8_t *val)
1242 {
1243 asm330lhb_status_reg_t status_reg;
1244 int32_t ret;
1245
1246 ret = asm330lhb_read_reg(ctx, ASM330LHB_STATUS_REG,
1247 (uint8_t *)&status_reg, 1);
1248 *val = status_reg.boot_check_fail;
1249
1250 return ret;
1251 }
1252
1253 /**
1254 * @brief Accelerometer X-axis user offset correction expressed in two’s
1255 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1256 * The value must be in the range [-127 127].[set]
1257 *
1258 * @param ctx Read / write interface definitions.(ptr)
1259 * @param buff Buffer that contains data to write
1260 * @retval Interface status (MANDATORY: return 0 -> no Error).
1261 *
1262 */
asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1263 int32_t asm330lhb_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1264 {
1265 int32_t ret;
1266 ret = asm330lhb_write_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1);
1267 return ret;
1268 }
1269
1270 /**
1271 * @brief Accelerometer X-axis user offset correction expressed in two’s
1272 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1273 * The value must be in the range [-127 127].[get]
1274 *
1275 * @param ctx Read / write interface definitions.(ptr)
1276 * @param buff Buffer that stores data read
1277 * @retval Interface status (MANDATORY: return 0 -> no Error).
1278 *
1279 */
asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1280 int32_t asm330lhb_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1281 {
1282 int32_t ret;
1283 ret = asm330lhb_read_reg(ctx, ASM330LHB_X_OFS_USR, buff, 1);
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1289 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1290 * The value must be in the range [-127 127].[set]
1291 *
1292 * @param ctx Read / write interface definitions.(ptr)
1293 * @param buff Buffer that contains data to write
1294 * @retval Interface status (MANDATORY: return 0 -> no Error).
1295 *
1296 */
asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1297 int32_t asm330lhb_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1298 {
1299 int32_t ret;
1300 ret = asm330lhb_write_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1);
1301 return ret;
1302 }
1303
1304 /**
1305 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1306 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1307 * The value must be in the range [-127 127].[get]
1308 *
1309 * @param ctx Read / write interface definitions.(ptr)
1310 * @param buff Buffer that stores data read
1311 * @retval Interface status (MANDATORY: return 0 -> no Error).
1312 *
1313 */
asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1314 int32_t asm330lhb_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1315 {
1316 int32_t ret;
1317 ret = asm330lhb_read_reg(ctx, ASM330LHB_Y_OFS_USR, buff, 1);
1318 return ret;
1319 }
1320
1321 /**
1322 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1323 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1324 * The value must be in the range [-127 127].[set]
1325 *
1326 * @param ctx Read / write interface definitions.(ptr)
1327 * @param buff Buffer that contains data to write
1328 * @retval Interface status (MANDATORY: return 0 -> no Error).
1329 *
1330 */
asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1331 int32_t asm330lhb_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1332 {
1333 int32_t ret;
1334 ret = asm330lhb_write_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1);
1335 return ret;
1336 }
1337
1338 /**
1339 * @brief Accelerometer X-axis user offset correction expressed in two’s
1340 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1341 * The value must be in the range [-127 127].[get]
1342 *
1343 * @param ctx Read / write interface definitions.(ptr)
1344 * @param buff Buffer that stores data read
1345 * @retval Interface status (MANDATORY: return 0 -> no Error).
1346 *
1347 */
asm330lhb_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1348 int32_t asm330lhb_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1349 {
1350 int32_t ret;
1351 ret = asm330lhb_read_reg(ctx, ASM330LHB_Z_OFS_USR, buff, 1);
1352 return ret;
1353 }
1354
1355 /**
1356 * @brief Enables user offset on out.[set]
1357 *
1358 * @param ctx Read / write interface definitions.(ptr)
1359 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1360 * @retval Interface status (MANDATORY: return 0 -> no Error).
1361 *
1362 */
asm330lhb_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1363 int32_t asm330lhb_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1364 {
1365 asm330lhb_ctrl7_g_t ctrl7_g;
1366 int32_t ret;
1367
1368 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1369 if (ret == 0)
1370 {
1371 ctrl7_g.usr_off_on_out = (uint8_t)val;
1372 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1373 }
1374 return ret;
1375 }
1376
1377 /**
1378 * @brief Get user offset on out flag.[get]
1379 *
1380 * @param ctx Read / write interface definitions.(ptr)
1381 * @param val Get values of usr_off_on_out in reg CTRL7_G
1382 * @retval Interface status (MANDATORY: return 0 -> no Error).
1383 *
1384 */
asm330lhb_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1385 int32_t asm330lhb_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1386 {
1387 asm330lhb_ctrl7_g_t ctrl7_g;
1388 int32_t ret;
1389
1390 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1391 *val = ctrl7_g.usr_off_on_out;
1392
1393 return ret;
1394 }
1395
1396 /**
1397 * @}
1398 *
1399 */
1400
1401 /**
1402 * @defgroup ASM330LHB_Timestamp
1403 * @brief This section groups all the functions that manage the
1404 * timestamp generation.
1405 * @{
1406 *
1407 */
1408
1409 /**
1410 * @brief Reset timestamp counter.[set]
1411 *
1412 * @param ctx Read / write interface definitions.(ptr)
1413 * @retval Interface status (MANDATORY: return 0 -> no Error).
1414 *
1415 */
asm330lhb_timestamp_rst(const stmdev_ctx_t * ctx)1416 int32_t asm330lhb_timestamp_rst(const stmdev_ctx_t *ctx)
1417 {
1418 uint8_t rst_val = 0xAA;
1419
1420 return asm330lhb_write_reg(ctx, ASM330LHB_TIMESTAMP2, &rst_val, 1);
1421 }
1422
1423 /**
1424 * @brief Enables timestamp counter.[set]
1425 *
1426 * @param ctx Read / write interface definitions.(ptr)
1427 * @param val Change the values of timestamp_en in reg CTRL10_C
1428 * @retval Interface status (MANDATORY: return 0 -> no Error).
1429 *
1430 */
asm330lhb_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1431 int32_t asm330lhb_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1432 {
1433 asm330lhb_ctrl10_c_t ctrl10_c;
1434 int32_t ret;
1435
1436 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1437 if (ret == 0)
1438 {
1439 ctrl10_c.timestamp_en = (uint8_t)val;
1440 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL10_C,
1441 (uint8_t *)&ctrl10_c, 1);
1442 }
1443 return ret;
1444 }
1445
1446 /**
1447 * @brief Enables timestamp counter.[get]
1448 *
1449 * @param ctx Read / write interface definitions.(ptr)
1450 * @param val Change the values of timestamp_en in reg CTRL10_C
1451 * @retval Interface status (MANDATORY: return 0 -> no Error).
1452 *
1453 */
asm330lhb_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1454 int32_t asm330lhb_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1455 {
1456 asm330lhb_ctrl10_c_t ctrl10_c;
1457 int32_t ret;
1458
1459 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1460 *val = ctrl10_c.timestamp_en;
1461
1462 return ret;
1463 }
1464
1465 /**
1466 * @brief Timestamp first data output register (r).
1467 * The value is expressed as a 32-bit word and the bit resolution
1468 * is 25 μs.[get]
1469 *
1470 * @param ctx Read / write interface definitions.(ptr)
1471 * @param buff Buffer that stores data read
1472 * @retval Interface status (MANDATORY: return 0 -> no Error).
1473 *
1474 */
asm330lhb_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1475 int32_t asm330lhb_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1476 {
1477 uint8_t buff[4];
1478 int32_t ret;
1479
1480 ret = asm330lhb_read_reg(ctx, ASM330LHB_TIMESTAMP0, buff, 4);
1481 *val = buff[3];
1482 *val = (*val * 256U) + buff[2];
1483 *val = (*val * 256U) + buff[1];
1484 *val = (*val * 256U) + buff[0];
1485
1486 return ret;
1487 }
1488
1489 /**
1490 * @}
1491 *
1492 */
1493
1494 /**
1495 * @defgroup ASM330LHB_Data output
1496 * @brief This section groups all the data output functions.
1497 * @{
1498 *
1499 */
1500
1501 /**
1502 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1503 *
1504 * @param ctx Read / write interface definitions.(ptr)
1505 * @param val Change the values of rounding in reg CTRL5_C
1506 * @retval Interface status (MANDATORY: return 0 -> no Error).
1507 *
1508 */
asm330lhb_rounding_mode_set(const stmdev_ctx_t * ctx,asm330lhb_rounding_t val)1509 int32_t asm330lhb_rounding_mode_set(const stmdev_ctx_t *ctx,
1510 asm330lhb_rounding_t val)
1511 {
1512 asm330lhb_ctrl5_c_t ctrl5_c;
1513 int32_t ret;
1514
1515 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1516 if (ret == 0)
1517 {
1518 ctrl5_c.rounding = (uint8_t)val;
1519 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1520 }
1521 return ret;
1522 }
1523
1524 /**
1525 * @brief Gyroscope UI chain full-scale selection.[get]
1526 *
1527 * @param ctx Read / write interface definitions.(ptr)
1528 * @param val Get the values of rounding in reg CTRL5_C
1529 * @retval Interface status (MANDATORY: return 0 -> no Error).
1530 *
1531 */
asm330lhb_rounding_mode_get(const stmdev_ctx_t * ctx,asm330lhb_rounding_t * val)1532 int32_t asm330lhb_rounding_mode_get(const stmdev_ctx_t *ctx,
1533 asm330lhb_rounding_t *val)
1534 {
1535 asm330lhb_ctrl5_c_t ctrl5_c;
1536 int32_t ret;
1537
1538 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1539 switch (ctrl5_c.rounding)
1540 {
1541 case ASM330LHB_NO_ROUND:
1542 *val = ASM330LHB_NO_ROUND;
1543 break;
1544 case ASM330LHB_ROUND_XL:
1545 *val = ASM330LHB_ROUND_XL;
1546 break;
1547 case ASM330LHB_ROUND_GY:
1548 *val = ASM330LHB_ROUND_GY;
1549 break;
1550 case ASM330LHB_ROUND_GY_XL:
1551 *val = ASM330LHB_ROUND_GY_XL;
1552 break;
1553 default:
1554 *val = ASM330LHB_NO_ROUND;
1555 break;
1556 }
1557 return ret;
1558 }
1559
1560 /**
1561 * @brief Temperature data output register (r).
1562 * L and H registers together express a 16-bit word in two’s
1563 * complement.[get]
1564 *
1565 * @param ctx Read / write interface definitions.(ptr)
1566 * @param buff Buffer that stores data read
1567 * @retval Interface status (MANDATORY: return 0 -> no Error).
1568 *
1569 */
asm330lhb_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1570 int32_t asm330lhb_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1571 {
1572 uint8_t buff[2];
1573 int32_t ret;
1574
1575 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUT_TEMP_L, buff, 2);
1576 *val = (int16_t)buff[1];
1577 *val = (*val * 256) + (int16_t)buff[0];
1578
1579 return ret;
1580 }
1581
1582 /**
1583 * @brief Angular rate sensor. The value is expressed as a 16-bit
1584 * word in two’s complement.[get]
1585 *
1586 * @param ctx Read / write interface definitions.(ptr)
1587 * @param buff Buffer that stores data read
1588 * @retval Interface status (MANDATORY: return 0 -> no Error).
1589 *
1590 */
asm330lhb_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1591 int32_t asm330lhb_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1592 {
1593 uint8_t buff[6];
1594 int32_t ret;
1595 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_G, buff, 6);
1596
1597 val[0] = (int16_t)buff[1];
1598 val[0] = (val[0] * 256) + (int16_t)buff[0];
1599 val[1] = (int16_t)buff[3];
1600 val[1] = (val[1] * 256) + (int16_t)buff[2];
1601 val[2] = (int16_t)buff[5];
1602 val[2] = (val[2] * 256) + (int16_t)buff[4];
1603
1604 return ret;
1605 }
1606
1607 /**
1608 * @brief Linear acceleration output register. The value is expressed as a
1609 * 16-bit word in two’s complement.[get]
1610 *
1611 * @param ctx Read / write interface definitions.(ptr)
1612 * @param buff Buffer that stores data read
1613 * @retval Interface status (MANDATORY: return 0 -> no Error).
1614 *
1615 */
asm330lhb_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1616 int32_t asm330lhb_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1617 {
1618 uint8_t buff[6];
1619 int32_t ret;
1620 ret = asm330lhb_read_reg(ctx, ASM330LHB_OUTX_L_A, buff, 6);
1621
1622 val[0] = (int16_t)buff[1];
1623 val[0] = (val[0] * 256) + (int16_t)buff[0];
1624 val[1] = (int16_t)buff[3];
1625 val[1] = (val[1] * 256) + (int16_t)buff[2];
1626 val[2] = (int16_t)buff[5];
1627 val[2] = (val[2] * 256) + (int16_t)buff[4];
1628
1629 return ret;
1630 }
1631
1632 /**
1633 * @brief FIFO data output.[get]
1634 *
1635 * @param ctx Read / write interface definitions.(ptr)
1636 * @param buff Buffer that stores data read
1637 * @retval Interface status (MANDATORY: return 0 -> no Error).
1638 *
1639 */
asm330lhb_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * val)1640 int32_t asm330lhb_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *val)
1641 {
1642 int32_t ret;
1643 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_X_L, val, 6);
1644 return ret;
1645 }
1646
1647 /**
1648 * @}
1649 *
1650 */
1651
1652 /**
1653 * @defgroup ASM330LHB_common
1654 * @brief This section groups common useful functions.
1655 * @{
1656 *
1657 */
1658
1659 /**
1660 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1661 * with respect to the typical.[set]
1662 * Step: 0.15%. 8-bit format, 2's complement.
1663 *
1664 * @param ctx Read / write interface definitions.(ptr)
1665 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1666 * @retval Interface status (MANDATORY: return 0 -> no Error).
1667 *
1668 */
asm330lhb_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1669 int32_t asm330lhb_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1670 {
1671 asm330lhb_internal_freq_fine_t internal_freq_fine;
1672 int32_t ret;
1673
1674 ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1675 (uint8_t *)&internal_freq_fine, 1);
1676 if (ret == 0)
1677 {
1678 internal_freq_fine.freq_fine = (uint8_t)val;
1679 ret = asm330lhb_write_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1680 (uint8_t *)&internal_freq_fine, 1);
1681 }
1682 return ret;
1683 }
1684
1685 /**
1686 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1687 * with respect to the typical.[get]
1688 * Step: 0.15%. 8-bit format, 2's complement.
1689 *
1690 * @param ctx Read / write interface definitions.(ptr)
1691 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1692 * @retval Interface status (MANDATORY: return 0 -> no Error).
1693 *
1694 */
asm330lhb_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1695 int32_t asm330lhb_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1696 {
1697 asm330lhb_internal_freq_fine_t internal_freq_fine;
1698 int32_t ret;
1699
1700 ret = asm330lhb_read_reg(ctx, ASM330LHB_INTERNAL_FREQ_FINE,
1701 (uint8_t *)&internal_freq_fine, 1);
1702 *val = internal_freq_fine.freq_fine;
1703
1704 return ret;
1705 }
1706
1707 /**
1708 * @brief Enable access to the embedded functions/sensor hub configuration
1709 * registers.[set]
1710 *
1711 * @param ctx Read / write interface definitions.(ptr)
1712 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1713 * @retval Interface status (MANDATORY: return 0 -> no Error).
1714 *
1715 */
asm330lhb_mem_bank_set(const stmdev_ctx_t * ctx,asm330lhb_reg_access_t val)1716 int32_t asm330lhb_mem_bank_set(const stmdev_ctx_t *ctx,
1717 asm330lhb_reg_access_t val)
1718 {
1719 asm330lhb_func_cfg_access_t func_cfg_access;
1720 int32_t ret;
1721
1722 ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1723 (uint8_t *)&func_cfg_access, 1);
1724 if (ret == 0)
1725 {
1726 func_cfg_access.reg_access = (uint8_t)val;
1727 ret = asm330lhb_write_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1728 (uint8_t *)&func_cfg_access, 1);
1729 }
1730 return ret;
1731 }
1732
1733 /**
1734 * @brief Enable access to the embedded functions/sensor hub configuration
1735 * registers.[get]
1736 *
1737 * @param ctx Read / write interface definitions.(ptr)
1738 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1739 * @retval Interface status (MANDATORY: return 0 -> no Error).
1740 *
1741 */
asm330lhb_mem_bank_get(const stmdev_ctx_t * ctx,asm330lhb_reg_access_t * val)1742 int32_t asm330lhb_mem_bank_get(const stmdev_ctx_t *ctx,
1743 asm330lhb_reg_access_t *val)
1744 {
1745 asm330lhb_func_cfg_access_t func_cfg_access;
1746 int32_t ret;
1747
1748 ret = asm330lhb_read_reg(ctx, ASM330LHB_FUNC_CFG_ACCESS,
1749 (uint8_t *)&func_cfg_access, 1);
1750 switch (func_cfg_access.reg_access)
1751 {
1752 case ASM330LHB_USER_BANK:
1753 *val = ASM330LHB_USER_BANK;
1754 break;
1755 case ASM330LHB_EMBEDDED_FUNC_BANK:
1756 *val = ASM330LHB_EMBEDDED_FUNC_BANK;
1757 break;
1758 default:
1759 *val = ASM330LHB_USER_BANK;
1760 break;
1761 }
1762 return ret;
1763 }
1764
1765 /**
1766 * @brief Write a line(byte) in a page.[set]
1767 *
1768 * @param ctx Read / write interface definitions.(ptr)
1769 * @param add Page line address
1770 * @param val Value to write
1771 * @retval Interface status (MANDATORY: return 0 -> no Error).
1772 *
1773 */
asm330lhb_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1774 int32_t asm330lhb_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
1775 uint8_t *val)
1776 {
1777 asm330lhb_page_rw_t page_rw;
1778 asm330lhb_page_sel_t page_sel;
1779 asm330lhb_page_address_t page_address;
1780 int32_t ret;
1781
1782 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1783 if (ret == 0)
1784 {
1785 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1786 }
1787 if (ret == 0)
1788 {
1789 page_rw.page_rw = 0x02U; /* page_write enable */
1790 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1791 }
1792 if (ret == 0)
1793 {
1794 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1795 }
1796 if (ret == 0)
1797 {
1798 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1799 page_sel.not_used_01 = 1;
1800 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1801 (uint8_t *)&page_sel, 1);
1802 }
1803 if (ret == 0)
1804 {
1805 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1806 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1807 (uint8_t *)&page_address, 1);
1808 }
1809 if (ret == 0)
1810 {
1811 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, val, 1);
1812 }
1813 if (ret == 0)
1814 {
1815 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1816 }
1817 if (ret == 0)
1818 {
1819 page_rw.page_rw = 0x00; /* page_write disable */
1820 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1821 }
1822 if (ret == 0)
1823 {
1824 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1825 }
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief Write buffer in a page.[set]
1831 *
1832 * @param ctx Read / write interface definitions.(ptr)
1833 * @param buf Page line address.(ptr)
1834 * @param val Value to write.
1835 * @param len buffer lenght.
1836 * @retval Interface status (MANDATORY: return 0 -> no Error).
1837 *
1838 */
asm330lhb_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1839 int32_t asm330lhb_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
1840 uint8_t *buf, uint8_t len)
1841 {
1842 asm330lhb_page_rw_t page_rw;
1843 asm330lhb_page_sel_t page_sel;
1844 asm330lhb_page_address_t page_address;
1845 int32_t ret;
1846 uint8_t msb, lsb;
1847 uint8_t i ;
1848
1849 msb = (uint8_t)(add / 256U);
1850 lsb = (uint8_t)(add - (msb * 256U));
1851
1852 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1853 if (ret == 0)
1854 {
1855 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1856 }
1857 if (ret == 0)
1858 {
1859 page_rw.page_rw = 0x02U; /* page_write enable*/
1860 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1861 }
1862 if (ret == 0)
1863 {
1864 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1865 }
1866 if (ret == 0)
1867 {
1868 page_sel.page_sel = msb;
1869 page_sel.not_used_01 = 1;
1870 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1871 (uint8_t *)&page_sel, 1);
1872 }
1873 if (ret == 0)
1874 {
1875 page_address.page_addr = lsb;
1876 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1877 (uint8_t *)&page_address, 1);
1878 }
1879 for (i = 0; i < len; i++)
1880 {
1881 if (ret == 0)
1882 {
1883 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_VALUE, &buf[i], 1);
1884 if (ret == 0)
1885 {
1886 /* Check if page wrap */
1887 if (lsb == 0x00U)
1888 {
1889 msb++;
1890 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
1891 (uint8_t *)&page_sel, 1);
1892 }
1893 lsb++;
1894 }
1895 if (ret == 0)
1896 {
1897 page_sel.page_sel = msb;
1898 page_sel.not_used_01 = 1;
1899 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1900 (uint8_t *)&page_sel, 1);
1901 }
1902 }
1903 }
1904
1905 if (ret == 0)
1906 {
1907 page_sel.page_sel = 0;
1908 page_sel.not_used_01 = 1;
1909 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1910 (uint8_t *)&page_sel, 1);
1911 }
1912 if (ret == 0)
1913 {
1914 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1915 }
1916 if (ret == 0)
1917 {
1918 page_rw.page_rw = 0x00U; /* page_write disable */
1919 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1920 }
1921 if (ret == 0)
1922 {
1923 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1924 }
1925 return ret;
1926 }
1927
1928 /**
1929 * @brief Read a line(byte) in a page.[get]
1930 *
1931 * @param ctx Read / write interface definitions.(ptr)
1932 * @param add Page line address.
1933 * @param val Read value.(ptr)
1934 * @retval Interface status (MANDATORY: return 0 -> no Error).
1935 *
1936 */
asm330lhb_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1937 int32_t asm330lhb_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
1938 uint8_t *val)
1939 {
1940 asm330lhb_page_rw_t page_rw;
1941 asm330lhb_page_sel_t page_sel;
1942 asm330lhb_page_address_t page_address;
1943 int32_t ret;
1944
1945 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
1946 if (ret == 0)
1947 {
1948 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1949 }
1950 if (ret == 0)
1951 {
1952 page_rw.page_rw = 0x01U; /* page_read enable*/
1953 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1954 }
1955 if (ret == 0)
1956 {
1957 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL, (uint8_t *)&page_sel, 1);
1958 }
1959 if (ret == 0)
1960 {
1961 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
1962 page_sel.not_used_01 = 1;
1963 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_SEL,
1964 (uint8_t *)&page_sel, 1);
1965 }
1966 if (ret == 0)
1967 {
1968 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
1969 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_ADDRESS,
1970 (uint8_t *)&page_address, 1);
1971 }
1972 if (ret == 0)
1973 {
1974 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_VALUE, val, 2);
1975 }
1976 if (ret == 0)
1977 {
1978 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1979 }
1980 if (ret == 0)
1981 {
1982 page_rw.page_rw = 0x00U; /* page_read disable */
1983 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
1984 }
1985 if (ret == 0)
1986 {
1987 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
1988 }
1989 return ret;
1990 }
1991
1992 /**
1993 * @brief Data-ready pulsed / letched mode.[set]
1994 *
1995 * @param ctx Read / write interface definitions.(ptr)
1996 * @param val Change the values of dataready_pulsed in
1997 * reg COUNTER_BDR_REG1
1998 * @retval Interface status (MANDATORY: return 0 -> no Error).
1999 *
2000 */
asm330lhb_data_ready_mode_set(const stmdev_ctx_t * ctx,asm330lhb_dataready_pulsed_t val)2001 int32_t asm330lhb_data_ready_mode_set(const stmdev_ctx_t *ctx,
2002 asm330lhb_dataready_pulsed_t val)
2003 {
2004 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
2005 int32_t ret;
2006
2007 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
2008 (uint8_t *)&counter_bdr_reg1, 1);
2009 if (ret == 0)
2010 {
2011 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2012 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
2013 (uint8_t *)&counter_bdr_reg1, 1);
2014 }
2015 return ret;
2016 }
2017
2018 /**
2019 * @brief Data-ready pulsed / letched mode.[get]
2020 *
2021 * @param ctx Read / write interface definitions.(ptr)
2022 * @param val Get the values of dataready_pulsed in
2023 * reg COUNTER_BDR_REG1
2024 * @retval Interface status (MANDATORY: return 0 -> no Error).
2025 *
2026 */
asm330lhb_data_ready_mode_get(const stmdev_ctx_t * ctx,asm330lhb_dataready_pulsed_t * val)2027 int32_t asm330lhb_data_ready_mode_get(const stmdev_ctx_t *ctx,
2028 asm330lhb_dataready_pulsed_t *val)
2029 {
2030 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
2031 int32_t ret;
2032
2033 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
2034 (uint8_t *)&counter_bdr_reg1, 1);
2035 switch (counter_bdr_reg1.dataready_pulsed)
2036 {
2037 case ASM330LHB_DRDY_LATCHED:
2038 *val = ASM330LHB_DRDY_LATCHED;
2039 break;
2040 case ASM330LHB_DRDY_PULSED:
2041 *val = ASM330LHB_DRDY_PULSED;
2042 break;
2043 default:
2044 *val = ASM330LHB_DRDY_LATCHED;
2045 break;
2046 }
2047 return ret;
2048 }
2049
2050 /**
2051 * @brief Device Who am I.[get]
2052 *
2053 * @param ctx Read / write interface definitions.(ptr)
2054 * @param buff Buffer that stores data read
2055 * @retval Interface status (MANDATORY: return 0 -> no Error).
2056 *
2057 */
asm330lhb_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2058 int32_t asm330lhb_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2059 {
2060 int32_t ret;
2061 ret = asm330lhb_read_reg(ctx, ASM330LHB_WHO_AM_I, buff, 1);
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Software reset. Restore the default values in user registers.[set]
2067 *
2068 * @param ctx Read / write interface definitions.(ptr)
2069 * @param val Change the values of sw_reset in reg CTRL3_C
2070 * @retval Interface status (MANDATORY: return 0 -> no Error).
2071 *
2072 */
asm330lhb_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2073 int32_t asm330lhb_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2074 {
2075 asm330lhb_ctrl3_c_t ctrl3_c;
2076 int32_t ret;
2077
2078 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2079 if (ret == 0)
2080 {
2081 ctrl3_c.sw_reset = (uint8_t)val;
2082 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2083 }
2084 return ret;
2085 }
2086
2087 /**
2088 * @brief Software reset. Restore the default values in user registers.[get]
2089 *
2090 * @param ctx Read / write interface definitions.(ptr)
2091 * @param val Change the values of sw_reset in reg CTRL3_C
2092 * @retval Interface status (MANDATORY: return 0 -> no Error).
2093 *
2094 */
asm330lhb_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2095 int32_t asm330lhb_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2096 {
2097 asm330lhb_ctrl3_c_t ctrl3_c;
2098 int32_t ret;
2099
2100 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2101 *val = ctrl3_c.sw_reset;
2102
2103 return ret;
2104 }
2105
2106 /**
2107 * @brief Register address automatically incremented during a multiple byte
2108 * access with a serial interface.[set]
2109 *
2110 * @param ctx Read / write interface definitions.(ptr)
2111 * @param val Change the values of if_inc in reg CTRL3_C
2112 * @retval Interface status (MANDATORY: return 0 -> no Error).
2113 *
2114 */
asm330lhb_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2115 int32_t asm330lhb_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2116 {
2117 asm330lhb_ctrl3_c_t ctrl3_c;
2118 int32_t ret;
2119
2120 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2121 if (ret == 0)
2122 {
2123 ctrl3_c.if_inc = (uint8_t)val;
2124 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2125 }
2126 return ret;
2127 }
2128
2129 /**
2130 * @brief Register address automatically incremented during a multiple byte
2131 * access with a serial interface.[get]
2132 *
2133 * @param ctx Read / write interface definitions.(ptr)
2134 * @param val Change the values of if_inc in reg CTRL3_C
2135 * @retval Interface status (MANDATORY: return 0 -> no Error).
2136 *
2137 */
asm330lhb_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2138 int32_t asm330lhb_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2139 {
2140 asm330lhb_ctrl3_c_t ctrl3_c;
2141 int32_t ret;
2142
2143 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2144 *val = ctrl3_c.if_inc;
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Reboot memory content. Reload the calibration parameters.[set]
2151 *
2152 * @param ctx Read / write interface definitions.(ptr)
2153 * @param val Change the values of boot in reg CTRL3_C
2154 * @retval Interface status (MANDATORY: return 0 -> no Error).
2155 *
2156 */
asm330lhb_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2157 int32_t asm330lhb_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2158 {
2159 asm330lhb_ctrl3_c_t ctrl3_c;
2160 int32_t ret;
2161
2162 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2163 if (ret == 0)
2164 {
2165 ctrl3_c.boot = (uint8_t)val;
2166 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2167 }
2168 return ret;
2169 }
2170
2171 /**
2172 * @brief Reboot memory content. Reload the calibration parameters.[get]
2173 *
2174 * @param ctx Read / write interface definitions.(ptr)
2175 * @param val Change the values of boot in reg CTRL3_C
2176 * @retval Interface status (MANDATORY: return 0 -> no Error).
2177 *
2178 */
asm330lhb_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2179 int32_t asm330lhb_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2180 {
2181 asm330lhb_ctrl3_c_t ctrl3_c;
2182 int32_t ret;
2183
2184 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2185 *val = ctrl3_c.boot;
2186
2187 return ret;
2188 }
2189
2190
2191
2192 /**
2193 * @brief Linear acceleration sensor self-test enable.[set]
2194 *
2195 * @param ctx Read / write interface definitions.(ptr)
2196 * @param val Change the values of st_xl in reg CTRL5_C
2197 * @retval Interface status (MANDATORY: return 0 -> no Error).
2198 *
2199 */
asm330lhb_xl_self_test_set(const stmdev_ctx_t * ctx,asm330lhb_st_xl_t val)2200 int32_t asm330lhb_xl_self_test_set(const stmdev_ctx_t *ctx,
2201 asm330lhb_st_xl_t val)
2202 {
2203 asm330lhb_ctrl5_c_t ctrl5_c;
2204 int32_t ret;
2205
2206 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2207 if (ret == 0)
2208 {
2209 ctrl5_c.st_xl = (uint8_t)val;
2210 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2211 }
2212 return ret;
2213 }
2214
2215 /**
2216 * @brief Linear acceleration sensor self-test enable.[get]
2217 *
2218 * @param ctx Read / write interface definitions.(ptr)
2219 * @param val Get the values of st_xl in reg CTRL5_C
2220 * @retval Interface status (MANDATORY: return 0 -> no Error).
2221 *
2222 */
asm330lhb_xl_self_test_get(const stmdev_ctx_t * ctx,asm330lhb_st_xl_t * val)2223 int32_t asm330lhb_xl_self_test_get(const stmdev_ctx_t *ctx,
2224 asm330lhb_st_xl_t *val)
2225 {
2226 asm330lhb_ctrl5_c_t ctrl5_c;
2227 int32_t ret;
2228
2229 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2230
2231 switch (ctrl5_c.st_xl)
2232 {
2233 case ASM330LHB_XL_ST_DISABLE:
2234 *val = ASM330LHB_XL_ST_DISABLE;
2235 break;
2236 case ASM330LHB_XL_ST_POSITIVE:
2237 *val = ASM330LHB_XL_ST_POSITIVE;
2238 break;
2239 case ASM330LHB_XL_ST_NEGATIVE:
2240 *val = ASM330LHB_XL_ST_NEGATIVE;
2241 break;
2242 default:
2243 *val = ASM330LHB_XL_ST_DISABLE;
2244 break;
2245 }
2246 return ret;
2247 }
2248
2249 /**
2250 * @brief Angular rate sensor self-test enable.[set]
2251 *
2252 * @param ctx Read / write interface definitions.(ptr)
2253 * @param val Change the values of st_g in reg CTRL5_C
2254 * @retval Interface status (MANDATORY: return 0 -> no Error).
2255 *
2256 */
asm330lhb_gy_self_test_set(const stmdev_ctx_t * ctx,asm330lhb_st_g_t val)2257 int32_t asm330lhb_gy_self_test_set(const stmdev_ctx_t *ctx,
2258 asm330lhb_st_g_t val)
2259 {
2260 asm330lhb_ctrl5_c_t ctrl5_c;
2261 int32_t ret;
2262
2263 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2264 if (ret == 0)
2265 {
2266 ctrl5_c.st_g = (uint8_t)val;
2267 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2268 }
2269 return ret;
2270 }
2271
2272 /**
2273 * @brief Angular rate sensor self-test enable.[get]
2274 *
2275 * @param ctx Read / write interface definitions.(ptr)
2276 * @param val Get the values of st_g in reg CTRL5_C
2277 * @retval Interface status (MANDATORY: return 0 -> no Error).
2278 *
2279 */
asm330lhb_gy_self_test_get(const stmdev_ctx_t * ctx,asm330lhb_st_g_t * val)2280 int32_t asm330lhb_gy_self_test_get(const stmdev_ctx_t *ctx,
2281 asm330lhb_st_g_t *val)
2282 {
2283 asm330lhb_ctrl5_c_t ctrl5_c;
2284 int32_t ret;
2285
2286 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2287
2288 switch (ctrl5_c.st_g)
2289 {
2290 case ASM330LHB_GY_ST_DISABLE:
2291 *val = ASM330LHB_GY_ST_DISABLE;
2292 break;
2293 case ASM330LHB_GY_ST_POSITIVE:
2294 *val = ASM330LHB_GY_ST_POSITIVE;
2295 break;
2296 case ASM330LHB_GY_ST_NEGATIVE:
2297 *val = ASM330LHB_GY_ST_NEGATIVE;
2298 break;
2299 default:
2300 *val = ASM330LHB_GY_ST_DISABLE;
2301 break;
2302 }
2303 return ret;
2304 }
2305
2306 /**
2307 * @}
2308 *
2309 */
2310
2311 /**
2312 * @defgroup ASM330LHB_filters
2313 * @brief This section group all the functions concerning the
2314 * filters configuration
2315 * @{
2316 *
2317 */
2318
2319 /**
2320 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2321 *
2322 * @param ctx Read / write interface definitions.(ptr)
2323 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2324 * @retval Interface status (MANDATORY: return 0 -> no Error).
2325 *
2326 */
asm330lhb_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2327 int32_t asm330lhb_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2328 {
2329 asm330lhb_ctrl1_xl_t ctrl1_xl;
2330 int32_t ret;
2331
2332 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2333 if (ret == 0)
2334 {
2335 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2336 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL1_XL,
2337 (uint8_t *)&ctrl1_xl, 1);
2338 }
2339 return ret;
2340 }
2341
2342 /**
2343 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2344 *
2345 * @param ctx Read / write interface definitions.(ptr)
2346 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2347 * @retval Interface status (MANDATORY: return 0 -> no Error).
2348 *
2349 */
asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2350 int32_t asm330lhb_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2351 {
2352 asm330lhb_ctrl1_xl_t ctrl1_xl;
2353 int32_t ret;
2354
2355 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2356 *val = ctrl1_xl.lpf2_xl_en;
2357
2358 return ret;
2359 }
2360
2361 /**
2362 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2363 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2364 *
2365 * @param ctx Read / write interface definitions.(ptr)
2366 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2367 * @retval Interface status (MANDATORY: return 0 -> no Error).
2368 *
2369 */
asm330lhb_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2370 int32_t asm330lhb_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2371 {
2372 asm330lhb_ctrl4_c_t ctrl4_c;
2373 int32_t ret;
2374
2375 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2376 if (ret == 0)
2377 {
2378 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2379 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2380 }
2381 return ret;
2382 }
2383
2384 /**
2385 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2386 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2387 *
2388 * @param ctx Read / write interface definitions.(ptr)
2389 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2390 * @retval Interface status (MANDATORY: return 0 -> no Error).
2391 *
2392 */
asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2393 int32_t asm330lhb_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2394 {
2395 asm330lhb_ctrl4_c_t ctrl4_c;
2396 int32_t ret;
2397
2398 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2399 *val = ctrl4_c.lpf1_sel_g;
2400
2401 return ret;
2402 }
2403
2404 /**
2405 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2406 * (XL and Gyro independently masked).[set]
2407 *
2408 * @param ctx Read / write interface definitions.(ptr)
2409 * @param val Change the values of drdy_mask in reg CTRL4_C
2410 * @retval Interface status (MANDATORY: return 0 -> no Error).
2411 *
2412 */
asm330lhb_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2413 int32_t asm330lhb_filter_settling_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2414 {
2415 asm330lhb_ctrl4_c_t ctrl4_c;
2416 int32_t ret;
2417
2418 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2419 if (ret == 0)
2420 {
2421 ctrl4_c.drdy_mask = (uint8_t)val;
2422 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2423 }
2424 return ret;
2425 }
2426
2427 /**
2428 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2429 * (XL and Gyro independently masked).[get]
2430 *
2431 * @param ctx Read / write interface definitions.(ptr)
2432 * @param val Change the values of drdy_mask in reg CTRL4_C
2433 * @retval Interface status (MANDATORY: return 0 -> no Error).
2434 *
2435 */
asm330lhb_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2436 int32_t asm330lhb_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2437 uint8_t *val)
2438 {
2439 asm330lhb_ctrl4_c_t ctrl4_c;
2440 int32_t ret;
2441
2442 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2443 *val = ctrl4_c.drdy_mask;
2444
2445 return ret;
2446 }
2447
2448 /**
2449 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2450 *
2451 * @param ctx Read / write interface definitions.(ptr)
2452 * @param val Change the values of ftype in reg CTRL6_C
2453 * @retval Interface status (MANDATORY: return 0 -> no Error).
2454 *
2455 */
asm330lhb_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,asm330lhb_ftype_t val)2456 int32_t asm330lhb_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2457 asm330lhb_ftype_t val)
2458 {
2459 asm330lhb_ctrl6_c_t ctrl6_c;
2460 int32_t ret;
2461
2462 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2463 if (ret == 0)
2464 {
2465 ctrl6_c.ftype = (uint8_t)val;
2466 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2467 }
2468 return ret;
2469 }
2470
2471 /**
2472 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2473 *
2474 * @param ctx Read / write interface definitions.(ptr)
2475 * @param val Get the values of ftype in reg CTRL6_C
2476 * @retval Interface status (MANDATORY: return 0 -> no Error).
2477 *
2478 */
asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,asm330lhb_ftype_t * val)2479 int32_t asm330lhb_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2480 asm330lhb_ftype_t *val)
2481 {
2482 asm330lhb_ctrl6_c_t ctrl6_c;
2483 int32_t ret;
2484
2485 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2486
2487 switch (ctrl6_c.ftype)
2488 {
2489 case ASM330LHB_ULTRA_LIGHT:
2490 *val = ASM330LHB_ULTRA_LIGHT;
2491 break;
2492 case ASM330LHB_VERY_LIGHT:
2493 *val = ASM330LHB_VERY_LIGHT;
2494 break;
2495 case ASM330LHB_LIGHT:
2496 *val = ASM330LHB_LIGHT;
2497 break;
2498 case ASM330LHB_MEDIUM:
2499 *val = ASM330LHB_MEDIUM;
2500 break;
2501 case ASM330LHB_STRONG:
2502 *val = ASM330LHB_STRONG;
2503 break;
2504 case ASM330LHB_VERY_STRONG:
2505 *val = ASM330LHB_VERY_STRONG;
2506 break;
2507 case ASM330LHB_AGGRESSIVE:
2508 *val = ASM330LHB_AGGRESSIVE;
2509 break;
2510 case ASM330LHB_XTREME:
2511 *val = ASM330LHB_XTREME;
2512 break;
2513 default:
2514 *val = ASM330LHB_ULTRA_LIGHT;
2515 break;
2516 }
2517 return ret;
2518 }
2519
2520 /**
2521 * @brief Low pass filter 2 on 6D function selection.[set]
2522 *
2523 * @param ctx Read / write interface definitions.(ptr)
2524 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2525 * @retval Interface status (MANDATORY: return 0 -> no Error).
2526 *
2527 */
asm330lhb_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2528 int32_t asm330lhb_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2529 {
2530 asm330lhb_ctrl8_xl_t ctrl8_xl;
2531 int32_t ret;
2532
2533 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2534 if (ret == 0)
2535 {
2536 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2537 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2538 (uint8_t *)&ctrl8_xl, 1);
2539 }
2540 return ret;
2541 }
2542
2543 /**
2544 * @brief Low pass filter 2 on 6D function selection.[get]
2545 *
2546 * @param ctx Read / write interface definitions.(ptr)
2547 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2548 * @retval Interface status (MANDATORY: return 0 -> no Error).
2549 *
2550 */
asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2551 int32_t asm330lhb_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2552 {
2553 asm330lhb_ctrl8_xl_t ctrl8_xl;
2554 int32_t ret;
2555
2556 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2557 *val = ctrl8_xl.low_pass_on_6d;
2558
2559 return ret;
2560 }
2561
2562 /**
2563 * @brief Accelerometer slope filter / high-pass filter selection
2564 * on output.[set]
2565 *
2566 * @param ctx Read / write interface definitions.(ptr)
2567 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2568 * @retval Interface status (MANDATORY: return 0 -> no Error).
2569 *
2570 */
asm330lhb_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,asm330lhb_hp_slope_xl_en_t val)2571 int32_t asm330lhb_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2572 asm330lhb_hp_slope_xl_en_t val)
2573 {
2574 asm330lhb_ctrl8_xl_t ctrl8_xl;
2575 int32_t ret;
2576
2577 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2578 if (ret == 0)
2579 {
2580 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2581 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2582 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2583 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2584 (uint8_t *)&ctrl8_xl, 1);
2585 }
2586 return ret;
2587 }
2588
2589 /**
2590 * @brief Accelerometer slope filter / high-pass filter selection on
2591 * output.[get]
2592 *
2593 * @param ctx Read / write interface definitions.(ptr)
2594 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2595 * @retval Interface status (MANDATORY: return 0 -> no Error).
2596 *
2597 */
asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,asm330lhb_hp_slope_xl_en_t * val)2598 int32_t asm330lhb_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2599 asm330lhb_hp_slope_xl_en_t *val)
2600 {
2601 asm330lhb_ctrl8_xl_t ctrl8_xl;
2602 int32_t ret;
2603
2604 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2605 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en << 4) +
2606 ctrl8_xl.hpcf_xl))
2607 {
2608 case ASM330LHB_HP_PATH_DISABLE_ON_OUT:
2609 *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT;
2610 break;
2611 case ASM330LHB_SLOPE_ODR_DIV_4:
2612 *val = ASM330LHB_SLOPE_ODR_DIV_4;
2613 break;
2614 case ASM330LHB_HP_ODR_DIV_10:
2615 *val = ASM330LHB_HP_ODR_DIV_10;
2616 break;
2617 case ASM330LHB_HP_ODR_DIV_20:
2618 *val = ASM330LHB_HP_ODR_DIV_20;
2619 break;
2620 case ASM330LHB_HP_ODR_DIV_45:
2621 *val = ASM330LHB_HP_ODR_DIV_45;
2622 break;
2623 case ASM330LHB_HP_ODR_DIV_100:
2624 *val = ASM330LHB_HP_ODR_DIV_100;
2625 break;
2626 case ASM330LHB_HP_ODR_DIV_200:
2627 *val = ASM330LHB_HP_ODR_DIV_200;
2628 break;
2629 case ASM330LHB_HP_ODR_DIV_400:
2630 *val = ASM330LHB_HP_ODR_DIV_400;
2631 break;
2632 case ASM330LHB_HP_ODR_DIV_800:
2633 *val = ASM330LHB_HP_ODR_DIV_800;
2634 break;
2635 case ASM330LHB_HP_REF_MD_ODR_DIV_10:
2636 *val = ASM330LHB_HP_REF_MD_ODR_DIV_10;
2637 break;
2638 case ASM330LHB_HP_REF_MD_ODR_DIV_20:
2639 *val = ASM330LHB_HP_REF_MD_ODR_DIV_20;
2640 break;
2641 case ASM330LHB_HP_REF_MD_ODR_DIV_45:
2642 *val = ASM330LHB_HP_REF_MD_ODR_DIV_45;
2643 break;
2644 case ASM330LHB_HP_REF_MD_ODR_DIV_100:
2645 *val = ASM330LHB_HP_REF_MD_ODR_DIV_100;
2646 break;
2647 case ASM330LHB_HP_REF_MD_ODR_DIV_200:
2648 *val = ASM330LHB_HP_REF_MD_ODR_DIV_200;
2649 break;
2650 case ASM330LHB_HP_REF_MD_ODR_DIV_400:
2651 *val = ASM330LHB_HP_REF_MD_ODR_DIV_400;
2652 break;
2653 case ASM330LHB_HP_REF_MD_ODR_DIV_800:
2654 *val = ASM330LHB_HP_REF_MD_ODR_DIV_800;
2655 break;
2656 case ASM330LHB_LP_ODR_DIV_10:
2657 *val = ASM330LHB_LP_ODR_DIV_10;
2658 break;
2659 case ASM330LHB_LP_ODR_DIV_20:
2660 *val = ASM330LHB_LP_ODR_DIV_20;
2661 break;
2662 case ASM330LHB_LP_ODR_DIV_45:
2663 *val = ASM330LHB_LP_ODR_DIV_45;
2664 break;
2665 case ASM330LHB_LP_ODR_DIV_100:
2666 *val = ASM330LHB_LP_ODR_DIV_100;
2667 break;
2668 case ASM330LHB_LP_ODR_DIV_200:
2669 *val = ASM330LHB_LP_ODR_DIV_200;
2670 break;
2671 case ASM330LHB_LP_ODR_DIV_400:
2672 *val = ASM330LHB_LP_ODR_DIV_400;
2673 break;
2674 case ASM330LHB_LP_ODR_DIV_800:
2675 *val = ASM330LHB_LP_ODR_DIV_800;
2676 break;
2677 default:
2678 *val = ASM330LHB_HP_PATH_DISABLE_ON_OUT;
2679 break;
2680 }
2681 return ret;
2682 }
2683
2684 /**
2685 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2686 * The filter sets the second samples after writing this bit.
2687 * Active only during device exit from powerdown mode.[set]
2688 *
2689 * @param ctx Read / write interface definitions.(ptr)
2690 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2691 * @retval Interface status (MANDATORY: return 0 -> no Error).
2692 *
2693 */
asm330lhb_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2694 int32_t asm330lhb_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2695 {
2696 asm330lhb_ctrl8_xl_t ctrl8_xl;
2697 int32_t ret;
2698
2699 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2700 if (ret == 0)
2701 {
2702 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2703 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL8_XL,
2704 (uint8_t *)&ctrl8_xl, 1);
2705 }
2706 return ret;
2707 }
2708
2709 /**
2710 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2711 * The filter sets the second samples after writing
2712 * this bit. Active only during device exit from powerdown mode.[get]
2713 *
2714 * @param ctx Read / write interface definitions.(ptr)
2715 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2716 * @retval Interface status (MANDATORY: return 0 -> no Error).
2717 *
2718 */
asm330lhb_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2719 int32_t asm330lhb_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2720 {
2721 asm330lhb_ctrl8_xl_t ctrl8_xl;
2722 int32_t ret;
2723
2724 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2725 *val = ctrl8_xl.fastsettl_mode_xl;
2726
2727 return ret;
2728 }
2729
2730 /**
2731 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2732 * functions.[set]
2733 *
2734 * @param ctx Read / write interface definitions.(ptr)
2735 * @param val Change the values of slope_fds in reg INT_CFG0
2736 * @retval Interface status (MANDATORY: return 0 -> no Error).
2737 *
2738 */
asm330lhb_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhb_slope_fds_t val)2739 int32_t asm330lhb_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2740 asm330lhb_slope_fds_t val)
2741 {
2742 asm330lhb_int_cfg0_t int_cfg0;
2743 int32_t ret;
2744
2745 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2746 if (ret == 0)
2747 {
2748 int_cfg0.slope_fds = (uint8_t)val;
2749 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
2750 (uint8_t *)&int_cfg0, 1);
2751 }
2752 return ret;
2753 }
2754
2755 /**
2756 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2757 * functions.[get]
2758 *
2759 * @param ctx Read / write interface definitions.(ptr)
2760 * @param val Get the values of slope_fds in reg INT_CFG0
2761 * @retval Interface status (MANDATORY: return 0 -> no Error).
2762 *
2763 */
asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhb_slope_fds_t * val)2764 int32_t asm330lhb_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2765 asm330lhb_slope_fds_t *val)
2766 {
2767 asm330lhb_int_cfg0_t int_cfg0;
2768 int32_t ret;
2769
2770 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
2771 switch (int_cfg0.slope_fds)
2772 {
2773 case ASM330LHB_USE_SLOPE:
2774 *val = ASM330LHB_USE_SLOPE;
2775 break;
2776 case ASM330LHB_USE_HPF:
2777 *val = ASM330LHB_USE_HPF;
2778 break;
2779 default:
2780 *val = ASM330LHB_USE_SLOPE;
2781 break;
2782 }
2783 return ret;
2784 }
2785
2786 /**
2787 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2788 * only if the gyro is in HP mode.[set]
2789 *
2790 * @param ctx Read / write interface definitions.(ptr)
2791 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2792 * @retval Interface status (MANDATORY: return 0 -> no Error).
2793 *
2794 */
asm330lhb_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,asm330lhb_hpm_g_t val)2795 int32_t asm330lhb_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2796 asm330lhb_hpm_g_t val)
2797 {
2798 asm330lhb_ctrl7_g_t ctrl7_g;
2799 int32_t ret;
2800
2801 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2802 if (ret == 0)
2803 {
2804 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2805 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2806 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2807 }
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief Enables gyroscope digital high-pass filter. The filter is
2813 * enabled only if the gyro is in HP mode.[get]
2814 *
2815 * @param ctx Read / write interface definitions.(ptr)
2816 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2817 * @retval Interface status (MANDATORY: return 0 -> no Error).
2818 *
2819 */
asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,asm330lhb_hpm_g_t * val)2820 int32_t asm330lhb_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
2821 asm330lhb_hpm_g_t *val)
2822 {
2823 asm330lhb_ctrl7_g_t ctrl7_g;
2824 int32_t ret;
2825
2826 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2827
2828 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
2829 {
2830 case ASM330LHB_HP_FILTER_NONE:
2831 *val = ASM330LHB_HP_FILTER_NONE;
2832 break;
2833 case ASM330LHB_HP_FILTER_16mHz:
2834 *val = ASM330LHB_HP_FILTER_16mHz;
2835 break;
2836 case ASM330LHB_HP_FILTER_65mHz:
2837 *val = ASM330LHB_HP_FILTER_65mHz;
2838 break;
2839 case ASM330LHB_HP_FILTER_260mHz:
2840 *val = ASM330LHB_HP_FILTER_260mHz;
2841 break;
2842 case ASM330LHB_HP_FILTER_1Hz04:
2843 *val = ASM330LHB_HP_FILTER_1Hz04;
2844 break;
2845 default:
2846 *val = ASM330LHB_HP_FILTER_NONE;
2847 break;
2848 }
2849 return ret;
2850 }
2851
2852 /**
2853 * @}
2854 *
2855 */
2856
2857 /**
2858 * @defgroup ASM330LHB_ serial_interface
2859 * @brief This section groups all the functions concerning main
2860 * serial interface management (not auxiliary)
2861 * @{
2862 *
2863 */
2864
2865 /**
2866 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2867 *
2868 * @param ctx Read / write interface definitions.(ptr)
2869 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
2870 * @retval Interface status (MANDATORY: return 0 -> no Error).
2871 *
2872 */
asm330lhb_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,asm330lhb_sdo_pu_en_t val)2873 int32_t asm330lhb_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
2874 asm330lhb_sdo_pu_en_t val)
2875 {
2876 asm330lhb_pin_ctrl_t pin_ctrl;
2877 int32_t ret;
2878
2879 ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2880 if (ret == 0)
2881 {
2882 pin_ctrl.sdo_pu_en = (uint8_t)val;
2883 ret = asm330lhb_write_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2884 }
2885 return ret;
2886 }
2887
2888 /**
2889 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2890 *
2891 * @param ctx Read / write interface definitions.(ptr)
2892 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2893 * @retval Interface status (MANDATORY: return 0 -> no Error).
2894 *
2895 */
asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,asm330lhb_sdo_pu_en_t * val)2896 int32_t asm330lhb_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
2897 asm330lhb_sdo_pu_en_t *val)
2898 {
2899 asm330lhb_pin_ctrl_t pin_ctrl;
2900 int32_t ret;
2901
2902 ret = asm330lhb_read_reg(ctx, ASM330LHB_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2903
2904 switch (pin_ctrl.sdo_pu_en)
2905 {
2906 case ASM330LHB_PULL_UP_DISC:
2907 *val = ASM330LHB_PULL_UP_DISC;
2908 break;
2909 case ASM330LHB_PULL_UP_CONNECT:
2910 *val = ASM330LHB_PULL_UP_CONNECT;
2911 break;
2912 default:
2913 *val = ASM330LHB_PULL_UP_DISC;
2914 break;
2915 }
2916 return ret;
2917 }
2918
2919 /**
2920 * @brief Connect/Disconnect INT1 pull-down.[set]
2921 *
2922 * @param ctx Read / write interface definitions.(ptr)
2923 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
2924 * @retval Interface status (MANDATORY: return 0 -> no Error).
2925 *
2926 */
asm330lhb_int1_mode_set(const stmdev_ctx_t * ctx,asm330lhb_pd_dis_int1_t val)2927 int32_t asm330lhb_int1_mode_set(const stmdev_ctx_t *ctx,
2928 asm330lhb_pd_dis_int1_t val)
2929 {
2930 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
2931 int32_t ret;
2932
2933 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2934 if (ret == 0)
2935 {
2936 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
2937 ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB,
2938 (uint8_t *)&i3c_bus_avb, 1);
2939 }
2940 return ret;
2941 }
2942
2943 /**
2944 * @brief Connect/Disconnect INT1 pull-down.[get]
2945 *
2946 * @param ctx Read / write interface definitions.(ptr)
2947 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
2948 * @retval Interface status (MANDATORY: return 0 -> no Error).
2949 *
2950 */
asm330lhb_int1_mode_get(const stmdev_ctx_t * ctx,asm330lhb_pd_dis_int1_t * val)2951 int32_t asm330lhb_int1_mode_get(const stmdev_ctx_t *ctx,
2952 asm330lhb_pd_dis_int1_t *val)
2953 {
2954 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
2955 int32_t ret;
2956
2957 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
2958
2959 switch (i3c_bus_avb.pd_dis_int1)
2960 {
2961 case ASM330LHB_PULL_DOWN_CONNECT:
2962 *val = ASM330LHB_PULL_DOWN_CONNECT;
2963 break;
2964 case ASM330LHB_PULL_DOWN_DISC:
2965 *val = ASM330LHB_PULL_DOWN_DISC;
2966 break;
2967 default:
2968 *val = ASM330LHB_PULL_DOWN_CONNECT;
2969 break;
2970 }
2971 return ret;
2972 }
2973
2974 /**
2975 * @brief SPI Serial Interface Mode selection.[set]
2976 *
2977 * @param ctx Read / write interface definitions.(ptr)
2978 * @param val Change the values of sim in reg CTRL3_C
2979 * @retval Interface status (MANDATORY: return 0 -> no Error).
2980 *
2981 */
asm330lhb_spi_mode_set(const stmdev_ctx_t * ctx,asm330lhb_sim_t val)2982 int32_t asm330lhb_spi_mode_set(const stmdev_ctx_t *ctx, asm330lhb_sim_t val)
2983 {
2984 asm330lhb_ctrl3_c_t ctrl3_c;
2985 int32_t ret;
2986
2987 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2988 if (ret == 0)
2989 {
2990 ctrl3_c.sim = (uint8_t)val;
2991 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2992 }
2993 return ret;
2994 }
2995
2996 /**
2997 * @brief SPI Serial Interface Mode selection.[get]
2998 *
2999 * @param ctx Read / write interface definitions.(ptr)
3000 * @param val Get the values of sim in reg CTRL3_C
3001 * @retval Interface status (MANDATORY: return 0 -> no Error).
3002 *
3003 */
asm330lhb_spi_mode_get(const stmdev_ctx_t * ctx,asm330lhb_sim_t * val)3004 int32_t asm330lhb_spi_mode_get(const stmdev_ctx_t *ctx, asm330lhb_sim_t *val)
3005 {
3006 asm330lhb_ctrl3_c_t ctrl3_c;
3007 int32_t ret;
3008
3009 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3010
3011 switch (ctrl3_c.sim)
3012 {
3013 case ASM330LHB_SPI_4_WIRE:
3014 *val = ASM330LHB_SPI_4_WIRE;
3015 break;
3016 case ASM330LHB_SPI_3_WIRE:
3017 *val = ASM330LHB_SPI_3_WIRE;
3018 break;
3019 default:
3020 *val = ASM330LHB_SPI_4_WIRE;
3021 break;
3022 }
3023 return ret;
3024 }
3025
3026 /**
3027 * @brief Disable / Enable I2C interface.[set]
3028 *
3029 * @param ctx Read / write interface definitions.(ptr)
3030 * @param val Change the values of i2c_disable in reg CTRL4_C
3031 * @retval Interface status (MANDATORY: return 0 -> no Error).
3032 *
3033 */
asm330lhb_i2c_interface_set(const stmdev_ctx_t * ctx,asm330lhb_i2c_disable_t val)3034 int32_t asm330lhb_i2c_interface_set(const stmdev_ctx_t *ctx,
3035 asm330lhb_i2c_disable_t val)
3036 {
3037 asm330lhb_ctrl4_c_t ctrl4_c;
3038 int32_t ret;
3039
3040 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3041 if (ret == 0)
3042 {
3043 ctrl4_c.i2c_disable = (uint8_t)val;
3044 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3045 }
3046 return ret;
3047 }
3048
3049 /**
3050 * @brief Disable / Enable I2C interface.[get]
3051 *
3052 * @param ctx Read / write interface definitions.(ptr)
3053 * @param val Get the values of i2c reg CTRL4_C
3054 * @retval Interface status (MANDATORY: return 0 -> no Error).
3055 *
3056 */
asm330lhb_i2c_interface_get(const stmdev_ctx_t * ctx,asm330lhb_i2c_disable_t * val)3057 int32_t asm330lhb_i2c_interface_get(const stmdev_ctx_t *ctx,
3058 asm330lhb_i2c_disable_t *val)
3059 {
3060 asm330lhb_ctrl4_c_t ctrl4_c;
3061 int32_t ret;
3062
3063 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3064
3065 switch (ctrl4_c.i2c_disable)
3066 {
3067 case ASM330LHB_I2C_ENABLE:
3068 *val = ASM330LHB_I2C_ENABLE;
3069 break;
3070 case ASM330LHB_I2C_DISABLE:
3071 *val = ASM330LHB_I2C_DISABLE;
3072 break;
3073 default:
3074 *val = ASM330LHB_I2C_ENABLE;
3075 break;
3076 }
3077 return ret;
3078 }
3079
3080 /**
3081 * @brief I3C Enable/Disable communication protocol.[set]
3082 *
3083 * @param ctx Read / write interface definitions.(ptr)
3084 * @param val Change the values of i3c_disable in reg CTRL9_XL
3085 * @retval Interface status (MANDATORY: return 0 -> no Error).
3086 *
3087 */
asm330lhb_i3c_disable_set(const stmdev_ctx_t * ctx,asm330lhb_i3c_disable_t val)3088 int32_t asm330lhb_i3c_disable_set(const stmdev_ctx_t *ctx,
3089 asm330lhb_i3c_disable_t val)
3090 {
3091 asm330lhb_ctrl9_xl_t ctrl9_xl;
3092 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
3093 int32_t ret;
3094
3095 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3096 if (ret == 0)
3097 {
3098 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3099 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
3100 (uint8_t *)&ctrl9_xl, 1);
3101 }
3102 if (ret == 0)
3103 {
3104 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3105 (uint8_t *)&i3c_bus_avb, 1);
3106 }
3107 if (ret == 0)
3108 {
3109 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3110 ret = asm330lhb_write_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3111 (uint8_t *)&i3c_bus_avb, 1);
3112 }
3113 return ret;
3114 }
3115
3116 /**
3117 * @brief I3C Enable/Disable communication protocol.[get]
3118 *
3119 * @param ctx Read / write interface definitions.(ptr)
3120 * @param val Change the values of i3c_disable in reg CTRL9_XL
3121 * @retval Interface status (MANDATORY: return 0 -> no Error).
3122 *
3123 */
asm330lhb_i3c_disable_get(const stmdev_ctx_t * ctx,asm330lhb_i3c_disable_t * val)3124 int32_t asm330lhb_i3c_disable_get(const stmdev_ctx_t *ctx,
3125 asm330lhb_i3c_disable_t *val)
3126 {
3127 asm330lhb_ctrl9_xl_t ctrl9_xl;
3128 asm330lhb_i3c_bus_avb_t i3c_bus_avb;
3129 int32_t ret;
3130
3131 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
3132 if (ret == 0)
3133 {
3134 ret = asm330lhb_read_reg(ctx, ASM330LHB_I3C_BUS_AVB,
3135 (uint8_t *)&i3c_bus_avb, 1);
3136 }
3137 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
3138 {
3139 case ASM330LHB_I3C_DISABLE:
3140 *val = ASM330LHB_I3C_DISABLE;
3141 break;
3142 case ASM330LHB_I3C_ENABLE_T_50us:
3143 *val = ASM330LHB_I3C_ENABLE_T_50us;
3144 break;
3145 case ASM330LHB_I3C_ENABLE_T_2us:
3146 *val = ASM330LHB_I3C_ENABLE_T_2us;
3147 break;
3148 case ASM330LHB_I3C_ENABLE_T_1ms:
3149 *val = ASM330LHB_I3C_ENABLE_T_1ms;
3150 break;
3151 case ASM330LHB_I3C_ENABLE_T_25ms:
3152 *val = ASM330LHB_I3C_ENABLE_T_25ms;
3153 break;
3154 default:
3155 *val = ASM330LHB_I3C_DISABLE;
3156 break;
3157 }
3158 return ret;
3159 }
3160
3161 /**
3162 * @}
3163 *
3164 */
3165
3166 /**
3167 * @defgroup ASM330LHB_interrupt_pins
3168 * @brief This section groups all the functions that manage
3169 * interrupt pins
3170 * @{
3171 *
3172 */
3173
3174 /**
3175 * @brief Select the signal that need to route on int1 pad.[set]
3176 *
3177 * @param ctx read / write interface definitions
3178 * @param val struct of registers: INT1_CTRL,
3179 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3180 * FSM_INT1_B
3181 *
3182 */
asm330lhb_pin_int1_route_set(const stmdev_ctx_t * ctx,asm330lhb_pin_int1_route_t * val)3183 int32_t asm330lhb_pin_int1_route_set(const stmdev_ctx_t *ctx,
3184 asm330lhb_pin_int1_route_t *val)
3185 {
3186 asm330lhb_pin_int2_route_t pin_int2_route;
3187 asm330lhb_int_cfg1_t int_cfg1;
3188 int32_t ret;
3189
3190 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3191 if (ret == 0)
3192 {
3193 ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT1,
3194 (uint8_t *)&val->mlc_int1, 1);
3195 }
3196 if (ret == 0)
3197 {
3198 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT1,
3199 (uint8_t *)&val->emb_func_int1, 1);
3200 }
3201 if (ret == 0)
3202 {
3203 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_A,
3204 (uint8_t *)&val->fsm_int1_a, 1);
3205 }
3206 if (ret == 0)
3207 {
3208 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT1_B,
3209 (uint8_t *)&val->fsm_int1_b, 1);
3210 }
3211 if (ret == 0)
3212 {
3213 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3214 }
3215
3216 if (ret == 0)
3217 {
3218 if ((val->emb_func_int1.int1_fsm_lc
3219 | val->fsm_int1_a.int1_fsm1
3220 | val->fsm_int1_a.int1_fsm2
3221 | val->fsm_int1_a.int1_fsm3
3222 | val->fsm_int1_a.int1_fsm4
3223 | val->fsm_int1_a.int1_fsm5
3224 | val->fsm_int1_a.int1_fsm6
3225 | val->fsm_int1_a.int1_fsm7
3226 | val->fsm_int1_a.int1_fsm8
3227 | val->fsm_int1_b.int1_fsm9
3228 | val->fsm_int1_b.int1_fsm10
3229 | val->fsm_int1_b.int1_fsm11
3230 | val->fsm_int1_b.int1_fsm12
3231 | val->fsm_int1_b.int1_fsm13
3232 | val->fsm_int1_b.int1_fsm14
3233 | val->fsm_int1_b.int1_fsm15
3234 | val->fsm_int1_b.int1_fsm16
3235 | val->mlc_int1.int1_mlc1
3236 | val->mlc_int1.int1_mlc2
3237 | val->mlc_int1.int1_mlc3
3238 | val->mlc_int1.int1_mlc4
3239 | val->mlc_int1.int1_mlc5
3240 | val->mlc_int1.int1_mlc6
3241 | val->mlc_int1.int1_mlc7
3242 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
3243 {
3244 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3245 }
3246 else
3247 {
3248 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3249 }
3250 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT1_CTRL,
3251 (uint8_t *)&val->int1_ctrl, 1);
3252 }
3253 if (ret == 0)
3254 {
3255 ret = asm330lhb_write_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3256 }
3257
3258 if (ret == 0)
3259 {
3260 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3261 }
3262
3263 if (ret == 0)
3264 {
3265 ret = asm330lhb_pin_int2_route_get(ctx, &pin_int2_route);
3266 }
3267 if (ret == 0)
3268 {
3269 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3270 | pin_int2_route.int2_ctrl.int2_drdy_g
3271 | pin_int2_route.int2_ctrl.int2_drdy_temp
3272 | pin_int2_route.int2_ctrl.int2_drdy_xl
3273 | pin_int2_route.int2_ctrl.int2_fifo_full
3274 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3275 | pin_int2_route.int2_ctrl.int2_fifo_th
3276 | pin_int2_route.md2_cfg.int2_6d
3277 | pin_int2_route.md2_cfg.int2_ff
3278 | pin_int2_route.md2_cfg.int2_wu
3279 | pin_int2_route.md2_cfg.int2_sleep_change
3280 | val->int1_ctrl.den_drdy_flag
3281 | val->int1_ctrl.int1_boot
3282 | val->int1_ctrl.int1_cnt_bdr
3283 | val->int1_ctrl.int1_drdy_g
3284 | val->int1_ctrl.int1_drdy_xl
3285 | val->int1_ctrl.int1_fifo_full
3286 | val->int1_ctrl.int1_fifo_ovr
3287 | val->int1_ctrl.int1_fifo_th
3288 | val->md1_cfg.int1_6d
3289 | val->md1_cfg.int1_ff
3290 | val->md1_cfg.int1_wu
3291 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3292 {
3293 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3294 }
3295 else
3296 {
3297 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3298 }
3299 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3300 }
3301 return ret;
3302 }
3303
3304 /**
3305 * @brief Select the signal that need to route on int1 pad.[get]
3306 *
3307 * @param ctx read / write interface definitions
3308 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3309 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3310 *
3311 */
asm330lhb_pin_int1_route_get(const stmdev_ctx_t * ctx,asm330lhb_pin_int1_route_t * val)3312 int32_t asm330lhb_pin_int1_route_get(const stmdev_ctx_t *ctx,
3313 asm330lhb_pin_int1_route_t *val)
3314 {
3315 int32_t ret;
3316
3317 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3318 if (ret == 0)
3319 {
3320 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT1,
3321 (uint8_t *)&val->mlc_int1, 1);
3322 }
3323 if (ret == 0)
3324 {
3325 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT1,
3326 (uint8_t *)&val->emb_func_int1, 1);
3327 }
3328 if (ret == 0)
3329 {
3330 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_A,
3331 (uint8_t *)&val->fsm_int1_a, 1);
3332 }
3333 if (ret == 0)
3334 {
3335 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT1_B,
3336 (uint8_t *)&val->fsm_int1_b, 1);
3337 }
3338 if (ret == 0)
3339 {
3340 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3341 }
3342 if (ret == 0)
3343 {
3344
3345 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT1_CTRL,
3346 (uint8_t *)&val->int1_ctrl, 1);
3347 }
3348 if (ret == 0)
3349 {
3350 ret = asm330lhb_read_reg(ctx, ASM330LHB_MD1_CFG, (uint8_t *)&val->md1_cfg, 1);
3351 }
3352
3353 return ret;
3354 }
3355
3356 /**
3357 * @brief Select the signal that need to route on int2 pad.[set]
3358 *
3359 * @param ctx read / write interface definitions
3360 * @param val union of registers INT2_CTRL, MD2_CFG,
3361 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3362 *
3363 */
asm330lhb_pin_int2_route_set(const stmdev_ctx_t * ctx,asm330lhb_pin_int2_route_t * val)3364 int32_t asm330lhb_pin_int2_route_set(const stmdev_ctx_t *ctx,
3365 asm330lhb_pin_int2_route_t *val)
3366 {
3367 asm330lhb_pin_int1_route_t pin_int1_route;
3368 asm330lhb_int_cfg1_t int_cfg1;
3369 int32_t ret;
3370
3371 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3372 if (ret == 0)
3373 {
3374 ret = asm330lhb_write_reg(ctx, ASM330LHB_MLC_INT2,
3375 (uint8_t *)&val->mlc_int2, 1);
3376 }
3377 if (ret == 0)
3378 {
3379 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INT2,
3380 (uint8_t *)&val->emb_func_int2, 1);
3381 }
3382 if (ret == 0)
3383 {
3384 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_A,
3385 (uint8_t *)&val->fsm_int2_a, 1);
3386 }
3387 if (ret == 0)
3388 {
3389 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_INT2_B,
3390 (uint8_t *)&val->fsm_int2_b, 1);
3391 }
3392 if (ret == 0)
3393 {
3394 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3395 }
3396
3397 if (ret == 0)
3398 {
3399 if ((val->emb_func_int2.int2_fsm_lc
3400 | val->fsm_int2_a.int2_fsm1
3401 | val->fsm_int2_a.int2_fsm2
3402 | val->fsm_int2_a.int2_fsm3
3403 | val->fsm_int2_a.int2_fsm4
3404 | val->fsm_int2_a.int2_fsm5
3405 | val->fsm_int2_a.int2_fsm6
3406 | val->fsm_int2_a.int2_fsm7
3407 | val->fsm_int2_a.int2_fsm8
3408 | val->fsm_int2_b.int2_fsm9
3409 | val->fsm_int2_b.int2_fsm10
3410 | val->fsm_int2_b.int2_fsm11
3411 | val->fsm_int2_b.int2_fsm12
3412 | val->fsm_int2_b.int2_fsm13
3413 | val->fsm_int2_b.int2_fsm14
3414 | val->fsm_int2_b.int2_fsm15
3415 | val->fsm_int2_b.int2_fsm16
3416 | val->mlc_int2.int2_mlc1
3417 | val->mlc_int2.int2_mlc2
3418 | val->mlc_int2.int2_mlc3
3419 | val->mlc_int2.int2_mlc4
3420 | val->mlc_int2.int2_mlc5
3421 | val->mlc_int2.int2_mlc6
3422 | val->mlc_int2.int2_mlc7
3423 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
3424 {
3425 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3426 }
3427 else
3428 {
3429 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3430 }
3431 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT2_CTRL,
3432 (uint8_t *)&val->int2_ctrl, 1);
3433 }
3434 if (ret == 0)
3435 {
3436 ret = asm330lhb_write_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3437 }
3438 if (ret == 0)
3439 {
3440 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3441 }
3442
3443 if (ret == 0)
3444 {
3445 ret = asm330lhb_pin_int1_route_get(ctx, &pin_int1_route);
3446 }
3447
3448 if (ret == 0)
3449 {
3450 if ((val->int2_ctrl.int2_cnt_bdr
3451 | val->int2_ctrl.int2_drdy_g
3452 | val->int2_ctrl.int2_drdy_temp
3453 | val->int2_ctrl.int2_drdy_xl
3454 | val->int2_ctrl.int2_fifo_full
3455 | val->int2_ctrl.int2_fifo_ovr
3456 | val->int2_ctrl.int2_fifo_th
3457 | val->md2_cfg.int2_6d
3458 | val->md2_cfg.int2_ff
3459 | val->md2_cfg.int2_wu
3460 | val->md2_cfg.int2_sleep_change
3461 | pin_int1_route.int1_ctrl.den_drdy_flag
3462 | pin_int1_route.int1_ctrl.int1_boot
3463 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3464 | pin_int1_route.int1_ctrl.int1_drdy_g
3465 | pin_int1_route.int1_ctrl.int1_drdy_xl
3466 | pin_int1_route.int1_ctrl.int1_fifo_full
3467 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3468 | pin_int1_route.int1_ctrl.int1_fifo_th
3469 | pin_int1_route.md1_cfg.int1_6d
3470 | pin_int1_route.md1_cfg.int1_ff
3471 | pin_int1_route.md1_cfg.int1_wu
3472 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3473 {
3474 int_cfg1.interrupts_enable = PROPERTY_ENABLE;
3475 }
3476 else
3477 {
3478 int_cfg1.interrupts_enable = PROPERTY_DISABLE;
3479 }
3480 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *) &int_cfg1, 1);
3481 }
3482 return ret;
3483 }
3484
3485 /**
3486 * @brief Select the signal that need to route on int2 pad.[get]
3487 *
3488 * @param ctx read / write interface definitions
3489 * @param val union of registers INT2_CTRL, MD2_CFG,
3490 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3491 *
3492 */
asm330lhb_pin_int2_route_get(const stmdev_ctx_t * ctx,asm330lhb_pin_int2_route_t * val)3493 int32_t asm330lhb_pin_int2_route_get(const stmdev_ctx_t *ctx,
3494 asm330lhb_pin_int2_route_t *val)
3495 {
3496 int32_t ret;
3497
3498 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3499 if (ret == 0)
3500 {
3501 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC_INT2,
3502 (uint8_t *)&val->mlc_int2, 1);
3503 }
3504 if (ret == 0)
3505 {
3506 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INT2,
3507 (uint8_t *)&val->emb_func_int2, 1);
3508 }
3509 if (ret == 0)
3510 {
3511 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_A,
3512 (uint8_t *)&val->fsm_int2_a, 1);
3513 }
3514 if (ret == 0)
3515 {
3516 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_INT2_B,
3517 (uint8_t *)&val->fsm_int2_b, 1);
3518 }
3519 if (ret == 0)
3520 {
3521 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3522 }
3523 if (ret == 0)
3524 {
3525
3526 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT2_CTRL,
3527 (uint8_t *)&val->int2_ctrl, 1);
3528 }
3529 if (ret == 0)
3530 {
3531 ret = asm330lhb_read_reg(ctx, ASM330LHB_MD2_CFG, (uint8_t *)&val->md2_cfg, 1);
3532 }
3533 return ret;
3534 }
3535
3536 /**
3537 * @brief Push-pull/open drain selection on interrupt pads.[set]
3538 *
3539 * @param ctx Read / write interface definitions.(ptr)
3540 * @param val Change the values of pp_od in reg CTRL3_C
3541 * @retval Interface status (MANDATORY: return 0 -> no Error).
3542 *
3543 */
asm330lhb_pin_mode_set(const stmdev_ctx_t * ctx,asm330lhb_pp_od_t val)3544 int32_t asm330lhb_pin_mode_set(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t val)
3545 {
3546 asm330lhb_ctrl3_c_t ctrl3_c;
3547 int32_t ret;
3548
3549 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3550 if (ret == 0)
3551 {
3552 ctrl3_c.pp_od = (uint8_t)val;
3553 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3554 }
3555 return ret;
3556 }
3557
3558 /**
3559 * @brief Push-pull/open drain selection on interrupt pads.[get]
3560 *
3561 * @param ctx Read / write interface definitions.(ptr)
3562 * @param val Get the values of pp_od in reg CTRL3_C
3563 * @retval Interface status (MANDATORY: return 0 -> no Error).
3564 *
3565 */
asm330lhb_pin_mode_get(const stmdev_ctx_t * ctx,asm330lhb_pp_od_t * val)3566 int32_t asm330lhb_pin_mode_get(const stmdev_ctx_t *ctx, asm330lhb_pp_od_t *val)
3567 {
3568 asm330lhb_ctrl3_c_t ctrl3_c;
3569 int32_t ret;
3570
3571 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3572
3573 switch (ctrl3_c.pp_od)
3574 {
3575 case ASM330LHB_PUSH_PULL:
3576 *val = ASM330LHB_PUSH_PULL;
3577 break;
3578 case ASM330LHB_OPEN_DRAIN:
3579 *val = ASM330LHB_OPEN_DRAIN;
3580 break;
3581 default:
3582 *val = ASM330LHB_PUSH_PULL;
3583 break;
3584 }
3585 return ret;
3586 }
3587
3588 /**
3589 * @brief Interrupt active-high/low.[set]
3590 *
3591 * @param ctx Read / write interface definitions.(ptr)
3592 * @param val Change the values of h_lactive in reg CTRL3_C
3593 * @retval Interface status (MANDATORY: return 0 -> no Error).
3594 *
3595 */
asm330lhb_pin_polarity_set(const stmdev_ctx_t * ctx,asm330lhb_h_lactive_t val)3596 int32_t asm330lhb_pin_polarity_set(const stmdev_ctx_t *ctx,
3597 asm330lhb_h_lactive_t val)
3598 {
3599 asm330lhb_ctrl3_c_t ctrl3_c;
3600 int32_t ret;
3601
3602 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3603 if (ret == 0)
3604 {
3605 ctrl3_c.h_lactive = (uint8_t)val;
3606 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3607 }
3608 return ret;
3609 }
3610
3611 /**
3612 * @brief Interrupt active-high/low.[get]
3613 *
3614 * @param ctx Read / write interface definitions.(ptr)
3615 * @param val Get the values of h_lactive in reg CTRL3_C
3616 * @retval Interface status (MANDATORY: return 0 -> no Error).
3617 *
3618 */
asm330lhb_pin_polarity_get(const stmdev_ctx_t * ctx,asm330lhb_h_lactive_t * val)3619 int32_t asm330lhb_pin_polarity_get(const stmdev_ctx_t *ctx,
3620 asm330lhb_h_lactive_t *val)
3621 {
3622 asm330lhb_ctrl3_c_t ctrl3_c;
3623 int32_t ret;
3624
3625 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3626
3627 switch (ctrl3_c.h_lactive)
3628 {
3629 case ASM330LHB_ACTIVE_HIGH:
3630 *val = ASM330LHB_ACTIVE_HIGH;
3631 break;
3632 case ASM330LHB_ACTIVE_LOW:
3633 *val = ASM330LHB_ACTIVE_LOW;
3634 break;
3635 default:
3636 *val = ASM330LHB_ACTIVE_HIGH;
3637 break;
3638 }
3639 return ret;
3640 }
3641
3642 /**
3643 * @brief All interrupt signals become available on INT1 pin.[set]
3644 *
3645 * @param ctx Read / write interface definitions.(ptr)
3646 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3647 * @retval Interface status (MANDATORY: return 0 -> no Error).
3648 *
3649 */
asm330lhb_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3650 int32_t asm330lhb_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3651 {
3652 asm330lhb_ctrl4_c_t ctrl4_c;
3653 int32_t ret;
3654
3655 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3656 if (ret == 0)
3657 {
3658 ctrl4_c.int2_on_int1 = (uint8_t)val;
3659 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3660 }
3661 return ret;
3662 }
3663
3664 /**
3665 * @brief All interrupt signals become available on INT1 pin.[get]
3666 *
3667 * @param ctx Read / write interface definitions.(ptr)
3668 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3669 * @retval Interface status (MANDATORY: return 0 -> no Error).
3670 *
3671 */
asm330lhb_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3672 int32_t asm330lhb_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3673 {
3674 asm330lhb_ctrl4_c_t ctrl4_c;
3675 int32_t ret;
3676
3677 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3678 *val = ctrl4_c.int2_on_int1;
3679
3680 return ret;
3681 }
3682
3683 /**
3684 * @brief All interrupt signals notification mode.[set]
3685 *
3686 * @param ctx Read / write interface definitions.(ptr)
3687 * @param val Change the values of lir in reg INT_CFG0
3688 * @retval Interface status (MANDATORY: return 0 -> no Error).
3689 *
3690 */
asm330lhb_int_notification_set(const stmdev_ctx_t * ctx,asm330lhb_lir_t val)3691 int32_t asm330lhb_int_notification_set(const stmdev_ctx_t *ctx,
3692 asm330lhb_lir_t val)
3693 {
3694 asm330lhb_int_cfg0_t int_cfg0;
3695 asm330lhb_page_rw_t page_rw;
3696 int32_t ret;
3697
3698 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3699 if (ret == 0)
3700 {
3701 int_cfg0.lir = (uint8_t)val & 0x01U;
3702 int_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3703 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
3704 (uint8_t *)&int_cfg0, 1);
3705 }
3706 if (ret == 0)
3707 {
3708 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3709 }
3710 if (ret == 0)
3711 {
3712 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3713 }
3714 if (ret == 0)
3715 {
3716 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3717 ret = asm330lhb_write_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3718 }
3719 if (ret == 0)
3720 {
3721 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3722 }
3723 return ret;
3724 }
3725
3726 /**
3727 * @brief All interrupt signals notification mode.[get]
3728 *
3729 * @param ctx Read / write interface definitions.(ptr)
3730 * @param val Get the values of lir in reg INT_CFG0
3731 * @retval Interface status (MANDATORY: return 0 -> no Error).
3732 *
3733 */
asm330lhb_int_notification_get(const stmdev_ctx_t * ctx,asm330lhb_lir_t * val)3734 int32_t asm330lhb_int_notification_get(const stmdev_ctx_t *ctx,
3735 asm330lhb_lir_t *val)
3736 {
3737 asm330lhb_int_cfg0_t int_cfg0;
3738 asm330lhb_page_rw_t page_rw;
3739 int32_t ret;
3740
3741 *val = ASM330LHB_ALL_INT_PULSED;
3742 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
3743
3744 if (ret == 0)
3745 {
3746 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
3747 }
3748 if (ret == 0)
3749 {
3750 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_RW, (uint8_t *)&page_rw, 1);
3751 }
3752 if (ret == 0)
3753 {
3754 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
3755 }
3756 switch ((page_rw.emb_func_lir << 1) + int_cfg0.lir)
3757 {
3758 case ASM330LHB_ALL_INT_PULSED:
3759 *val = ASM330LHB_ALL_INT_PULSED;
3760 break;
3761 case ASM330LHB_BASE_LATCHED_EMB_PULSED:
3762 *val = ASM330LHB_BASE_LATCHED_EMB_PULSED;
3763 break;
3764 case ASM330LHB_BASE_PULSED_EMB_LATCHED:
3765 *val = ASM330LHB_BASE_PULSED_EMB_LATCHED;
3766 break;
3767 case ASM330LHB_ALL_INT_LATCHED:
3768 *val = ASM330LHB_ALL_INT_LATCHED;
3769 break;
3770 default:
3771 *val = ASM330LHB_ALL_INT_PULSED;
3772 break;
3773 }
3774 return ret;
3775 }
3776
3777 /**
3778 * @}
3779 *
3780 */
3781
3782 /**
3783 * @defgroup ASM330LHB_Wake_Up_event
3784 * @brief This section groups all the functions that manage the
3785 * Wake Up event generation.
3786 * @{
3787 *
3788 */
3789
3790 /**
3791 * @brief Weight of 1 LSB of wakeup threshold.[set]
3792 * 0: 1 LSB =FS_XL / 64
3793 * 1: 1 LSB = FS_XL / 256
3794 *
3795 * @param ctx Read / write interface definitions.(ptr)
3796 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
3797 * @retval Interface status (MANDATORY: return 0 -> no Error).
3798 *
3799 */
asm330lhb_wkup_ths_weight_set(const stmdev_ctx_t * ctx,asm330lhb_wake_ths_w_t val)3800 int32_t asm330lhb_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
3801 asm330lhb_wake_ths_w_t val)
3802 {
3803 asm330lhb_wake_up_dur_t wake_up_dur;
3804 int32_t ret;
3805
3806 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3807 (uint8_t *)&wake_up_dur, 1);
3808 if (ret == 0)
3809 {
3810 wake_up_dur.wake_ths_w = (uint8_t)val;
3811 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3812 (uint8_t *)&wake_up_dur, 1);
3813 }
3814 return ret;
3815 }
3816
3817 /**
3818 * @brief Weight of 1 LSB of wakeup threshold.[get]
3819 * 0: 1 LSB =FS_XL / 64
3820 * 1: 1 LSB = FS_XL / 256
3821 *
3822 * @param ctx Read / write interface definitions.(ptr)
3823 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
3824 * @retval Interface status (MANDATORY: return 0 -> no Error).
3825 *
3826 */
asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t * ctx,asm330lhb_wake_ths_w_t * val)3827 int32_t asm330lhb_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
3828 asm330lhb_wake_ths_w_t *val)
3829 {
3830 asm330lhb_wake_up_dur_t wake_up_dur;
3831 int32_t ret;
3832
3833 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3834 (uint8_t *)&wake_up_dur, 1);
3835
3836 switch (wake_up_dur.wake_ths_w)
3837 {
3838 case ASM330LHB_LSb_FS_DIV_64:
3839 *val = ASM330LHB_LSb_FS_DIV_64;
3840 break;
3841 case ASM330LHB_LSb_FS_DIV_256:
3842 *val = ASM330LHB_LSb_FS_DIV_256;
3843 break;
3844 default:
3845 *val = ASM330LHB_LSb_FS_DIV_64;
3846 break;
3847 }
3848 return ret;
3849 }
3850
3851 /**
3852 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3853 * WAKE_UP_DUR.[set]
3854 *
3855 * @param ctx Read / write interface definitions.(ptr)
3856 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3857 * @retval Interface status (MANDATORY: return 0 -> no Error).
3858 *
3859 */
asm330lhb_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3860 int32_t asm330lhb_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3861 {
3862 asm330lhb_wake_up_ths_t wake_up_ths;
3863 int32_t ret;
3864
3865 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3866 (uint8_t *)&wake_up_ths, 1);
3867 if (ret == 0)
3868 {
3869 wake_up_ths.wk_ths = (uint8_t)val;
3870 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS,
3871 (uint8_t *)&wake_up_ths, 1);
3872 }
3873 return ret;
3874 }
3875
3876 /**
3877 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3878 * WAKE_UP_DUR.[get]
3879 *
3880 * @param ctx Read / write interface definitions.(ptr)
3881 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3882 * @retval Interface status (MANDATORY: return 0 -> no Error).
3883 *
3884 */
asm330lhb_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3885 int32_t asm330lhb_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3886 {
3887 asm330lhb_wake_up_ths_t wake_up_ths;
3888 int32_t ret;
3889
3890 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3891 (uint8_t *)&wake_up_ths, 1);
3892 *val = wake_up_ths.wk_ths;
3893
3894 return ret;
3895 }
3896
3897 /**
3898 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
3899 *
3900 * @param ctx Read / write interface definitions.(ptr)
3901 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3902 * @retval Interface status (MANDATORY: return 0 -> no Error).
3903 *
3904 */
asm330lhb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)3905 int32_t asm330lhb_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx, uint8_t val)
3906 {
3907 asm330lhb_wake_up_ths_t wake_up_ths;
3908 int32_t ret;
3909
3910 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3911 (uint8_t *)&wake_up_ths, 1);
3912 if (ret == 0)
3913 {
3914 wake_up_ths.usr_off_on_wu = (uint8_t)val;
3915 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_THS,
3916 (uint8_t *)&wake_up_ths, 1);
3917 }
3918 return ret;
3919 }
3920
3921 /**
3922 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
3923 *
3924 * @param ctx Read / write interface definitions.(ptr)
3925 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3926 * @retval Interface status (MANDATORY: return 0 -> no Error).
3927 *
3928 */
asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)3929 int32_t asm330lhb_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
3930 uint8_t *val)
3931 {
3932 asm330lhb_wake_up_ths_t wake_up_ths;
3933 int32_t ret;
3934
3935 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_THS,
3936 (uint8_t *)&wake_up_ths, 1);
3937 *val = wake_up_ths.usr_off_on_wu;
3938
3939 return ret;
3940 }
3941
3942 /**
3943 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
3944 *
3945 * @param ctx Read / write interface definitions.(ptr)
3946 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3947 * @retval Interface status (MANDATORY: return 0 -> no Error).
3948 *
3949 */
asm330lhb_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3950 int32_t asm330lhb_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3951 {
3952 asm330lhb_wake_up_dur_t wake_up_dur;
3953 int32_t ret;
3954
3955 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3956 (uint8_t *)&wake_up_dur, 1);
3957 if (ret == 0)
3958 {
3959 wake_up_dur.wake_dur = (uint8_t)val;
3960 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3961 (uint8_t *)&wake_up_dur, 1);
3962 }
3963 return ret;
3964 }
3965
3966 /**
3967 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3968 *
3969 * @param ctx Read / write interface definitions.(ptr)
3970 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3971 * @retval Interface status (MANDATORY: return 0 -> no Error).
3972 *
3973 */
asm330lhb_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3974 int32_t asm330lhb_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3975 {
3976 asm330lhb_wake_up_dur_t wake_up_dur;
3977 int32_t ret;
3978
3979 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
3980 (uint8_t *)&wake_up_dur, 1);
3981 *val = wake_up_dur.wake_dur;
3982
3983 return ret;
3984 }
3985
3986 /**
3987 * @}
3988 *
3989 */
3990
3991 /**
3992 * @defgroup ASM330LHB_ Activity/Inactivity_detection
3993 * @brief This section groups all the functions concerning
3994 * activity/inactivity detection.
3995 * @{
3996 *
3997 */
3998
3999 /**
4000 * @brief Enables gyroscope Sleep mode.[set]
4001 *
4002 * @param ctx Read / write interface definitions.(ptr)
4003 * @param val Change the values of sleep_g in reg CTRL4_C
4004 * @retval Interface status (MANDATORY: return 0 -> no Error).
4005 *
4006 */
asm330lhb_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4007 int32_t asm330lhb_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4008 {
4009 asm330lhb_ctrl4_c_t ctrl4_c;
4010 int32_t ret;
4011
4012 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4013 if (ret == 0)
4014 {
4015 ctrl4_c.sleep_g = (uint8_t)val;
4016 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4017 }
4018 return ret;
4019 }
4020
4021 /**
4022 * @brief Enables gyroscope Sleep mode.[get]
4023 *
4024 * @param ctx Read / write interface definitions.(ptr)
4025 * @param val Change the values of sleep_g in reg CTRL4_C
4026 * @retval Interface status (MANDATORY: return 0 -> no Error).
4027 *
4028 */
asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4029 int32_t asm330lhb_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4030 {
4031 asm330lhb_ctrl4_c_t ctrl4_c;
4032 int32_t ret;
4033
4034 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4035 *val = ctrl4_c.sleep_g;
4036
4037 return ret;
4038 }
4039
4040 /**
4041 * @brief Drives the sleep status instead of sleep change on INT pins
4042 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4043 * are enabled).[set]
4044 *
4045 * @param ctx Read / write interface definitions.(ptr)
4046 * @param val Change the values of sleep_status_on_int in reg INT_CFG0
4047 * @retval Interface status (MANDATORY: return 0 -> no Error).
4048 *
4049 */
asm330lhb_act_pin_notification_set(const stmdev_ctx_t * ctx,asm330lhb_sleep_status_on_int_t val)4050 int32_t asm330lhb_act_pin_notification_set(const stmdev_ctx_t *ctx,
4051 asm330lhb_sleep_status_on_int_t val)
4052 {
4053 asm330lhb_int_cfg0_t int_cfg0;
4054 int32_t ret;
4055
4056 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4057 if (ret == 0)
4058 {
4059 int_cfg0. sleep_status_on_int = (uint8_t)val;
4060 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG0,
4061 (uint8_t *)&int_cfg0, 1);
4062 }
4063 return ret;
4064 }
4065
4066 /**
4067 * @brief Drives the sleep status instead of sleep change on INT pins
4068 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
4069 * are enabled).[get]
4070 *
4071 * @param ctx Read / write interface definitions.(ptr)
4072 * @param val Get the values of sleep_status_on_int in reg INT_CFG0
4073 * @retval Interface status (MANDATORY: return 0 -> no Error).
4074 *
4075 */
asm330lhb_act_pin_notification_get(const stmdev_ctx_t * ctx,asm330lhb_sleep_status_on_int_t * val)4076 int32_t asm330lhb_act_pin_notification_get(const stmdev_ctx_t *ctx,
4077 asm330lhb_sleep_status_on_int_t *val)
4078 {
4079 asm330lhb_int_cfg0_t int_cfg0;
4080 int32_t ret;
4081
4082 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG0, (uint8_t *)&int_cfg0, 1);
4083 switch (int_cfg0. sleep_status_on_int)
4084 {
4085 case ASM330LHB_DRIVE_SLEEP_CHG_EVENT:
4086 *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT;
4087 break;
4088 case ASM330LHB_DRIVE_SLEEP_STATUS:
4089 *val = ASM330LHB_DRIVE_SLEEP_STATUS;
4090 break;
4091 default:
4092 *val = ASM330LHB_DRIVE_SLEEP_CHG_EVENT;
4093 break;
4094 }
4095 return ret;
4096 }
4097
4098 /**
4099 * @brief Enable inactivity function.[set]
4100 *
4101 * @param ctx Read / write interface definitions.(ptr)
4102 * @param val Change the values of inact_en in reg INT_CFG1
4103 * @retval Interface status (MANDATORY: return 0 -> no Error).
4104 *
4105 */
asm330lhb_act_mode_set(const stmdev_ctx_t * ctx,asm330lhb_inact_en_t val)4106 int32_t asm330lhb_act_mode_set(const stmdev_ctx_t *ctx, asm330lhb_inact_en_t val)
4107 {
4108 asm330lhb_int_cfg1_t int_cfg1;
4109 int32_t ret;
4110
4111 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4112 if (ret == 0)
4113 {
4114 int_cfg1.inact_en = (uint8_t)val;
4115 ret = asm330lhb_write_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4116 }
4117 return ret;
4118 }
4119
4120 /**
4121 * @brief Enable inactivity function.[get]
4122 *
4123 * @param ctx Read / write interface definitions.(ptr)
4124 * @param val Get the values of inact_en in reg INT_CFG1
4125 * @retval Interface status (MANDATORY: return 0 -> no Error).
4126 *
4127 */
asm330lhb_act_mode_get(const stmdev_ctx_t * ctx,asm330lhb_inact_en_t * val)4128 int32_t asm330lhb_act_mode_get(const stmdev_ctx_t *ctx,
4129 asm330lhb_inact_en_t *val)
4130 {
4131 asm330lhb_int_cfg1_t int_cfg1;
4132 int32_t ret;
4133
4134 ret = asm330lhb_read_reg(ctx, ASM330LHB_INT_CFG1, (uint8_t *)&int_cfg1, 1);
4135
4136 switch (int_cfg1.inact_en)
4137 {
4138 case ASM330LHB_XL_AND_GY_NOT_AFFECTED:
4139 *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED;
4140 break;
4141 case ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED:
4142 *val = ASM330LHB_XL_12Hz5_GY_NOT_AFFECTED;
4143 break;
4144 case ASM330LHB_XL_12Hz5_GY_SLEEP:
4145 *val = ASM330LHB_XL_12Hz5_GY_SLEEP;
4146 break;
4147 case ASM330LHB_XL_12Hz5_GY_PD:
4148 *val = ASM330LHB_XL_12Hz5_GY_PD;
4149 break;
4150 default:
4151 *val = ASM330LHB_XL_AND_GY_NOT_AFFECTED;
4152 break;
4153 }
4154 return ret;
4155 }
4156
4157 /**
4158 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
4159 *
4160 * @param ctx Read / write interface definitions.(ptr)
4161 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4162 * @retval Interface status (MANDATORY: return 0 -> no Error).
4163 *
4164 */
asm330lhb_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4165 int32_t asm330lhb_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4166 {
4167 asm330lhb_wake_up_dur_t wake_up_dur;
4168 int32_t ret;
4169
4170 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4171 (uint8_t *)&wake_up_dur, 1);
4172 if (ret == 0)
4173 {
4174 wake_up_dur.sleep_dur = (uint8_t)val;
4175 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4176 (uint8_t *)&wake_up_dur, 1);
4177 }
4178 return ret;
4179 }
4180
4181 /**
4182 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
4183 *
4184 * @param ctx Read / write interface definitions.(ptr)
4185 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4186 * @retval Interface status (MANDATORY: return 0 -> no Error).
4187 *
4188 */
asm330lhb_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4189 int32_t asm330lhb_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4190 {
4191 asm330lhb_wake_up_dur_t wake_up_dur;
4192 int32_t ret;
4193
4194 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4195 (uint8_t *)&wake_up_dur, 1);
4196 *val = wake_up_dur.sleep_dur;
4197
4198 return ret;
4199 }
4200
4201 /**
4202 * @}
4203 *
4204 */
4205
4206 /**
4207 * @defgroup ASM330LHB_ Six_position_detection(6D/4D)
4208 * @brief This section groups all the functions concerning six
4209 * position detection (6D).
4210 * @{
4211 *
4212 */
4213
4214 /**
4215 * @brief Threshold for 4D/6D function.[set]
4216 *
4217 * @param ctx Read / write interface definitions.(ptr)
4218 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4219 * @retval Interface status (MANDATORY: return 0 -> no Error).
4220 *
4221 */
asm330lhb_6d_threshold_set(const stmdev_ctx_t * ctx,asm330lhb_sixd_ths_t val)4222 int32_t asm330lhb_6d_threshold_set(const stmdev_ctx_t *ctx,
4223 asm330lhb_sixd_ths_t val)
4224 {
4225 asm330lhb_ths_6d_t ths_6d;
4226 int32_t ret;
4227
4228 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4229 (uint8_t *)&ths_6d, 1);
4230 if (ret == 0)
4231 {
4232 ths_6d.sixd_ths = (uint8_t)val;
4233 ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D,
4234 (uint8_t *)&ths_6d, 1);
4235 }
4236 return ret;
4237 }
4238
4239 /**
4240 * @brief Threshold for 4D/6D function.[get]
4241 *
4242 * @param ctx Read / write interface definitions.(ptr)
4243 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4244 * @retval Interface status (MANDATORY: return 0 -> no Error).
4245 *
4246 */
asm330lhb_6d_threshold_get(const stmdev_ctx_t * ctx,asm330lhb_sixd_ths_t * val)4247 int32_t asm330lhb_6d_threshold_get(const stmdev_ctx_t *ctx,
4248 asm330lhb_sixd_ths_t *val)
4249 {
4250 asm330lhb_ths_6d_t ths_6d;
4251 int32_t ret;
4252
4253 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4254 (uint8_t *)&ths_6d, 1);
4255
4256 switch (ths_6d.sixd_ths)
4257 {
4258 case ASM330LHB_DEG_80:
4259 *val = ASM330LHB_DEG_80;
4260 break;
4261 case ASM330LHB_DEG_70:
4262 *val = ASM330LHB_DEG_70;
4263 break;
4264 case ASM330LHB_DEG_60:
4265 *val = ASM330LHB_DEG_60;
4266 break;
4267 case ASM330LHB_DEG_50:
4268 *val = ASM330LHB_DEG_50;
4269 break;
4270 default:
4271 *val = ASM330LHB_DEG_80;
4272 break;
4273 }
4274 return ret;
4275 }
4276
4277 /**
4278 * @brief 4D orientation detection enable.[set]
4279 *
4280 * @param ctx Read / write interface definitions.(ptr)
4281 * @param val Change the values of d4d_en in reg TAP_THS_6D
4282 * @retval Interface status (MANDATORY: return 0 -> no Error).
4283 *
4284 */
asm330lhb_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4285 int32_t asm330lhb_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4286 {
4287 asm330lhb_ths_6d_t ths_6d;
4288 int32_t ret;
4289
4290 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4291 (uint8_t *)&ths_6d, 1);
4292 if (ret == 0)
4293 {
4294 ths_6d.d4d_en = (uint8_t)val;
4295 ret = asm330lhb_write_reg(ctx, ASM330LHB_THS_6D,
4296 (uint8_t *)&ths_6d, 1);
4297 }
4298 return ret;
4299 }
4300
4301 /**
4302 * @brief 4D orientation detection enable.[get]
4303 *
4304 * @param ctx Read / write interface definitions.(ptr)
4305 * @param val Change the values of d4d_en in reg TAP_THS_6D
4306 * @retval Interface status (MANDATORY: return 0 -> no Error).
4307 *
4308 */
asm330lhb_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4309 int32_t asm330lhb_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4310 {
4311 asm330lhb_ths_6d_t ths_6d;
4312 int32_t ret;
4313
4314 ret = asm330lhb_read_reg(ctx, ASM330LHB_THS_6D,
4315 (uint8_t *)&ths_6d, 1);
4316 *val = ths_6d.d4d_en;
4317
4318 return ret;
4319 }
4320
4321 /**
4322 * @}
4323 *
4324 */
4325
4326 /**
4327 * @defgroup ASM330LHB_free_fall
4328 * @brief This section group all the functions concerning the free
4329 * fall detection.
4330 * @{
4331 *
4332 */
4333
4334 /**
4335 * @brief Free fall threshold setting.[set]
4336 *
4337 * @param ctx Read / write interface definitions.(ptr)
4338 * @param val Change the values of ff_ths in reg FREE_FALL
4339 * @retval Interface status (MANDATORY: return 0 -> no Error).
4340 *
4341 */
asm330lhb_ff_threshold_set(const stmdev_ctx_t * ctx,asm330lhb_ff_ths_t val)4342 int32_t asm330lhb_ff_threshold_set(const stmdev_ctx_t *ctx,
4343 asm330lhb_ff_ths_t val)
4344 {
4345 asm330lhb_free_fall_t free_fall;
4346 int32_t ret;
4347
4348 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1);
4349 if (ret == 0)
4350 {
4351 free_fall.ff_ths = (uint8_t)val;
4352 ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL,
4353 (uint8_t *)&free_fall, 1);
4354 }
4355 return ret;
4356 }
4357
4358 /**
4359 * @brief Free fall threshold setting.[get]
4360 *
4361 * @param ctx Read / write interface definitions.(ptr)
4362 * @param val Get the values of ff_ths in reg FREE_FALL
4363 * @retval Interface status (MANDATORY: return 0 -> no Error).
4364 *
4365 */
asm330lhb_ff_threshold_get(const stmdev_ctx_t * ctx,asm330lhb_ff_ths_t * val)4366 int32_t asm330lhb_ff_threshold_get(const stmdev_ctx_t *ctx,
4367 asm330lhb_ff_ths_t *val)
4368 {
4369 asm330lhb_free_fall_t free_fall;
4370 int32_t ret;
4371
4372 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL, (uint8_t *)&free_fall, 1);
4373
4374 switch (free_fall.ff_ths)
4375 {
4376 case ASM330LHB_FF_TSH_156mg:
4377 *val = ASM330LHB_FF_TSH_156mg;
4378 break;
4379 case ASM330LHB_FF_TSH_219mg:
4380 *val = ASM330LHB_FF_TSH_219mg;
4381 break;
4382 case ASM330LHB_FF_TSH_250mg:
4383 *val = ASM330LHB_FF_TSH_250mg;
4384 break;
4385 case ASM330LHB_FF_TSH_312mg:
4386 *val = ASM330LHB_FF_TSH_312mg;
4387 break;
4388 case ASM330LHB_FF_TSH_344mg:
4389 *val = ASM330LHB_FF_TSH_344mg;
4390 break;
4391 case ASM330LHB_FF_TSH_406mg:
4392 *val = ASM330LHB_FF_TSH_406mg;
4393 break;
4394 case ASM330LHB_FF_TSH_469mg:
4395 *val = ASM330LHB_FF_TSH_469mg;
4396 break;
4397 case ASM330LHB_FF_TSH_500mg:
4398 *val = ASM330LHB_FF_TSH_500mg;
4399 break;
4400 default:
4401 *val = ASM330LHB_FF_TSH_156mg;
4402 break;
4403 }
4404 return ret;
4405 }
4406
4407 /**
4408 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
4409 *
4410 * @param ctx Read / write interface definitions.(ptr)
4411 * @param val Change the values of ff_dur in reg FREE_FALL
4412 * @retval Interface status (MANDATORY: return 0 -> no Error).
4413 *
4414 */
asm330lhb_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4415 int32_t asm330lhb_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4416 {
4417 asm330lhb_wake_up_dur_t wake_up_dur;
4418 asm330lhb_free_fall_t free_fall;
4419 int32_t ret;
4420
4421 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4422 (uint8_t *)&wake_up_dur, 1);
4423 if (ret == 0)
4424 {
4425 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4426 ret = asm330lhb_write_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4427 (uint8_t *)&wake_up_dur, 1);
4428 }
4429 if (ret == 0)
4430 {
4431 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL,
4432 (uint8_t *)&free_fall, 1);
4433 }
4434 if (ret == 0)
4435 {
4436 free_fall.ff_dur = val & 0x1FU;
4437 ret = asm330lhb_write_reg(ctx, ASM330LHB_FREE_FALL,
4438 (uint8_t *)&free_fall, 1);
4439 }
4440 return ret;
4441 }
4442
4443 /**
4444 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
4445 *
4446 * @param ctx Read / write interface definitions.(ptr)
4447 * @param val Change the values of ff_dur in reg FREE_FALL
4448 * @retval Interface status (MANDATORY: return 0 -> no Error).
4449 *
4450 */
asm330lhb_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4451 int32_t asm330lhb_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4452 {
4453 asm330lhb_wake_up_dur_t wake_up_dur;
4454 asm330lhb_free_fall_t free_fall;
4455 int32_t ret;
4456
4457 ret = asm330lhb_read_reg(ctx, ASM330LHB_WAKE_UP_DUR,
4458 (uint8_t *)&wake_up_dur, 1);
4459
4460 if (ret == 0)
4461 {
4462 ret = asm330lhb_read_reg(ctx, ASM330LHB_FREE_FALL,
4463 (uint8_t *)&free_fall, 1);
4464 }
4465 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4466
4467 return ret;
4468 }
4469
4470 /**
4471 * @}
4472 *
4473 */
4474
4475 /**
4476 * @defgroup ASM330LHB_fifo
4477 * @brief This section group all the functions concerning
4478 * the fifo usage
4479 * @{
4480 *
4481 */
4482
4483 /**
4484 * @brief FIFO watermark level selection.[set]
4485 *
4486 * @param ctx Read / write interface definitions.(ptr)
4487 * @param val Change the values of wtm in reg FIFO_CTRL1
4488 * @retval Interface status (MANDATORY: return 0 -> no Error).
4489 *
4490 */
asm330lhb_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)4491 int32_t asm330lhb_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
4492 {
4493 asm330lhb_fifo_ctrl1_t fifo_ctrl1;
4494 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4495 int32_t ret;
4496
4497 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4498 ret += asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4499
4500 if (ret == 0)
4501 {
4502 fifo_ctrl1.wtm = (uint8_t)(val & 0xFFU);
4503 fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
4504 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4505 ret += asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4506 }
4507
4508 return ret;
4509 }
4510
4511 /**
4512 * @brief FIFO watermark level selection.[get]
4513 *
4514 * @param ctx Read / write interface definitions.(ptr)
4515 * @param val Change the values of wtm in reg FIFO_CTRL1
4516 * @retval Interface status (MANDATORY: return 0 -> no Error).
4517 *
4518 */
asm330lhb_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)4519 int32_t asm330lhb_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
4520 {
4521 asm330lhb_fifo_ctrl1_t fifo_ctrl1;
4522 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4523 int32_t ret;
4524
4525 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4526 (uint8_t *)&fifo_ctrl2, 1);
4527 if (ret == 0)
4528 {
4529 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL1,
4530 (uint8_t *)&fifo_ctrl1, 1);
4531 }
4532 *val = fifo_ctrl2.wtm;
4533 *val = (*val * 256U) + fifo_ctrl1.wtm;
4534 return ret;
4535 }
4536
4537 /**
4538 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4539 *
4540 * @param ctx Read / write interface definitions.(ptr)
4541 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4542 * @retval Interface status (MANDATORY: return 0 -> no Error).
4543 *
4544 */
asm330lhb_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4545 int32_t asm330lhb_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4546 uint8_t val)
4547 {
4548 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4549 int32_t ret;
4550
4551 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4552 (uint8_t *)&fifo_ctrl2, 1);
4553 if (ret == 0)
4554 {
4555 fifo_ctrl2.odrchg_en = (uint8_t)val;
4556 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
4557 (uint8_t *)&fifo_ctrl2, 1);
4558 }
4559
4560 return ret;
4561 }
4562
4563 /**
4564 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4565 *
4566 * @param ctx Read / write interface definitions.(ptr)
4567 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
4568 * @retval Interface status (MANDATORY: return 0 -> no Error).
4569 *
4570 */
asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4571 int32_t asm330lhb_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4572 uint8_t *val)
4573 {
4574 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4575 int32_t ret;
4576
4577 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4578 (uint8_t *)&fifo_ctrl2, 1);
4579 *val = fifo_ctrl2.odrchg_en;
4580
4581 return ret;
4582 }
4583
4584 /**
4585 * @brief Sensing chain FIFO stop values memorization at threshold
4586 * level.[set]
4587 *
4588 * @param ctx Read / write interface definitions.(ptr)
4589 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4590 * @retval Interface status (MANDATORY: return 0 -> no Error).
4591 *
4592 */
asm330lhb_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4593 int32_t asm330lhb_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4594 {
4595 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4596 int32_t ret;
4597
4598 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4599 (uint8_t *)&fifo_ctrl2, 1);
4600 if (ret == 0)
4601 {
4602 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
4603 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL2,
4604 (uint8_t *)&fifo_ctrl2, 1);
4605 }
4606 return ret;
4607 }
4608
4609 /**
4610 * @brief Sensing chain FIFO stop values memorization at threshold
4611 * level.[get]
4612 *
4613 * @param ctx Read / write interface definitions.(ptr)
4614 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4615 * @retval Interface status (MANDATORY: return 0 -> no Error).
4616 *
4617 */
asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)4618 int32_t asm330lhb_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4619 {
4620 asm330lhb_fifo_ctrl2_t fifo_ctrl2;
4621 int32_t ret;
4622
4623 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL2,
4624 (uint8_t *)&fifo_ctrl2, 1);
4625 *val = fifo_ctrl2.stop_on_wtm;
4626
4627 return ret;
4628 }
4629
4630 /**
4631 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4632 * for accelerometer data.[set]
4633 *
4634 * @param ctx Read / write interface definitions.(ptr)
4635 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
4636 * @retval Interface status (MANDATORY: return 0 -> no Error).
4637 *
4638 */
asm330lhb_fifo_xl_batch_set(const stmdev_ctx_t * ctx,asm330lhb_bdr_xl_t val)4639 int32_t asm330lhb_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
4640 asm330lhb_bdr_xl_t val)
4641 {
4642 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4643 int32_t ret;
4644
4645 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4646 (uint8_t *)&fifo_ctrl3, 1);
4647 if (ret == 0)
4648 {
4649 fifo_ctrl3.bdr_xl = (uint8_t)val;
4650 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3,
4651 (uint8_t *)&fifo_ctrl3, 1);
4652 }
4653 return ret;
4654 }
4655
4656 /**
4657 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4658 * for accelerometer data.[get]
4659 *
4660 * @param ctx Read / write interface definitions.(ptr)
4661 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
4662 * @retval Interface status (MANDATORY: return 0 -> no Error).
4663 *
4664 */
asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t * ctx,asm330lhb_bdr_xl_t * val)4665 int32_t asm330lhb_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
4666 asm330lhb_bdr_xl_t *val)
4667 {
4668 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4669 int32_t ret;
4670
4671 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4672 (uint8_t *)&fifo_ctrl3, 1);
4673
4674 switch (fifo_ctrl3.bdr_xl)
4675 {
4676 case ASM330LHB_XL_NOT_BATCHED:
4677 *val = ASM330LHB_XL_NOT_BATCHED;
4678 break;
4679 case ASM330LHB_XL_BATCHED_AT_12Hz5:
4680 *val = ASM330LHB_XL_BATCHED_AT_12Hz5;
4681 break;
4682 case ASM330LHB_XL_BATCHED_AT_26Hz:
4683 *val = ASM330LHB_XL_BATCHED_AT_26Hz;
4684 break;
4685 case ASM330LHB_XL_BATCHED_AT_52Hz:
4686 *val = ASM330LHB_XL_BATCHED_AT_52Hz;
4687 break;
4688 case ASM330LHB_XL_BATCHED_AT_104Hz:
4689 *val = ASM330LHB_XL_BATCHED_AT_104Hz;
4690 break;
4691 case ASM330LHB_XL_BATCHED_AT_208Hz:
4692 *val = ASM330LHB_XL_BATCHED_AT_208Hz;
4693 break;
4694 case ASM330LHB_XL_BATCHED_AT_417Hz:
4695 *val = ASM330LHB_XL_BATCHED_AT_417Hz;
4696 break;
4697 case ASM330LHB_XL_BATCHED_AT_833Hz:
4698 *val = ASM330LHB_XL_BATCHED_AT_833Hz;
4699 break;
4700 case ASM330LHB_XL_BATCHED_AT_1667Hz:
4701 *val = ASM330LHB_XL_BATCHED_AT_1667Hz;
4702 break;
4703 case ASM330LHB_XL_BATCHED_AT_1Hz6:
4704 *val = ASM330LHB_XL_BATCHED_AT_1Hz6;
4705 break;
4706 default:
4707 *val = ASM330LHB_XL_NOT_BATCHED;
4708 break;
4709 }
4710 return ret;
4711 }
4712
4713 /**
4714 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4715 * for gyroscope data.[set]
4716 *
4717 * @param ctx Read / write interface definitions.(ptr)
4718 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
4719 * @retval Interface status (MANDATORY: return 0 -> no Error).
4720 *
4721 */
asm330lhb_fifo_gy_batch_set(const stmdev_ctx_t * ctx,asm330lhb_bdr_gy_t val)4722 int32_t asm330lhb_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
4723 asm330lhb_bdr_gy_t val)
4724 {
4725 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4726 int32_t ret;
4727
4728 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4729 (uint8_t *)&fifo_ctrl3, 1);
4730 if (ret == 0)
4731 {
4732 fifo_ctrl3.bdr_gy = (uint8_t)val;
4733 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL3,
4734 (uint8_t *)&fifo_ctrl3, 1);
4735 }
4736 return ret;
4737 }
4738
4739 /**
4740 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4741 * for gyroscope data.[get]
4742 *
4743 * @param ctx Read / write interface definitions.(ptr)
4744 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
4745 * @retval Interface status (MANDATORY: return 0 -> no Error).
4746 *
4747 */
asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t * ctx,asm330lhb_bdr_gy_t * val)4748 int32_t asm330lhb_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
4749 asm330lhb_bdr_gy_t *val)
4750 {
4751 asm330lhb_fifo_ctrl3_t fifo_ctrl3;
4752 int32_t ret;
4753
4754 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL3,
4755 (uint8_t *)&fifo_ctrl3, 1);
4756
4757 switch (fifo_ctrl3.bdr_gy)
4758 {
4759 case ASM330LHB_GY_NOT_BATCHED:
4760 *val = ASM330LHB_GY_NOT_BATCHED;
4761 break;
4762 case ASM330LHB_GY_BATCHED_AT_12Hz5:
4763 *val = ASM330LHB_GY_BATCHED_AT_12Hz5;
4764 break;
4765 case ASM330LHB_GY_BATCHED_AT_26Hz:
4766 *val = ASM330LHB_GY_BATCHED_AT_26Hz;
4767 break;
4768 case ASM330LHB_GY_BATCHED_AT_52Hz:
4769 *val = ASM330LHB_GY_BATCHED_AT_52Hz;
4770 break;
4771 case ASM330LHB_GY_BATCHED_AT_104Hz:
4772 *val = ASM330LHB_GY_BATCHED_AT_104Hz;
4773 break;
4774 case ASM330LHB_GY_BATCHED_AT_208Hz:
4775 *val = ASM330LHB_GY_BATCHED_AT_208Hz;
4776 break;
4777 case ASM330LHB_GY_BATCHED_AT_417Hz:
4778 *val = ASM330LHB_GY_BATCHED_AT_417Hz;
4779 break;
4780 case ASM330LHB_GY_BATCHED_AT_833Hz:
4781 *val = ASM330LHB_GY_BATCHED_AT_833Hz;
4782 break;
4783 case ASM330LHB_GY_BATCHED_AT_1667Hz:
4784 *val = ASM330LHB_GY_BATCHED_AT_1667Hz;
4785 break;
4786 case ASM330LHB_GY_BATCHED_AT_6Hz5:
4787 *val = ASM330LHB_GY_BATCHED_AT_6Hz5;
4788 break;
4789 default:
4790 *val = ASM330LHB_GY_NOT_BATCHED;
4791 break;
4792 }
4793 return ret;
4794 }
4795
4796 /**
4797 * @brief FIFO mode selection.[set]
4798 *
4799 * @param ctx Read / write interface definitions.(ptr)
4800 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
4801 * @retval Interface status (MANDATORY: return 0 -> no Error).
4802 *
4803 */
asm330lhb_fifo_mode_set(const stmdev_ctx_t * ctx,asm330lhb_fifo_mode_t val)4804 int32_t asm330lhb_fifo_mode_set(const stmdev_ctx_t *ctx,
4805 asm330lhb_fifo_mode_t val)
4806 {
4807 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4808 int32_t ret;
4809
4810 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4811 (uint8_t *)&fifo_ctrl4, 1);
4812 if (ret == 0)
4813 {
4814 fifo_ctrl4.fifo_mode = (uint8_t)val;
4815 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4816 (uint8_t *)&fifo_ctrl4, 1);
4817 }
4818 return ret;
4819 }
4820
4821 /**
4822 * @brief FIFO mode selection.[get]
4823 *
4824 * @param ctx Read / write interface definitions.(ptr)
4825 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
4826 * @retval Interface status (MANDATORY: return 0 -> no Error).
4827 *
4828 */
asm330lhb_fifo_mode_get(const stmdev_ctx_t * ctx,asm330lhb_fifo_mode_t * val)4829 int32_t asm330lhb_fifo_mode_get(const stmdev_ctx_t *ctx,
4830 asm330lhb_fifo_mode_t *val)
4831 {
4832 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4833 int32_t ret;
4834
4835 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4836 (uint8_t *)&fifo_ctrl4, 1);
4837
4838 switch (fifo_ctrl4.fifo_mode)
4839 {
4840 case ASM330LHB_BYPASS_MODE:
4841 *val = ASM330LHB_BYPASS_MODE;
4842 break;
4843 case ASM330LHB_FIFO_MODE:
4844 *val = ASM330LHB_FIFO_MODE;
4845 break;
4846 case ASM330LHB_STREAM_TO_FIFO_MODE:
4847 *val = ASM330LHB_STREAM_TO_FIFO_MODE;
4848 break;
4849 case ASM330LHB_BYPASS_TO_STREAM_MODE:
4850 *val = ASM330LHB_BYPASS_TO_STREAM_MODE;
4851 break;
4852 case ASM330LHB_STREAM_MODE:
4853 *val = ASM330LHB_STREAM_MODE;
4854 break;
4855 case ASM330LHB_BYPASS_TO_FIFO_MODE:
4856 *val = ASM330LHB_BYPASS_TO_FIFO_MODE;
4857 break;
4858 default:
4859 *val = ASM330LHB_BYPASS_MODE;
4860 break;
4861 }
4862 return ret;
4863 }
4864
4865 /**
4866 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4867 * for temperature data.[set]
4868 *
4869 * @param ctx Read / write interface definitions.(ptr)
4870 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
4871 * @retval Interface status (MANDATORY: return 0 -> no Error).
4872 *
4873 */
asm330lhb_fifo_temp_batch_set(const stmdev_ctx_t * ctx,asm330lhb_odr_t_batch_t val)4874 int32_t asm330lhb_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4875 asm330lhb_odr_t_batch_t val)
4876 {
4877 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4878 int32_t ret;
4879
4880 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4881 (uint8_t *)&fifo_ctrl4, 1);
4882 if (ret == 0)
4883 {
4884 fifo_ctrl4.odr_t_batch = (uint8_t)val;
4885 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4886 (uint8_t *)&fifo_ctrl4, 1);
4887 }
4888 return ret;
4889 }
4890
4891 /**
4892 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4893 * for temperature data.[get]
4894 *
4895 * @param ctx Read / write interface definitions.(ptr)
4896 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
4897 * @retval Interface status (MANDATORY: return 0 -> no Error).
4898 *
4899 */
asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t * ctx,asm330lhb_odr_t_batch_t * val)4900 int32_t asm330lhb_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4901 asm330lhb_odr_t_batch_t *val)
4902 {
4903 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4904 int32_t ret;
4905
4906 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4907 (uint8_t *)&fifo_ctrl4, 1);
4908
4909 switch (fifo_ctrl4.odr_t_batch)
4910 {
4911 case ASM330LHB_TEMP_NOT_BATCHED:
4912 *val = ASM330LHB_TEMP_NOT_BATCHED;
4913 break;
4914 case ASM330LHB_TEMP_BATCHED_AT_52Hz:
4915 *val = ASM330LHB_TEMP_BATCHED_AT_52Hz;
4916 break;
4917 case ASM330LHB_TEMP_BATCHED_AT_12Hz5:
4918 *val = ASM330LHB_TEMP_BATCHED_AT_12Hz5;
4919 break;
4920 case ASM330LHB_TEMP_BATCHED_AT_1Hz6:
4921 *val = ASM330LHB_TEMP_BATCHED_AT_1Hz6;
4922 break;
4923 default:
4924 *val = ASM330LHB_TEMP_NOT_BATCHED;
4925 break;
4926 }
4927 return ret;
4928 }
4929
4930 /**
4931 * @brief Selects decimation for timestamp batching in FIFO.
4932 * Writing rate will be the maximum rate between XL and
4933 * GYRO BDR divided by decimation decoder.[set]
4934 *
4935 * @param ctx Read / write interface definitions.(ptr)
4936 * @param val Change the values of dec_ts_batch in reg FIFO_CTRL4
4937 * @retval Interface status (MANDATORY: return 0 -> no Error).
4938 *
4939 */
asm330lhb_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,asm330lhb_dec_ts_batch_t val)4940 int32_t asm330lhb_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
4941 asm330lhb_dec_ts_batch_t val)
4942 {
4943 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4944 int32_t ret;
4945
4946 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4947 (uint8_t *)&fifo_ctrl4, 1);
4948 if (ret == 0)
4949 {
4950 fifo_ctrl4.dec_ts_batch = (uint8_t)val;
4951 ret = asm330lhb_write_reg(ctx, ASM330LHB_FIFO_CTRL4,
4952 (uint8_t *)&fifo_ctrl4, 1);
4953 }
4954 return ret;
4955 }
4956
4957 /**
4958 * @brief Selects decimation for timestamp batching in FIFO.
4959 * Writing rate will be the maximum rate between XL and
4960 * GYRO BDR divided by decimation decoder.[get]
4961 *
4962 * @param ctx Read / write interface definitions.(ptr)
4963 * @param val Get the values of dec_ts_batch in reg
4964 * FIFO_CTRL4
4965 * @retval Interface status (MANDATORY: return 0 -> no Error).
4966 *
4967 */
asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,asm330lhb_dec_ts_batch_t * val)4968 int32_t asm330lhb_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
4969 asm330lhb_dec_ts_batch_t *val)
4970 {
4971 asm330lhb_fifo_ctrl4_t fifo_ctrl4;
4972 int32_t ret;
4973
4974 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_CTRL4,
4975 (uint8_t *)&fifo_ctrl4, 1);
4976
4977 switch (fifo_ctrl4.dec_ts_batch)
4978 {
4979 case ASM330LHB_NO_DECIMATION:
4980 *val = ASM330LHB_NO_DECIMATION;
4981 break;
4982 case ASM330LHB_DEC_1:
4983 *val = ASM330LHB_DEC_1;
4984 break;
4985 case ASM330LHB_DEC_8:
4986 *val = ASM330LHB_DEC_8;
4987 break;
4988 case ASM330LHB_DEC_32:
4989 *val = ASM330LHB_DEC_32;
4990 break;
4991 default:
4992 *val = ASM330LHB_NO_DECIMATION;
4993 break;
4994 }
4995 return ret;
4996 }
4997
4998 /**
4999 * @brief Selects the trigger for the internal counter of batching events
5000 * between XL and gyro.[set]
5001 *
5002 * @param ctx Read / write interface definitions.(ptr)
5003 * @param val Change the values of trig_counter_bdr in
5004 * reg COUNTER_BDR_REG1
5005 * @retval Interface status (MANDATORY: return 0 -> no Error).
5006 *
5007 */
asm330lhb_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,asm330lhb_trig_counter_bdr_t val)5008 int32_t asm330lhb_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
5009 asm330lhb_trig_counter_bdr_t val)
5010 {
5011 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5012 int32_t ret;
5013
5014 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5015 (uint8_t *)&counter_bdr_reg1, 1);
5016 if (ret == 0)
5017 {
5018 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
5019 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5020 (uint8_t *)&counter_bdr_reg1, 1);
5021 }
5022 return ret;
5023 }
5024
5025 /**
5026 * @brief Selects the trigger for the internal counter of batching events
5027 * between XL and gyro.[get]
5028 *
5029 * @param ctx Read / write interface definitions.(ptr)
5030 * @param val Get the values of trig_counter_bdr
5031 * in reg COUNTER_BDR_REG1
5032 * @retval Interface status (MANDATORY: return 0 -> no Error).
5033 *
5034 */
asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,asm330lhb_trig_counter_bdr_t * val)5035 int32_t asm330lhb_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
5036 asm330lhb_trig_counter_bdr_t *val)
5037 {
5038 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5039 int32_t ret;
5040
5041 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5042 (uint8_t *)&counter_bdr_reg1, 1);
5043
5044 switch (counter_bdr_reg1.trig_counter_bdr)
5045 {
5046 case ASM330LHB_XL_BATCH_EVENT:
5047 *val = ASM330LHB_XL_BATCH_EVENT;
5048 break;
5049 case ASM330LHB_GYRO_BATCH_EVENT:
5050 *val = ASM330LHB_GYRO_BATCH_EVENT;
5051 break;
5052 default:
5053 *val = ASM330LHB_XL_BATCH_EVENT;
5054 break;
5055 }
5056 return ret;
5057 }
5058
5059 /**
5060 * @brief Resets the internal counter of batching events for a single sensor.
5061 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5062 *
5063 * @param ctx Read / write interface definitions.(ptr)
5064 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5065 * @retval Interface status (MANDATORY: return 0 -> no Error).
5066 *
5067 */
asm330lhb_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)5068 int32_t asm330lhb_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val)
5069 {
5070 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5071 int32_t ret;
5072
5073 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5074 (uint8_t *)&counter_bdr_reg1, 1);
5075 if (ret == 0)
5076 {
5077 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
5078 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5079 (uint8_t *)&counter_bdr_reg1, 1);
5080 }
5081 return ret;
5082 }
5083
5084 /**
5085 * @brief Resets the internal counter of batching events for a single sensor.
5086 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5087 *
5088 * @param ctx Read / write interface definitions.(ptr)
5089 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
5090 * @retval Interface status (MANDATORY: return 0 -> no Error).
5091 *
5092 */
asm330lhb_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)5093 int32_t asm330lhb_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val)
5094 {
5095 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5096 int32_t ret;
5097
5098 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5099 (uint8_t *)&counter_bdr_reg1, 1);
5100 *val = counter_bdr_reg1.rst_counter_bdr;
5101
5102 return ret;
5103 }
5104
5105 /**
5106 * @brief Batch data rate counter.[set]
5107 *
5108 * @param ctx Read / write interface definitions.(ptr)
5109 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5110 * and COUNTER_BDR_REG1.
5111 * @retval Interface status (MANDATORY: return 0 -> no Error).
5112 *
5113 */
asm330lhb_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5114 int32_t asm330lhb_batch_counter_threshold_set(const stmdev_ctx_t *ctx, uint16_t val)
5115 {
5116 asm330lhb_counter_bdr_reg2_t counter_bdr_reg1;
5117 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2;
5118 int32_t ret;
5119
5120 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5121 (uint8_t *)&counter_bdr_reg1, 1);
5122 if (ret == 0)
5123 {
5124 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
5125 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5126 (uint8_t *)&counter_bdr_reg1, 1);
5127 }
5128 if (ret == 0)
5129 {
5130 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val - (counter_bdr_reg1.cnt_bdr_th * 256U));
5131 ret = asm330lhb_write_reg(ctx, ASM330LHB_COUNTER_BDR_REG2,
5132 (uint8_t *)&counter_bdr_reg2, 1);
5133 }
5134 return ret;
5135 }
5136
5137 /**
5138 * @brief Batch data rate counter.[get]
5139 *
5140 * @param ctx Read / write interface definitions.(ptr)
5141 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
5142 * and COUNTER_BDR_REG1.
5143 * @retval Interface status (MANDATORY: return 0 -> no Error).
5144 *
5145 */
asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5146 int32_t asm330lhb_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5147 uint16_t *val)
5148 {
5149 asm330lhb_counter_bdr_reg1_t counter_bdr_reg1;
5150 asm330lhb_counter_bdr_reg2_t counter_bdr_reg2;
5151 int32_t ret;
5152
5153 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG1,
5154 (uint8_t *)&counter_bdr_reg1, 1);
5155 if (ret == 0)
5156 {
5157 ret = asm330lhb_read_reg(ctx, ASM330LHB_COUNTER_BDR_REG2,
5158 (uint8_t *)&counter_bdr_reg2, 1);
5159 }
5160
5161 *val = counter_bdr_reg1.cnt_bdr_th;
5162 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
5163 return ret;
5164 }
5165
5166 /**
5167 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
5168 *
5169 * @param ctx Read / write interface definitions.(ptr)
5170 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
5171 * @retval Interface status (MANDATORY: return 0 -> no Error).
5172 *
5173 */
asm330lhb_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5174 int32_t asm330lhb_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
5175 {
5176 uint8_t reg[2];
5177 asm330lhb_fifo_status1_t *fifo_status1 = (asm330lhb_fifo_status1_t *)®[0];
5178 asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)®[1];
5179 int32_t ret;
5180
5181 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5182 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
5183 if (ret == 0)
5184 {
5185 *val = fifo_status2->diff_fifo;
5186 *val = (*val * 256U) + fifo_status1->diff_fifo;
5187 }
5188
5189 return ret;
5190 }
5191
5192 /**
5193 * @brief Smart FIFO status.[get]
5194 *
5195 * @param ctx Read / write interface definitions.(ptr)
5196 * @param val Read registers FIFO_STATUS2
5197 * @retval Interface status (MANDATORY: return 0 -> no Error).
5198 *
5199 */
asm330lhb_fifo_status_get(const stmdev_ctx_t * ctx,asm330lhb_fifo_status2_t * val)5200 int32_t asm330lhb_fifo_status_get(const stmdev_ctx_t *ctx,
5201 asm330lhb_fifo_status2_t *val)
5202 {
5203 uint8_t reg[2];
5204 asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)®[1];
5205 int32_t ret;
5206
5207 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5208 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
5209 if (ret == 0)
5210 {
5211 *val = *fifo_status2;
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief Smart FIFO full status.[get]
5219 *
5220 * @param ctx Read / write interface definitions.(ptr)
5221 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
5222 * @retval Interface status (MANDATORY: return 0 -> no Error).
5223 *
5224 */
asm330lhb_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5225 int32_t asm330lhb_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5226 {
5227 uint8_t reg[2];
5228 asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)®[1];
5229 int32_t ret;
5230
5231 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5232 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
5233 if (ret == 0)
5234 {
5235 *val = fifo_status2->fifo_full_ia;
5236 }
5237
5238 return ret;
5239 }
5240
5241 /**
5242 * @brief FIFO overrun status.[get]
5243 *
5244 * @param ctx Read / write interface definitions.(ptr)
5245 * @param val Read the values of fifo_over_run_latched in
5246 * reg FIFO_STATUS2
5247 * @retval Interface status (MANDATORY: return 0 -> no Error).
5248 *
5249 */
asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5250 int32_t asm330lhb_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5251 {
5252 uint8_t reg[2];
5253 asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)®[1];
5254 int32_t ret;
5255
5256 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5257 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
5258 if (ret == 0)
5259 {
5260 *val = fifo_status2->fifo_ovr_ia;
5261 }
5262
5263 return ret;
5264 }
5265
5266 /**
5267 * @brief FIFO watermark status.[get]
5268 *
5269 * @param ctx Read / write interface definitions.(ptr)
5270 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
5271 * @retval Interface status (MANDATORY: return 0 -> no Error).
5272 *
5273 */
asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5274 int32_t asm330lhb_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5275 {
5276 uint8_t reg[2];
5277 asm330lhb_fifo_status2_t *fifo_status2 = (asm330lhb_fifo_status2_t *)®[1];
5278 int32_t ret;
5279
5280 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
5281 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_STATUS1, (uint8_t *)reg, 2);
5282 if (ret == 0)
5283 {
5284 *val = fifo_status2->fifo_wtm_ia;
5285 }
5286
5287 return ret;
5288 }
5289
5290 /**
5291 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
5292 *
5293 * @param ctx Read / write interface definitions.(ptr)
5294 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
5295 * @retval Interface status (MANDATORY: return 0 -> no Error).
5296 *
5297 */
asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,asm330lhb_fifo_tag_t * val)5298 int32_t asm330lhb_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
5299 asm330lhb_fifo_tag_t *val)
5300 {
5301 asm330lhb_fifo_data_out_tag_t fifo_data_out_tag;
5302 int32_t ret;
5303
5304 ret = asm330lhb_read_reg(ctx, ASM330LHB_FIFO_DATA_OUT_TAG,
5305 (uint8_t *)&fifo_data_out_tag, 1);
5306
5307 switch (fifo_data_out_tag.tag_sensor)
5308 {
5309 case ASM330LHB_GYRO_NC_TAG:
5310 *val = ASM330LHB_GYRO_NC_TAG;
5311 break;
5312 case ASM330LHB_XL_NC_TAG:
5313 *val = ASM330LHB_XL_NC_TAG;
5314 break;
5315 case ASM330LHB_TEMPERATURE_TAG:
5316 *val = ASM330LHB_TEMPERATURE_TAG;
5317 break;
5318 case ASM330LHB_TIMESTAMP_TAG:
5319 *val = ASM330LHB_TIMESTAMP_TAG;
5320 break;
5321 case ASM330LHB_CFG_CHANGE_TAG:
5322 *val = ASM330LHB_CFG_CHANGE_TAG;
5323 break;
5324 default:
5325 *val = ASM330LHB_XL_NC_TAG;
5326 break;
5327 }
5328 return ret;
5329 }
5330
5331 /**
5332 * @}
5333 *
5334 */
5335
5336 /**
5337 * @defgroup ASM330LHB_DEN_functionality
5338 * @brief This section groups all the functions concerning
5339 * DEN functionality.
5340 * @{
5341 *
5342 */
5343
5344 /**
5345 * @brief DEN functionality marking mode.[set]
5346 *
5347 * @param ctx Read / write interface definitions.(ptr)
5348 * @param val Change the values of den_mode in reg CTRL6_C
5349 * @retval Interface status (MANDATORY: return 0 -> no Error).
5350 *
5351 */
asm330lhb_den_mode_set(const stmdev_ctx_t * ctx,asm330lhb_den_mode_t val)5352 int32_t asm330lhb_den_mode_set(const stmdev_ctx_t *ctx, asm330lhb_den_mode_t val)
5353 {
5354 asm330lhb_ctrl6_c_t ctrl6_c;
5355 int32_t ret;
5356
5357 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5358 if (ret == 0)
5359 {
5360 ctrl6_c.den_mode = (uint8_t)val;
5361 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5362 }
5363 return ret;
5364 }
5365
5366 /**
5367 * @brief DEN functionality marking mode.[get]
5368 *
5369 * @param ctx Read / write interface definitions.(ptr)
5370 * @param val Get the values of den_mode in reg CTRL6_C
5371 * @retval Interface status (MANDATORY: return 0 -> no Error).
5372 *
5373 */
asm330lhb_den_mode_get(const stmdev_ctx_t * ctx,asm330lhb_den_mode_t * val)5374 int32_t asm330lhb_den_mode_get(const stmdev_ctx_t *ctx,
5375 asm330lhb_den_mode_t *val)
5376 {
5377 asm330lhb_ctrl6_c_t ctrl6_c;
5378 int32_t ret;
5379
5380 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5381
5382 switch (ctrl6_c.den_mode)
5383 {
5384 case ASM330LHB_DEN_DISABLE:
5385 *val = ASM330LHB_DEN_DISABLE;
5386 break;
5387 case ASM330LHB_LEVEL_FIFO:
5388 *val = ASM330LHB_LEVEL_FIFO;
5389 break;
5390 case ASM330LHB_LEVEL_LETCHED:
5391 *val = ASM330LHB_LEVEL_LETCHED;
5392 break;
5393 case ASM330LHB_LEVEL_TRIGGER:
5394 *val = ASM330LHB_LEVEL_TRIGGER;
5395 break;
5396 case ASM330LHB_EDGE_TRIGGER:
5397 *val = ASM330LHB_EDGE_TRIGGER;
5398 break;
5399 default:
5400 *val = ASM330LHB_DEN_DISABLE;
5401 break;
5402 }
5403 return ret;
5404 }
5405
5406 /**
5407 * @brief DEN active level configuration.[set]
5408 *
5409 * @param ctx Read / write interface definitions.(ptr)
5410 * @param val Change the values of den_lh in reg CTRL9_XL
5411 * @retval Interface status (MANDATORY: return 0 -> no Error).
5412 *
5413 */
asm330lhb_den_polarity_set(const stmdev_ctx_t * ctx,asm330lhb_den_lh_t val)5414 int32_t asm330lhb_den_polarity_set(const stmdev_ctx_t *ctx,
5415 asm330lhb_den_lh_t val)
5416 {
5417 asm330lhb_ctrl9_xl_t ctrl9_xl;
5418 int32_t ret;
5419
5420 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5421 if (ret == 0)
5422 {
5423 ctrl9_xl.den_lh = (uint8_t)val;
5424 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5425 (uint8_t *)&ctrl9_xl, 1);
5426 }
5427 return ret;
5428 }
5429
5430 /**
5431 * @brief DEN active level configuration.[get]
5432 *
5433 * @param ctx Read / write interface definitions.(ptr)
5434 * @param val Get the values of den_lh in reg CTRL9_XL
5435 * @retval Interface status (MANDATORY: return 0 -> no Error).
5436 *
5437 */
asm330lhb_den_polarity_get(const stmdev_ctx_t * ctx,asm330lhb_den_lh_t * val)5438 int32_t asm330lhb_den_polarity_get(const stmdev_ctx_t *ctx,
5439 asm330lhb_den_lh_t *val)
5440 {
5441 asm330lhb_ctrl9_xl_t ctrl9_xl;
5442 int32_t ret;
5443
5444 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5445
5446 switch (ctrl9_xl.den_lh)
5447 {
5448 case ASM330LHB_DEN_ACT_LOW:
5449 *val = ASM330LHB_DEN_ACT_LOW;
5450 break;
5451 case ASM330LHB_DEN_ACT_HIGH:
5452 *val = ASM330LHB_DEN_ACT_HIGH;
5453 break;
5454 default:
5455 *val = ASM330LHB_DEN_ACT_LOW;
5456 break;
5457 }
5458 return ret;
5459 }
5460
5461 /**
5462 * @brief DEN configuration.[set]
5463 *
5464 * @param ctx Read / write interface definitions.(ptr)
5465 * @param val Change the values of den_xl_g in reg CTRL9_XL
5466 * @retval Interface status (MANDATORY: return 0 -> no Error).
5467 *
5468 */
asm330lhb_den_enable_set(const stmdev_ctx_t * ctx,asm330lhb_den_xl_g_t val)5469 int32_t asm330lhb_den_enable_set(const stmdev_ctx_t *ctx,
5470 asm330lhb_den_xl_g_t val)
5471 {
5472 asm330lhb_ctrl9_xl_t ctrl9_xl;
5473 int32_t ret;
5474
5475 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5476 if (ret == 0)
5477 {
5478 ctrl9_xl.den_xl_g = (uint8_t)val;
5479 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5480 (uint8_t *)&ctrl9_xl, 1);
5481 }
5482 return ret;
5483 }
5484
5485 /**
5486 * @brief DEN configuration.[get]
5487 *
5488 * @param ctx Read / write interface definitions.(ptr)
5489 * @param val Get the values of den_xl_g in reg CTRL9_XL
5490 * @retval Interface status (MANDATORY: return 0 -> no Error).
5491 *
5492 */
asm330lhb_den_enable_get(const stmdev_ctx_t * ctx,asm330lhb_den_xl_g_t * val)5493 int32_t asm330lhb_den_enable_get(const stmdev_ctx_t *ctx,
5494 asm330lhb_den_xl_g_t *val)
5495 {
5496 asm330lhb_ctrl9_xl_t ctrl9_xl;
5497 int32_t ret;
5498
5499 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5500
5501 switch (ctrl9_xl.den_xl_g)
5502 {
5503 case ASM330LHB_STAMP_IN_GY_DATA:
5504 *val = ASM330LHB_STAMP_IN_GY_DATA;
5505 break;
5506 case ASM330LHB_STAMP_IN_XL_DATA:
5507 *val = ASM330LHB_STAMP_IN_XL_DATA;
5508 break;
5509 case ASM330LHB_STAMP_IN_GY_XL_DATA:
5510 *val = ASM330LHB_STAMP_IN_GY_XL_DATA;
5511 break;
5512 default:
5513 *val = ASM330LHB_STAMP_IN_GY_DATA;
5514 break;
5515 }
5516 return ret;
5517 }
5518
5519 /**
5520 * @brief DEN value stored in LSB of X-axis.[set]
5521 *
5522 * @param ctx Read / write interface definitions.(ptr)
5523 * @param val Change the values of den_z in reg CTRL9_XL
5524 * @retval Interface status (MANDATORY: return 0 -> no Error).
5525 *
5526 */
asm330lhb_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)5527 int32_t asm330lhb_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5528 {
5529 asm330lhb_ctrl9_xl_t ctrl9_xl;
5530 int32_t ret;
5531
5532 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5533 if (ret == 0)
5534 {
5535 ctrl9_xl.den_z = (uint8_t)val;
5536 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5537 (uint8_t *)&ctrl9_xl, 1);
5538 }
5539 return ret;
5540 }
5541
5542 /**
5543 * @brief DEN value stored in LSB of X-axis.[get]
5544 *
5545 * @param ctx Read / write interface definitions.(ptr)
5546 * @param val Change the values of den_z in reg CTRL9_XL
5547 * @retval Interface status (MANDATORY: return 0 -> no Error).
5548 *
5549 */
asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5550 int32_t asm330lhb_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
5551 {
5552 asm330lhb_ctrl9_xl_t ctrl9_xl;
5553 int32_t ret;
5554
5555 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5556 *val = ctrl9_xl.den_z;
5557
5558 return ret;
5559 }
5560
5561 /**
5562 * @brief DEN value stored in LSB of Y-axis.[set]
5563 *
5564 * @param ctx Read / write interface definitions.(ptr)
5565 * @param val Change the values of den_y in reg CTRL9_XL
5566 * @retval Interface status (MANDATORY: return 0 -> no Error).
5567 *
5568 */
asm330lhb_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)5569 int32_t asm330lhb_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5570 {
5571 asm330lhb_ctrl9_xl_t ctrl9_xl;
5572 int32_t ret;
5573
5574 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5575 if (ret == 0)
5576 {
5577 ctrl9_xl.den_y = (uint8_t)val;
5578 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL,
5579 (uint8_t *)&ctrl9_xl, 1);
5580 }
5581 return ret;
5582 }
5583
5584 /**
5585 * @brief DEN value stored in LSB of Y-axis.[get]
5586 *
5587 * @param ctx Read / write interface definitions.(ptr)
5588 * @param val Change the values of den_y in reg CTRL9_XL
5589 * @retval Interface status (MANDATORY: return 0 -> no Error).
5590 *
5591 */
asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5592 int32_t asm330lhb_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
5593 {
5594 asm330lhb_ctrl9_xl_t ctrl9_xl;
5595 int32_t ret;
5596
5597 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5598 *val = ctrl9_xl.den_y;
5599
5600 return ret;
5601 }
5602
5603 /**
5604 * @brief DEN value stored in LSB of Z-axis.[set]
5605 *
5606 * @param ctx Read / write interface definitions.(ptr)
5607 * @param val Change the values of den_x in reg CTRL9_XL
5608 * @retval Interface status (MANDATORY: return 0 -> no Error).
5609 *
5610 */
asm330lhb_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)5611 int32_t asm330lhb_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5612 {
5613 asm330lhb_ctrl9_xl_t ctrl9_xl;
5614 int32_t ret;
5615
5616 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5617 if (ret == 0)
5618 {
5619 ctrl9_xl.den_x = (uint8_t)val;
5620 ret = asm330lhb_write_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5621 }
5622 return ret;
5623 }
5624
5625 /**
5626 * @brief DEN value stored in LSB of Z-axis.[get]
5627 *
5628 * @param ctx Read / write interface definitions.(ptr)
5629 * @param val Change the values of den_x in reg CTRL9_XL
5630 * @retval Interface status (MANDATORY: return 0 -> no Error).
5631 *
5632 */
asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5633 int32_t asm330lhb_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
5634 {
5635 asm330lhb_ctrl9_xl_t ctrl9_xl;
5636 int32_t ret;
5637
5638 ret = asm330lhb_read_reg(ctx, ASM330LHB_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5639 *val = ctrl9_xl.den_x;
5640
5641 return ret;
5642 }
5643
5644 /**
5645 * @}
5646 *
5647 */
5648
5649 /**
5650 * @defgroup ASM330LHB_finite_state_machine
5651 * @brief This section groups all the functions that manage the
5652 * state_machine.
5653 * @{
5654 *
5655 */
5656
5657 /**
5658 * @brief FSM status register[get]
5659 *
5660 * @param ctx read / write interface definitions
5661 * @param val register ASM330LHB_FSM_STATUS_A_MAINPAGE,
5662 * ASM330LHB_FSM_STATUS_B_MAINPAGE
5663 *
5664 */
asm330lhb_fsm_status_get(const stmdev_ctx_t * ctx,asm330lhb_fsm_status_t * val)5665 int32_t asm330lhb_fsm_status_get(const stmdev_ctx_t *ctx,
5666 asm330lhb_fsm_status_t *val)
5667 {
5668 asm330lhb_fsm_status_a_mainpage_t status_a;
5669 asm330lhb_fsm_status_b_mainpage_t status_b;
5670 int32_t ret;
5671
5672 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_A_MAINPAGE,
5673 (uint8_t *)&status_a, 1);
5674 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_STATUS_B_MAINPAGE,
5675 (uint8_t *)&status_b, 1);
5676
5677 val->fsm1 = status_a.is_fsm1;
5678 val->fsm2 = status_a.is_fsm2;
5679 val->fsm3 = status_a.is_fsm3;
5680 val->fsm4 = status_a.is_fsm4;
5681 val->fsm5 = status_a.is_fsm5;
5682 val->fsm6 = status_a.is_fsm6;
5683 val->fsm7 = status_a.is_fsm7;
5684 val->fsm8 = status_a.is_fsm8;
5685 val->fsm9 = status_b.is_fsm9;
5686 val->fsm10 = status_b.is_fsm10;
5687 val->fsm11 = status_b.is_fsm11;
5688 val->fsm12 = status_b.is_fsm12;
5689 val->fsm13 = status_b.is_fsm13;
5690 val->fsm14 = status_b.is_fsm14;
5691 val->fsm15 = status_b.is_fsm15;
5692 val->fsm16 = status_b.is_fsm16;
5693 return ret;
5694 }
5695
5696 /**
5697 * @brief prgsens_out: [get] Output value of all FSMs.
5698 *
5699 * @param ctx_t *ctx: read / write interface definitions
5700 * @param uint8_t * : buffer that stores data read
5701 *
5702 */
asm330lhb_fsm_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)5703 int32_t asm330lhb_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
5704 {
5705 int32_t ret;
5706 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5707 if (ret == 0)
5708 {
5709 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_OUTS1, buff, 16);
5710 }
5711 if (ret == 0)
5712 {
5713 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5714 }
5715 return ret;
5716 }
5717
5718 /**
5719 * @brief Interrupt status bit for FSM long counter timeout interrupt
5720 * event.[get]
5721 *
5722 * @param ctx Read / write interface definitions.(ptr)
5723 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
5724 * @retval Interface status (MANDATORY: return 0 -> no Error).
5725 *
5726 */
asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)5727 int32_t asm330lhb_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
5728 uint8_t *val)
5729 {
5730 asm330lhb_emb_func_status_t emb_func_status;
5731 int32_t ret;
5732
5733 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5734 if (ret == 0)
5735 {
5736 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_STATUS,
5737 (uint8_t *)&emb_func_status, 1);
5738 }
5739 if (ret == 0)
5740 {
5741 *val = emb_func_status.is_fsm_lc;
5742 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5743 }
5744 return ret;
5745 }
5746
asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t * ctx,uint8_t val)5747 int32_t asm330lhb_emb_func_clk_dis_set(const stmdev_ctx_t *ctx, uint8_t val)
5748 {
5749 asm330lhb_page_sel_t page_sel;
5750 int32_t ret;
5751
5752 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5753 if (ret == 0)
5754 {
5755 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
5756 (uint8_t *)&page_sel, 1);
5757
5758 page_sel.emb_func_clk_dis = val;
5759 }
5760
5761 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5762
5763 return ret;
5764 }
5765
asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t * ctx,uint8_t * val)5766 int32_t asm330lhb_emb_func_clk_dis_get(const stmdev_ctx_t *ctx, uint8_t *val)
5767 {
5768 asm330lhb_page_sel_t page_sel;
5769 int32_t ret;
5770
5771 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5772 if (ret == 0)
5773 {
5774 ret = asm330lhb_read_reg(ctx, ASM330LHB_PAGE_SEL,
5775 (uint8_t *)&page_sel, 1);
5776
5777 *val = page_sel.emb_func_clk_dis;
5778 }
5779
5780 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5781
5782 return ret;
5783 }
5784
5785 /**
5786 * @brief Embedded final state machine functions mode.[set]
5787 *
5788 * @param ctx Read / write interface definitions.(ptr)
5789 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
5790 * @retval Interface status (MANDATORY: return 0 -> no Error).
5791 *
5792 */
asm330lhb_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)5793 int32_t asm330lhb_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
5794 {
5795 int32_t ret;
5796 asm330lhb_emb_func_en_b_t emb_func_en_b;
5797
5798 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5799
5800 if (ret == 0)
5801 {
5802 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5803 (uint8_t *)&emb_func_en_b, 1);
5804 }
5805 if (ret == 0)
5806 {
5807 emb_func_en_b.fsm_en = (uint8_t)val;
5808 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5809 (uint8_t *)&emb_func_en_b, 1);
5810 }
5811 if (ret == 0)
5812 {
5813 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5814 }
5815 return ret;
5816 }
5817
5818 /**
5819 * @brief Embedded final state machine functions mode.[get]
5820 *
5821 * @param ctx Read / write interface definitions.(ptr)
5822 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
5823 * @retval Interface status (MANDATORY: return 0 -> no Error).
5824 *
5825 */
asm330lhb_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)5826 int32_t asm330lhb_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
5827 {
5828 int32_t ret;
5829 asm330lhb_emb_func_en_b_t emb_func_en_b;
5830
5831 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5832 if (ret == 0)
5833 {
5834 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5835 (uint8_t *)&emb_func_en_b, 1);
5836 }
5837 if (ret == 0)
5838 {
5839 *val = emb_func_en_b.fsm_en;
5840 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5841 (uint8_t *)&emb_func_en_b, 1);
5842 }
5843 if (ret == 0)
5844 {
5845 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5846 }
5847 return ret;
5848 }
5849
5850 /**
5851 * @brief Embedded final state machine functions mode.[set]
5852 *
5853 * @param ctx Read / write interface definitions.(ptr)
5854 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5855 * @retval Interface status (MANDATORY: return 0 -> no Error).
5856 *
5857 */
asm330lhb_fsm_enable_set(const stmdev_ctx_t * ctx,asm330lhb_emb_fsm_enable_t * val)5858 int32_t asm330lhb_fsm_enable_set(const stmdev_ctx_t *ctx,
5859 asm330lhb_emb_fsm_enable_t *val)
5860 {
5861 asm330lhb_emb_func_en_b_t emb_func_en_b;
5862 int32_t ret;
5863
5864 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5865 if (ret == 0)
5866 {
5867 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_A,
5868 (uint8_t *)&val->fsm_enable_a, 1);
5869 }
5870 if (ret == 0)
5871 {
5872 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_ENABLE_B,
5873 (uint8_t *)&val->fsm_enable_b, 1);
5874 }
5875 if (ret == 0)
5876 {
5877 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5878 (uint8_t *)&emb_func_en_b, 1);
5879 }
5880 if (ret == 0)
5881 {
5882 if ((val->fsm_enable_a.fsm1_en |
5883 val->fsm_enable_a.fsm2_en |
5884 val->fsm_enable_a.fsm3_en |
5885 val->fsm_enable_a.fsm4_en |
5886 val->fsm_enable_a.fsm5_en |
5887 val->fsm_enable_a.fsm6_en |
5888 val->fsm_enable_a.fsm7_en |
5889 val->fsm_enable_a.fsm8_en |
5890 val->fsm_enable_b.fsm9_en |
5891 val->fsm_enable_b.fsm10_en |
5892 val->fsm_enable_b.fsm11_en |
5893 val->fsm_enable_b.fsm12_en |
5894 val->fsm_enable_b.fsm13_en |
5895 val->fsm_enable_b.fsm14_en |
5896 val->fsm_enable_b.fsm15_en |
5897 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
5898 {
5899 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
5900 }
5901 else
5902 {
5903 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
5904 }
5905 }
5906 if (ret == 0)
5907 {
5908 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B,
5909 (uint8_t *)&emb_func_en_b, 1);
5910 }
5911 if (ret == 0)
5912 {
5913 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5914 }
5915 return ret;
5916 }
5917
5918 /**
5919 * @brief Embedded final state machine functions mode.[get]
5920 *
5921 * @param ctx Read / write interface definitions.(ptr)
5922 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5923 * @retval Interface status (MANDATORY: return 0 -> no Error).
5924 *
5925 */
asm330lhb_fsm_enable_get(const stmdev_ctx_t * ctx,asm330lhb_emb_fsm_enable_t * val)5926 int32_t asm330lhb_fsm_enable_get(const stmdev_ctx_t *ctx,
5927 asm330lhb_emb_fsm_enable_t *val)
5928 {
5929 int32_t ret;
5930
5931 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5932 if (ret == 0)
5933 {
5934 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_A,
5935 (uint8_t *)&val->fsm_enable_a, 1);
5936 }
5937 if (ret == 0)
5938 {
5939 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_ENABLE_B,
5940 (uint8_t *)&val->fsm_enable_b, 1);
5941 }
5942 if (ret == 0)
5943 {
5944 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5945 }
5946 return ret;
5947 }
5948
5949 /**
5950 * @brief FSM long counter status register. Long counter value is an
5951 * unsigned integer value (16-bit format).[set]
5952 *
5953 * @param ctx Read / write interface definitions.(ptr)
5954 * @param buff Buffer that contains data to write
5955 * @retval Interface status (MANDATORY: return 0 -> no Error).
5956 *
5957 */
asm330lhb_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)5958 int32_t asm330lhb_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
5959 {
5960 uint8_t buff[2];
5961 int32_t ret;
5962
5963 buff[1] = (uint8_t)(val / 256U);
5964 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5965
5966 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5967 if (ret == 0)
5968 {
5969 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2);
5970 }
5971 if (ret == 0)
5972 {
5973 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
5974 }
5975 return ret;
5976 }
5977
5978 /**
5979 * @brief FSM long counter status register. Long counter value is an
5980 * unsigned integer value (16-bit format).[get]
5981 *
5982 * @param ctx Read / write interface definitions.(ptr)
5983 * @param buff Buffer that stores data read
5984 * @retval Interface status (MANDATORY: return 0 -> no Error).
5985 *
5986 */
asm330lhb_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)5987 int32_t asm330lhb_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
5988 {
5989 uint8_t buff[2];
5990 int32_t ret;
5991
5992 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
5993 if (ret == 0)
5994 {
5995 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_L, buff, 2);
5996 *val = buff[1];
5997 *val = (*val * 256U) + buff[0];
5998 }
5999 if (ret == 0)
6000 {
6001 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6002 }
6003 return ret;
6004 }
6005
6006 /**
6007 * @brief Clear FSM long counter value.[set]
6008 *
6009 * @param ctx Read / write interface definitions.(ptr)
6010 * @param val Change the values of fsm_lc_clr in reg
6011 * FSM_LONG_COUNTER_CLEAR
6012 * @retval Interface status (MANDATORY: return 0 -> no Error).
6013 *
6014 */
asm330lhb_long_clr_set(const stmdev_ctx_t * ctx,asm330lhb_fsm_lc_clr_t val)6015 int32_t asm330lhb_long_clr_set(const stmdev_ctx_t *ctx,
6016 asm330lhb_fsm_lc_clr_t val)
6017 {
6018 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear;
6019 int32_t ret;
6020
6021 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6022 if (ret == 0)
6023 {
6024 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
6025 (uint8_t *)&fsm_long_counter_clear, 1);
6026 }
6027 if (ret == 0)
6028 {
6029 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
6030 ret = asm330lhb_write_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
6031 (uint8_t *)&fsm_long_counter_clear, 1);
6032 }
6033 if (ret == 0)
6034 {
6035 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6036 }
6037 return ret;
6038 }
6039
6040 /**
6041 * @brief Clear FSM long counter value.[get]
6042 *
6043 * @param ctx Read / write interface definitions.(ptr)
6044 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
6045 * @retval Interface status (MANDATORY: return 0 -> no Error).
6046 *
6047 */
asm330lhb_long_clr_get(const stmdev_ctx_t * ctx,asm330lhb_fsm_lc_clr_t * val)6048 int32_t asm330lhb_long_clr_get(const stmdev_ctx_t *ctx,
6049 asm330lhb_fsm_lc_clr_t *val)
6050 {
6051 asm330lhb_fsm_long_counter_clear_t fsm_long_counter_clear;
6052 int32_t ret;
6053
6054 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6055
6056 if (ret == 0)
6057 {
6058 ret = asm330lhb_read_reg(ctx, ASM330LHB_FSM_LONG_COUNTER_CLEAR,
6059 (uint8_t *)&fsm_long_counter_clear, 1);
6060 }
6061 if (ret == 0)
6062 {
6063 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6064 }
6065 switch (fsm_long_counter_clear.fsm_lc_clr)
6066 {
6067 case ASM330LHB_LC_NORMAL:
6068 *val = ASM330LHB_LC_NORMAL;
6069 break;
6070 case ASM330LHB_LC_CLEAR:
6071 *val = ASM330LHB_LC_CLEAR;
6072 break;
6073 case ASM330LHB_LC_CLEAR_DONE:
6074 *val = ASM330LHB_LC_CLEAR_DONE;
6075 break;
6076 default:
6077 *val = ASM330LHB_LC_NORMAL;
6078 break;
6079 }
6080 return ret;
6081 }
6082
6083 /**
6084 * @brief Finite State Machine ODR configuration.[set]
6085 *
6086 * @param ctx Read / write interface definitions.(ptr)
6087 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6088 * @retval Interface status (MANDATORY: return 0 -> no Error).
6089 *
6090 */
asm330lhb_fsm_data_rate_set(const stmdev_ctx_t * ctx,asm330lhb_fsm_odr_t val)6091 int32_t asm330lhb_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6092 asm330lhb_fsm_odr_t val)
6093 {
6094 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6095 int32_t ret;
6096
6097 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6098
6099 if (ret == 0)
6100 {
6101 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6102 (uint8_t *)&emb_func_odr_cfg_b, 1);
6103 }
6104 if (ret == 0)
6105 {
6106 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
6107 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
6108 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
6109 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6110 (uint8_t *)&emb_func_odr_cfg_b, 1);
6111 }
6112 if (ret == 0)
6113 {
6114 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6115 }
6116 return ret;
6117 }
6118
6119 /**
6120 * @brief Finite State Machine ODR configuration.[get]
6121 *
6122 * @param ctx Read / write interface definitions.(ptr)
6123 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
6124 * @retval Interface status (MANDATORY: return 0 -> no Error).
6125 *
6126 */
asm330lhb_fsm_data_rate_get(const stmdev_ctx_t * ctx,asm330lhb_fsm_odr_t * val)6127 int32_t asm330lhb_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6128 asm330lhb_fsm_odr_t *val)
6129 {
6130 asm330lhb_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
6131 int32_t ret;
6132
6133 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6134
6135 if (ret == 0)
6136 {
6137 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_B,
6138 (uint8_t *)&emb_func_odr_cfg_b, 1);
6139 }
6140 if (ret == 0)
6141 {
6142 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6143 }
6144 switch (emb_func_odr_cfg_b.fsm_odr)
6145 {
6146 case ASM330LHB_ODR_FSM_12Hz5:
6147 *val = ASM330LHB_ODR_FSM_12Hz5;
6148 break;
6149 case ASM330LHB_ODR_FSM_26Hz:
6150 *val = ASM330LHB_ODR_FSM_26Hz;
6151 break;
6152 case ASM330LHB_ODR_FSM_52Hz:
6153 *val = ASM330LHB_ODR_FSM_52Hz;
6154 break;
6155 case ASM330LHB_ODR_FSM_104Hz:
6156 *val = ASM330LHB_ODR_FSM_104Hz;
6157 break;
6158 default:
6159 *val = ASM330LHB_ODR_FSM_12Hz5;
6160 break;
6161 }
6162 return ret;
6163 }
6164
6165 /**
6166 * @brief FSM initialization request.[set]
6167 *
6168 * @param ctx Read / write interface definitions.(ptr)
6169 * @param val Change the values of fsm_init in reg FSM_INIT
6170 * @retval Interface status (MANDATORY: return 0 -> no Error).
6171 *
6172 */
asm330lhb_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)6173 int32_t asm330lhb_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
6174 {
6175 asm330lhb_emb_func_init_b_t emb_func_init_b;
6176 int32_t ret;
6177
6178 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6179
6180 if (ret == 0)
6181 {
6182 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6183 (uint8_t *)&emb_func_init_b, 1);
6184 }
6185 if (ret == 0)
6186 {
6187 emb_func_init_b.fsm_init = (uint8_t)val;
6188 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6189 (uint8_t *)&emb_func_init_b, 1);
6190 }
6191 if (ret == 0)
6192 {
6193 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6194 }
6195 return ret;
6196 }
6197
6198 /**
6199 * @brief FSM initialization request.[get]
6200 *
6201 * @param ctx Read / write interface definitions.(ptr)
6202 * @param val Change the values of fsm_init in reg FSM_INIT
6203 * @retval Interface status (MANDATORY: return 0 -> no Error).
6204 *
6205 */
asm330lhb_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6206 int32_t asm330lhb_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
6207 {
6208 asm330lhb_emb_func_init_b_t emb_func_init_b;
6209 int32_t ret;
6210
6211 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6212 if (ret == 0)
6213 {
6214 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6215 (uint8_t *)&emb_func_init_b, 1);
6216 }
6217 if (ret == 0)
6218 {
6219 *val = emb_func_init_b.fsm_init;
6220 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6221 }
6222 return ret;
6223 }
6224
6225 /**
6226 * @brief FSM long counter timeout register (r/w). The long counter
6227 * timeout value is an unsigned integer value (16-bit format).
6228 * When the long counter value reached this value, the FSM
6229 * generates an interrupt.[set]
6230 *
6231 * @param ctx Read / write interface definitions.(ptr)
6232 * @param buff Buffer that contains data to write
6233 * @retval Interface status (MANDATORY: return 0 -> no Error).
6234 *
6235 */
asm330lhb_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)6236 int32_t asm330lhb_long_cnt_int_value_set(const stmdev_ctx_t *ctx, uint16_t val)
6237 {
6238 uint8_t buff[2];
6239 int32_t ret;
6240
6241 buff[1] = (uint8_t)(val / 256U);
6242 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6243 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]);
6244
6245 if (ret == 0)
6246 {
6247 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H,
6248 &buff[1]);
6249 }
6250 return ret;
6251 }
6252
6253 /**
6254 * @brief FSM long counter timeout register (r/w). The long counter
6255 * timeout value is an unsigned integer value (16-bit format).
6256 * When the long counter value reached this value, the FSM generates
6257 * an interrupt.[get]
6258 *
6259 * @param ctx Read / write interface definitions.(ptr)
6260 * @param buff Buffer that stores data read
6261 * @retval Interface status (MANDATORY: return 0 -> no Error).
6262 *
6263 */
asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)6264 int32_t asm330lhb_long_cnt_int_value_get(const stmdev_ctx_t *ctx, uint16_t *val)
6265 {
6266 uint8_t buff[2];
6267 int32_t ret;
6268
6269 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_L, &buff[0]);
6270
6271 if (ret == 0)
6272 {
6273 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_LC_TIMEOUT_H,
6274 &buff[1]);
6275 *val = buff[1];
6276 *val = (*val * 256U) + buff[0];
6277 }
6278 return ret;
6279 }
6280
6281 /**
6282 * @brief FSM number of programs register.[set]
6283 *
6284 * @param ctx Read / write interface definitions.(ptr)
6285 * @param buff Buffer that contains data to write
6286 * @retval Interface status (MANDATORY: return 0 -> no Error).
6287 *
6288 */
asm330lhb_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)6289 int32_t asm330lhb_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t *buff)
6290 {
6291 int32_t ret;
6292
6293 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff);
6294
6295 if (ret == 0)
6296 {
6297 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_PROGRAMS + 0x01U,
6298 buff);
6299 }
6300 return ret;
6301 }
6302
6303 /**
6304 * @brief FSM number of programs register.[get]
6305 *
6306 * @param ctx Read / write interface definitions.(ptr)
6307 * @param buff Buffer that stores data read
6308 * @retval Interface status (MANDATORY: return 0 -> no Error).
6309 *
6310 */
asm330lhb_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)6311 int32_t asm330lhb_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6312 {
6313 int32_t ret;
6314
6315 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_PROGRAMS, buff);
6316
6317 return ret;
6318 }
6319
6320 /**
6321 * @brief FSM start address register (r/w). First available address is
6322 * 0x033C.[set]
6323 *
6324 * @param ctx Read / write interface definitions.(ptr)
6325 * @param buff Buffer that contains data to write
6326 * @retval Interface status (MANDATORY: return 0 -> no Error).
6327 *
6328 */
asm330lhb_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)6329 int32_t asm330lhb_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
6330 {
6331 uint8_t buff[2];
6332 int32_t ret;
6333
6334 buff[1] = (uint8_t)(val / 256U);
6335 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6336
6337 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]);
6338 if (ret == 0)
6339 {
6340 ret = asm330lhb_ln_pg_write_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]);
6341 }
6342 return ret;
6343 }
6344
6345 /**
6346 * @brief FSM start address register (r/w). First available address
6347 * is 0x033C.[get]
6348 *
6349 * @param ctx Read / write interface definitions.(ptr)
6350 * @param buff Buffer that stores data read
6351 * @retval Interface status (MANDATORY: return 0 -> no Error).
6352 *
6353 */
asm330lhb_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)6354 int32_t asm330lhb_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
6355 {
6356 uint8_t buff[2];
6357 int32_t ret;
6358
6359 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_L, &buff[0]);
6360 if (ret == 0)
6361 {
6362 ret = asm330lhb_ln_pg_read_byte(ctx, ASM330LHB_FSM_START_ADD_H, &buff[1]);
6363 *val = buff[1];
6364 *val = (*val * 256U) + buff[0];
6365 }
6366 return ret;
6367 }
6368
6369 /**
6370 * @}
6371 *
6372 */
6373
6374 /**
6375 * @addtogroup Machine Learning Core
6376 * @brief This section group all the functions concerning the
6377 * usage of Machine Learning Core
6378 * @{
6379 *
6380 */
6381
6382 /**
6383 * @brief Enable Machine Learning Core.[set]
6384 *
6385 * @param ctx read / write interface definitions
6386 * @param val change the values of mlc_en in
6387 * reg EMB_FUNC_EN_B and mlc_init
6388 * in EMB_FUNC_INIT_B
6389 *
6390 */
asm330lhb_mlc_set(const stmdev_ctx_t * ctx,uint8_t val)6391 int32_t asm330lhb_mlc_set(const stmdev_ctx_t *ctx, uint8_t val)
6392 {
6393 asm330lhb_emb_func_en_b_t reg;
6394 int32_t ret;
6395
6396 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6397 if (ret == 0)
6398 {
6399 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6400 }
6401 if (ret == 0)
6402 {
6403 reg.mlc_en = val;
6404 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6405 }
6406 if ((val != PROPERTY_DISABLE) && (ret == 0))
6407 {
6408 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6409 (uint8_t *)®, 1);
6410 if (ret == 0)
6411 {
6412 reg.mlc_en = val;
6413 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6414 (uint8_t *)®, 1);
6415 }
6416 }
6417 if (ret == 0)
6418 {
6419 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6420 }
6421 return ret;
6422 }
6423
6424 /**
6425 * @brief Enable Machine Learning Core.[get]
6426 *
6427 * @param ctx read / write interface definitions
6428 * @param val Get the values of mlc_en in
6429 * reg EMB_FUNC_EN_B
6430 *
6431 */
asm330lhb_mlc_get(const stmdev_ctx_t * ctx,uint8_t * val)6432 int32_t asm330lhb_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val)
6433 {
6434 asm330lhb_emb_func_en_b_t reg;
6435 int32_t ret;
6436
6437 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6438 if (ret == 0)
6439 {
6440 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_EN_B, (uint8_t *)®, 1);
6441 }
6442 if (ret == 0)
6443 {
6444 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6445 *val = reg.mlc_en;
6446 }
6447 return ret;
6448 }
6449
6450 /**
6451 * @brief Machine Learning Core status register[get]
6452 *
6453 * @param ctx read / write interface definitions
6454 * @param val register MLC_STATUS_MAINPAGE
6455 *
6456 */
asm330lhb_mlc_status_get(const stmdev_ctx_t * ctx,asm330lhb_mlc_status_mainpage_t * val)6457 int32_t asm330lhb_mlc_status_get(const stmdev_ctx_t *ctx,
6458 asm330lhb_mlc_status_mainpage_t *val)
6459 {
6460 return asm330lhb_read_reg(ctx, ASM330LHB_MLC_STATUS_MAINPAGE,
6461 (uint8_t *) val, 1);
6462 }
6463
6464 /**
6465 * @brief Machine Learning Core data rate selection.[set]
6466 *
6467 * @param ctx read / write interface definitions
6468 * @param val get the values of mlc_odr in
6469 * reg EMB_FUNC_ODR_CFG_C
6470 *
6471 */
asm330lhb_mlc_data_rate_set(const stmdev_ctx_t * ctx,asm330lhb_mlc_odr_t val)6472 int32_t asm330lhb_mlc_data_rate_set(const stmdev_ctx_t *ctx,
6473 asm330lhb_mlc_odr_t val)
6474 {
6475 asm330lhb_emb_func_odr_cfg_c_t reg;
6476 int32_t ret;
6477
6478 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6479 if (ret == 0)
6480 {
6481 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6482 (uint8_t *)®, 1);
6483 }
6484 if (ret == 0)
6485 {
6486 reg.mlc_odr = (uint8_t)val;
6487 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6488 (uint8_t *)®, 1);
6489 }
6490 if (ret == 0)
6491 {
6492 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6493 }
6494
6495 return ret;
6496 }
6497
6498 /**
6499 * @brief Machine Learning Core data rate selection.[get]
6500 *
6501 * @param ctx read / write interface definitions
6502 * @param val change the values of mlc_odr in
6503 * reg EMB_FUNC_ODR_CFG_C
6504 *
6505 */
asm330lhb_mlc_data_rate_get(const stmdev_ctx_t * ctx,asm330lhb_mlc_odr_t * val)6506 int32_t asm330lhb_mlc_data_rate_get(const stmdev_ctx_t *ctx,
6507 asm330lhb_mlc_odr_t *val)
6508 {
6509 asm330lhb_emb_func_odr_cfg_c_t reg;
6510 int32_t ret;
6511
6512 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6513 if (ret == 0)
6514 {
6515 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_ODR_CFG_C,
6516 (uint8_t *)®, 1);
6517 }
6518 if (ret == 0)
6519 {
6520 switch (reg.mlc_odr)
6521 {
6522 case ASM330LHB_ODR_PRGS_12Hz5:
6523 *val = ASM330LHB_ODR_PRGS_12Hz5;
6524 break;
6525 case ASM330LHB_ODR_PRGS_26Hz:
6526 *val = ASM330LHB_ODR_PRGS_26Hz;
6527 break;
6528 case ASM330LHB_ODR_PRGS_52Hz:
6529 *val = ASM330LHB_ODR_PRGS_52Hz;
6530 break;
6531 case ASM330LHB_ODR_PRGS_104Hz:
6532 *val = ASM330LHB_ODR_PRGS_104Hz;
6533 break;
6534 default:
6535 *val = ASM330LHB_ODR_PRGS_12Hz5;
6536 break;
6537 }
6538 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6539 }
6540 return ret;
6541 }
6542
6543 /**
6544 * @brief MLC initialization request.[set]
6545 *
6546 * @param ctx Read / write interface definitions.(ptr)
6547 * @param val Change the values of mlc_init
6548 * @retval Interface status (MANDATORY: return 0 -> no Error).
6549 *
6550 */
asm330lhb_mlc_init_set(const stmdev_ctx_t * ctx,uint8_t val)6551 int32_t asm330lhb_mlc_init_set(const stmdev_ctx_t *ctx, uint8_t val)
6552 {
6553 asm330lhb_emb_func_init_b_t emb_func_init_b;
6554 int32_t ret;
6555
6556 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6557
6558 if (ret == 0)
6559 {
6560 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6561 (uint8_t *)&emb_func_init_b, 1);
6562 }
6563 if (ret == 0)
6564 {
6565 emb_func_init_b.mlc_init = (uint8_t)val;
6566 ret = asm330lhb_write_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6567 (uint8_t *)&emb_func_init_b, 1);
6568 }
6569
6570 ret += asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6571
6572 return ret;
6573 }
6574
6575 /**
6576 * @brief MLC initialization request.[get]
6577 *
6578 * @param ctx Read / write interface definitions.(ptr)
6579 * @param val Get the values of mlc_init
6580 * @retval Interface status (MANDATORY: return 0 -> no Error).
6581 *
6582 */
asm330lhb_mlc_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6583 int32_t asm330lhb_mlc_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
6584 {
6585 asm330lhb_emb_func_init_b_t emb_func_init_b;
6586 int32_t ret;
6587
6588 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6589 if (ret == 0)
6590 {
6591 ret = asm330lhb_read_reg(ctx, ASM330LHB_EMB_FUNC_INIT_B,
6592 (uint8_t *)&emb_func_init_b, 1);
6593 }
6594 if (ret == 0)
6595 {
6596 *val = emb_func_init_b.mlc_init;
6597 }
6598
6599 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6600
6601 return ret;
6602 }
6603
6604 /**
6605 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
6606 *
6607 * @param ctx_t *ctx: read / write interface definitions
6608 * @param uint8_t * : buffer that stores data read
6609 *
6610 */
asm330lhb_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)6611 int32_t asm330lhb_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6612 {
6613 int32_t ret;
6614 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_EMBEDDED_FUNC_BANK);
6615 if (ret == 0)
6616 {
6617 ret = asm330lhb_read_reg(ctx, ASM330LHB_MLC0_SRC, buff, 8);
6618 }
6619 if (ret == 0)
6620 {
6621 ret = asm330lhb_mem_bank_set(ctx, ASM330LHB_USER_BANK);
6622 }
6623 return ret;
6624 }
6625
6626 /**
6627 * @}
6628 *
6629 */
6630
6631 /**
6632 * @}
6633 *
6634 */
6635
6636 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
6637
