1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <lib/psci/psci.h> 13 #include <plat/arm/common/plat_arm.h> 14 #include <plat/common/platform.h> 15 16 /* Allow ARM Standard platforms to override these functions */ 17 #pragma weak plat_arm_program_trusted_mailbox 18 19 #if !ARM_RECOM_STATE_ID_ENC 20 /******************************************************************************* 21 * ARM standard platform handler called to check the validity of the power state 22 * parameter. 23 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)24int arm_validate_power_state(unsigned int power_state, 25 psci_power_state_t *req_state) 26 { 27 unsigned int pstate = psci_get_pstate_type(power_state); 28 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 29 unsigned int i; 30 31 assert(req_state != NULL); 32 33 if (pwr_lvl > PLAT_MAX_PWR_LVL) 34 return PSCI_E_INVALID_PARAMS; 35 36 /* Sanity check the requested state */ 37 if (pstate == PSTATE_TYPE_STANDBY) { 38 /* 39 * It's possible to enter standby only on power level 0 40 * Ignore any other power level. 41 */ 42 if (pwr_lvl != ARM_PWR_LVL0) 43 return PSCI_E_INVALID_PARAMS; 44 45 req_state->pwr_domain_state[ARM_PWR_LVL0] = 46 ARM_LOCAL_STATE_RET; 47 } else { 48 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 49 req_state->pwr_domain_state[i] = 50 ARM_LOCAL_STATE_OFF; 51 } 52 53 /* 54 * We expect the 'state id' to be zero. 55 */ 56 if (psci_get_pstate_id(power_state) != 0U) 57 return PSCI_E_INVALID_PARAMS; 58 59 return PSCI_E_SUCCESS; 60 } 61 62 #else 63 /******************************************************************************* 64 * ARM standard platform handler called to check the validity of the power 65 * state parameter. The power state parameter has to be a composite power 66 * state. 67 ******************************************************************************/ arm_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)68int arm_validate_power_state(unsigned int power_state, 69 psci_power_state_t *req_state) 70 { 71 unsigned int state_id; 72 int i; 73 74 assert(req_state != NULL); 75 76 /* 77 * Currently we are using a linear search for finding the matching 78 * entry in the idle power state array. This can be made a binary 79 * search if the number of entries justify the additional complexity. 80 */ 81 for (i = 0; !!arm_pm_idle_states[i]; i++) { 82 #if PSCI_OS_INIT_MODE 83 if ((power_state & ~ARM_LAST_AT_PLVL_MASK) == 84 arm_pm_idle_states[i]) 85 #else 86 if (power_state == arm_pm_idle_states[i]) 87 #endif /* __PSCI_OS_INIT_MODE__ */ 88 break; 89 } 90 91 /* Return error if entry not found in the idle state array */ 92 if (!arm_pm_idle_states[i]) 93 return PSCI_E_INVALID_PARAMS; 94 95 i = 0; 96 state_id = psci_get_pstate_id(power_state); 97 98 /* Parse the State ID and populate the state info parameter */ 99 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) { 100 req_state->pwr_domain_state[i] = state_id & 101 ARM_LOCAL_PSTATE_MASK; 102 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 103 } 104 #if PSCI_OS_INIT_MODE 105 req_state->last_at_pwrlvl = state_id & ARM_LOCAL_PSTATE_MASK; 106 #endif /* __PSCI_OS_INIT_MODE__ */ 107 108 return PSCI_E_SUCCESS; 109 } 110 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 111 112 /******************************************************************************* 113 * ARM standard platform handler called to check the validity of the non secure 114 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 115 ******************************************************************************/ arm_validate_ns_entrypoint(uintptr_t entrypoint)116int arm_validate_ns_entrypoint(uintptr_t entrypoint) 117 { 118 /* 119 * Check if the non secure entrypoint lies within the non 120 * secure DRAM. 121 */ 122 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 123 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 124 return 0; 125 } 126 #ifdef __aarch64__ 127 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 128 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 129 return 0; 130 } 131 #endif 132 133 return -1; 134 } 135 arm_validate_psci_entrypoint(uintptr_t entrypoint)136int arm_validate_psci_entrypoint(uintptr_t entrypoint) 137 { 138 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : 139 PSCI_E_INVALID_ADDRESS; 140 } 141 142 /****************************************************************************** 143 * Helper function to save the platform state before a system suspend. Save the 144 * state of the system components which are not in the Always ON power domain. 145 *****************************************************************************/ arm_system_pwr_domain_save(void)146void arm_system_pwr_domain_save(void) 147 { 148 /* Assert system power domain is available on the platform */ 149 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 150 151 plat_arm_gic_save(); 152 153 /* 154 * Unregister console now so that it is not registered for a second 155 * time during resume. 156 */ 157 arm_console_runtime_end(); 158 159 /* 160 * All the other peripheral which are configured by ARM TF are 161 * re-initialized on resume from system suspend. Hence we 162 * don't save their state here. 163 */ 164 } 165 166 /****************************************************************************** 167 * Helper function to resume the platform from system suspend. Reinitialize 168 * the system components which are not in the Always ON power domain. 169 * TODO: Unify the platform setup when waking up from cold boot and system 170 * resume in arm_bl31_platform_setup(). 171 *****************************************************************************/ arm_system_pwr_domain_resume(void)172void arm_system_pwr_domain_resume(void) 173 { 174 /* Initialize the console */ 175 arm_console_runtime_init(); 176 177 /* Assert system power domain is available on the platform */ 178 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 179 180 plat_arm_gic_resume(); 181 182 plat_arm_security_setup(); 183 arm_configure_sys_timer(); 184 } 185 186 /******************************************************************************* 187 * ARM platform function to program the mailbox for a cpu before it is released 188 * from reset. This function assumes that the Trusted mail box base is within 189 * the ARM_SHARED_RAM region 190 ******************************************************************************/ plat_arm_program_trusted_mailbox(uintptr_t address)191void plat_arm_program_trusted_mailbox(uintptr_t address) 192 { 193 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 194 195 *mailbox = address; 196 197 /* 198 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 199 * ARM_SHARED_RAM region. 200 */ 201 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 202 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= 203 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 204 } 205 206 /******************************************************************************* 207 * The ARM Standard platform definition of platform porting API 208 * `plat_setup_psci_ops`. 209 ******************************************************************************/ plat_setup_psci_ops(uintptr_t sec_entrypoint,const plat_psci_ops_t ** psci_ops)210int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 211 const plat_psci_ops_t **psci_ops) 212 { 213 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 214 215 /* Setup mailbox with entry point. */ 216 plat_arm_program_trusted_mailbox(sec_entrypoint); 217 return 0; 218 } 219
