1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <drivers/arm/tzc_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/cassert.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 #include <lib/spinlock.h> 17 #include <lib/utils_def.h> 18 #include <lib/xlat_tables/xlat_tables_compat.h> 19 20 /******************************************************************************* 21 * Forward declarations 22 ******************************************************************************/ 23 struct meminfo; 24 struct image_info; 25 struct bl_params; 26 27 typedef struct arm_tzc_regions_info { 28 unsigned long long base; 29 unsigned long long end; 30 unsigned int sec_attr; 31 unsigned int nsaid_permissions; 32 } arm_tzc_regions_info_t; 33 34 /******************************************************************************* 35 * Default mapping definition of the TrustZone Controller for ARM standard 36 * platforms. 37 * Configure: 38 * - Region 0 with no access; 39 * - Region 1 with secure access only; 40 * - the remaining DRAM regions access from the given Non-Secure masters. 41 ******************************************************************************/ 42 #if SPM_MM 43 #define ARM_TZC_REGIONS_DEF \ 44 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 45 TZC_REGION_S_RDWR, 0}, \ 46 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 49 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 50 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 51 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 52 PLAT_ARM_TZC_NS_DEV_ACCESS} 53 54 #elif ENABLE_RME 55 #define ARM_TZC_REGIONS_DEF \ 56 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 57 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 58 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 60 /* Realm and Shared area share the same PAS */ \ 61 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 64 PLAT_ARM_TZC_NS_DEV_ACCESS} 65 66 #else 67 #define ARM_TZC_REGIONS_DEF \ 68 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 69 TZC_REGION_S_RDWR, 0}, \ 70 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 71 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 72 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 73 PLAT_ARM_TZC_NS_DEV_ACCESS} 74 #endif 75 76 #define ARM_CASSERT_MMAP \ 77 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 78 assert_plat_arm_mmap_mismatch); \ 79 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 80 <= MAX_MMAP_REGIONS, \ 81 assert_max_mmap_regions); 82 83 void arm_setup_romlib(void); 84 85 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 86 /* 87 * Use this macro to instantiate lock before it is used in below 88 * arm_lock_xxx() macros 89 */ 90 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 91 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 92 93 #if !HW_ASSISTED_COHERENCY 94 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 95 #else 96 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 97 #endif 98 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 99 100 /* 101 * These are wrapper macros to the Coherent Memory Bakery Lock API. 102 */ 103 #define arm_lock_init() bakery_lock_init(&arm_lock) 104 #define arm_lock_get() bakery_lock_get(&arm_lock) 105 #define arm_lock_release() bakery_lock_release(&arm_lock) 106 107 #else 108 109 /* 110 * Empty macros for all other BL stages other than BL31 and BL32 111 */ 112 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 113 #define ARM_LOCK_GET_INSTANCE 0 114 #define arm_lock_init() 115 #define arm_lock_get() 116 #define arm_lock_release() 117 118 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 119 120 #if ARM_RECOM_STATE_ID_ENC 121 /* 122 * Macros used to parse state information from State-ID if it is using the 123 * recommended encoding for State-ID. 124 */ 125 #define ARM_LOCAL_PSTATE_WIDTH 4 126 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 127 128 #if PSCI_OS_INIT_MODE 129 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 130 (ARM_LOCAL_PSTATE_WIDTH * \ 131 (PLAT_MAX_PWR_LVL + 1))) 132 #endif /* __PSCI_OS_INIT_MODE__ */ 133 134 /* Macros to construct the composite power state */ 135 136 /* Make composite power state parameter till power level 0 */ 137 #if PSCI_EXTENDED_STATE_ID 138 139 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 140 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 141 #else 142 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 143 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 144 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 145 ((type) << PSTATE_TYPE_SHIFT)) 146 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 147 148 /* Make composite power state parameter till power level 1 */ 149 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 150 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 151 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 152 153 /* Make composite power state parameter till power level 2 */ 154 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 155 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 156 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 157 158 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 159 160 /* ARM State switch error codes */ 161 #define STATE_SW_E_PARAM (-2) 162 #define STATE_SW_E_DENIED (-3) 163 164 /* plat_get_rotpk_info() flags */ 165 #define ARM_ROTPK_REGS_ID 1 166 #define ARM_ROTPK_DEVEL_RSA_ID 2 167 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 168 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 169 170 /* IO storage utility functions */ 171 int arm_io_setup(void); 172 173 /* Set image specification in IO block policy */ 174 int arm_set_image_source(unsigned int image_id, const char *part_name, 175 uintptr_t *dev_handle, uintptr_t *image_spec); 176 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 177 178 /* Security utility functions */ 179 void arm_tzc400_setup(uintptr_t tzc_base, 180 const arm_tzc_regions_info_t *tzc_regions); 181 struct tzc_dmc500_driver_data; 182 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 183 const arm_tzc_regions_info_t *tzc_regions); 184 185 /* Console utility functions */ 186 void arm_console_boot_init(void); 187 void arm_console_boot_end(void); 188 void arm_console_runtime_init(void); 189 void arm_console_runtime_end(void); 190 191 /* Systimer utility function */ 192 void arm_configure_sys_timer(void); 193 194 /* PM utility functions */ 195 int arm_validate_power_state(unsigned int power_state, 196 psci_power_state_t *req_state); 197 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 198 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 199 void arm_system_pwr_domain_save(void); 200 void arm_system_pwr_domain_resume(void); 201 int arm_psci_read_mem_protect(int *enabled); 202 int arm_nor_psci_write_mem_protect(int val); 203 void arm_nor_psci_do_static_mem_protect(void); 204 void arm_nor_psci_do_dyn_mem_protect(void); 205 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 206 207 /* Topology utility function */ 208 int arm_check_mpidr(u_register_t mpidr); 209 210 /* BL1 utility functions */ 211 void arm_bl1_early_platform_setup(void); 212 void arm_bl1_platform_setup(void); 213 void arm_bl1_plat_arch_setup(void); 214 215 /* BL2 utility functions */ 216 void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout); 217 void arm_bl2_platform_setup(void); 218 void arm_bl2_plat_arch_setup(void); 219 uint32_t arm_get_spsr_for_bl32_entry(void); 220 uint32_t arm_get_spsr_for_bl33_entry(void); 221 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 222 int arm_bl2_handle_post_image_load(unsigned int image_id); 223 struct bl_params *arm_get_next_bl_params(void); 224 225 /* BL2 at EL3 functions */ 226 void arm_bl2_el3_early_platform_setup(void); 227 void arm_bl2_el3_plat_arch_setup(void); 228 229 /* BL2U utility functions */ 230 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 231 void *plat_info); 232 void arm_bl2u_platform_setup(void); 233 void arm_bl2u_plat_arch_setup(void); 234 235 /* BL31 utility functions */ 236 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 237 uintptr_t hw_config, void *plat_params_from_bl2); 238 void arm_bl31_platform_setup(void); 239 void arm_bl31_plat_runtime_setup(void); 240 void arm_bl31_plat_arch_setup(void); 241 242 /* TSP utility functions */ 243 void arm_tsp_early_platform_setup(void); 244 245 /* SP_MIN utility functions */ 246 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 247 uintptr_t hw_config, void *plat_params_from_bl2); 248 void arm_sp_min_plat_runtime_setup(void); 249 void arm_sp_min_plat_arch_setup(void); 250 251 /* FIP TOC validity check */ 252 bool arm_io_is_toc_valid(void); 253 254 /* Utility functions for Dynamic Config */ 255 void arm_bl2_dyn_cfg_init(void); 256 void arm_bl1_set_mbedtls_heap(void); 257 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 258 259 #if MEASURED_BOOT 260 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 261 int arm_set_nt_fw_info( 262 /* 263 * Currently OP-TEE does not support reading DTBs from Secure memory 264 * and this option should be removed when feature is supported. 265 */ 266 #ifdef SPD_opteed 267 uintptr_t log_addr, 268 #endif 269 size_t log_size, uintptr_t *ns_log_addr); 270 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 271 size_t log_max_size); 272 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 273 size_t *log_max_size); 274 #endif /* MEASURED_BOOT */ 275 276 /* 277 * Free the memory storing initialization code only used during an images boot 278 * time so it can be reclaimed for runtime data 279 */ 280 void arm_free_init_memory(void); 281 282 /* 283 * Make the higher level translation tables read-only 284 */ 285 void arm_xlat_make_tables_readonly(void); 286 287 /* 288 * Mandatory functions required in ARM standard platforms 289 */ 290 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 291 void plat_arm_gic_driver_init(void); 292 void plat_arm_gic_init(void); 293 void plat_arm_gic_cpuif_enable(void); 294 void plat_arm_gic_cpuif_disable(void); 295 void plat_arm_gic_redistif_on(void); 296 void plat_arm_gic_redistif_off(void); 297 void plat_arm_gic_pcpu_init(void); 298 void plat_arm_gic_save(void); 299 void plat_arm_gic_resume(void); 300 void plat_arm_security_setup(void); 301 void plat_arm_pwrc_setup(void); 302 void plat_arm_interconnect_init(void); 303 void plat_arm_interconnect_enter_coherency(void); 304 void plat_arm_interconnect_exit_coherency(void); 305 void plat_arm_program_trusted_mailbox(uintptr_t address); 306 bool plat_arm_bl1_fwu_needed(void); 307 __dead2 void plat_arm_error_handler(int err); 308 __dead2 void plat_arm_system_reset(void); 309 310 /* 311 * Optional functions in ARM standard platforms 312 */ 313 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 314 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 315 unsigned int *flags); 316 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 317 unsigned int *flags); 318 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 319 unsigned int *flags); 320 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 321 unsigned int *flags); 322 323 #if ARM_PLAT_MT 324 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 325 #endif 326 327 /* 328 * This function is called after loading SCP_BL2 image and it is used to perform 329 * any platform-specific actions required to handle the SCP firmware. 330 */ 331 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 332 333 /* 334 * Optional functions required in ARM standard platforms 335 */ 336 void plat_arm_io_setup(void); 337 int plat_arm_get_alt_image_source( 338 unsigned int image_id, 339 uintptr_t *dev_handle, 340 uintptr_t *image_spec); 341 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 342 const mmap_region_t *plat_arm_get_mmap(void); 343 344 /* Allow platform to override psci_pm_ops during runtime */ 345 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 346 347 /* Execution state switch in ARM platforms */ 348 int arm_execution_state_switch(unsigned int smc_fid, 349 uint32_t pc_hi, 350 uint32_t pc_lo, 351 uint32_t cookie_hi, 352 uint32_t cookie_lo, 353 void *handle); 354 355 /* Optional functions for SP_MIN */ 356 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 357 u_register_t arg2, u_register_t arg3); 358 359 /* global variables */ 360 extern plat_psci_ops_t plat_arm_psci_pm_ops; 361 extern const mmap_region_t plat_arm_mmap[]; 362 extern const unsigned int arm_pm_idle_states[]; 363 364 /* secure watchdog */ 365 void plat_arm_secure_wdt_start(void); 366 void plat_arm_secure_wdt_stop(void); 367 void plat_arm_secure_wdt_refresh(void); 368 369 /* Get SOC-ID of ARM platform */ 370 uint32_t plat_arm_get_soc_id(void); 371 372 #endif /* PLAT_ARM_H */ 373
