1 /*
2 * SPDX-FileCopyrightText: Copyright 2023-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_s4.c
22 * Description: s8 version of convolution using symmetric quantization with 4 bit weights.
23 *
24 * $Date: 17 May 2024
25 * $Revision: V.1.2.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup Public
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /*
44 * Basic s8 convolution function with int4 weights.
45 *
46 * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels
47 * are multiples of 4 or at least greater than 4.
48 *
49 */
arm_convolve_s4(const cmsis_nn_context * ctx,const cmsis_nn_conv_params * conv_params,const cmsis_nn_per_channel_quant_params * quant_params,const cmsis_nn_dims * input_dims,const int8_t * input_data,const cmsis_nn_dims * filter_dims,const int8_t * packed_filter_data,const cmsis_nn_dims * bias_dims,const int32_t * bias_data,const cmsis_nn_dims * output_dims,int8_t * output_data)50 arm_cmsis_nn_status arm_convolve_s4(const cmsis_nn_context *ctx,
51 const cmsis_nn_conv_params *conv_params,
52 const cmsis_nn_per_channel_quant_params *quant_params,
53 const cmsis_nn_dims *input_dims,
54 const int8_t *input_data,
55 const cmsis_nn_dims *filter_dims,
56 const int8_t *packed_filter_data,
57 const cmsis_nn_dims *bias_dims,
58 const int32_t *bias_data,
59 const cmsis_nn_dims *output_dims,
60 int8_t *output_data)
61 {
62 (void)bias_dims;
63
64 if (ctx->buf == NULL)
65 {
66 return ARM_CMSIS_NN_ARG_ERROR;
67 }
68 int16_t *buffer_a = (int16_t *)ctx->buf;
69
70 const int32_t input_batches = input_dims->n;
71 const uint16_t input_x = input_dims->w;
72 const uint16_t input_y = input_dims->h;
73 const uint16_t input_ch = input_dims->c;
74 const uint16_t kernel_x = filter_dims->w;
75 const uint16_t kernel_y = filter_dims->h;
76 const uint16_t output_x = output_dims->w;
77 const uint16_t output_y = output_dims->h;
78 const uint16_t output_ch = output_dims->c;
79
80 const uint16_t pad_x = conv_params->padding.w;
81 const uint16_t pad_y = conv_params->padding.h;
82 const uint16_t stride_x = conv_params->stride.w;
83 const uint16_t stride_y = conv_params->stride.h;
84 const int32_t dilation_x = conv_params->dilation.w;
85 const int32_t dilation_y = conv_params->dilation.h;
86 const int32_t out_offset = conv_params->output_offset;
87 const int32_t out_activation_min = conv_params->activation.min;
88 const int32_t out_activation_max = conv_params->activation.max;
89 const int32_t rhs_cols = kernel_x * kernel_y * input_ch;
90 const int32_t input_offset = conv_params->input_offset;
91
92 int32_t *output_mult = quant_params->multiplier;
93 int32_t *output_shift = quant_params->shift;
94
95 int i_batch;
96 for (i_batch = 0; i_batch < input_batches; i_batch++)
97 {
98 #if defined(ARM_MATH_MVEI)
99 /* Generate up to four columns from the input tensor a GEMM computation */
100 int8_t *im2col_buf = (int8_t *)buffer_a;
101 const int32_t rhs_rows = output_dims->c;
102 int8_t *out = output_data;
103 int32_t lhs_rows = 0;
104
105 /* This part implements the im2col function */
106 for (int i_out_y = 0; i_out_y < output_y; i_out_y++)
107 {
108 for (int i_out_x = 0; i_out_x < output_x; i_out_x++)
109 {
110 const int32_t base_idx_x = stride_x * i_out_x - pad_x;
111 const int32_t base_idx_y = stride_y * i_out_y - pad_y;
112
113 for (int32_t i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++)
114 {
115 for (int32_t i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++)
116 {
117 const int32_t k_y = base_idx_y + dilation_y * i_ker_y;
118 const int32_t k_x = base_idx_x + dilation_x * i_ker_x;
119
120 if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x)
121 {
122 arm_memset_s8(im2col_buf, (int8_t)-input_offset, sizeof(int8_t) * input_ch);
123 }
124 else
125 {
126 arm_memcpy_s8(im2col_buf, input_data + (k_y * input_x + k_x) * input_ch, input_ch);
127 }
128 im2col_buf += input_ch;
129 }
130 }
131 lhs_rows++;
132
133 /* Computation is filed for every 4 columns */
134 if (lhs_rows == 4)
135 {
136 arm_nn_mat_mult_nt_t_s4((int8_t *)buffer_a,
137 packed_filter_data,
138 bias_data,
139 out,
140 output_mult,
141 output_shift,
142 lhs_rows,
143 rhs_rows,
144 rhs_cols,
145 input_offset,
146 out_offset,
147 out_activation_min,
148 out_activation_max,
149 rhs_cols);
150 out += lhs_rows * rhs_rows;
151
152 lhs_rows = 0;
153 im2col_buf = (int8_t *)buffer_a;
154 }
155 }
156 }
157
158 /* Handle left over columns */
159 if (lhs_rows != 0)
160 {
161 arm_nn_mat_mult_nt_t_s4((int8_t *)buffer_a,
162 packed_filter_data,
163 bias_data,
164 out,
165 output_mult,
166 output_shift,
167 lhs_rows,
168 rhs_rows,
169 rhs_cols,
170 input_offset,
171 out_offset,
172 out_activation_min,
173 out_activation_max,
174 rhs_cols);
175 out += lhs_rows * rhs_rows;
176 lhs_rows = 0;
177 im2col_buf = (int8_t *)buffer_a;
178 }
179 #else // #if defined(ARM_MATH_MVEI)
180 int16_t *two_column_buf = buffer_a;
181 int8_t *out = output_data;
182 int32_t lhs_rows = 0;
183
184 /* This part implements the im2col function */
185 for (int i_out_y = 0; i_out_y < output_y; i_out_y++)
186 {
187 for (int i_out_x = 0; i_out_x < output_x; i_out_x++)
188 {
189 const int32_t base_idx_x = stride_x * i_out_x - pad_x;
190 const int32_t base_idx_y = stride_y * i_out_y - pad_y;
191
192 for (int32_t i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++)
193 {
194 for (int32_t i_ker_x = 0; i_ker_x < kernel_x; i_ker_x++)
195 {
196 const int32_t k_y = base_idx_y + dilation_y * i_ker_y;
197 const int32_t k_x = base_idx_x + dilation_x * i_ker_x;
198
199 if (k_y < 0 || k_y >= input_y || k_x < 0 || k_x >= input_x)
200 {
201 /* Filling 0 for out-of-bound paddings */
202 memset(two_column_buf, 0, sizeof(int16_t) * input_ch);
203 }
204 else
205 {
206 /* Copying the pixel data to column */
207 arm_q7_to_q15_with_offset(
208 input_data + (k_y * input_x + k_x) * input_ch, two_column_buf, input_ch, input_offset);
209 }
210 two_column_buf += input_ch;
211 }
212 }
213 lhs_rows++;
214 /* Computation is filed for every 2 columns */
215 if (lhs_rows == 2)
216 {
217 out = arm_nn_mat_mult_kernel_s4_s16(packed_filter_data,
218 buffer_a,
219 output_ch,
220 output_shift,
221 output_mult,
222 out_offset,
223 out_activation_min,
224 out_activation_max,
225 rhs_cols,
226 bias_data,
227 out);
228
229 /* counter reset */
230 two_column_buf = buffer_a;
231 lhs_rows = 0;
232 }
233 }
234
235 if (out == NULL)
236 {
237 return ARM_CMSIS_NN_NO_IMPL_ERROR;
238 }
239 }
240
241 /* Handle left over columns */
242 if (lhs_rows != 0)
243 {
244 const int8_t *ker_a_ptr = packed_filter_data;
245 int i;
246 int8_t spilled_ker_a = 0;
247 for (i = 0; i < output_ch; i++)
248 {
249 /* Load the accumulator with bias first */
250 int32_t sum = 0;
251 if (bias_data)
252 {
253 sum = bias_data[i];
254 }
255
256 const int16_t *ip_as_col = buffer_a;
257
258 if (rhs_cols % 2 && (i % 2))
259 {
260 int16_t ip_b0 = *ip_as_col++;
261 sum += spilled_ker_a * ip_b0;
262 }
263
264 #if defined(ARM_MATH_DSP)
265 /* 4 multiply and accumulates are done in one loop. */
266 uint16_t col_count = rhs_cols / 4;
267 while (col_count)
268 {
269 int32_t ker_a1, ker_a2;
270 int32_t ip_b1, ip_b2;
271
272 read_and_pad_s4_ordered(ker_a_ptr, &ker_a1, &ker_a2);
273 ker_a_ptr += 2;
274 ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col);
275 sum = SMLAD(ker_a1, ip_b1, sum);
276 ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col);
277 sum = SMLAD(ker_a2, ip_b2, sum);
278
279 col_count--;
280 }
281 col_count = (rhs_cols & 0x3) >> 1;
282 #else
283 uint16_t col_count = rhs_cols >> 1;
284 #endif
285
286 while (col_count)
287 {
288 int8_t ker_a0 = (int8_t)(*ker_a_ptr << 4) >> 4;
289 int8_t ker_a1 = *ker_a_ptr >> 4;
290 ker_a_ptr++;
291
292 int16_t ip_b0 = *ip_as_col++;
293 sum += ker_a0 * ip_b0;
294
295 ip_b0 = *ip_as_col++;
296 sum += ker_a1 * ip_b0;
297
298 col_count--;
299 }
300
301 if (rhs_cols % 2 && !(i % 2))
302 {
303 int8_t ker_a0 = (int8_t)(*ker_a_ptr << 4) >> 4;
304 spilled_ker_a = *ker_a_ptr >> 4;
305 ker_a_ptr++;
306 int16_t ip_b0 = *ip_as_col;
307
308 sum += ker_a0 * ip_b0;
309 }
310
311 sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]);
312 sum += out_offset;
313 sum = MAX(sum, out_activation_min);
314 sum = MIN(sum, out_activation_max);
315 *out++ = (int8_t)sum;
316 }
317 }
318 #endif
319 /* Advance to the next batch */
320 input_data += (input_x * input_y * input_ch);
321 output_data += (output_x * output_y * output_ch);
322 }
323
324 /* Return to application */
325 return ARM_CMSIS_NN_SUCCESS;
326 }
327
328 /**
329 * @} end of NNConv group
330 */
331
