1 /*
2 * Copyright (C) 2010-2020 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q7_basic.c
22 * Description: Q7 version of convolution
23 *
24 * $Date: 09. October 2020
25 * $Revision: V.1.0.1
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup groupNN
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /**
44 * @brief Basic Q7 convolution function
45 * @param[in] Im_in pointer to input tensor
46 * @param[in] dim_im_in input tensor dimention
47 * @param[in] ch_im_in number of input tensor channels
48 * @param[in] wt pointer to kernel weights
49 * @param[in] ch_im_out number of filters, i.e., output tensor channels
50 * @param[in] dim_kernel filter kernel size
51 * @param[in] padding padding sizes
52 * @param[in] stride convolution stride
53 * @param[in] bias pointer to bias
54 * @param[in] bias_shift amount of left-shift for bias
55 * @param[in] out_shift amount of right-shift for output
56 * @param[in,out] Im_out pointer to output tensor
57 * @param[in] dim_im_out output tensor dimension
58 * @param[in,out] bufferA pointer to buffer space for input
59 * @param[in,out] bufferB pointer to buffer space for output
60 * @return The function returns <code>ARM_MATH_SUCCESS</code>
61 *
62 * @details
63 *
64 * <b>Buffer size:</b>
65 *
66 * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
67 *
68 * bufferB size: 0
69 *
70 * This basic version is designed to work for any input tensor and weight
71 * dimension.
72 */
73
arm_convolve_HWC_q7_basic(const q7_t * Im_in,const uint16_t dim_im_in,const uint16_t ch_im_in,const q7_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel,const uint16_t padding,const uint16_t stride,const q7_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q7_t * Im_out,const uint16_t dim_im_out,q15_t * bufferA,q7_t * bufferB)74 arm_status arm_convolve_HWC_q7_basic(const q7_t *Im_in,
75 const uint16_t dim_im_in,
76 const uint16_t ch_im_in,
77 const q7_t *wt,
78 const uint16_t ch_im_out,
79 const uint16_t dim_kernel,
80 const uint16_t padding,
81 const uint16_t stride,
82 const q7_t *bias,
83 const uint16_t bias_shift,
84 const uint16_t out_shift,
85 q7_t *Im_out,
86 const uint16_t dim_im_out,
87 q15_t *bufferA,
88 q7_t *bufferB)
89 {
90 (void)bufferB;
91 #if defined(ARM_MATH_DSP)
92 /* Run the following code for Cortex-M4 and Cortex-M7 */
93
94 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
95
96 /*
97 * Here we use bufferA as q15_t internally as computation are done with q15_t level
98 * im2col are done to output in q15_t format from q7_t input
99 */
100 q15_t *pBuffer = bufferA;
101 q7_t *pOut = Im_out;
102
103 /* This part implements the im2col function */
104 for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
105 {
106 for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
107 {
108 for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
109 {
110 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
111 {
112 if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
113 {
114 /* Filling 0 for out-of-bound paddings */
115 /* arm_fill_q15(0, pBuffer, ch_im_in); */
116 memset(pBuffer, 0, sizeof(q15_t) * ch_im_in);
117 }
118 else
119 {
120 /* Copying the pixel data to column */
121 arm_q7_to_q15_no_shift(
122 (q7_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in);
123 }
124 pBuffer += ch_im_in;
125 }
126 }
127
128 /* Computation is filed for every 2 columns */
129 if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel)
130 {
131 pOut = arm_nn_mat_mult_kernel_q7_q15(
132 wt, bufferA, ch_im_out, ch_im_in * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut);
133
134 /* counter reset */
135 pBuffer = bufferA;
136 }
137 }
138 }
139
140 /* left-over because odd number of output pixels */
141 if (pBuffer != bufferA)
142 {
143 const q7_t *pA = wt;
144 int i;
145
146 for (i = 0; i < ch_im_out; i++)
147 {
148 /* Load the accumulator with bias first */
149 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
150
151 /* Point to the beging of the im2col buffer */
152 const q15_t *pB = bufferA;
153
154 /* Each time it process 4 entries */
155 uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2;
156
157 while (colCnt)
158 {
159 q31_t inA1, inA2;
160 q31_t inB1, inB2;
161
162 pA = read_and_pad(pA, &inA1, &inA2);
163
164 inB1 = arm_nn_read_q15x2_ia(&pB);
165 sum = __SMLAD(inA1, inB1, sum);
166 inB2 = arm_nn_read_q15x2_ia(&pB);
167
168 sum = __SMLAD(inA2, inB2, sum);
169
170 colCnt--;
171 }
172 colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3;
173 while (colCnt)
174 {
175 q7_t inA1 = *pA++;
176 q15_t inB1 = *pB++;
177 sum += inA1 * inB1;
178 colCnt--;
179 }
180 *pOut++ = (q7_t)__SSAT((sum >> out_shift), 8);
181 }
182 }
183 #else
184 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
185
186 int i, j, k, l, m, n;
187 int conv_out;
188 int in_row, in_col;
189
190 for (i = 0; i < ch_im_out; i++)
191 {
192 for (j = 0; j < dim_im_out; j++)
193 {
194 for (k = 0; k < dim_im_out; k++)
195 {
196 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
197 for (m = 0; m < dim_kernel; m++)
198 {
199 for (n = 0; n < dim_kernel; n++)
200 {
201 // if-for implementation
202 in_row = stride * j + m - padding;
203 in_col = stride * k + n - padding;
204 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
205 {
206 for (l = 0; l < ch_im_in; l++)
207 {
208 conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] *
209 wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l];
210 }
211 }
212 }
213 }
214 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t)__SSAT((conv_out >> out_shift), 8);
215 }
216 }
217 }
218
219 #endif /* ARM_MATH_DSP */
220
221 /* Return to application */
222 return ARM_MATH_SUCCESS;
223 }
224
225 /**
226 * @} end of NNConv group
227 */
228
