1 /*
2 * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q15_fast.c
22 * Description: Fast Q15 version of convolution
23 *
24 * $Date: January 26, 2021
25 * $Revision: V.1.0.2
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup groupNN
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /**
44 * @brief Fast Q15 convolution function (non-sqaure shape)
45 * @param[in] Im_in pointer to input tensor
46 * @param[in] dim_im_in_x input tensor dimention x
47 * @param[in] dim_im_in_y input tensor dimention y
48 * @param[in] ch_im_in number of input tensor channels
49 * @param[in] wt pointer to kernel weights
50 * @param[in] ch_im_out number of filters, i.e., output tensor channels
51 * @param[in] dim_kernel_x filter kernel size x
52 * @param[in] dim_kernel_y filter kernel size y
53 * @param[in] padding_x padding size x
54 * @param[in] padding_y padding size y
55 * @param[in] stride_x convolution stride x
56 * @param[in] stride_y convolution stride y
57 * @param[in] bias pointer to bias
58 * @param[in] bias_shift amount of left-shift for bias
59 * @param[in] out_shift amount of right-shift for output
60 * @param[in,out] Im_out pointer to output tensor
61 * @param[in] dim_im_out_x output tensor dimension x
62 * @param[in] dim_im_out_y output tensor dimension y
63 * @param[in,out] bufferA pointer to buffer space for input
64 * @param[in,out] bufferB pointer to buffer space for output
65 * @return The function returns either
66 * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
67 *
68 * @details
69 *
70 * <b>Buffer size:</b>
71 *
72 * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
73 *
74 * bufferB size: 0
75 *
76 * <b>Input dimension constraints:</b>
77 *
78 * ch_im_in is multiple of 2
79 *
80 * ch_im_out is multiple of 2
81 *
82 */
83
arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in,const uint16_t dim_im_in_x,const uint16_t dim_im_in_y,const uint16_t ch_im_in,const q15_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel_x,const uint16_t dim_kernel_y,const uint16_t padding_x,const uint16_t padding_y,const uint16_t stride_x,const uint16_t stride_y,const q15_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q15_t * Im_out,const uint16_t dim_im_out_x,const uint16_t dim_im_out_y,q15_t * bufferA,q7_t * bufferB)84 arm_status arm_convolve_HWC_q15_fast_nonsquare(const q15_t *Im_in,
85 const uint16_t dim_im_in_x,
86 const uint16_t dim_im_in_y,
87 const uint16_t ch_im_in,
88 const q15_t *wt,
89 const uint16_t ch_im_out,
90 const uint16_t dim_kernel_x,
91 const uint16_t dim_kernel_y,
92 const uint16_t padding_x,
93 const uint16_t padding_y,
94 const uint16_t stride_x,
95 const uint16_t stride_y,
96 const q15_t *bias,
97 const uint16_t bias_shift,
98 const uint16_t out_shift,
99 q15_t *Im_out,
100 const uint16_t dim_im_out_x,
101 const uint16_t dim_im_out_y,
102 q15_t *bufferA,
103 q7_t *bufferB)
104 {
105 (void)bufferB;
106 #if defined(ARM_MATH_DSP)
107 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
108
109 q15_t *pBuffer = bufferA;
110 q15_t *im_buffer = bufferA;
111 q15_t *pOut = Im_out;
112
113 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
114 {
115 /* check if the input dimension meets the constraints */
116 return ARM_MATH_SIZE_MISMATCH;
117 }
118
119 /* Run the following code for Cortex-M4 and Cortex-M7 */
120
121 /* This part implements the im2col function */
122 for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++)
123 {
124 for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++)
125 {
126 for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y;
127 i_ker_y++)
128 {
129 for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x;
130 i_ker_x++)
131 {
132 if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x)
133 {
134 /* arm_fill_q15(0, pBuffer, ch_im_in); */
135 memset(pBuffer, 0, sizeof(q15_t) * ch_im_in);
136 }
137 else
138 {
139 /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer,
140 * ch_im_in); */
141 memcpy(pBuffer,
142 (q15_t *)Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in,
143 sizeof(q15_t) * ch_im_in);
144 }
145 pBuffer += ch_im_in;
146 }
147 }
148
149 if (i_out_x & 0x1)
150 {
151 int i;
152 /* initialize the matrix pointers for A */
153 const q15_t *pA = wt;
154
155 /* set up the second output pointers */
156 q15_t *pOut2 = pOut + ch_im_out;
157
158 /* this loop over rows in A */
159 for (i = 0; i < ch_im_out; i += 2)
160 {
161 /* setup pointers for B */
162 const q15_t *pB = im_buffer;
163 const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x;
164
165 /* aling the second pointer for A */
166 const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x;
167
168 /* init the sum with bias */
169 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
170 q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
171 q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
172 q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
173
174 uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1;
175 /* accumulate over the vector */
176 while (colCnt)
177 {
178 q31_t inA1 = arm_nn_read_q15x2_ia(&pA);
179 q31_t inB1 = arm_nn_read_q15x2_ia(&pB);
180 q31_t inA2 = arm_nn_read_q15x2_ia(&pA2);
181 q31_t inB2 = arm_nn_read_q15x2_ia(&pB2);
182
183 sum = __SMLAD(inA1, inB1, sum);
184 sum2 = __SMLAD(inA1, inB2, sum2);
185 sum3 = __SMLAD(inA2, inB1, sum3);
186 sum4 = __SMLAD(inA2, inB2, sum4);
187
188 colCnt--;
189 } /* while over colCnt */
190 colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1;
191 while (colCnt)
192 {
193 q15_t inA1 = *pA++;
194 q15_t inB1 = *pB++;
195 q15_t inA2 = *pA2++;
196 q15_t inB2 = *pB2++;
197
198 sum += inA1 * inB1;
199 sum2 += inA1 * inB2;
200 sum3 += inA2 * inB1;
201 sum4 += inA2 * inB2;
202 colCnt--;
203 } /* while over colCnt */
204 *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16);
205 *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16);
206 *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16);
207 *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16);
208
209 /* skip the row computed with A2 */
210 pA += ch_im_in * dim_kernel_y * dim_kernel_x;
211 } /* for over ch_im_out */
212
213 pOut += ch_im_out;
214 /* counter reset */
215 pBuffer = im_buffer;
216 }
217 }
218 }
219
220 #else
221 (void)bufferA;
222 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
223 int i, j, k, l, m, n;
224 int conv_out;
225 int in_row, in_col;
226
227 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
228 {
229 /* check if the input dimension meets the constraints */
230 return ARM_MATH_SIZE_MISMATCH;
231 }
232
233 for (i = 0; i < ch_im_out; i++)
234 {
235 for (j = 0; j < dim_im_out_y; j++)
236 {
237 for (k = 0; k < dim_im_out_x; k++)
238 {
239 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
240 for (m = 0; m < dim_kernel_y; m++)
241 {
242 for (n = 0; n < dim_kernel_x; n++)
243 {
244 in_row = stride_y * j + m - padding_y;
245 in_col = stride_x * k + n - padding_x;
246 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x)
247 {
248 for (l = 0; l < ch_im_in; l++)
249 {
250 conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] *
251 wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + n) * ch_im_in +
252 l];
253 }
254 }
255 }
256 }
257 Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16);
258 }
259 }
260 }
261
262 #endif /* ARM_MATH_DSP */
263
264 /* Return to application */
265 return ARM_MATH_SUCCESS;
266 }
267
268 /**
269 * @} end of NNConv group
270 */
271
