1 /*
2 * Copyright (C) 2010-2021 Arm Limited or its affiliates. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_HWC_q15_fast.c
22 * Description: Fast Q15 version of convolution
23 *
24 * $Date: January 26, 2021
25 * $Revision: V.1.0.2
26 *
27 * Target Processor: Cortex-M cores
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup groupNN
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /**
44 * @brief Fast Q15 convolution function
45 * @param[in] Im_in pointer to input tensor
46 * @param[in] dim_im_in input tensor dimention
47 * @param[in] ch_im_in number of input tensor channels
48 * @param[in] wt pointer to kernel weights
49 * @param[in] ch_im_out number of filters, i.e., output tensor channels
50 * @param[in] dim_kernel filter kernel size
51 * @param[in] padding padding sizes
52 * @param[in] stride convolution stride
53 * @param[in] bias pointer to bias
54 * @param[in] bias_shift amount of left-shift for bias
55 * @param[in] out_shift amount of right-shift for output
56 * @param[in,out] Im_out pointer to output tensor
57 * @param[in] dim_im_out output tensor dimension
58 * @param[in,out] bufferA pointer to buffer space for input
59 * @param[in,out] bufferB pointer to buffer space for output
60 * @return The function returns either
61 * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
62 *
63 * @details
64 *
65 * <b>Buffer size:</b>
66 *
67 * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel
68 *
69 * bufferB size: 0
70 *
71 * <b>Input dimension constraints:</b>
72 *
73 * ch_im_in is multiple of 2
74 *
75 * ch_im_out is multiple of 2
76 *
77 */
78
arm_convolve_HWC_q15_fast(const q15_t * Im_in,const uint16_t dim_im_in,const uint16_t ch_im_in,const q15_t * wt,const uint16_t ch_im_out,const uint16_t dim_kernel,const uint16_t padding,const uint16_t stride,const q15_t * bias,const uint16_t bias_shift,const uint16_t out_shift,q15_t * Im_out,const uint16_t dim_im_out,q15_t * bufferA,q7_t * bufferB)79 arm_status arm_convolve_HWC_q15_fast(const q15_t *Im_in,
80 const uint16_t dim_im_in,
81 const uint16_t ch_im_in,
82 const q15_t *wt,
83 const uint16_t ch_im_out,
84 const uint16_t dim_kernel,
85 const uint16_t padding,
86 const uint16_t stride,
87 const q15_t *bias,
88 const uint16_t bias_shift,
89 const uint16_t out_shift,
90 q15_t *Im_out,
91 const uint16_t dim_im_out,
92 q15_t *bufferA,
93 q7_t *bufferB)
94 {
95 (void)bufferB;
96 #if defined(ARM_MATH_DSP)
97 int16_t i_out_y, i_out_x, i_ker_y, i_ker_x;
98
99 q15_t *pBuffer = bufferA;
100 q15_t *im_buffer = bufferA;
101 q15_t *pOut = Im_out;
102
103 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
104 {
105 /* check if the input dimension meets the constraints */
106 return ARM_MATH_SIZE_MISMATCH;
107 }
108
109 /* Run the following code for Cortex-M4 and Cortex-M7 */
110
111 /* This part implements the im2col function */
112 for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++)
113 {
114 for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++)
115 {
116 for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++)
117 {
118 for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++)
119 {
120 if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in)
121 {
122 /* arm_fill_q15(0, pBuffer, ch_im_in); */
123 memset(pBuffer, 0, sizeof(q15_t) * ch_im_in);
124 }
125 else
126 {
127 /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer,
128 * ch_im_in); */
129 memcpy(pBuffer,
130 (q15_t *)Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in,
131 sizeof(q15_t) * ch_im_in);
132 }
133 pBuffer += ch_im_in;
134 }
135 }
136
137 if (i_out_x & 0x1)
138 {
139 int i;
140 /* initialize the matrix pointers for A */
141 const q15_t *pA = wt;
142
143 /* set up the second output pointers */
144 q15_t *pOut2 = pOut + ch_im_out;
145
146 /* this loop over rows in A */
147 for (i = 0; i < ch_im_out; i += 2)
148 {
149 /* setup pointers for B */
150 const q15_t *pB = im_buffer;
151 const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel;
152
153 /* aling the second pointer for A */
154 const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel;
155
156 /* init the sum with bias */
157 q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
158 q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
159 q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
160 q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift);
161
162 uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1;
163 /* accumulate over the vector */
164 while (colCnt)
165 {
166 q31_t inA1 = arm_nn_read_q15x2_ia(&pA);
167 q31_t inB1 = arm_nn_read_q15x2_ia(&pB);
168 q31_t inA2 = arm_nn_read_q15x2_ia(&pA2);
169 q31_t inB2 = arm_nn_read_q15x2_ia(&pB2);
170
171 sum = __SMLAD(inA1, inB1, sum);
172 sum2 = __SMLAD(inA1, inB2, sum2);
173 sum3 = __SMLAD(inA2, inB1, sum3);
174 sum4 = __SMLAD(inA2, inB2, sum4);
175
176 colCnt--;
177 } /* while over colCnt */
178 colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1;
179 while (colCnt)
180 {
181 q15_t inA1 = *pA++;
182 q15_t inB1 = *pB++;
183 q15_t inA2 = *pA2++;
184 q15_t inB2 = *pB2++;
185
186 sum += inA1 * inB1;
187 sum2 += inA1 * inB2;
188 sum3 += inA2 * inB1;
189 sum4 += inA2 * inB2;
190 colCnt--;
191 } /* while over colCnt */
192 *pOut++ = (q15_t)__SSAT(sum >> out_shift, 16);
193 *pOut++ = (q15_t)__SSAT(sum3 >> out_shift, 16);
194 *pOut2++ = (q15_t)__SSAT(sum2 >> out_shift, 16);
195 *pOut2++ = (q15_t)__SSAT(sum4 >> out_shift, 16);
196
197 /* skip the row computed with A2 */
198 pA += ch_im_in * dim_kernel * dim_kernel;
199 } /* for over ch_im_out */
200
201 pOut += ch_im_out;
202 /* counter reset */
203 pBuffer = im_buffer;
204 }
205 }
206 }
207
208 #else
209 (void)bufferA;
210 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
211 int i, j, k, l, m, n;
212 int conv_out;
213 int in_row, in_col;
214
215 if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0)
216 {
217 /* check if the input dimension meets the constraints */
218 return ARM_MATH_SIZE_MISMATCH;
219 }
220
221 for (i = 0; i < ch_im_out; i++)
222 {
223 for (j = 0; j < dim_im_out; j++)
224 {
225 for (k = 0; k < dim_im_out; k++)
226 {
227 conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift);
228 for (m = 0; m < dim_kernel; m++)
229 {
230 for (n = 0; n < dim_kernel; n++)
231 {
232 in_row = stride * j + m - padding;
233 in_col = stride * k + n - padding;
234 if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in)
235 {
236 for (l = 0; l < ch_im_in; l++)
237 {
238 conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] *
239 wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l];
240 }
241 }
242 }
243 }
244 Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t)__SSAT((conv_out >> out_shift), 16);
245 }
246 }
247 }
248
249 #endif /* ARM_MATH_DSP */
250
251 /* Return to application */
252 return ARM_MATH_SUCCESS;
253 }
254
255 /**
256 * @} end of NNConv group
257 */
258
