1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include "sdkconfig.h"
15 #include "esp32/rom/spi_flash.h"
16 #include "soc/spi_periph.h"
17 #include "spi_flash_defs.h"
18
19
20 #define SPI_IDX 1
21 #define OTH_IDX 0
22
23
24 extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
25
is_issi_chip(const esp_rom_spiflash_chip_t * chip)26 static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip)
27 {
28 return (((chip->device_id >> 16)&0xff) == 0x9D);
29 }
30
esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t * spi)31 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi)
32 {
33 uint32_t status;
34 #if CONFIG_IDF_TARGET_ESP32
35 //wait for spi control ready
36 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
37 }
38 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
39 }
40 #elif CONFIG_IDF_TARGET_ESP32S2
41 while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) {
42 }
43 while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) {
44 }
45 #endif
46 //wait for flash status ready
47 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) {
48 return ESP_ROM_SPIFLASH_RESULT_ERR;
49 }
50 return ESP_ROM_SPIFLASH_RESULT_OK;
51 }
52
53
54 /* Modified version of esp_rom_spiflash_unlock() that replaces version in ROM.
55
56 This works around a bug where esp_rom_spiflash_unlock sometimes reads the wrong
57 high status byte (RDSR2 result) and then copies it back to the
58 flash status, which can cause the CMP bit or Status Register
59 Protect bit to become set.
60
61 Like other ROM SPI functions, this function is not designed to be
62 called directly from an RTOS environment without taking precautions
63 about interrupts, CPU coordination, flash mapping. However some of
64 the functions in esp_spi_flash.c call it.
65 */
esp_rom_spiflash_unlock(void)66 __attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void)
67 {
68 uint32_t status;
69 uint32_t new_status;
70
71 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
72
73 if (is_issi_chip(&g_rom_spiflash_chip)) {
74 // ISSI chips have different QE position
75
76 if (esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
77 return ESP_ROM_SPIFLASH_RESULT_ERR;
78 }
79
80 /* Clear all bits in the mask.
81 (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
82 */
83 new_status = status & (~ESP_ROM_SPIFLASH_BP_MASK_ISSI);
84 // Skip if nothing needs to be cleared. Otherwise will waste time waiting for the flash to clear nothing.
85 if (new_status == status) return ESP_ROM_SPIFLASH_RESULT_OK;
86
87 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
88 } else {
89 if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
90 return ESP_ROM_SPIFLASH_RESULT_ERR;
91 }
92
93 /* Clear all bits except QE, if it is set.
94 (This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
95 */
96 new_status = status & ESP_ROM_SPIFLASH_QE;
97 SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
98 }
99
100 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
101 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN);
102 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
103 }
104 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
105 esp_rom_spiflash_result_t ret = esp_rom_spiflash_write_status(&g_rom_spiflash_chip, new_status);
106 // WEL bit should be cleared after operations regardless of writing succeed or not.
107 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
108 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI);
109 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
110 }
111 return ret;
112 }
113
114 #if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
115
116 extern uint8_t g_rom_spiflash_dummy_len_plus[];
117
118
119 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
120
121 //only support spi1
esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t * spi)122 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi)
123 {
124 esp_rom_spiflash_wait_idle(spi);
125
126 // Chip erase.
127 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);
128 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
129
130 // check erase is finished.
131 esp_rom_spiflash_wait_idle(spi);
132
133 return ESP_ROM_SPIFLASH_RESULT_OK;
134 }
135
136 //only support spi1
esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t * spi,uint32_t addr)137 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
138 {
139 //check if addr is 4k alignment
140 if (0 != (addr & 0xfff)) {
141 return ESP_ROM_SPIFLASH_RESULT_ERR;
142 }
143
144 esp_rom_spiflash_wait_idle(spi);
145
146 // sector erase 4Kbytes erase is sector erase.
147 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
148 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);
149 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
150
151 esp_rom_spiflash_wait_idle(spi);
152
153 return ESP_ROM_SPIFLASH_RESULT_OK;
154 }
155
156 //only support spi1
esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t * spi,uint32_t addr)157 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
158 {
159 esp_rom_spiflash_wait_idle(spi);
160
161 // sector erase 4Kbytes erase is sector erase.
162 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
163 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);
164 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
165
166 esp_rom_spiflash_wait_idle(spi);
167
168 return ESP_ROM_SPIFLASH_RESULT_OK;
169 }
170
171 //only support spi1
esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t * spi,uint32_t spi_addr,uint32_t * addr_source,int32_t byte_length)172 static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t *spi, uint32_t spi_addr,
173 uint32_t *addr_source, int32_t byte_length)
174 {
175 uint32_t temp_addr;
176 int32_t temp_bl;
177 uint8_t i;
178 uint8_t remain_word_num;
179
180 //check 4byte alignment
181 if (0 != (byte_length & 0x3)) {
182 return ESP_ROM_SPIFLASH_RESULT_ERR;
183 }
184
185 //check if write in one page
186 if ((spi->page_size) < ((spi_addr % (spi->page_size)) + byte_length)) {
187 return ESP_ROM_SPIFLASH_RESULT_ERR;
188 }
189
190 esp_rom_spiflash_wait_idle(spi);
191
192 temp_addr = spi_addr;
193 temp_bl = byte_length;
194
195 while (temp_bl > 0 ) {
196 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
197 return ESP_ROM_SPIFLASH_RESULT_ERR;
198 }
199 if ( temp_bl >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM ) {
200 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block
201
202 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM >> 2); i++) {
203 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
204 }
205 temp_bl = temp_bl - 32;
206 temp_addr = temp_addr + 32;
207 } else {
208 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN ));
209
210 remain_word_num = (0 == (temp_bl & 0x3)) ? (temp_bl >> 2) : (temp_bl >> 2) + 1;
211 for (i = 0; i < remain_word_num; i++) {
212 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
213 temp_bl = temp_bl - 4;
214 }
215 temp_bl = 0;
216 }
217 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);
218 while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 );
219
220 esp_rom_spiflash_wait_idle(spi);
221 }
222
223 return ESP_ROM_SPIFLASH_RESULT_OK;
224 }
225
esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t * spi,uint32_t * status)226 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status)
227 {
228 uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG;
229
230 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
231 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
232 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter
233 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);
234 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
235
236 status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);
237 }
238 } else {
239 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
240 esp_rom_spiflash_read_user_cmd(&status_value, 0x05);
241 }
242 }
243 *status = status_value;
244
245 return ESP_ROM_SPIFLASH_RESULT_OK;
246 }
247
esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t * spi,uint32_t * status)248 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status)
249 {
250 esp_rom_spiflash_result_t ret;
251 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
252 ret = esp_rom_spiflash_read_user_cmd(status, 0x35);
253 *status = *status << 8;
254 return ret;
255 }
256
esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t * spi,uint32_t status_value)257 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value)
258 {
259 esp_rom_spiflash_wait_idle(spi);
260
261 // update status value by status_value
262 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter
263 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);
264 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
265 esp_rom_spiflash_wait_idle(spi);
266
267 return ESP_ROM_SPIFLASH_RESULT_OK;
268 }
269
270 //only support spi1
esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t * spi,uint32_t flash_addr,uint32_t * addr_dest,int32_t byte_length)271 static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t *spi, uint32_t flash_addr,
272 uint32_t *addr_dest, int32_t byte_length)
273 {
274 uint32_t temp_addr;
275 int32_t temp_length;
276 uint8_t i;
277 uint8_t remain_word_num;
278
279 //address range check
280 if ((flash_addr + byte_length) > (spi->chip_size)) {
281 return ESP_ROM_SPIFLASH_RESULT_ERR;
282 }
283
284 temp_addr = flash_addr;
285 temp_length = byte_length;
286
287 esp_rom_spiflash_wait_idle(spi);
288
289 while (temp_length > 0) {
290 if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) {
291 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN));
292 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
293 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
294 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
295 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
296
297 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) {
298 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
299 }
300 temp_length = temp_length - ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
301 temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
302 } else {
303 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN ));
304 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
305 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
306 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
307 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
308
309 remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1;
310 for (i = 0; i < remain_word_num; i++) {
311 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
312 }
313 temp_length = 0;
314 }
315 }
316
317 return ESP_ROM_SPIFLASH_RESULT_OK;
318 }
319
esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t * spi)320 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi)
321 {
322 uint32_t flash_status = 0;
323
324 esp_rom_spiflash_wait_idle(spi);
325
326 //enable write
327 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation
328 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
329
330 // make sure the flash is ready for writing
331 while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
332 esp_rom_spiflash_read_status(spi, &flash_status);
333 }
334
335 return ESP_ROM_SPIFLASH_RESULT_OK;
336 }
337
spi_cache_mode_switch(uint32_t modebit)338 static void spi_cache_mode_switch(uint32_t modebit)
339 {
340 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
341 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
342 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
343 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN);
344 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
345 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xEB);
346 } else if (modebit & SPI_FASTRD_MODE) {
347 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
348 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
349 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN);
350 if ((modebit & SPI_FREAD_QUAD)) {
351 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
352 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
353 } else if ((modebit & SPI_FREAD_DIO)) {
354 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN);
355 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
356 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
357 } else if ((modebit & SPI_FREAD_DUAL)) {
358 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
359 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x3B);
360 } else {
361 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
362 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x0B);
363 }
364 } else {
365 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
366 if (g_rom_spiflash_dummy_len_plus[0] == 0) {
367 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
368 } else {
369 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
370 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1);
371 }
372 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR);
373 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN);
374 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x03);
375 }
376 }
377
esp_rom_spiflash_lock(void)378 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void)
379 {
380 uint32_t status;
381
382 //read QE bit, not write if not QE
383 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status)) {
384 return ESP_ROM_SPIFLASH_RESULT_ERR;
385 }
386 //enable 2 byte status writing
387 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
388
389 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
390 return ESP_ROM_SPIFLASH_RESULT_ERR;
391 }
392
393 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status | ESP_ROM_SPIFLASH_WR_PROTECT)) {
394 return ESP_ROM_SPIFLASH_RESULT_ERR;
395 }
396
397 return ESP_ROM_SPIFLASH_RESULT_OK;
398 }
399
400
esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)401 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)
402 {
403 uint32_t modebit;
404 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
405 }
406 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
407 }
408 //clear old mode bit
409 CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
410 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(0), SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
411 //configure read mode
412 switch (mode) {
413 case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_FREAD_QIO | SPI_FASTRD_MODE; break;
414 case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_FREAD_QUAD | SPI_FASTRD_MODE; break;
415 case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_FREAD_DIO | SPI_FASTRD_MODE; break;
416 case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_FREAD_DUAL | SPI_FASTRD_MODE; break;
417 case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_FASTRD_MODE; break;
418 case ESP_ROM_SPIFLASH_SLOWRD_MODE: modebit = 0; break;
419 default : modebit = 0;
420 }
421
422 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit);
423 SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit);
424 spi_cache_mode_switch(modebit);
425
426 return ESP_ROM_SPIFLASH_RESULT_OK;
427 }
428
esp_rom_spiflash_erase_chip(void)429 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void)
430 {
431 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
432 return ESP_ROM_SPIFLASH_RESULT_ERR;
433 }
434
435 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_chip_internal(&g_rom_spiflash_chip)) {
436 return ESP_ROM_SPIFLASH_RESULT_ERR;
437 }
438
439 return ESP_ROM_SPIFLASH_RESULT_OK;
440 }
441
esp_rom_spiflash_erase_block(uint32_t block_num)442 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num)
443 {
444 // flash write is always 1 line currently
445 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
446 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
447 //check program size
448 if (block_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.block_size))) {
449 return ESP_ROM_SPIFLASH_RESULT_ERR;
450 }
451
452 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
453 return ESP_ROM_SPIFLASH_RESULT_ERR;
454 }
455
456 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block_internal(&g_rom_spiflash_chip, block_num * (g_rom_spiflash_chip.block_size))) {
457 return ESP_ROM_SPIFLASH_RESULT_ERR;
458 }
459 return ESP_ROM_SPIFLASH_RESULT_OK;
460 }
461
esp_rom_spiflash_erase_sector(uint32_t sector_num)462 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num)
463 {
464 // flash write is always 1 line currently
465 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
466 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
467 //check program size
468 if (sector_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.sector_size))) {
469 return ESP_ROM_SPIFLASH_RESULT_ERR;
470 }
471
472 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
473 return ESP_ROM_SPIFLASH_RESULT_ERR;
474 }
475
476 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector_internal(&g_rom_spiflash_chip, sector_num * (g_rom_spiflash_chip.sector_size))) {
477 return ESP_ROM_SPIFLASH_RESULT_ERR;
478 }
479
480 return ESP_ROM_SPIFLASH_RESULT_OK;
481 }
482
esp_rom_spiflash_write(uint32_t target,const uint32_t * src_addr,int32_t len)483 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t *src_addr, int32_t len)
484 {
485 uint32_t page_size;
486 uint32_t pgm_len, pgm_num;
487 uint8_t i;
488
489 // flash write is always 1 line currently
490 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
491 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
492 //check program size
493 if ( (target + len) > (g_rom_spiflash_chip.chip_size)) {
494 return ESP_ROM_SPIFLASH_RESULT_ERR;
495 }
496
497 page_size = g_rom_spiflash_chip.page_size;
498 pgm_len = page_size - (target % page_size);
499 if (len < pgm_len) {
500 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
501 target, (uint32_t *)src_addr, len)) {
502 return ESP_ROM_SPIFLASH_RESULT_ERR;
503 }
504 } else {
505 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
506 target, (uint32_t *)src_addr, pgm_len)) {
507 return ESP_ROM_SPIFLASH_RESULT_ERR;
508 }
509
510 //whole page program
511 pgm_num = (len - pgm_len) / page_size;
512 for (i = 0; i < pgm_num; i++) {
513 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
514 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), page_size)) {
515 return ESP_ROM_SPIFLASH_RESULT_ERR;
516 }
517 pgm_len += page_size;
518 }
519
520 //remain parts to program
521 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
522 target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), len - pgm_len)) {
523 return ESP_ROM_SPIFLASH_RESULT_ERR;
524 }
525 }
526 return ESP_ROM_SPIFLASH_RESULT_OK;
527 }
528
esp_rom_spiflash_write_encrypted(uint32_t flash_addr,uint32_t * data,uint32_t len)529 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len)
530 {
531 esp_rom_spiflash_result_t ret = ESP_ROM_SPIFLASH_RESULT_OK;
532 uint32_t i;
533
534 if ((flash_addr & 0x1f) || (len & 0x1f)) { //check 32 byte alignment
535 return ESP_ROM_SPIFLASH_RESULT_ERR;
536 }
537
538 esp_rom_spiflash_write_encrypted_enable();
539
540 for (i = 0; i < (len >> 5); i++) {
541 if ((ret = esp_rom_spiflash_prepare_encrypted_data(flash_addr + (i << 5), data + (i << 3))) != ESP_ROM_SPIFLASH_RESULT_OK) {
542 break;
543 }
544
545 if ((ret = esp_rom_spiflash_write(flash_addr + (i << 5), data, 32)) != ESP_ROM_SPIFLASH_RESULT_OK) {
546 break;
547 }
548 }
549
550 esp_rom_spiflash_write_encrypted_disable();
551
552 return ret;
553 }
554
esp_rom_spiflash_read(uint32_t target,uint32_t * dest_addr,int32_t len)555 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_addr, int32_t len)
556 {
557 // QIO or SIO, non-QIO regard as SIO
558 uint32_t modebit;
559 modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
560 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
561 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
562 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
563 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
564 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
565 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
566 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB);
567 } else if (modebit & SPI_FASTRD_MODE) {
568 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
569 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
570 if (modebit & SPI_FREAD_DIO) {
571 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
572 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
573 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
574 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB);
575 } else {
576 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
577 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
578 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
579 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB);
580 }
581 } else {
582 if ((modebit & SPI_FREAD_QUAD)) {
583 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x6B);
584 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B);
585 } else if ((modebit & SPI_FREAD_DUAL)) {
586 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x3B);
587 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B);
588 } else {
589 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x0B);
590 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x0B);
591 }
592 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
593 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN);
594 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
595 }
596 } else {
597 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
598 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
599 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
600 } else {
601 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
602 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
603 }
604 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
605 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
606 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03);
607 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
608 }
609
610 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, target, dest_addr, len)) {
611 return ESP_ROM_SPIFLASH_RESULT_ERR;
612 }
613 return ESP_ROM_SPIFLASH_RESULT_OK;
614 }
615
esp_rom_spiflash_erase_area(uint32_t start_addr,uint32_t area_len)616 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len)
617 {
618 int32_t total_sector_num;
619 int32_t head_sector_num;
620 uint32_t sector_no;
621 uint32_t sector_num_per_block;
622
623 //set read mode to Fastmode ,not QDIO mode for erase
624 //
625 // TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this
626 // function is not used in IDF.
627 esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE);
628
629 //check if area is oversize of flash
630 if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) {
631 return ESP_ROM_SPIFLASH_RESULT_ERR;
632 }
633
634 //start_addr is aligned as sector boundary
635 if (0 != (start_addr % g_rom_spiflash_chip.sector_size)) {
636 return ESP_ROM_SPIFLASH_RESULT_ERR;
637 }
638
639 //Unlock flash to enable erase
640 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/)) {
641 return ESP_ROM_SPIFLASH_RESULT_ERR;
642 }
643
644 sector_no = start_addr / g_rom_spiflash_chip.sector_size;
645 sector_num_per_block = g_rom_spiflash_chip.block_size / g_rom_spiflash_chip.sector_size;
646 total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size)) ? area_len / g_rom_spiflash_chip.sector_size :
647 1 + (area_len / g_rom_spiflash_chip.sector_size);
648
649 //check if erase area reach over block boundary
650 head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block);
651
652 head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num;
653
654 //JJJ, BUG of 6.0 erase
655 //middle part of area is aligned by blocks
656 total_sector_num -= head_sector_num;
657
658 //head part of area is erased
659 while (0 != head_sector_num) {
660 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
661 return ESP_ROM_SPIFLASH_RESULT_ERR;
662 }
663 sector_no++;
664 head_sector_num--;
665 }
666 while (total_sector_num > sector_num_per_block) {
667 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) {
668 return ESP_ROM_SPIFLASH_RESULT_ERR;
669 }
670 sector_no += sector_num_per_block;
671 total_sector_num -= sector_num_per_block;
672 }
673
674 //tail part of area burn
675 while (0 < total_sector_num) {
676 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
677 return ESP_ROM_SPIFLASH_RESULT_ERR;
678 }
679 sector_no++;
680 total_sector_num--;
681 }
682
683 return ESP_ROM_SPIFLASH_RESULT_OK;
684 }
685
esp_rom_spiflash_write_disable(void)686 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
687 {
688 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI);
689 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
690 return ESP_ROM_SPIFLASH_RESULT_OK;
691 }
692
693 #endif
694
