1 /* 2 * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 typedef volatile struct apb_saradc_dev_s { 15 union { 16 struct { 17 uint32_t start_force: 1; 18 uint32_t start: 1; 19 uint32_t reserved2: 1; 20 uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ 21 uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ 22 uint32_t sar_clk_gated: 1; 23 uint32_t sar_clk_div: 8; /*SAR clock divider*/ 24 uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ 25 uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ 26 uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ 27 uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ 28 uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ 29 uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ 30 uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ 31 uint32_t reserved29: 1; 32 uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ 33 }; 34 uint32_t val; 35 } ctrl; 36 union { 37 struct { 38 uint32_t meas_num_limit: 1; 39 uint32_t max_meas_num: 8; /*max conversion number*/ 40 uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ 41 uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ 42 uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/ 43 uint32_t timer_target: 12; /*to set saradc timer target*/ 44 uint32_t timer_en: 1; /*to enable saradc timer trigger*/ 45 uint32_t reserved25: 7; 46 }; 47 uint32_t val; 48 } ctrl2; 49 union { 50 struct { 51 uint32_t reserved0: 16; 52 uint32_t sample_num: 8; /*sample number*/ 53 uint32_t sample_cycle: 8; /*sample cycles*/ 54 }; 55 uint32_t val; 56 } fsm; 57 union { 58 struct { 59 uint32_t xpd_wait: 8; 60 uint32_t rstb_wait: 8; 61 uint32_t standby_wait: 8; 62 uint32_t reserved24: 8; 63 }; 64 uint32_t val; 65 } fsm_wait; 66 uint32_t sar1_status; /**/ 67 uint32_t sar2_status; /**/ 68 uint32_t sar1_patt_tab[4]; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ 69 uint32_t sar2_patt_tab[4]; 70 union { 71 struct { 72 uint32_t reserved0: 2; 73 uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ 74 uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ 75 uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ 76 uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ 77 uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ 78 uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ 79 uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ 80 uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ 81 uint32_t reserved13: 19; 82 }; 83 uint32_t val; 84 } apb_adc_arb_ctrl; 85 union { 86 struct { 87 uint32_t adc2_filter_reset: 1; /*reset_adc2_filter*/ 88 uint32_t adc1_filter_reset: 1; /*reset_adc1_filter*/ 89 uint32_t reserved2: 14; 90 uint32_t adc2_filter_factor: 7; /*apb_adc2_filter_factor*/ 91 uint32_t adc1_filter_factor: 7; /*apb_adc1_filter_factor*/ 92 uint32_t adc2_filter_en: 1; /*enable apb_adc2_filter*/ 93 uint32_t adc1_filter_en: 1; /*enable apb_adc1_filter*/ 94 }; 95 uint32_t val; 96 } filter_ctrl; 97 union { 98 struct { 99 uint32_t adc2_filter_data:16; 100 uint32_t adc1_filter_data:16; 101 }; 102 uint32_t val; 103 } filter_status; 104 union { 105 struct { 106 uint32_t clk_en: 1; 107 uint32_t reserved1: 1; 108 uint32_t adc2_thres_mode: 1; 109 uint32_t adc1_thres_mode: 1; 110 uint32_t adc2_thres: 13; 111 uint32_t adc1_thres: 13; 112 uint32_t adc2_thres_en: 1; 113 uint32_t adc1_thres_en: 1; 114 }; 115 uint32_t val; 116 } thres_ctrl; 117 union { 118 struct { 119 uint32_t reserved0: 28; 120 uint32_t adc2_thres: 1; 121 uint32_t adc1_thres: 1; 122 uint32_t adc2_done: 1; 123 uint32_t adc1_done: 1; 124 }; 125 uint32_t val; 126 } int_ena; 127 union { 128 struct { 129 uint32_t reserved0: 28; 130 uint32_t adc2_thres: 1; 131 uint32_t adc1_thres: 1; 132 uint32_t adc2_done: 1; 133 uint32_t adc1_done: 1; 134 }; 135 uint32_t val; 136 } int_raw; 137 union { 138 struct { 139 uint32_t reserved0: 28; 140 uint32_t adc2_thres: 1; 141 uint32_t adc1_thres: 1; 142 uint32_t adc2_done: 1; 143 uint32_t adc1_done: 1; 144 }; 145 uint32_t val; 146 } int_st; 147 union { 148 struct { 149 uint32_t reserved0: 28; 150 uint32_t adc2_thres: 1; 151 uint32_t adc1_thres: 1; 152 uint32_t adc2_done: 1; 153 uint32_t adc1_done: 1; 154 }; 155 uint32_t val; 156 } int_clr; 157 union { 158 struct { 159 uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ 160 uint32_t reserved16: 14; 161 uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ 162 uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ 163 }; 164 uint32_t val; 165 } dma_conf; 166 union { 167 struct { 168 uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ 169 uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ 170 uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ 171 uint32_t reserved20: 1; 172 uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ 173 uint32_t reserved23: 9; 174 }; 175 uint32_t val; 176 } apb_adc_clkm_conf; 177 union { 178 struct { 179 uint32_t dac_timer_target: 12; /*dac_timer target*/ 180 uint32_t dac_timer_en: 1; /*enable read dac data*/ 181 uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/ 182 uint32_t apb_dac_trans: 1; /*enable dma_dac*/ 183 uint32_t dac_reset_fifo: 1; 184 uint32_t apb_dac_rst: 1; 185 uint32_t reserved17: 15; 186 }; 187 uint32_t val; 188 } apb_dac_ctrl; 189 uint32_t reserved_64; 190 uint32_t reserved_68; 191 uint32_t reserved_6c; 192 uint32_t reserved_70; 193 uint32_t reserved_74; 194 uint32_t reserved_78; 195 uint32_t reserved_7c; 196 uint32_t reserved_80; 197 uint32_t reserved_84; 198 uint32_t reserved_88; 199 uint32_t reserved_8c; 200 uint32_t reserved_90; 201 uint32_t reserved_94; 202 uint32_t reserved_98; 203 uint32_t reserved_9c; 204 uint32_t reserved_a0; 205 uint32_t reserved_a4; 206 uint32_t reserved_a8; 207 uint32_t reserved_ac; 208 uint32_t reserved_b0; 209 uint32_t reserved_b4; 210 uint32_t reserved_b8; 211 uint32_t reserved_bc; 212 uint32_t reserved_c0; 213 uint32_t reserved_c4; 214 uint32_t reserved_c8; 215 uint32_t reserved_cc; 216 uint32_t reserved_d0; 217 uint32_t reserved_d4; 218 uint32_t reserved_d8; 219 uint32_t reserved_dc; 220 uint32_t reserved_e0; 221 uint32_t reserved_e4; 222 uint32_t reserved_e8; 223 uint32_t reserved_ec; 224 uint32_t reserved_f0; 225 uint32_t reserved_f4; 226 uint32_t reserved_f8; 227 uint32_t reserved_fc; 228 uint32_t reserved_100; 229 uint32_t reserved_104; 230 uint32_t reserved_108; 231 uint32_t reserved_10c; 232 uint32_t reserved_110; 233 uint32_t reserved_114; 234 uint32_t reserved_118; 235 uint32_t reserved_11c; 236 uint32_t reserved_120; 237 uint32_t reserved_124; 238 uint32_t reserved_128; 239 uint32_t reserved_12c; 240 uint32_t reserved_130; 241 uint32_t reserved_134; 242 uint32_t reserved_138; 243 uint32_t reserved_13c; 244 uint32_t reserved_140; 245 uint32_t reserved_144; 246 uint32_t reserved_148; 247 uint32_t reserved_14c; 248 uint32_t reserved_150; 249 uint32_t reserved_154; 250 uint32_t reserved_158; 251 uint32_t reserved_15c; 252 uint32_t reserved_160; 253 uint32_t reserved_164; 254 uint32_t reserved_168; 255 uint32_t reserved_16c; 256 uint32_t reserved_170; 257 uint32_t reserved_174; 258 uint32_t reserved_178; 259 uint32_t reserved_17c; 260 uint32_t reserved_180; 261 uint32_t reserved_184; 262 uint32_t reserved_188; 263 uint32_t reserved_18c; 264 uint32_t reserved_190; 265 uint32_t reserved_194; 266 uint32_t reserved_198; 267 uint32_t reserved_19c; 268 uint32_t reserved_1a0; 269 uint32_t reserved_1a4; 270 uint32_t reserved_1a8; 271 uint32_t reserved_1ac; 272 uint32_t reserved_1b0; 273 uint32_t reserved_1b4; 274 uint32_t reserved_1b8; 275 uint32_t reserved_1bc; 276 uint32_t reserved_1c0; 277 uint32_t reserved_1c4; 278 uint32_t reserved_1c8; 279 uint32_t reserved_1cc; 280 uint32_t reserved_1d0; 281 uint32_t reserved_1d4; 282 uint32_t reserved_1d8; 283 uint32_t reserved_1dc; 284 uint32_t reserved_1e0; 285 uint32_t reserved_1e4; 286 uint32_t reserved_1e8; 287 uint32_t reserved_1ec; 288 uint32_t reserved_1f0; 289 uint32_t reserved_1f4; 290 uint32_t reserved_1f8; 291 uint32_t reserved_1fc; 292 uint32_t reserved_200; 293 uint32_t reserved_204; 294 uint32_t reserved_208; 295 uint32_t reserved_20c; 296 uint32_t reserved_210; 297 uint32_t reserved_214; 298 uint32_t reserved_218; 299 uint32_t reserved_21c; 300 uint32_t reserved_220; 301 uint32_t reserved_224; 302 uint32_t reserved_228; 303 uint32_t reserved_22c; 304 uint32_t reserved_230; 305 uint32_t reserved_234; 306 uint32_t reserved_238; 307 uint32_t reserved_23c; 308 uint32_t reserved_240; 309 uint32_t reserved_244; 310 uint32_t reserved_248; 311 uint32_t reserved_24c; 312 uint32_t reserved_250; 313 uint32_t reserved_254; 314 uint32_t reserved_258; 315 uint32_t reserved_25c; 316 uint32_t reserved_260; 317 uint32_t reserved_264; 318 uint32_t reserved_268; 319 uint32_t reserved_26c; 320 uint32_t reserved_270; 321 uint32_t reserved_274; 322 uint32_t reserved_278; 323 uint32_t reserved_27c; 324 uint32_t reserved_280; 325 uint32_t reserved_284; 326 uint32_t reserved_288; 327 uint32_t reserved_28c; 328 uint32_t reserved_290; 329 uint32_t reserved_294; 330 uint32_t reserved_298; 331 uint32_t reserved_29c; 332 uint32_t reserved_2a0; 333 uint32_t reserved_2a4; 334 uint32_t reserved_2a8; 335 uint32_t reserved_2ac; 336 uint32_t reserved_2b0; 337 uint32_t reserved_2b4; 338 uint32_t reserved_2b8; 339 uint32_t reserved_2bc; 340 uint32_t reserved_2c0; 341 uint32_t reserved_2c4; 342 uint32_t reserved_2c8; 343 uint32_t reserved_2cc; 344 uint32_t reserved_2d0; 345 uint32_t reserved_2d4; 346 uint32_t reserved_2d8; 347 uint32_t reserved_2dc; 348 uint32_t reserved_2e0; 349 uint32_t reserved_2e4; 350 uint32_t reserved_2e8; 351 uint32_t reserved_2ec; 352 uint32_t reserved_2f0; 353 uint32_t reserved_2f4; 354 uint32_t reserved_2f8; 355 uint32_t reserved_2fc; 356 uint32_t reserved_300; 357 uint32_t reserved_304; 358 uint32_t reserved_308; 359 uint32_t reserved_30c; 360 uint32_t reserved_310; 361 uint32_t reserved_314; 362 uint32_t reserved_318; 363 uint32_t reserved_31c; 364 uint32_t reserved_320; 365 uint32_t reserved_324; 366 uint32_t reserved_328; 367 uint32_t reserved_32c; 368 uint32_t reserved_330; 369 uint32_t reserved_334; 370 uint32_t reserved_338; 371 uint32_t reserved_33c; 372 uint32_t reserved_340; 373 uint32_t reserved_344; 374 uint32_t reserved_348; 375 uint32_t reserved_34c; 376 uint32_t reserved_350; 377 uint32_t reserved_354; 378 uint32_t reserved_358; 379 uint32_t reserved_35c; 380 uint32_t reserved_360; 381 uint32_t reserved_364; 382 uint32_t reserved_368; 383 uint32_t reserved_36c; 384 uint32_t reserved_370; 385 uint32_t reserved_374; 386 uint32_t reserved_378; 387 uint32_t reserved_37c; 388 uint32_t reserved_380; 389 uint32_t reserved_384; 390 uint32_t reserved_388; 391 uint32_t reserved_38c; 392 uint32_t reserved_390; 393 uint32_t reserved_394; 394 uint32_t reserved_398; 395 uint32_t reserved_39c; 396 uint32_t reserved_3a0; 397 uint32_t reserved_3a4; 398 uint32_t reserved_3a8; 399 uint32_t reserved_3ac; 400 uint32_t reserved_3b0; 401 uint32_t reserved_3b4; 402 uint32_t reserved_3b8; 403 uint32_t reserved_3bc; 404 uint32_t reserved_3c0; 405 uint32_t reserved_3c4; 406 uint32_t reserved_3c8; 407 uint32_t reserved_3cc; 408 uint32_t reserved_3d0; 409 uint32_t reserved_3d4; 410 uint32_t reserved_3d8; 411 uint32_t reserved_3dc; 412 uint32_t reserved_3e0; 413 uint32_t reserved_3e4; 414 uint32_t reserved_3e8; 415 uint32_t reserved_3ec; 416 uint32_t reserved_3f0; 417 uint32_t reserved_3f4; 418 uint32_t reserved_3f8; 419 uint32_t apb_ctrl_date; /**/ 420 } apb_saradc_dev_t; 421 extern apb_saradc_dev_t APB_SARADC; 422 #ifdef __cplusplus 423 } 424 #endif 425
