apb2_clock (definition) in projects: Zephyr-Core-3.6.0

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Searched defs:apb2_clock (Results 1 – 5 of 5) sorted by relevance

/Zephyr-Core-3.6.0/drivers/clock_control/
D	clock_stm32_ll_common.c	`284 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); in stm32_clock_control_get_subsys_rate() local 287 uint32_t apb2_clock = apb1_clock; in stm32_clock_control_get_subsys_rate() local`
D	clock_stm32_ll_wba.c	`167 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); in stm32_clock_control_get_subsys_rate() local`
D	clock_stm32_ll_u5.c	`222 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); in stm32_clock_control_get_subsys_rate() local`
D	clock_stm32_ll_h5.c	`216 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); in stm32_clock_control_get_subsys_rate() local`
D	clock_stm32_ll_h7.c	`446 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_D2PPRE2); in stm32_clock_control_get_subsys_rate() local`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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acpica-3.7.0
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babblesim_base-3.7.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
babblesim_ext_libCryptov1-3.7.0-3.6.0-3.5.0-3.4.0
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