1 /* 2 * Copyright (c) 2015, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * o Redistributions of source code must retain the above copyright notice, this list 9 * of conditions and the following disclaimer. 10 * 11 * o Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "fsl_xcvr.h" 32 33 /******************************************************************************* 34 * Definitions 35 ******************************************************************************/ 36 37 /******************************************************************************* 38 * Prototypes 39 ******************************************************************************/ 40 41 /******************************************************************************* 42 * Variables 43 ******************************************************************************/ 44 45 /******************************************************************************* 46 * Code 47 ******************************************************************************/ 48 const xcvr_mode_config_t ant_mode_config = 49 { 50 .radio_mode = ANT_MODE, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK 52 #if !RADIO_IS_GEN_2P1 53 | SIM_SCGC5_ANT_MASK 54 #endif /* !RADIO_IS_GEN_2P1 */ 55 , 56 57 /* XCVR_MISC configs */ 58 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 59 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 60 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 61 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | 62 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | 63 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), 64 65 /* XCVR_PHY configs */ 66 .phy_pre_ref0_init = RW0PS(0, 0x1B) | 67 RW0PS(1, 0x1CU) | 68 RW0PS(2, 0x1CU) | 69 RW0PS(3, 0x1CU) | 70 RW0PS(4, 0x1DU) | 71 RW0PS(5, 0x1DU) | 72 RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ 73 .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ 74 RW1PS(7, 0x1EU) | 75 RW1PS(8, 0x1EU) | 76 RW1PS(9, 0x1EU) | 77 RW1PS(10, 0x1EU) | 78 RW1PS(11, 0x1DU) | 79 RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ 80 .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ 81 RW2PS(13, 0x1CU) | 82 RW2PS(14, 0x1CU) | 83 RW2PS(15, 0x1CU), 84 85 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | 86 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 87 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 88 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 89 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 90 XCVR_PHY_CFG1_CTS_THRESH(0xF8) | 91 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 92 93 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 94 #if !RADIO_IS_GEN_2P1 95 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 96 #endif /* !RADIO_IS_GEN_2P1 */ 97 , 98 99 /* XCVR_RX_DIG configs */ 100 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 101 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ 102 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 103 104 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 105 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 106 107 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 108 /* XCVR_TSM configs */ 109 #if (DATA_PADDING_EN) 110 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), 111 #else 112 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), 113 #endif /* (DATA_PADDING_EN) */ 114 115 /* XCVR_TX_DIG configs */ 116 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 117 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | 118 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 119 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | 120 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 121 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 122 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 123 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 124 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), 125 .tx_gfsk_coeff1_26mhz = 0, 126 .tx_gfsk_coeff2_26mhz = 0, 127 .tx_gfsk_coeff1_32mhz = 0, 128 .tx_gfsk_coeff2_32mhz = 0, 129 }; 130 131 /* MODE & DATA RATE combined configuration */ 132 const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = 133 { 134 .radio_mode = ANT_MODE, 135 .data_rate = DR_1MBPS, 136 137 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 138 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 139 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 140 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 141 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 142 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 143 144 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 145 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , 146 147 /* AGC configs */ 148 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | 149 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 150 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 151 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 152 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 153 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 154 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | 155 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 156 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 157 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 158 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 159 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 160 161 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 162 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, 163 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, 164 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, 165 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, 166 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, 167 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, 168 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, 169 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, 170 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, 171 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, 172 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, 173 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, 174 175 /* ANT 32MHz Channel Filter */ 176 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, 177 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, 178 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, 179 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, 180 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, 181 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, 182 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, 183 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, 184 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, 185 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, 186 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, 187 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, 188 189 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 190 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 191 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 192 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 193 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 194 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 195 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 196 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 197 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 198 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 199 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 200 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 201 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 202 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 203 204 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 205 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 206 }; 207 208
