1 /** 2 ****************************************************************************** 3 * @file ais3624dq_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ais3624dq_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef AIS3624DQ_REGS_H 23 #define AIS3624DQ_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup AIS3624DQ 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup AIS3624DQ_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 172 #define AIS3624DQ_I2C_ADD_L 0x31 173 #define AIS3624DQ_I2C_ADD_H 0x33 174 175 /** Device Identification (Who am I) **/ 176 #define AIS3624DQ_ID 0x32 177 178 /** 179 * @} 180 * 181 */ 182 183 #define AIS3624DQ_WHO_AM_I 0x0FU 184 #define AIS3624DQ_CTRL_REG1 0x20U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t xen : 1; 189 uint8_t yen : 1; 190 uint8_t zen : 1; 191 uint8_t dr : 2; 192 uint8_t pm : 3; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t pm : 3; 195 uint8_t dr : 2; 196 uint8_t zen : 1; 197 uint8_t yen : 1; 198 uint8_t xen : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } ais3624dq_ctrl_reg1_t; 201 202 #define AIS3624DQ_CTRL_REG2 0x21U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t hpcf : 2; 207 uint8_t hpen : 2; 208 uint8_t fds : 1; 209 uint8_t hpm : 2; 210 uint8_t boot : 1; 211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 212 uint8_t boot : 1; 213 uint8_t hpm : 2; 214 uint8_t fds : 1; 215 uint8_t hpen : 2; 216 uint8_t hpcf : 2; 217 #endif /* DRV_BYTE_ORDER */ 218 } ais3624dq_ctrl_reg2_t; 219 220 #define AIS3624DQ_CTRL_REG3 0x22U 221 typedef struct 222 { 223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 224 uint8_t i1_cfg : 2; 225 uint8_t lir1 : 1; 226 uint8_t i2_cfg : 2; 227 uint8_t lir2 : 1; 228 uint8_t pp_od : 1; 229 uint8_t ihl : 1; 230 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 231 uint8_t ihl : 1; 232 uint8_t pp_od : 1; 233 uint8_t lir2 : 1; 234 uint8_t i2_cfg : 2; 235 uint8_t lir1 : 1; 236 uint8_t i1_cfg : 2; 237 #endif /* DRV_BYTE_ORDER */ 238 } ais3624dq_ctrl_reg3_t; 239 240 #define AIS3624DQ_CTRL_REG4 0x23U 241 typedef struct 242 { 243 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 244 uint8_t sim : 1; 245 uint8_t st : 3; /* STsign + ST */ 246 uint8_t fs : 2; 247 uint8_t ble : 1; 248 uint8_t bdu : 1; 249 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 250 uint8_t bdu : 1; 251 uint8_t ble : 1; 252 uint8_t fs : 2; 253 uint8_t st : 3; /* STsign + ST */ 254 uint8_t sim : 1; 255 #endif /* DRV_BYTE_ORDER */ 256 } ais3624dq_ctrl_reg4_t; 257 258 #define AIS3624DQ_CTRL_REG5 0x24U 259 typedef struct 260 { 261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 262 uint8_t turnon : 2; 263 uint8_t not_used_01 : 6; 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t not_used_01 : 6; 266 uint8_t turnon : 2; 267 #endif /* DRV_BYTE_ORDER */ 268 } ais3624dq_ctrl_reg5_t; 269 270 #define AIS3624DQ_HP_FILTER_RESET 0x25U 271 #define AIS3624DQ_REFERENCE 0x26U 272 #define AIS3624DQ_STATUS_REG 0x27U 273 typedef struct 274 { 275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 276 uint8_t xda : 1; 277 uint8_t yda : 1; 278 uint8_t zda : 1; 279 uint8_t zyxda : 1; 280 uint8_t _xor : 1; 281 uint8_t yor : 1; 282 uint8_t zor : 1; 283 uint8_t zyxor : 1; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t zyxor : 1; 286 uint8_t zor : 1; 287 uint8_t yor : 1; 288 uint8_t _xor : 1; 289 uint8_t zyxda : 1; 290 uint8_t zda : 1; 291 uint8_t yda : 1; 292 uint8_t xda : 1; 293 #endif /* DRV_BYTE_ORDER */ 294 } ais3624dq_status_reg_t; 295 296 #define AIS3624DQ_OUT_X_L 0x28U 297 #define AIS3624DQ_OUT_X_H 0x29U 298 #define AIS3624DQ_OUT_Y_L 0x2AU 299 #define AIS3624DQ_OUT_Y_H 0x2BU 300 #define AIS3624DQ_OUT_Z_L 0x2CU 301 #define AIS3624DQ_OUT_Z_H 0x2DU 302 #define AIS3624DQ_INT1_CFG 0x30U 303 typedef struct 304 { 305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 306 uint8_t xlie : 1; 307 uint8_t xhie : 1; 308 uint8_t ylie : 1; 309 uint8_t yhie : 1; 310 uint8_t zlie : 1; 311 uint8_t zhie : 1; 312 uint8_t _6d : 1; 313 uint8_t aoi : 1; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t aoi : 1; 316 uint8_t _6d : 1; 317 uint8_t zhie : 1; 318 uint8_t zlie : 1; 319 uint8_t yhie : 1; 320 uint8_t ylie : 1; 321 uint8_t xhie : 1; 322 uint8_t xlie : 1; 323 #endif /* DRV_BYTE_ORDER */ 324 } ais3624dq_int1_cfg_t; 325 326 #define AIS3624DQ_INT1_SRC 0x31U 327 typedef struct 328 { 329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 330 uint8_t xl : 1; 331 uint8_t xh : 1; 332 uint8_t yl : 1; 333 uint8_t yh : 1; 334 uint8_t zl : 1; 335 uint8_t zh : 1; 336 uint8_t ia : 1; 337 uint8_t not_used_01 : 1; 338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 339 uint8_t not_used_01 : 1; 340 uint8_t ia : 1; 341 uint8_t zh : 1; 342 uint8_t zl : 1; 343 uint8_t yh : 1; 344 uint8_t yl : 1; 345 uint8_t xh : 1; 346 uint8_t xl : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } ais3624dq_int1_src_t; 349 350 #define AIS3624DQ_INT1_THS 0x32U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t ths : 7; 355 uint8_t not_used_01 : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t not_used_01 : 1; 358 uint8_t ths : 7; 359 #endif /* DRV_BYTE_ORDER */ 360 } ais3624dq_int1_ths_t; 361 362 #define AIS3624DQ_INT1_DURATION 0x33U 363 typedef struct 364 { 365 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 366 uint8_t d : 7; 367 uint8_t not_used_01 : 1; 368 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 369 uint8_t not_used_01 : 1; 370 uint8_t d : 7; 371 #endif /* DRV_BYTE_ORDER */ 372 373 } ais3624dq_int1_duration_t; 374 375 #define AIS3624DQ_INT2_CFG 0x34U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t xlie : 1; 380 uint8_t xhie : 1; 381 uint8_t ylie : 1; 382 uint8_t yhie : 1; 383 uint8_t zlie : 1; 384 uint8_t zhie : 1; 385 uint8_t _6d : 1; 386 uint8_t aoi : 1; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t aoi : 1; 389 uint8_t _6d : 1; 390 uint8_t zhie : 1; 391 uint8_t zlie : 1; 392 uint8_t yhie : 1; 393 uint8_t ylie : 1; 394 uint8_t xhie : 1; 395 uint8_t xlie : 1; 396 #endif /* DRV_BYTE_ORDER */ 397 398 } ais3624dq_int2_cfg_t; 399 400 #define AIS3624DQ_INT2_SRC 0x35U 401 typedef struct 402 { 403 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 404 uint8_t xl : 1; 405 uint8_t xh : 1; 406 uint8_t yl : 1; 407 uint8_t yh : 1; 408 uint8_t zl : 1; 409 uint8_t zh : 1; 410 uint8_t ia : 1; 411 uint8_t not_used_01 : 1; 412 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 413 uint8_t not_used_01 : 1; 414 uint8_t ia : 1; 415 uint8_t zh : 1; 416 uint8_t zl : 1; 417 uint8_t yh : 1; 418 uint8_t yl : 1; 419 uint8_t xh : 1; 420 uint8_t xl : 1; 421 #endif /* DRV_BYTE_ORDER */ 422 423 } ais3624dq_int2_src_t; 424 425 #define AIS3624DQ_INT2_THS 0x36U 426 typedef struct 427 { 428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 429 uint8_t ths : 7; 430 uint8_t not_used_01 : 1; 431 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 432 uint8_t not_used_01 : 1; 433 uint8_t ths : 7; 434 #endif /* DRV_BYTE_ORDER */ 435 } ais3624dq_int2_ths_t; 436 437 #define AIS3624DQ_INT2_DURATION 0x37U 438 typedef struct 439 { 440 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 441 uint8_t d : 7; 442 uint8_t not_used_01 : 1; 443 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 444 uint8_t not_used_01 : 1; 445 uint8_t d : 7; 446 #endif /* DRV_BYTE_ORDER */ 447 } ais3624dq_int2_duration_t; 448 449 /** 450 * @defgroup AIS3624DQ_Register_Union 451 * @brief This union group all the registers having a bit-field 452 * description. 453 * This union is useful but it's not needed by the driver. 454 * 455 * REMOVING this union you are compliant with: 456 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 457 * 458 * @{ 459 * 460 */ 461 typedef union 462 { 463 ais3624dq_ctrl_reg1_t ctrl_reg1; 464 ais3624dq_ctrl_reg2_t ctrl_reg2; 465 ais3624dq_ctrl_reg3_t ctrl_reg3; 466 ais3624dq_ctrl_reg4_t ctrl_reg4; 467 ais3624dq_ctrl_reg5_t ctrl_reg5; 468 ais3624dq_status_reg_t status_reg; 469 ais3624dq_int1_cfg_t int1_cfg; 470 ais3624dq_int1_src_t int1_src; 471 ais3624dq_int1_ths_t int1_ths; 472 ais3624dq_int1_duration_t int1_duration; 473 ais3624dq_int2_cfg_t int2_cfg; 474 ais3624dq_int2_src_t int2_src; 475 ais3624dq_int2_ths_t int2_ths; 476 ais3624dq_int2_duration_t int2_duration; 477 bitwise_t bitwise; 478 uint8_t byte; 479 } ais3624dq_reg_t; 480 481 /** 482 * @} 483 * 484 */ 485 486 #ifndef __weak 487 #define __weak __attribute__((weak)) 488 #endif /* __weak */ 489 490 /* 491 * These are the basic platform dependent I/O routines to read 492 * and write device registers connected on a standard bus. 493 * The driver keeps offering a default implementation based on function 494 * pointers to read/write routines for backward compatibility. 495 * The __weak directive allows the final application to overwrite 496 * them with a custom implementation. 497 */ 498 499 int32_t ais3624dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 500 uint8_t *data, 501 uint16_t len); 502 int32_t ais3624dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 503 uint8_t *data, 504 uint16_t len); 505 506 float_t ais3624dq_from_fs6_to_mg(int16_t lsb); 507 float_t ais3624dq_from_fs12_to_mg(int16_t lsb); 508 float_t ais3624dq_from_fs24_to_mg(int16_t lsb); 509 510 int32_t ais3624dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 511 int32_t ais3624dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 512 513 int32_t ais3624dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 514 int32_t ais3624dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 515 516 int32_t ais3624dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 517 int32_t ais3624dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 518 519 typedef enum 520 { 521 AIS3624DQ_ODR_OFF = 0x00, 522 AIS3624DQ_ODR_Hz5 = 0x02, 523 AIS3624DQ_ODR_1Hz = 0x03, 524 AIS3624DQ_ODR_2Hz = 0x04, 525 AIS3624DQ_ODR_5Hz = 0x05, 526 AIS3624DQ_ODR_10Hz = 0x06, 527 AIS3624DQ_ODR_50Hz = 0x01, 528 AIS3624DQ_ODR_100Hz = 0x11, 529 AIS3624DQ_ODR_400Hz = 0x21, 530 AIS3624DQ_ODR_1kHz = 0x31, 531 } ais3624dq_dr_t; 532 int32_t ais3624dq_data_rate_set(const stmdev_ctx_t *ctx, 533 ais3624dq_dr_t val); 534 int32_t ais3624dq_data_rate_get(const stmdev_ctx_t *ctx, 535 ais3624dq_dr_t *val); 536 537 typedef enum 538 { 539 AIS3624DQ_NORMAL_MODE = 0, 540 AIS3624DQ_REF_MODE_ENABLE = 1, 541 } ais3624dq_hpm_t; 542 int32_t ais3624dq_reference_mode_set(const stmdev_ctx_t *ctx, 543 ais3624dq_hpm_t val); 544 int32_t ais3624dq_reference_mode_get(const stmdev_ctx_t *ctx, 545 ais3624dq_hpm_t *val); 546 547 typedef enum 548 { 549 AIS3624DQ_6g = 0, 550 AIS3624DQ_12g = 1, 551 AIS3624DQ_24g = 3, 552 } ais3624dq_fs_t; 553 int32_t ais3624dq_full_scale_set(const stmdev_ctx_t *ctx, 554 ais3624dq_fs_t val); 555 int32_t ais3624dq_full_scale_get(const stmdev_ctx_t *ctx, 556 ais3624dq_fs_t *val); 557 558 int32_t ais3624dq_block_data_update_set(const stmdev_ctx_t *ctx, 559 uint8_t val); 560 int32_t ais3624dq_block_data_update_get(const stmdev_ctx_t *ctx, 561 uint8_t *val); 562 563 int32_t ais3624dq_status_reg_get(const stmdev_ctx_t *ctx, 564 ais3624dq_status_reg_t *val); 565 566 int32_t ais3624dq_flag_data_ready_get(const stmdev_ctx_t *ctx, 567 uint8_t *val); 568 569 int32_t ais3624dq_acceleration_raw_get(const stmdev_ctx_t *ctx, 570 int16_t *val); 571 572 int32_t ais3624dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 573 574 int32_t ais3624dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 575 int32_t ais3624dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 576 577 typedef enum 578 { 579 AIS3624DQ_ST_DISABLE = 0, 580 AIS3624DQ_ST_POSITIVE = 1, 581 AIS3624DQ_ST_NEGATIVE = 5, 582 } ais3624dq_st_t; 583 int32_t ais3624dq_self_test_set(const stmdev_ctx_t *ctx, 584 ais3624dq_st_t val); 585 int32_t ais3624dq_self_test_get(const stmdev_ctx_t *ctx, 586 ais3624dq_st_t *val); 587 588 typedef enum 589 { 590 AIS3624DQ_LSB_AT_LOW_ADD = 0, 591 AIS3624DQ_MSB_AT_LOW_ADD = 1, 592 } ais3624dq_ble_t; 593 int32_t ais3624dq_data_format_set(const stmdev_ctx_t *ctx, 594 ais3624dq_ble_t val); 595 int32_t ais3624dq_data_format_get(const stmdev_ctx_t *ctx, 596 ais3624dq_ble_t *val); 597 598 typedef enum 599 { 600 AIS3624DQ_CUT_OFF_8Hz = 0, 601 AIS3624DQ_CUT_OFF_16Hz = 1, 602 AIS3624DQ_CUT_OFF_32Hz = 2, 603 AIS3624DQ_CUT_OFF_64Hz = 3, 604 } ais3624dq_hpcf_t; 605 int32_t ais3624dq_hp_bandwidth_set(const stmdev_ctx_t *ctx, 606 ais3624dq_hpcf_t val); 607 int32_t ais3624dq_hp_bandwidth_get(const stmdev_ctx_t *ctx, 608 ais3624dq_hpcf_t *val); 609 610 typedef enum 611 { 612 AIS3624DQ_HP_DISABLE = 0, 613 AIS3624DQ_HP_ON_OUT = 4, 614 AIS3624DQ_HP_ON_INT1 = 1, 615 AIS3624DQ_HP_ON_INT2 = 2, 616 AIS3624DQ_HP_ON_INT1_INT2 = 3, 617 AIS3624DQ_HP_ON_INT1_INT2_OUT = 7, 618 AIS3624DQ_HP_ON_INT2_OUT = 6, 619 AIS3624DQ_HP_ON_INT1_OUT = 5, 620 } ais3624dq_hpen_t; 621 int32_t ais3624dq_hp_path_set(const stmdev_ctx_t *ctx, 622 ais3624dq_hpen_t val); 623 int32_t ais3624dq_hp_path_get(const stmdev_ctx_t *ctx, 624 ais3624dq_hpen_t *val); 625 626 int32_t ais3624dq_hp_reset_get(const stmdev_ctx_t *ctx); 627 628 int32_t ais3624dq_hp_reference_value_set(const stmdev_ctx_t *ctx, 629 uint8_t val); 630 int32_t ais3624dq_hp_reference_value_get(const stmdev_ctx_t *ctx, 631 uint8_t *val); 632 633 typedef enum 634 { 635 AIS3624DQ_SPI_4_WIRE = 0, 636 AIS3624DQ_SPI_3_WIRE = 1, 637 } ais3624dq_sim_t; 638 int32_t ais3624dq_spi_mode_set(const stmdev_ctx_t *ctx, 639 ais3624dq_sim_t val); 640 int32_t ais3624dq_spi_mode_get(const stmdev_ctx_t *ctx, 641 ais3624dq_sim_t *val); 642 643 typedef enum 644 { 645 AIS3624DQ_PAD1_INT1_SRC = 0, 646 AIS3624DQ_PAD1_INT1_OR_INT2_SRC = 1, 647 AIS3624DQ_PAD1_DRDY = 2, 648 AIS3624DQ_PAD1_BOOT = 3, 649 } ais3624dq_i1_cfg_t; 650 int32_t ais3624dq_pin_int1_route_set(const stmdev_ctx_t *ctx, 651 ais3624dq_i1_cfg_t val); 652 int32_t ais3624dq_pin_int1_route_get(const stmdev_ctx_t *ctx, 653 ais3624dq_i1_cfg_t *val); 654 655 typedef enum 656 { 657 AIS3624DQ_INT1_PULSED = 0, 658 AIS3624DQ_INT1_LATCHED = 1, 659 } ais3624dq_lir1_t; 660 int32_t ais3624dq_int1_notification_set(const stmdev_ctx_t *ctx, 661 ais3624dq_lir1_t val); 662 int32_t ais3624dq_int1_notification_get(const stmdev_ctx_t *ctx, 663 ais3624dq_lir1_t *val); 664 665 typedef enum 666 { 667 AIS3624DQ_PAD2_INT2_SRC = 0, 668 AIS3624DQ_PAD2_INT1_OR_INT2_SRC = 1, 669 AIS3624DQ_PAD2_DRDY = 2, 670 AIS3624DQ_PAD2_BOOT = 3, 671 } ais3624dq_i2_cfg_t; 672 int32_t ais3624dq_pin_int2_route_set(const stmdev_ctx_t *ctx, 673 ais3624dq_i2_cfg_t val); 674 int32_t ais3624dq_pin_int2_route_get(const stmdev_ctx_t *ctx, 675 ais3624dq_i2_cfg_t *val); 676 677 typedef enum 678 { 679 AIS3624DQ_INT2_PULSED = 0, 680 AIS3624DQ_INT2_LATCHED = 1, 681 } ais3624dq_lir2_t; 682 int32_t ais3624dq_int2_notification_set(const stmdev_ctx_t *ctx, 683 ais3624dq_lir2_t val); 684 int32_t ais3624dq_int2_notification_get(const stmdev_ctx_t *ctx, 685 ais3624dq_lir2_t *val); 686 687 typedef enum 688 { 689 AIS3624DQ_PUSH_PULL = 0, 690 AIS3624DQ_OPEN_DRAIN = 1, 691 } ais3624dq_pp_od_t; 692 int32_t ais3624dq_pin_mode_set(const stmdev_ctx_t *ctx, 693 ais3624dq_pp_od_t val); 694 int32_t ais3624dq_pin_mode_get(const stmdev_ctx_t *ctx, 695 ais3624dq_pp_od_t *val); 696 697 typedef enum 698 { 699 AIS3624DQ_ACTIVE_HIGH = 0, 700 AIS3624DQ_ACTIVE_LOW = 1, 701 } ais3624dq_ihl_t; 702 int32_t ais3624dq_pin_polarity_set(const stmdev_ctx_t *ctx, 703 ais3624dq_ihl_t val); 704 int32_t ais3624dq_pin_polarity_get(const stmdev_ctx_t *ctx, 705 ais3624dq_ihl_t *val); 706 707 typedef struct 708 { 709 uint8_t int1_xlie : 1; 710 uint8_t int1_xhie : 1; 711 uint8_t int1_ylie : 1; 712 uint8_t int1_yhie : 1; 713 uint8_t int1_zlie : 1; 714 uint8_t int1_zhie : 1; 715 } ais3624dq_int1_on_th_conf_t; 716 int32_t ais3624dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, 717 ais3624dq_int1_on_th_conf_t val); 718 int32_t ais3624dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, 719 ais3624dq_int1_on_th_conf_t *val); 720 721 typedef enum 722 { 723 AIS3624DQ_INT1_ON_THRESHOLD_OR = 0, 724 AIS3624DQ_INT1_ON_THRESHOLD_AND = 1, 725 } ais3624dq_int1_aoi_t; 726 int32_t ais3624dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, 727 ais3624dq_int1_aoi_t val); 728 int32_t ais3624dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, 729 ais3624dq_int1_aoi_t *val); 730 731 int32_t ais3624dq_int1_src_get(const stmdev_ctx_t *ctx, 732 ais3624dq_int1_src_t *val); 733 734 int32_t ais3624dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 735 int32_t ais3624dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 736 737 int32_t ais3624dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 738 int32_t ais3624dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 739 740 typedef struct 741 { 742 uint8_t int2_xlie : 1; 743 uint8_t int2_xhie : 1; 744 uint8_t int2_ylie : 1; 745 uint8_t int2_yhie : 1; 746 uint8_t int2_zlie : 1; 747 uint8_t int2_zhie : 1; 748 } ais3624dq_int2_on_th_conf_t; 749 int32_t ais3624dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, 750 ais3624dq_int2_on_th_conf_t val); 751 int32_t ais3624dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, 752 ais3624dq_int2_on_th_conf_t *val); 753 754 typedef enum 755 { 756 AIS3624DQ_INT2_ON_THRESHOLD_OR = 0, 757 AIS3624DQ_INT2_ON_THRESHOLD_AND = 1, 758 } ais3624dq_int2_aoi_t; 759 int32_t ais3624dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, 760 ais3624dq_int2_aoi_t val); 761 int32_t ais3624dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, 762 ais3624dq_int2_aoi_t *val); 763 764 int32_t ais3624dq_int2_src_get(const stmdev_ctx_t *ctx, 765 ais3624dq_int2_src_t *val); 766 767 int32_t ais3624dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 768 int32_t ais3624dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 769 770 int32_t ais3624dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 771 int32_t ais3624dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 772 773 int32_t ais3624dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); 774 int32_t ais3624dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); 775 776 typedef enum 777 { 778 AIS3624DQ_6D_INT1_DISABLE = 0, 779 AIS3624DQ_6D_INT1_MOVEMENT = 1, 780 AIS3624DQ_6D_INT1_POSITION = 3, 781 } ais3624dq_int1_6d_t; 782 int32_t ais3624dq_int1_6d_mode_set(const stmdev_ctx_t *ctx, 783 ais3624dq_int1_6d_t val); 784 int32_t ais3624dq_int1_6d_mode_get(const stmdev_ctx_t *ctx, 785 ais3624dq_int1_6d_t *val); 786 787 int32_t ais3624dq_int1_6d_src_get(const stmdev_ctx_t *ctx, 788 ais3624dq_int1_src_t *val); 789 790 int32_t ais3624dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, 791 uint8_t val); 792 int32_t ais3624dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, 793 uint8_t *val); 794 795 typedef enum 796 { 797 AIS3624DQ_6D_INT2_DISABLE = 0, 798 AIS3624DQ_6D_INT2_MOVEMENT = 1, 799 AIS3624DQ_6D_INT2_POSITION = 3, 800 } ais3624dq_int2_6d_t; 801 int32_t ais3624dq_int2_6d_mode_set(const stmdev_ctx_t *ctx, 802 ais3624dq_int2_6d_t val); 803 int32_t ais3624dq_int2_6d_mode_get(const stmdev_ctx_t *ctx, 804 ais3624dq_int2_6d_t *val); 805 806 int32_t ais3624dq_int2_6d_src_get(const stmdev_ctx_t *ctx, 807 ais3624dq_int2_src_t *val); 808 809 int32_t ais3624dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, 810 uint8_t val); 811 int32_t ais3624dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, 812 uint8_t *val); 813 814 /** 815 *@} 816 * 817 */ 818 819 #ifdef __cplusplus 820 } 821 #endif 822 823 #endif /* AIS3624DQ_REGS_H */ 824 825 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 826
