1 /**
2 ******************************************************************************
3 * @file ais328dq_reg.c
4 * @author Sensors Software Solution Team
5 * @brief AIS328DQ driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ais328dq_reg.h"
21
22 /**
23 * @defgroup AIS328DQ
24 * @brief This file provides a set of functions needed to drive the
25 * ais328dq enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup AIS328DQ_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ais328dq_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ais328dq_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
ais328dq_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak ais328dq_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup AIS328DQ_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
ais328dq_from_fs2_to_mg(int16_t lsb)97 float_t ais328dq_from_fs2_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb * 0.98f / 16.0f);
100 }
101
ais328dq_from_fs4_to_mg(int16_t lsb)102 float_t ais328dq_from_fs4_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb * 1.95f / 16.0f);
105 }
106
ais328dq_from_fs8_to_mg(int16_t lsb)107 float_t ais328dq_from_fs8_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb * 3.91f / 16.0f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup AIS328DQ_Data_Generation
119 * @brief This section group all the functions concerning
120 * data generation
121 * @{
122 *
123 */
124
125 /**
126 * @brief X axis enable/disable.[set]
127 *
128 * @param ctx read / write interface definitions(ptr)
129 * @param val change the values of xen in reg CTRL_REG1
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
ais328dq_axis_x_data_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t ais328dq_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 ais328dq_ctrl_reg1_t ctrl_reg1;
136 int32_t ret;
137
138 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
139 (uint8_t *)&ctrl_reg1, 1);
140
141 if (ret == 0)
142 {
143 ctrl_reg1.xen = val;
144 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
145 (uint8_t *)&ctrl_reg1, 1);
146 }
147
148 return ret;
149 }
150
151 /**
152 * @brief X axis enable/disable.[get]
153 *
154 * @param ctx read / write interface definitions(ptr)
155 * @param val change the values of xen in reg CTRL_REG1
156 * @retval interface status (MANDATORY: return 0 -> no Error)
157 *
158 */
ais328dq_axis_x_data_get(const stmdev_ctx_t * ctx,uint8_t * val)159 int32_t ais328dq_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
160 {
161 ais328dq_ctrl_reg1_t ctrl_reg1;
162 int32_t ret;
163
164 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
165 (uint8_t *)&ctrl_reg1, 1);
166 *val = ctrl_reg1.xen;
167
168 return ret;
169 }
170
171 /**
172 * @brief Y axis enable/disable.[set]
173 *
174 * @param ctx read / write interface definitions(ptr)
175 * @param val change the values of yen in reg CTRL_REG1
176 * @retval interface status (MANDATORY: return 0 -> no Error)
177 *
178 */
ais328dq_axis_y_data_set(const stmdev_ctx_t * ctx,uint8_t val)179 int32_t ais328dq_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val)
180 {
181 ais328dq_ctrl_reg1_t ctrl_reg1;
182 int32_t ret;
183
184 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
185 (uint8_t *)&ctrl_reg1, 1);
186
187 if (ret == 0)
188 {
189 ctrl_reg1.yen = val;
190 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
191 (uint8_t *)&ctrl_reg1, 1);
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief Y axis enable/disable.[get]
199 *
200 * @param ctx read / write interface definitions(ptr)
201 * @param val change the values of yen in reg CTRL_REG1
202 * @retval interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
ais328dq_axis_y_data_get(const stmdev_ctx_t * ctx,uint8_t * val)205 int32_t ais328dq_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
206 {
207 ais328dq_ctrl_reg1_t ctrl_reg1;
208 int32_t ret;
209
210 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
211 (uint8_t *)&ctrl_reg1, 1);
212 *val = ctrl_reg1.yen;
213
214 return ret;
215 }
216
217 /**
218 * @brief Z axis enable/disable.[set]
219 *
220 * @param ctx read / write interface definitions(ptr)
221 * @param val change the values of zen in reg CTRL_REG1
222 * @retval interface status (MANDATORY: return 0 -> no Error)
223 *
224 */
ais328dq_axis_z_data_set(const stmdev_ctx_t * ctx,uint8_t val)225 int32_t ais328dq_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val)
226 {
227 ais328dq_ctrl_reg1_t ctrl_reg1;
228 int32_t ret;
229
230 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
231 (uint8_t *)&ctrl_reg1, 1);
232
233 if (ret == 0)
234 {
235 ctrl_reg1.zen = val;
236 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
237 (uint8_t *)&ctrl_reg1, 1);
238 }
239
240 return ret;
241 }
242
243 /**
244 * @brief Z axis enable/disable.[get]
245 *
246 * @param ctx read / write interface definitions(ptr)
247 * @param val change the values of zen in reg CTRL_REG1
248 * @retval interface status (MANDATORY: return 0 -> no Error)
249 *
250 */
ais328dq_axis_z_data_get(const stmdev_ctx_t * ctx,uint8_t * val)251 int32_t ais328dq_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
252 {
253 ais328dq_ctrl_reg1_t ctrl_reg1;
254 int32_t ret;
255
256 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
257 (uint8_t *)&ctrl_reg1, 1);
258 *val = ctrl_reg1.zen;
259
260 return ret;
261 }
262
263 /**
264 * @brief Accelerometer data rate selection.[set]
265 *
266 * @param ctx read / write interface definitions(ptr)
267 * @param val change the values of dr in reg CTRL_REG1
268 * @retval interface status (MANDATORY: return 0 -> no Error)
269 *
270 */
ais328dq_data_rate_set(const stmdev_ctx_t * ctx,ais328dq_dr_t val)271 int32_t ais328dq_data_rate_set(const stmdev_ctx_t *ctx, ais328dq_dr_t val)
272 {
273 ais328dq_ctrl_reg1_t ctrl_reg1;
274 int32_t ret;
275
276 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
277 (uint8_t *)&ctrl_reg1, 1);
278
279 if (ret == 0)
280 {
281 ctrl_reg1.pm = (uint8_t)val & 0x07U;
282 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
283 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG1,
284 (uint8_t *)&ctrl_reg1, 1);
285 }
286
287 return ret;
288 }
289
290 /**
291 * @brief Accelerometer data rate selection.[get]
292 *
293 * @param ctx read / write interface definitions(ptr)
294 * @param val Get the values of dr in reg CTRL_REG1
295 * @retval interface status (MANDATORY: return 0 -> no Error)
296 *
297 */
ais328dq_data_rate_get(const stmdev_ctx_t * ctx,ais328dq_dr_t * val)298 int32_t ais328dq_data_rate_get(const stmdev_ctx_t *ctx, ais328dq_dr_t *val)
299 {
300 ais328dq_ctrl_reg1_t ctrl_reg1;
301 int32_t ret;
302
303 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG1,
304 (uint8_t *)&ctrl_reg1, 1);
305
306 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
307 {
308 case AIS328DQ_ODR_OFF:
309 *val = AIS328DQ_ODR_OFF;
310 break;
311
312 case AIS328DQ_ODR_Hz5:
313 *val = AIS328DQ_ODR_Hz5;
314 break;
315
316 case AIS328DQ_ODR_1Hz:
317 *val = AIS328DQ_ODR_1Hz;
318 break;
319
320 case AIS328DQ_ODR_2Hz:
321 *val = AIS328DQ_ODR_2Hz;
322 break;
323
324 case AIS328DQ_ODR_5Hz:
325 *val = AIS328DQ_ODR_5Hz;
326 break;
327
328 case AIS328DQ_ODR_10Hz:
329 *val = AIS328DQ_ODR_10Hz;
330 break;
331
332 case AIS328DQ_ODR_50Hz:
333 *val = AIS328DQ_ODR_50Hz;
334 break;
335
336 case AIS328DQ_ODR_100Hz:
337 *val = AIS328DQ_ODR_100Hz;
338 break;
339
340 case AIS328DQ_ODR_400Hz:
341 *val = AIS328DQ_ODR_400Hz;
342 break;
343
344 case AIS328DQ_ODR_1kHz:
345 *val = AIS328DQ_ODR_1kHz;
346 break;
347
348 default:
349 *val = AIS328DQ_ODR_OFF;
350 break;
351 }
352
353 return ret;
354 }
355
356 /**
357 * @brief High pass filter mode selection.[set]
358 *
359 * @param ctx read / write interface definitions(ptr)
360 * @param val change the values of hpm in reg CTRL_REG2
361 * @retval interface status (MANDATORY: return 0 -> no Error)
362 *
363 */
ais328dq_reference_mode_set(const stmdev_ctx_t * ctx,ais328dq_hpm_t val)364 int32_t ais328dq_reference_mode_set(const stmdev_ctx_t *ctx,
365 ais328dq_hpm_t val)
366 {
367 ais328dq_ctrl_reg2_t ctrl_reg2;
368 int32_t ret;
369
370 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
371 (uint8_t *)&ctrl_reg2, 1);
372
373 if (ret == 0)
374 {
375 ctrl_reg2.hpm = (uint8_t)val;
376 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
377 (uint8_t *)&ctrl_reg2, 1);
378 }
379
380 return ret;
381 }
382
383 /**
384 * @brief High pass filter mode selection.[get]
385 *
386 * @param ctx read / write interface definitions(ptr)
387 * @param val Get the values of hpm in reg CTRL_REG2
388 * @retval interface status (MANDATORY: return 0 -> no Error)
389 *
390 */
ais328dq_reference_mode_get(const stmdev_ctx_t * ctx,ais328dq_hpm_t * val)391 int32_t ais328dq_reference_mode_get(const stmdev_ctx_t *ctx,
392 ais328dq_hpm_t *val)
393 {
394 ais328dq_ctrl_reg2_t ctrl_reg2;
395 int32_t ret;
396
397 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
398 (uint8_t *)&ctrl_reg2, 1);
399
400 switch (ctrl_reg2.hpm)
401 {
402 case AIS328DQ_NORMAL_MODE:
403 *val = AIS328DQ_NORMAL_MODE;
404 break;
405
406 case AIS328DQ_REF_MODE_ENABLE:
407 *val = AIS328DQ_REF_MODE_ENABLE;
408 break;
409
410 default:
411 *val = AIS328DQ_NORMAL_MODE;
412 break;
413 }
414
415 return ret;
416 }
417
418 /**
419 * @brief Accelerometer full-scale selection.[set]
420 *
421 * @param ctx read / write interface definitions(ptr)
422 * @param val change the values of fs in reg CTRL_REG4
423 * @retval interface status (MANDATORY: return 0 -> no Error)
424 *
425 */
ais328dq_full_scale_set(const stmdev_ctx_t * ctx,ais328dq_fs_t val)426 int32_t ais328dq_full_scale_set(const stmdev_ctx_t *ctx, ais328dq_fs_t val)
427 {
428 ais328dq_ctrl_reg4_t ctrl_reg4;
429 int32_t ret;
430
431 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
432 (uint8_t *)&ctrl_reg4, 1);
433
434 if (ret == 0)
435 {
436 ctrl_reg4.fs = (uint8_t)val;
437 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
438 (uint8_t *)&ctrl_reg4, 1);
439 }
440
441 return ret;
442 }
443
444 /**
445 * @brief Accelerometer full-scale selection.[get]
446 *
447 * @param ctx read / write interface definitions(ptr)
448 * @param val Get the values of fs in reg CTRL_REG4
449 * @retval interface status (MANDATORY: return 0 -> no Error)
450 *
451 */
ais328dq_full_scale_get(const stmdev_ctx_t * ctx,ais328dq_fs_t * val)452 int32_t ais328dq_full_scale_get(const stmdev_ctx_t *ctx, ais328dq_fs_t *val)
453 {
454 ais328dq_ctrl_reg4_t ctrl_reg4;
455 int32_t ret;
456
457 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
458 (uint8_t *)&ctrl_reg4, 1);
459
460 switch (ctrl_reg4.fs)
461 {
462 case AIS328DQ_2g:
463 *val = AIS328DQ_2g;
464 break;
465
466 case AIS328DQ_4g:
467 *val = AIS328DQ_4g;
468 break;
469
470 case AIS328DQ_8g:
471 *val = AIS328DQ_8g;
472 break;
473
474 default:
475 *val = AIS328DQ_2g;
476 break;
477 }
478
479 return ret;
480 }
481
482 /**
483 * @brief Block data update.[set]
484 *
485 * @param ctx read / write interface definitions(ptr)
486 * @param val change the values of bdu in reg CTRL_REG4
487 * @retval interface status (MANDATORY: return 0 -> no Error)
488 *
489 */
ais328dq_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)490 int32_t ais328dq_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
491 {
492 ais328dq_ctrl_reg4_t ctrl_reg4;
493 int32_t ret;
494
495 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
496 (uint8_t *)&ctrl_reg4, 1);
497
498 if (ret == 0)
499 {
500 ctrl_reg4.bdu = val;
501 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
502 (uint8_t *)&ctrl_reg4, 1);
503 }
504
505 return ret;
506 }
507
508 /**
509 * @brief Block data update.[get]
510 *
511 * @param ctx read / write interface definitions(ptr)
512 * @param val change the values of bdu in reg CTRL_REG4
513 * @retval interface status (MANDATORY: return 0 -> no Error)
514 *
515 */
ais328dq_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)516 int32_t ais328dq_block_data_update_get(const stmdev_ctx_t *ctx,
517 uint8_t *val)
518 {
519 ais328dq_ctrl_reg4_t ctrl_reg4;
520 int32_t ret;
521
522 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
523 (uint8_t *)&ctrl_reg4, 1);
524 *val = ctrl_reg4.bdu;
525
526 return ret;
527 }
528
529 /**
530 * @brief The STATUS_REG register is read by the interface.[get]
531 *
532 * @param ctx read / write interface definitions(ptr)
533 * @param val registers STATUS_REG
534 * @retval interface status (MANDATORY: return 0 -> no Error)
535 *
536 */
ais328dq_status_reg_get(const stmdev_ctx_t * ctx,ais328dq_status_reg_t * val)537 int32_t ais328dq_status_reg_get(const stmdev_ctx_t *ctx,
538 ais328dq_status_reg_t *val)
539 {
540 int32_t ret;
541
542 ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG, (uint8_t *) val, 1);
543
544 return ret;
545 }
546
547 /**
548 * @brief Accelerometer new data available.[get]
549 *
550 * @param ctx read / write interface definitions(ptr)
551 * @param val change the values of zyxda in reg STATUS_REG
552 * @retval interface status (MANDATORY: return 0 -> no Error)
553 *
554 */
ais328dq_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)555 int32_t ais328dq_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
556 {
557 ais328dq_status_reg_t status_reg;
558 int32_t ret;
559
560 ret = ais328dq_read_reg(ctx, AIS328DQ_STATUS_REG,
561 (uint8_t *)&status_reg, 1);
562 *val = status_reg.zyxda;
563
564 return ret;
565 }
566
567 /**
568 * @}
569 *
570 */
571
572 /**
573 * @defgroup AIS328DQ_Data_Output
574 * @brief This section groups all the data output functions.
575 * @{
576 *
577 */
578
579 /**
580 * @brief Linear acceleration output register. The value is expressed
581 * as a 16-bit word in two’s complement.[get]
582 *
583 * @param ctx read / write interface definitions(ptr)
584 * @param buff buffer that stores data read
585 * @retval interface status (MANDATORY: return 0 -> no Error)
586 *
587 */
ais328dq_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)588 int32_t ais328dq_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
589 {
590 uint8_t buff[6];
591 int32_t ret;
592
593 ret = ais328dq_read_reg(ctx, AIS328DQ_OUT_X_L, buff, 6);
594 val[0] = (int16_t)buff[1];
595 val[0] = (val[0] * 256) + (int16_t)buff[0];
596 val[1] = (int16_t)buff[3];
597 val[1] = (val[1] * 256) + (int16_t)buff[2];
598 val[2] = (int16_t)buff[5];
599 val[2] = (val[2] * 256) + (int16_t)buff[4];
600
601 return ret;
602 }
603
604 /**
605 * @}
606 *
607 */
608
609 /**
610 * @defgroup AIS328DQ_Common
611 * @brief This section groups common useful functions.
612 * @{
613 *
614 */
615
616 /**
617 * @brief Device Who am I.[get]
618 *
619 * @param ctx read / write interface definitions(ptr)
620 * @param buff buffer that stores data read
621 * @retval interface status (MANDATORY: return 0 -> no Error)
622 *
623 */
ais328dq_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)624 int32_t ais328dq_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
625 {
626 int32_t ret;
627
628 ret = ais328dq_read_reg(ctx, AIS328DQ_WHO_AM_I, buff, 1);
629
630 return ret;
631 }
632
633 /**
634 * @brief Reboot memory content. Reload the calibration parameters.[set]
635 *
636 * @param ctx read / write interface definitions(ptr)
637 * @param val change the values of boot in reg CTRL_REG2
638 * @retval interface status (MANDATORY: return 0 -> no Error)
639 *
640 */
ais328dq_boot_set(const stmdev_ctx_t * ctx,uint8_t val)641 int32_t ais328dq_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
642 {
643 ais328dq_ctrl_reg2_t ctrl_reg2;
644 int32_t ret;
645
646 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
647 (uint8_t *)&ctrl_reg2, 1);
648
649 if (ret == 0)
650 {
651 ctrl_reg2.boot = val;
652 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
653 (uint8_t *)&ctrl_reg2, 1);
654 }
655
656 return ret;
657 }
658
659 /**
660 * @brief Reboot memory content. Reload the calibration parameters.[get]
661 *
662 * @param ctx read / write interface definitions(ptr)
663 * @param val change the values of boot in reg CTRL_REG2
664 * @retval interface status (MANDATORY: return 0 -> no Error)
665 *
666 */
ais328dq_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)667 int32_t ais328dq_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
668 {
669 ais328dq_ctrl_reg2_t ctrl_reg2;
670 int32_t ret;
671
672 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
673 (uint8_t *)&ctrl_reg2, 1);
674 *val = ctrl_reg2.boot;
675
676 return ret;
677 }
678
679 /**
680 * @brief Linear acceleration sensor self-test enable.[set]
681 *
682 * @param ctx read / write interface definitions(ptr)
683 * @param val change the values of st in reg CTRL_REG4
684 * @retval interface status (MANDATORY: return 0 -> no Error)
685 *
686 */
ais328dq_self_test_set(const stmdev_ctx_t * ctx,ais328dq_st_t val)687 int32_t ais328dq_self_test_set(const stmdev_ctx_t *ctx, ais328dq_st_t val)
688 {
689 ais328dq_ctrl_reg4_t ctrl_reg4;
690 int32_t ret;
691
692 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
693 (uint8_t *)&ctrl_reg4, 1);
694
695 if (ret == 0)
696 {
697 ctrl_reg4.st = (uint8_t)val;
698 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
699 (uint8_t *)&ctrl_reg4, 1);
700 }
701
702 return ret;
703 }
704
705 /**
706 * @brief Linear acceleration sensor self-test enable.[get]
707 *
708 * @param ctx read / write interface definitions(ptr)
709 * @param val Get the values of st in reg CTRL_REG4
710 * @retval interface status (MANDATORY: return 0 -> no Error)
711 *
712 */
ais328dq_self_test_get(const stmdev_ctx_t * ctx,ais328dq_st_t * val)713 int32_t ais328dq_self_test_get(const stmdev_ctx_t *ctx, ais328dq_st_t *val)
714 {
715 ais328dq_ctrl_reg4_t ctrl_reg4;
716 int32_t ret;
717
718 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
719 (uint8_t *)&ctrl_reg4, 1);
720
721 switch (ctrl_reg4.st)
722 {
723 case AIS328DQ_ST_DISABLE:
724 *val = AIS328DQ_ST_DISABLE;
725 break;
726
727 case AIS328DQ_ST_POSITIVE:
728 *val = AIS328DQ_ST_POSITIVE;
729 break;
730
731 case AIS328DQ_ST_NEGATIVE:
732 *val = AIS328DQ_ST_NEGATIVE;
733 break;
734
735 default:
736 *val = AIS328DQ_ST_DISABLE;
737 break;
738 }
739
740 return ret;
741 }
742
743 /**
744 * @brief Big/Little Endian Data selection.[set]
745 *
746 * @param ctx read / write interface definitions(ptr)
747 * @param val change the values of ble in reg CTRL_REG4
748 * @retval interface status (MANDATORY: return 0 -> no Error)
749 *
750 */
ais328dq_data_format_set(const stmdev_ctx_t * ctx,ais328dq_ble_t val)751 int32_t ais328dq_data_format_set(const stmdev_ctx_t *ctx,
752 ais328dq_ble_t val)
753 {
754 ais328dq_ctrl_reg4_t ctrl_reg4;
755 int32_t ret;
756
757 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
758 (uint8_t *)&ctrl_reg4, 1);
759
760 if (ret == 0)
761 {
762 ctrl_reg4.ble = (uint8_t)val;
763 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
764 (uint8_t *)&ctrl_reg4, 1);
765 }
766
767 return ret;
768 }
769
770 /**
771 * @brief Big/Little Endian Data selection.[get]
772 *
773 * @param ctx read / write interface definitions(ptr)
774 * @param val Get the values of ble in reg CTRL_REG4
775 * @retval interface status (MANDATORY: return 0 -> no Error)
776 *
777 */
ais328dq_data_format_get(const stmdev_ctx_t * ctx,ais328dq_ble_t * val)778 int32_t ais328dq_data_format_get(const stmdev_ctx_t *ctx,
779 ais328dq_ble_t *val)
780 {
781 ais328dq_ctrl_reg4_t ctrl_reg4;
782 int32_t ret;
783
784 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
785 (uint8_t *)&ctrl_reg4, 1);
786
787 switch (ctrl_reg4.ble)
788 {
789 case AIS328DQ_LSB_AT_LOW_ADD:
790 *val = AIS328DQ_LSB_AT_LOW_ADD;
791 break;
792
793 case AIS328DQ_MSB_AT_LOW_ADD:
794 *val = AIS328DQ_MSB_AT_LOW_ADD;
795 break;
796
797 default:
798 *val = AIS328DQ_LSB_AT_LOW_ADD;
799 break;
800 }
801
802 return ret;
803 }
804
805 /**
806 * @}
807 *
808 */
809
810 /**
811 * @defgroup AIS328DQ_Filters
812 * @brief This section group all the functions concerning the
813 * filters configuration.
814 * @{
815 *
816 */
817
818 /**
819 * @brief High pass filter cut-off frequency configuration.[set]
820 *
821 * @param ctx read / write interface definitions(ptr)
822 * @param val change the values of hpcf in reg CTRL_REG2
823 * @retval interface status (MANDATORY: return 0 -> no Error)
824 *
825 */
ais328dq_hp_bandwidth_set(const stmdev_ctx_t * ctx,ais328dq_hpcf_t val)826 int32_t ais328dq_hp_bandwidth_set(const stmdev_ctx_t *ctx,
827 ais328dq_hpcf_t val)
828 {
829 ais328dq_ctrl_reg2_t ctrl_reg2;
830 int32_t ret;
831
832 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
833 (uint8_t *)&ctrl_reg2, 1);
834
835 if (ret == 0)
836 {
837 ctrl_reg2.hpcf = (uint8_t)val;
838 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
839 (uint8_t *)&ctrl_reg2, 1);
840 }
841
842 return ret;
843 }
844
845 /**
846 * @brief High pass filter cut-off frequency configuration.[get]
847 *
848 * @param ctx read / write interface definitions(ptr)
849 * @param val Get the values of hpcf in reg CTRL_REG2
850 * @retval interface status (MANDATORY: return 0 -> no Error)
851 *
852 */
ais328dq_hp_bandwidth_get(const stmdev_ctx_t * ctx,ais328dq_hpcf_t * val)853 int32_t ais328dq_hp_bandwidth_get(const stmdev_ctx_t *ctx,
854 ais328dq_hpcf_t *val)
855 {
856 ais328dq_ctrl_reg2_t ctrl_reg2;
857 int32_t ret;
858
859 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
860 (uint8_t *)&ctrl_reg2, 1);
861
862 switch (ctrl_reg2.hpcf)
863 {
864 case AIS328DQ_CUT_OFF_8Hz:
865 *val = AIS328DQ_CUT_OFF_8Hz;
866 break;
867
868 case AIS328DQ_CUT_OFF_16Hz:
869 *val = AIS328DQ_CUT_OFF_16Hz;
870 break;
871
872 case AIS328DQ_CUT_OFF_32Hz:
873 *val = AIS328DQ_CUT_OFF_32Hz;
874 break;
875
876 case AIS328DQ_CUT_OFF_64Hz:
877 *val = AIS328DQ_CUT_OFF_64Hz;
878 break;
879
880 default:
881 *val = AIS328DQ_CUT_OFF_8Hz;
882 break;
883 }
884
885 return ret;
886 }
887
888 /**
889 * @brief Select High Pass filter path.[set]
890 *
891 * @param ctx read / write interface definitions(ptr)
892 * @param val change the values of hpen in reg CTRL_REG2
893 * @retval interface status (MANDATORY: return 0 -> no Error)
894 *
895 */
ais328dq_hp_path_set(const stmdev_ctx_t * ctx,ais328dq_hpen_t val)896 int32_t ais328dq_hp_path_set(const stmdev_ctx_t *ctx, ais328dq_hpen_t val)
897 {
898 ais328dq_ctrl_reg2_t ctrl_reg2;
899 int32_t ret;
900
901 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
902 (uint8_t *)&ctrl_reg2, 1);
903
904 if (ret == 0)
905 {
906 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
907 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
908 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG2,
909 (uint8_t *)&ctrl_reg2, 1);
910 }
911
912 return ret;
913 }
914
915 /**
916 * @brief Select High Pass filter path.[get]
917 *
918 * @param ctx read / write interface definitions(ptr)
919 * @param val Get the values of hpen in reg CTRL_REG2
920 * @retval interface status (MANDATORY: return 0 -> no Error)
921 *
922 */
ais328dq_hp_path_get(const stmdev_ctx_t * ctx,ais328dq_hpen_t * val)923 int32_t ais328dq_hp_path_get(const stmdev_ctx_t *ctx, ais328dq_hpen_t *val)
924 {
925 ais328dq_ctrl_reg2_t ctrl_reg2;
926 int32_t ret;
927
928 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG2,
929 (uint8_t *)&ctrl_reg2, 1);
930
931 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
932 {
933 case AIS328DQ_HP_DISABLE:
934 *val = AIS328DQ_HP_DISABLE;
935 break;
936
937 case AIS328DQ_HP_ON_OUT:
938 *val = AIS328DQ_HP_ON_OUT;
939 break;
940
941 case AIS328DQ_HP_ON_INT1:
942 *val = AIS328DQ_HP_ON_INT1;
943 break;
944
945 case AIS328DQ_HP_ON_INT2:
946 *val = AIS328DQ_HP_ON_INT2;
947 break;
948
949 case AIS328DQ_HP_ON_INT1_INT2:
950 *val = AIS328DQ_HP_ON_INT1_INT2;
951 break;
952
953 case AIS328DQ_HP_ON_INT1_INT2_OUT:
954 *val = AIS328DQ_HP_ON_INT1_INT2_OUT;
955 break;
956
957 case AIS328DQ_HP_ON_INT2_OUT:
958 *val = AIS328DQ_HP_ON_INT2_OUT;
959 break;
960
961 case AIS328DQ_HP_ON_INT1_OUT:
962 *val = AIS328DQ_HP_ON_INT1_OUT;
963 break;
964
965 default:
966 *val = AIS328DQ_HP_DISABLE;
967 break;
968 }
969
970 return ret;
971 }
972
973 /**
974 * @brief Reading at this address zeroes instantaneously
975 * the content of the internal high pass-filter.
976 * If the high pass filter is enabled all three axes
977 * are instantaneously set to 0g. This allows to
978 * overcome the settling time of the high pass
979 * filter.[get]
980 *
981 * @param ctx read / write interface definitions(ptr)
982 * @retval interface status (MANDATORY: return 0 -> no Error)
983 *
984 */
ais328dq_hp_reset_get(stmdev_ctx_t * ctx)985 int32_t ais328dq_hp_reset_get(stmdev_ctx_t *ctx)
986 {
987 uint8_t dummy;
988 int32_t ret;
989
990 ret = ais328dq_read_reg(ctx, AIS328DQ_HP_FILTER_RESET,
991 (uint8_t *)&dummy, 1);
992
993 return ret;
994 }
995
996 /**
997 * @brief Reference value for high-pass filter.[set]
998 *
999 * @param ctx read / write interface definitions(ptr)
1000 * @param val change the values of ref in reg REFERENCE
1001 * @retval interface status (MANDATORY: return 0 -> no Error)
1002 *
1003 */
ais328dq_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)1004 int32_t ais328dq_hp_reference_value_set(const stmdev_ctx_t *ctx,
1005 uint8_t val)
1006 {
1007 int32_t ret;
1008
1009 ret = ais328dq_write_reg(ctx, AIS328DQ_REFERENCE, (uint8_t *)&val, 1);
1010
1011 return ret;
1012 }
1013
1014 /**
1015 * @brief Reference value for high-pass filter.[get]
1016 *
1017 * @param ctx read / write interface definitions(ptr)
1018 * @param val change the values of ref in reg REFERENCE
1019 * @retval interface status (MANDATORY: return 0 -> no Error)
1020 *
1021 */
ais328dq_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)1022 int32_t ais328dq_hp_reference_value_get(const stmdev_ctx_t *ctx,
1023 uint8_t *val)
1024 {
1025 int32_t ret;
1026
1027 ret = ais328dq_read_reg(ctx, AIS328DQ_REFERENCE, val, 1);
1028
1029 return ret;
1030 }
1031
1032 /**
1033 * @}
1034 *
1035 */
1036
1037 /**
1038 * @defgroup AIS328DQ_Serial_Interface
1039 * @brief This section groups all the functions concerning serial
1040 * interface management.
1041 * @{
1042 *
1043 */
1044
1045 /**
1046 * @brief SPI 3- or 4-wire interface.[set]
1047 *
1048 * @param ctx read / write interface definitions(ptr)
1049 * @param val change the values of sim in reg CTRL_REG4
1050 * @retval interface status (MANDATORY: return 0 -> no Error)
1051 *
1052 */
ais328dq_spi_mode_set(const stmdev_ctx_t * ctx,ais328dq_sim_t val)1053 int32_t ais328dq_spi_mode_set(const stmdev_ctx_t *ctx, ais328dq_sim_t val)
1054 {
1055 ais328dq_ctrl_reg4_t ctrl_reg4;
1056 int32_t ret;
1057
1058 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
1059 (uint8_t *)&ctrl_reg4, 1);
1060
1061 if (ret == 0)
1062 {
1063 ctrl_reg4.sim = (uint8_t)val;
1064 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG4,
1065 (uint8_t *)&ctrl_reg4, 1);
1066 }
1067
1068 return ret;
1069 }
1070
1071 /**
1072 * @brief SPI 3- or 4-wire interface.[get]
1073 *
1074 * @param ctx read / write interface definitions(ptr)
1075 * @param val Get the values of sim in reg CTRL_REG4
1076 * @retval interface status (MANDATORY: return 0 -> no Error)
1077 *
1078 */
ais328dq_spi_mode_get(const stmdev_ctx_t * ctx,ais328dq_sim_t * val)1079 int32_t ais328dq_spi_mode_get(const stmdev_ctx_t *ctx, ais328dq_sim_t *val)
1080 {
1081 ais328dq_ctrl_reg4_t ctrl_reg4;
1082 int32_t ret;
1083
1084 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG4,
1085 (uint8_t *)&ctrl_reg4, 1);
1086
1087 switch (ctrl_reg4.sim)
1088 {
1089 case AIS328DQ_SPI_4_WIRE:
1090 *val = AIS328DQ_SPI_4_WIRE;
1091 break;
1092
1093 case AIS328DQ_SPI_3_WIRE:
1094 *val = AIS328DQ_SPI_3_WIRE;
1095 break;
1096
1097 default:
1098 *val = AIS328DQ_SPI_4_WIRE;
1099 break;
1100 }
1101
1102 return ret;
1103 }
1104
1105 /**
1106 * @}
1107 *
1108 */
1109
1110 /**
1111 * @defgroup AIS328DQ_Interrupt_Pins
1112 * @brief This section groups all the functions that manage
1113 * interrupt pins.
1114 * @{
1115 *
1116 */
1117
1118 /**
1119 * @brief Data signal on INT 1 pad control bits.[set]
1120 *
1121 * @param ctx read / write interface definitions(ptr)
1122 * @param val change the values of i1_cfg in reg CTRL_REG3
1123 * @retval interface status (MANDATORY: return 0 -> no Error)
1124 *
1125 */
ais328dq_pin_int1_route_set(const stmdev_ctx_t * ctx,ais328dq_i1_cfg_t val)1126 int32_t ais328dq_pin_int1_route_set(const stmdev_ctx_t *ctx,
1127 ais328dq_i1_cfg_t val)
1128 {
1129 ais328dq_ctrl_reg3_t ctrl_reg3;
1130 int32_t ret;
1131
1132 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1133 (uint8_t *)&ctrl_reg3, 1);
1134
1135 if (ret == 0)
1136 {
1137 ctrl_reg3.i1_cfg = (uint8_t)val;
1138 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1139 (uint8_t *)&ctrl_reg3, 1);
1140 }
1141
1142 return ret;
1143 }
1144
1145 /**
1146 * @brief Data signal on INT 1 pad control bits.[get]
1147 *
1148 * @param ctx read / write interface definitions(ptr)
1149 * @param val Get the values of i1_cfg in reg CTRL_REG3
1150 * @retval interface status (MANDATORY: return 0 -> no Error)
1151 *
1152 */
ais328dq_pin_int1_route_get(const stmdev_ctx_t * ctx,ais328dq_i1_cfg_t * val)1153 int32_t ais328dq_pin_int1_route_get(const stmdev_ctx_t *ctx,
1154 ais328dq_i1_cfg_t *val)
1155 {
1156 ais328dq_ctrl_reg3_t ctrl_reg3;
1157 int32_t ret;
1158
1159 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1160 (uint8_t *)&ctrl_reg3, 1);
1161
1162 switch (ctrl_reg3.i1_cfg)
1163 {
1164 case AIS328DQ_PAD1_INT1_SRC:
1165 *val = AIS328DQ_PAD1_INT1_SRC;
1166 break;
1167
1168 case AIS328DQ_PAD1_INT1_OR_INT2_SRC:
1169 *val = AIS328DQ_PAD1_INT1_OR_INT2_SRC;
1170 break;
1171
1172 case AIS328DQ_PAD1_DRDY:
1173 *val = AIS328DQ_PAD1_DRDY;
1174 break;
1175
1176 case AIS328DQ_PAD1_BOOT:
1177 *val = AIS328DQ_PAD1_BOOT;
1178 break;
1179
1180 default:
1181 *val = AIS328DQ_PAD1_INT1_SRC;
1182 break;
1183 }
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1190 * register cleared by reading INT1_SRC register.[set]
1191 *
1192 * @param ctx read / write interface definitions(ptr)
1193 * @param val change the values of lir1 in reg CTRL_REG3
1194 * @retval interface status (MANDATORY: return 0 -> no Error)
1195 *
1196 */
ais328dq_int1_notification_set(const stmdev_ctx_t * ctx,ais328dq_lir1_t val)1197 int32_t ais328dq_int1_notification_set(const stmdev_ctx_t *ctx,
1198 ais328dq_lir1_t val)
1199 {
1200 ais328dq_ctrl_reg3_t ctrl_reg3;
1201 int32_t ret;
1202
1203 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1204 (uint8_t *)&ctrl_reg3, 1);
1205
1206 if (ret == 0)
1207 {
1208 ctrl_reg3.lir1 = (uint8_t)val;
1209 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1210 (uint8_t *)&ctrl_reg3, 1);
1211 }
1212
1213 return ret;
1214 }
1215
1216 /**
1217 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1218 * register cleared by reading INT1_SRC register.[get]
1219 *
1220 * @param ctx read / write interface definitions(ptr)
1221 * @param val Get the values of lir1 in reg CTRL_REG3
1222 * @retval interface status (MANDATORY: return 0 -> no Error)
1223 *
1224 */
ais328dq_int1_notification_get(const stmdev_ctx_t * ctx,ais328dq_lir1_t * val)1225 int32_t ais328dq_int1_notification_get(const stmdev_ctx_t *ctx,
1226 ais328dq_lir1_t *val)
1227 {
1228 ais328dq_ctrl_reg3_t ctrl_reg3;
1229 int32_t ret;
1230
1231 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1232 (uint8_t *)&ctrl_reg3, 1);
1233
1234 switch (ctrl_reg3.lir1)
1235 {
1236 case AIS328DQ_INT1_PULSED:
1237 *val = AIS328DQ_INT1_PULSED;
1238 break;
1239
1240 case AIS328DQ_INT1_LATCHED:
1241 *val = AIS328DQ_INT1_LATCHED;
1242 break;
1243
1244 default:
1245 *val = AIS328DQ_INT1_PULSED;
1246 break;
1247 }
1248
1249 return ret;
1250 }
1251
1252 /**
1253 * @brief Data signal on INT 2 pad control bits.[set]
1254 *
1255 * @param ctx read / write interface definitions(ptr)
1256 * @param val change the values of i2_cfg in reg CTRL_REG3
1257 * @retval interface status (MANDATORY: return 0 -> no Error)
1258 *
1259 */
ais328dq_pin_int2_route_set(const stmdev_ctx_t * ctx,ais328dq_i2_cfg_t val)1260 int32_t ais328dq_pin_int2_route_set(const stmdev_ctx_t *ctx,
1261 ais328dq_i2_cfg_t val)
1262 {
1263 ais328dq_ctrl_reg3_t ctrl_reg3;
1264 int32_t ret;
1265
1266 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1267 (uint8_t *)&ctrl_reg3, 1);
1268
1269 if (ret == 0)
1270 {
1271 ctrl_reg3.i2_cfg = (uint8_t)val;
1272 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1273 (uint8_t *)&ctrl_reg3, 1);
1274 }
1275
1276 return ret;
1277 }
1278
1279 /**
1280 * @brief Data signal on INT 2 pad control bits.[get]
1281 *
1282 * @param ctx read / write interface definitions(ptr)
1283 * @param val Get the values of i2_cfg in reg CTRL_REG3
1284 * @retval interface status (MANDATORY: return 0 -> no Error)
1285 *
1286 */
ais328dq_pin_int2_route_get(const stmdev_ctx_t * ctx,ais328dq_i2_cfg_t * val)1287 int32_t ais328dq_pin_int2_route_get(const stmdev_ctx_t *ctx,
1288 ais328dq_i2_cfg_t *val)
1289 {
1290 ais328dq_ctrl_reg3_t ctrl_reg3;
1291 int32_t ret;
1292
1293 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1294 (uint8_t *)&ctrl_reg3, 1);
1295
1296 switch (ctrl_reg3.i2_cfg)
1297 {
1298 case AIS328DQ_PAD2_INT2_SRC:
1299 *val = AIS328DQ_PAD2_INT2_SRC;
1300 break;
1301
1302 case AIS328DQ_PAD2_INT1_OR_INT2_SRC:
1303 *val = AIS328DQ_PAD2_INT1_OR_INT2_SRC;
1304 break;
1305
1306 case AIS328DQ_PAD2_DRDY:
1307 *val = AIS328DQ_PAD2_DRDY;
1308 break;
1309
1310 case AIS328DQ_PAD2_BOOT:
1311 *val = AIS328DQ_PAD2_BOOT;
1312 break;
1313
1314 default:
1315 *val = AIS328DQ_PAD2_INT2_SRC;
1316 break;
1317 }
1318
1319 return ret;
1320 }
1321
1322 /**
1323 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1324 * register cleared by reading INT2_SRC itself.[set]
1325 *
1326 * @param ctx read / write interface definitions(ptr)
1327 * @param val change the values of lir2 in reg CTRL_REG3
1328 * @retval interface status (MANDATORY: return 0 -> no Error)
1329 *
1330 */
ais328dq_int2_notification_set(const stmdev_ctx_t * ctx,ais328dq_lir2_t val)1331 int32_t ais328dq_int2_notification_set(const stmdev_ctx_t *ctx,
1332 ais328dq_lir2_t val)
1333 {
1334 ais328dq_ctrl_reg3_t ctrl_reg3;
1335 int32_t ret;
1336
1337 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1338 (uint8_t *)&ctrl_reg3, 1);
1339
1340 if (ret == 0)
1341 {
1342 ctrl_reg3.lir2 = (uint8_t)val;
1343 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1344 (uint8_t *)&ctrl_reg3, 1);
1345 }
1346
1347 return ret;
1348 }
1349
1350 /**
1351 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1352 * register cleared by reading INT2_SRC itself.[get]
1353 *
1354 * @param ctx read / write interface definitions(ptr)
1355 * @param val Get the values of lir2 in reg CTRL_REG3
1356 * @retval interface status (MANDATORY: return 0 -> no Error)
1357 *
1358 */
ais328dq_int2_notification_get(const stmdev_ctx_t * ctx,ais328dq_lir2_t * val)1359 int32_t ais328dq_int2_notification_get(const stmdev_ctx_t *ctx,
1360 ais328dq_lir2_t *val)
1361 {
1362 ais328dq_ctrl_reg3_t ctrl_reg3;
1363 int32_t ret;
1364
1365 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1366 (uint8_t *)&ctrl_reg3, 1);
1367
1368 switch (ctrl_reg3.lir2)
1369 {
1370 case AIS328DQ_INT2_PULSED:
1371 *val = AIS328DQ_INT2_PULSED;
1372 break;
1373
1374 case AIS328DQ_INT2_LATCHED:
1375 *val = AIS328DQ_INT2_LATCHED;
1376 break;
1377
1378 default:
1379 *val = AIS328DQ_INT2_PULSED;
1380 break;
1381 }
1382
1383 return ret;
1384 }
1385
1386 /**
1387 * @brief Push-pull/open drain selection on interrupt pads.[set]
1388 *
1389 * @param ctx read / write interface definitions(ptr)
1390 * @param val change the values of pp_od in reg CTRL_REG3
1391 * @retval interface status (MANDATORY: return 0 -> no Error)
1392 *
1393 */
ais328dq_pin_mode_set(const stmdev_ctx_t * ctx,ais328dq_pp_od_t val)1394 int32_t ais328dq_pin_mode_set(const stmdev_ctx_t *ctx, ais328dq_pp_od_t val)
1395 {
1396 ais328dq_ctrl_reg3_t ctrl_reg3;
1397 int32_t ret;
1398
1399 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1400 (uint8_t *)&ctrl_reg3, 1);
1401
1402 if (ret == 0)
1403 {
1404 ctrl_reg3.pp_od = (uint8_t)val;
1405 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1406 (uint8_t *)&ctrl_reg3, 1);
1407 }
1408
1409 return ret;
1410 }
1411
1412 /**
1413 * @brief Push-pull/open drain selection on interrupt pads.[get]
1414 *
1415 * @param ctx read / write interface definitions(ptr)
1416 * @param val Get the values of pp_od in reg CTRL_REG3
1417 * @retval interface status (MANDATORY: return 0 -> no Error)
1418 *
1419 */
ais328dq_pin_mode_get(const stmdev_ctx_t * ctx,ais328dq_pp_od_t * val)1420 int32_t ais328dq_pin_mode_get(const stmdev_ctx_t *ctx,
1421 ais328dq_pp_od_t *val)
1422 {
1423 ais328dq_ctrl_reg3_t ctrl_reg3;
1424 int32_t ret;
1425
1426 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1427 (uint8_t *)&ctrl_reg3, 1);
1428
1429 switch (ctrl_reg3.pp_od)
1430 {
1431 case AIS328DQ_PUSH_PULL:
1432 *val = AIS328DQ_PUSH_PULL;
1433 break;
1434
1435 case AIS328DQ_OPEN_DRAIN:
1436 *val = AIS328DQ_OPEN_DRAIN;
1437 break;
1438
1439 default:
1440 *val = AIS328DQ_PUSH_PULL;
1441 break;
1442 }
1443
1444 return ret;
1445 }
1446
1447 /**
1448 * @brief Interrupt active-high/low.[set]
1449 *
1450 * @param ctx read / write interface definitions(ptr)
1451 * @param val change the values of ihl in reg CTRL_REG3
1452 * @retval interface status (MANDATORY: return 0 -> no Error)
1453 *
1454 */
ais328dq_pin_polarity_set(const stmdev_ctx_t * ctx,ais328dq_ihl_t val)1455 int32_t ais328dq_pin_polarity_set(const stmdev_ctx_t *ctx,
1456 ais328dq_ihl_t val)
1457 {
1458 ais328dq_ctrl_reg3_t ctrl_reg3;
1459 int32_t ret;
1460
1461 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1462 (uint8_t *)&ctrl_reg3, 1);
1463
1464 if (ret == 0)
1465 {
1466 ctrl_reg3.ihl = (uint8_t)val;
1467 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG3,
1468 (uint8_t *)&ctrl_reg3, 1);
1469 }
1470
1471 return ret;
1472 }
1473
1474 /**
1475 * @brief Interrupt active-high/low.[get]
1476 *
1477 * @param ctx read / write interface definitions(ptr)
1478 * @param val Get the values of ihl in reg CTRL_REG3
1479 * @retval interface status (MANDATORY: return 0 -> no Error)
1480 *
1481 */
ais328dq_pin_polarity_get(const stmdev_ctx_t * ctx,ais328dq_ihl_t * val)1482 int32_t ais328dq_pin_polarity_get(const stmdev_ctx_t *ctx,
1483 ais328dq_ihl_t *val)
1484 {
1485 ais328dq_ctrl_reg3_t ctrl_reg3;
1486 int32_t ret;
1487
1488 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG3,
1489 (uint8_t *)&ctrl_reg3, 1);
1490
1491 switch (ctrl_reg3.ihl)
1492 {
1493 case AIS328DQ_ACTIVE_HIGH:
1494 *val = AIS328DQ_ACTIVE_HIGH;
1495 break;
1496
1497 case AIS328DQ_ACTIVE_LOW:
1498 *val = AIS328DQ_ACTIVE_LOW;
1499 break;
1500
1501 default:
1502 *val = AIS328DQ_ACTIVE_HIGH;
1503 break;
1504 }
1505
1506 return ret;
1507 }
1508
1509 /**
1510 * @}
1511 *
1512 */
1513
1514 /**
1515 * @defgroup AIS328DQ_interrupt_on_threshold
1516 * @brief This section groups all the functions that manage
1517 * the interrupt on threshold event generation.
1518 * @{
1519 *
1520 */
1521
1522 /**
1523 * @brief Configure the interrupt 1 threshold sign.[set]
1524 *
1525 * @param ctx read / write interface definitions(ptr)
1526 * @param val enable sign and axis for interrupt on threshold
1527 * @retval interface status (MANDATORY: return 0 -> no Error)
1528 *
1529 */
ais328dq_int1_on_threshold_conf_set(const stmdev_ctx_t * ctx,ais328dq_int1_on_th_conf_t val)1530 int32_t ais328dq_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1531 ais328dq_int1_on_th_conf_t val)
1532 {
1533 ais328dq_int1_cfg_t int1_cfg;
1534 int32_t ret;
1535
1536 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1537
1538 if (ret == 0)
1539 {
1540 int1_cfg.xlie = val.int1_xlie;
1541 int1_cfg.xhie = val.int1_xhie;
1542 int1_cfg.ylie = val.int1_ylie;
1543 int1_cfg.yhie = val.int1_yhie;
1544 int1_cfg.zlie = val.int1_zlie;
1545 int1_cfg.zhie = val.int1_zhie;
1546 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG,
1547 (uint8_t *)&int1_cfg, 1);
1548 }
1549
1550 return ret;
1551 }
1552
1553 /**
1554 * @brief Configure the interrupt 1 threshold sign.[get]
1555 *
1556 * @param ctx read / write interface definitions(ptr)
1557 * @param val enable sign and axis for interrupt on threshold
1558 * @retval interface status (MANDATORY: return 0 -> no Error)
1559 *
1560 */
ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t * ctx,ais328dq_int1_on_th_conf_t * val)1561 int32_t ais328dq_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1562 ais328dq_int1_on_th_conf_t *val)
1563 {
1564 ais328dq_int1_cfg_t int1_cfg;
1565 int32_t ret;
1566
1567 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1568 val->int1_xlie = int1_cfg.xlie;
1569 val->int1_xhie = int1_cfg.xhie;
1570 val->int1_ylie = int1_cfg.ylie;
1571 val->int1_yhie = int1_cfg.yhie;
1572 val->int1_zlie = int1_cfg.zlie;
1573 val->int1_zhie = int1_cfg.zhie;
1574
1575 return ret;
1576 }
1577
1578 /**
1579 * @brief AND/OR combination of Interrupt 1 events.[set]
1580 *
1581 * @param ctx read / write interface definitions(ptr)
1582 * @param val change the values of aoi in reg INT1_CFG
1583 * @retval interface status (MANDATORY: return 0 -> no Error)
1584 *
1585 */
ais328dq_int1_on_threshold_mode_set(const stmdev_ctx_t * ctx,ais328dq_int1_aoi_t val)1586 int32_t ais328dq_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1587 ais328dq_int1_aoi_t val)
1588 {
1589 ais328dq_int1_cfg_t int1_cfg;
1590 int32_t ret;
1591
1592 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1593
1594 if (ret == 0)
1595 {
1596 int1_cfg.aoi = (uint8_t) val;
1597 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG,
1598 (uint8_t *)&int1_cfg, 1);
1599 }
1600
1601 return ret;
1602 }
1603
1604 /**
1605 * @brief AND/OR combination of Interrupt 1 events.[get]
1606 *
1607 * @param ctx read / write interface definitions(ptr)
1608 * @param val Get the values of aoi in reg INT1_CFG
1609 * @retval interface status (MANDATORY: return 0 -> no Error)
1610 *
1611 */
ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t * ctx,ais328dq_int1_aoi_t * val)1612 int32_t ais328dq_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1613 ais328dq_int1_aoi_t *val)
1614 {
1615 ais328dq_int1_cfg_t int1_cfg;
1616 int32_t ret;
1617
1618 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1619
1620 switch (int1_cfg.aoi)
1621 {
1622 case AIS328DQ_INT1_ON_THRESHOLD_OR:
1623 *val = AIS328DQ_INT1_ON_THRESHOLD_OR;
1624 break;
1625
1626 case AIS328DQ_INT1_ON_THRESHOLD_AND:
1627 *val = AIS328DQ_INT1_ON_THRESHOLD_AND;
1628 break;
1629
1630 default:
1631 *val = AIS328DQ_INT1_ON_THRESHOLD_OR;
1632 break;
1633 }
1634
1635 return ret;
1636 }
1637
1638 /**
1639 * @brief Interrupt generator 1 on threshold source register.[get]
1640 *
1641 * @param ctx read / write interface definitions(ptr)
1642 * @param val registers INT1_SRC
1643 * @retval interface status (MANDATORY: return 0 -> no Error)
1644 *
1645 */
ais328dq_int1_src_get(const stmdev_ctx_t * ctx,ais328dq_int1_src_t * val)1646 int32_t ais328dq_int1_src_get(const stmdev_ctx_t *ctx,
1647 ais328dq_int1_src_t *val)
1648 {
1649 int32_t ret;
1650
1651 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t *) val, 1);
1652
1653 return ret;
1654 }
1655
1656 /**
1657 * @brief Interrupt 1 threshold.[set]
1658 *
1659 * @param ctx read / write interface definitions(ptr)
1660 * @param val change the values of ths in reg INT1_THS
1661 * @retval interface status (MANDATORY: return 0 -> no Error)
1662 *
1663 */
ais328dq_int1_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1664 int32_t ais328dq_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1665 {
1666 ais328dq_int1_ths_t int1_ths;
1667 int32_t ret;
1668
1669 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
1670
1671 if (ret == 0)
1672 {
1673 int1_ths.ths = val;
1674 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_THS,
1675 (uint8_t *)&int1_ths, 1);
1676 }
1677
1678 return ret;
1679 }
1680
1681 /**
1682 * @brief Interrupt 1 threshold.[get]
1683 *
1684 * @param ctx read / write interface definitions(ptr)
1685 * @param val change the values of ths in reg INT1_THS
1686 * @retval interface status (MANDATORY: return 0 -> no Error)
1687 *
1688 */
ais328dq_int1_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1689 int32_t ais328dq_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1690 {
1691 ais328dq_int1_ths_t int1_ths;
1692 int32_t ret;
1693
1694 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
1695 *val = int1_ths.ths;
1696
1697 return ret;
1698 }
1699
1700 /**
1701 * @brief Duration value for interrupt 1 generator.[set]
1702 *
1703 * @param ctx read / write interface definitions(ptr)
1704 * @param val change the values of d in reg INT1_DURATION
1705 * @retval interface status (MANDATORY: return 0 -> no Error)
1706 *
1707 */
ais328dq_int1_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1708 int32_t ais328dq_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1709 {
1710 ais328dq_int1_duration_t int1_duration;
1711 int32_t ret;
1712
1713 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_DURATION,
1714 (uint8_t *)&int1_duration, 1);
1715
1716 if (ret == 0)
1717 {
1718 int1_duration.d = val;
1719 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_DURATION,
1720 (uint8_t *)&int1_duration, 1);
1721 }
1722
1723 return ret;
1724 }
1725
1726 /**
1727 * @brief Duration value for interrupt 1 generator.[get]
1728 *
1729 * @param ctx read / write interface definitions(ptr)
1730 * @param val change the values of d in reg INT1_DURATION
1731 * @retval interface status (MANDATORY: return 0 -> no Error)
1732 *
1733 */
ais328dq_int1_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1734 int32_t ais328dq_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1735 {
1736 ais328dq_int1_duration_t int1_duration;
1737 int32_t ret;
1738
1739 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_DURATION,
1740 (uint8_t *)&int1_duration, 1);
1741 *val = int1_duration.d;
1742
1743 return ret;
1744 }
1745
1746 /**
1747 * @brief Configure the interrupt 2 threshold sign.[set]
1748 *
1749 * @param ctx read / write interface definitions(ptr)
1750 * @param val enable sign and axis for interrupt on threshold
1751 * @retval interface status (MANDATORY: return 0 -> no Error)
1752 *
1753 */
ais328dq_int2_on_threshold_conf_set(const stmdev_ctx_t * ctx,ais328dq_int2_on_th_conf_t val)1754 int32_t ais328dq_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1755 ais328dq_int2_on_th_conf_t val)
1756 {
1757 ais328dq_int2_cfg_t int2_cfg;
1758 int32_t ret;
1759
1760 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG,
1761 (uint8_t *)&int2_cfg, 1);
1762
1763 if (ret == 0)
1764 {
1765 int2_cfg.xlie = val.int2_xlie;
1766 int2_cfg.xhie = val.int2_xhie;
1767 int2_cfg.ylie = val.int2_ylie;
1768 int2_cfg.yhie = val.int2_yhie;
1769 int2_cfg.zlie = val.int2_zlie;
1770 int2_cfg.zhie = val.int2_zhie;
1771 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
1772 (uint8_t *)&int2_cfg, 1);
1773 }
1774
1775 return ret;
1776 }
1777
1778 /**
1779 * @brief Configure the interrupt 2 threshold sign.[get]
1780 *
1781 * @param ctx read / write interface definitions(ptr)
1782 * @param val enable sign and axis for interrupt on threshold
1783 * @retval interface status (MANDATORY: return 0 -> no Error)
1784 *
1785 */
ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t * ctx,ais328dq_int2_on_th_conf_t * val)1786 int32_t ais328dq_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1787 ais328dq_int2_on_th_conf_t *val)
1788 {
1789 ais328dq_int2_cfg_t int2_cfg;
1790 int32_t ret;
1791
1792 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1793 val->int2_xlie = int2_cfg.xlie;
1794 val->int2_xhie = int2_cfg.xhie;
1795 val->int2_ylie = int2_cfg.ylie;
1796 val->int2_yhie = int2_cfg.yhie;
1797 val->int2_zlie = int2_cfg.zlie;
1798 val->int2_zhie = int2_cfg.zhie;
1799
1800 return ret;
1801 }
1802
1803 /**
1804 * @brief AND/OR combination of Interrupt 2 events.[set]
1805 *
1806 * @param ctx read / write interface definitions(ptr)
1807 * @param val change the values of aoi in reg INT2_CFG
1808 * @retval interface status (MANDATORY: return 0 -> no Error)
1809 *
1810 */
ais328dq_int2_on_threshold_mode_set(const stmdev_ctx_t * ctx,ais328dq_int2_aoi_t val)1811 int32_t ais328dq_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1812 ais328dq_int2_aoi_t val)
1813 {
1814 ais328dq_int2_cfg_t int2_cfg;
1815 int32_t ret;
1816
1817 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1818
1819 if (ret == 0)
1820 {
1821 int2_cfg.aoi = (uint8_t) val;
1822 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
1823 (uint8_t *)&int2_cfg, 1);
1824 }
1825
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief AND/OR combination of Interrupt 2 events.[get]
1831 *
1832 * @param ctx read / write interface definitions(ptr)
1833 * @param val Get the values of aoi in reg INT2_CFG
1834 * @retval interface status (MANDATORY: return 0 -> no Error)
1835 *
1836 */
ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t * ctx,ais328dq_int2_aoi_t * val)1837 int32_t ais328dq_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1838 ais328dq_int2_aoi_t *val)
1839 {
1840 ais328dq_int2_cfg_t int2_cfg;
1841 int32_t ret;
1842
1843 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1844
1845 switch (int2_cfg.aoi)
1846 {
1847 case AIS328DQ_INT2_ON_THRESHOLD_OR:
1848 *val = AIS328DQ_INT2_ON_THRESHOLD_OR;
1849 break;
1850
1851 case AIS328DQ_INT2_ON_THRESHOLD_AND:
1852 *val = AIS328DQ_INT2_ON_THRESHOLD_AND;
1853 break;
1854
1855 default:
1856 *val = AIS328DQ_INT2_ON_THRESHOLD_OR;
1857 break;
1858 }
1859
1860 return ret;
1861 }
1862
1863 /**
1864 * @brief Interrupt generator 1 on threshold source register.[get]
1865 *
1866 * @param ctx read / write interface definitions(ptr)
1867 * @param val registers INT2_SRC
1868 * @retval interface status (MANDATORY: return 0 -> no Error)
1869 *
1870 */
ais328dq_int2_src_get(const stmdev_ctx_t * ctx,ais328dq_int2_src_t * val)1871 int32_t ais328dq_int2_src_get(const stmdev_ctx_t *ctx,
1872 ais328dq_int2_src_t *val)
1873 {
1874 int32_t ret;
1875
1876 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t *) val, 1);
1877
1878 return ret;
1879 }
1880
1881 /**
1882 * @brief Interrupt 2 threshold.[set]
1883 *
1884 * @param ctx read / write interface definitions(ptr)
1885 * @param val change the values of ths in reg INT2_THS
1886 * @retval interface status (MANDATORY: return 0 -> no Error)
1887 *
1888 */
ais328dq_int2_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1889 int32_t ais328dq_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1890 {
1891 ais328dq_int2_ths_t int2_ths;
1892 int32_t ret;
1893
1894 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
1895
1896 if (ret == 0)
1897 {
1898 int2_ths.ths = val;
1899 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_THS,
1900 (uint8_t *)&int2_ths, 1);
1901 }
1902
1903 return ret;
1904 }
1905
1906 /**
1907 * @brief Interrupt 2 threshold.[get]
1908 *
1909 * @param ctx read / write interface definitions(ptr)
1910 * @param val change the values of ths in reg INT2_THS
1911 * @retval interface status (MANDATORY: return 0 -> no Error)
1912 *
1913 */
ais328dq_int2_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1914 int32_t ais328dq_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1915 {
1916 ais328dq_int2_ths_t int2_ths;
1917 int32_t ret;
1918
1919 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
1920 *val = int2_ths.ths;
1921
1922 return ret;
1923 }
1924
1925 /**
1926 * @brief Duration value for interrupt 2 generator.[set]
1927 *
1928 * @param ctx read / write interface definitions(ptr)
1929 * @param val change the values of d in reg INT2_DURATION
1930 * @retval interface status (MANDATORY: return 0 -> no Error)
1931 *
1932 */
ais328dq_int2_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1933 int32_t ais328dq_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1934 {
1935 ais328dq_int2_duration_t int2_duration;
1936 int32_t ret;
1937
1938 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_DURATION,
1939 (uint8_t *)&int2_duration, 1);
1940
1941 if (ret == 0)
1942 {
1943 int2_duration.d = val;
1944 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_DURATION,
1945 (uint8_t *)&int2_duration, 1);
1946 }
1947
1948 return ret;
1949 }
1950
1951 /**
1952 * @brief Duration value for interrupt 2 generator.[get]
1953 *
1954 * @param ctx read / write interface definitions(ptr)
1955 * @param val change the values of d in reg INT2_DURATION
1956 * @retval interface status (MANDATORY: return 0 -> no Error)
1957 *
1958 */
ais328dq_int2_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1959 int32_t ais328dq_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1960 {
1961 ais328dq_int2_duration_t int2_duration;
1962 int32_t ret;
1963
1964 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_DURATION,
1965 (uint8_t *)&int2_duration, 1);
1966 *val = int2_duration.d;
1967
1968 return ret;
1969 }
1970
1971 /**
1972 * @}
1973 *
1974 */
1975
1976 /**
1977 * @defgroup AIS328DQ_Wake_Up_Event
1978 * @brief This section groups all the functions that manage the
1979 * Wake Up event generation.
1980 * @{
1981 *
1982 */
1983
1984 /**
1985 * @brief Turn-on mode selection for sleep to wake function.[set]
1986 *
1987 * @param ctx read / write interface definitions(ptr)
1988 * @param val change the values of turnon in reg CTRL_REG5
1989 * @retval interface status (MANDATORY: return 0 -> no Error)
1990 *
1991 */
ais328dq_wkup_to_sleep_set(const stmdev_ctx_t * ctx,uint8_t val)1992 int32_t ais328dq_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val)
1993 {
1994 ais328dq_ctrl_reg5_t ctrl_reg5;
1995 int32_t ret;
1996
1997 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5,
1998 (uint8_t *)&ctrl_reg5, 1);
1999
2000 if (ret == 0)
2001 {
2002 ctrl_reg5.turnon = val;
2003 ret = ais328dq_write_reg(ctx, AIS328DQ_CTRL_REG5,
2004 (uint8_t *)&ctrl_reg5, 1);
2005 }
2006
2007 return ret;
2008 }
2009
2010 /**
2011 * @brief Turn-on mode selection for sleep to wake function.[get]
2012 *
2013 * @param ctx read / write interface definitions(ptr)
2014 * @param val change the values of turnon in reg CTRL_REG5
2015 * @retval interface status (MANDATORY: return 0 -> no Error)
2016 *
2017 */
ais328dq_wkup_to_sleep_get(const stmdev_ctx_t * ctx,uint8_t * val)2018 int32_t ais328dq_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val)
2019 {
2020 ais328dq_ctrl_reg5_t ctrl_reg5;
2021 int32_t ret;
2022
2023 ret = ais328dq_read_reg(ctx, AIS328DQ_CTRL_REG5,
2024 (uint8_t *)&ctrl_reg5, 1);
2025 *val = ctrl_reg5.turnon;
2026
2027 return ret;
2028 }
2029
2030 /**
2031 * @}
2032 *
2033 */
2034
2035 /**
2036 * @defgroup AIS328DQ_Six_Position_Detection
2037 * @brief This section groups all the functions concerning six
2038 * position detection (6D).
2039 * @{
2040 *
2041 */
2042
2043 /**
2044 * @brief Configure the 6d on interrupt 1 generator.[set]
2045 *
2046 * @param ctx read / write interface definitions(ptr)
2047 * @param val change the values of 6d in reg INT1_CFG
2048 * @retval interface status (MANDATORY: return 0 -> no Error)
2049 *
2050 */
ais328dq_int1_6d_mode_set(const stmdev_ctx_t * ctx,ais328dq_int1_6d_t val)2051 int32_t ais328dq_int1_6d_mode_set(const stmdev_ctx_t *ctx,
2052 ais328dq_int1_6d_t val)
2053 {
2054 ais328dq_int1_cfg_t int1_cfg;
2055 int32_t ret;
2056
2057 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2058
2059 if (ret == 0)
2060 {
2061 int1_cfg._6d = (uint8_t)val & 0x01U;
2062 int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2063 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2064 }
2065
2066 return ret;
2067 }
2068
2069 /**
2070 * @brief Configure the 6d on interrupt 1 generator.[get]
2071 *
2072 * @param ctx read / write interface definitions(ptr)
2073 * @param val Get the values of 6d in reg INT1_CFG
2074 * @retval interface status (MANDATORY: return 0 -> no Error)
2075 *
2076 */
ais328dq_int1_6d_mode_get(const stmdev_ctx_t * ctx,ais328dq_int1_6d_t * val)2077 int32_t ais328dq_int1_6d_mode_get(const stmdev_ctx_t *ctx,
2078 ais328dq_int1_6d_t *val)
2079 {
2080 ais328dq_int1_cfg_t int1_cfg;
2081 int32_t ret;
2082
2083 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2084
2085 switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
2086 {
2087 case AIS328DQ_6D_INT1_DISABLE:
2088 *val = AIS328DQ_6D_INT1_DISABLE;
2089 break;
2090
2091 case AIS328DQ_6D_INT1_MOVEMENT:
2092 *val = AIS328DQ_6D_INT1_MOVEMENT;
2093 break;
2094
2095 case AIS328DQ_6D_INT1_POSITION:
2096 *val = AIS328DQ_6D_INT1_POSITION;
2097 break;
2098
2099 default:
2100 *val = AIS328DQ_6D_INT1_DISABLE;
2101 break;
2102 }
2103
2104 return ret;
2105 }
2106
2107 /**
2108 * @brief 6D on interrupt generator 1 source register.[get]
2109 *
2110 * @param ctx read / write interface definitions(ptr)
2111 * @param val registers INT1_SRC
2112 * @retval interface status (MANDATORY: return 0 -> no Error)
2113 *
2114 */
ais328dq_int1_6d_src_get(const stmdev_ctx_t * ctx,ais328dq_int1_src_t * val)2115 int32_t ais328dq_int1_6d_src_get(const stmdev_ctx_t *ctx,
2116 ais328dq_int1_src_t *val)
2117 {
2118 int32_t ret;
2119
2120 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_SRC, (uint8_t *) val, 1);
2121
2122 return ret;
2123 }
2124
2125 /**
2126 * @brief Interrupt 1 threshold.[set]
2127 *
2128 * @param ctx read / write interface definitions(ptr)
2129 * @param val change the values of ths in reg INT1_THS
2130 * @retval interface status (MANDATORY: return 0 -> no Error)
2131 *
2132 */
ais328dq_int1_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2133 int32_t ais328dq_int1_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2134 {
2135 ais328dq_int1_ths_t int1_ths;
2136 int32_t ret;
2137
2138 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2139
2140 if (ret == 0)
2141 {
2142 int1_ths.ths = val;
2143 ret = ais328dq_write_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2144 }
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Interrupt 1 threshold.[get]
2151 *
2152 * @param ctx read / write interface definitions(ptr)
2153 * @param val change the values of ths in reg INT1_THS
2154 * @retval interface status (MANDATORY: return 0 -> no Error)
2155 *
2156 */
ais328dq_int1_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2157 int32_t ais328dq_int1_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2158 {
2159 ais328dq_int1_ths_t int1_ths;
2160 int32_t ret;
2161
2162 ret = ais328dq_read_reg(ctx, AIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2163 *val = int1_ths.ths;
2164
2165 return ret;
2166 }
2167
2168 /**
2169 * @brief Configure the 6d on interrupt 2 generator.[set]
2170 *
2171 * @param ctx read / write interface definitions(ptr)
2172 * @param val change the values of 6d in reg INT2_CFG
2173 * @retval interface status (MANDATORY: return 0 -> no Error)
2174 *
2175 */
ais328dq_int2_6d_mode_set(const stmdev_ctx_t * ctx,ais328dq_int2_6d_t val)2176 int32_t ais328dq_int2_6d_mode_set(const stmdev_ctx_t *ctx,
2177 ais328dq_int2_6d_t val)
2178 {
2179 ais328dq_int2_cfg_t int2_cfg;
2180 int32_t ret;
2181
2182 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
2183
2184 if (ret == 0)
2185 {
2186 int2_cfg._6d = (uint8_t)val & 0x01U;
2187 int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2188 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_CFG,
2189 (uint8_t *)&int2_cfg, 1);
2190 }
2191
2192 return ret;
2193 }
2194
2195 /**
2196 * @brief Configure the 6d on interrupt 2 generator.[get]
2197 *
2198 * @param ctx read / write interface definitions(ptr)
2199 * @param val Get the values of 6d in reg INT2_CFG
2200 * @retval interface status (MANDATORY: return 0 -> no Error)
2201 *
2202 */
ais328dq_int2_6d_mode_get(const stmdev_ctx_t * ctx,ais328dq_int2_6d_t * val)2203 int32_t ais328dq_int2_6d_mode_get(const stmdev_ctx_t *ctx,
2204 ais328dq_int2_6d_t *val)
2205 {
2206 ais328dq_int2_cfg_t int2_cfg;
2207 int32_t ret;
2208
2209 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
2210
2211 switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
2212 {
2213 case AIS328DQ_6D_INT2_DISABLE:
2214 *val = AIS328DQ_6D_INT2_DISABLE;
2215 break;
2216
2217 case AIS328DQ_6D_INT2_MOVEMENT:
2218 *val = AIS328DQ_6D_INT2_MOVEMENT;
2219 break;
2220
2221 case AIS328DQ_6D_INT2_POSITION:
2222 *val = AIS328DQ_6D_INT2_POSITION;
2223 break;
2224
2225 default:
2226 *val = AIS328DQ_6D_INT2_DISABLE;
2227 break;
2228 }
2229
2230 return ret;
2231 }
2232
2233 /**
2234 * @brief 6D on interrupt generator 2 source register.[get]
2235 *
2236 * @param ctx read / write interface definitions(ptr)
2237 * @param val registers INT2_SRC
2238 * @retval interface status (MANDATORY: return 0 -> no Error)
2239 *
2240 */
ais328dq_int2_6d_src_get(const stmdev_ctx_t * ctx,ais328dq_int2_src_t * val)2241 int32_t ais328dq_int2_6d_src_get(const stmdev_ctx_t *ctx,
2242 ais328dq_int2_src_t *val)
2243 {
2244 int32_t ret;
2245
2246 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_SRC, (uint8_t *) val, 1);
2247
2248 return ret;
2249 }
2250
2251 /**
2252 * @brief Interrupt 2 threshold.[set]
2253 *
2254 * @param ctx read / write interface definitions(ptr)
2255 * @param val change the values of ths in reg INT2_THS
2256 * @retval interface status (MANDATORY: return 0 -> no Error)
2257 *
2258 */
ais328dq_int2_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2259 int32_t ais328dq_int2_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2260 {
2261 ais328dq_int2_ths_t int2_ths;
2262 int32_t ret;
2263
2264 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
2265
2266 if (ret == 0)
2267 {
2268 int2_ths.ths = val;
2269 ret = ais328dq_write_reg(ctx, AIS328DQ_INT2_THS,
2270 (uint8_t *)&int2_ths, 1);
2271 }
2272
2273 return ret;
2274 }
2275
2276 /**
2277 * @brief Interrupt 2 threshold.[get]
2278 *
2279 * @param ctx read / write interface definitions(ptr)
2280 * @param val change the values of ths in reg INT2_THS
2281 * @retval interface status (MANDATORY: return 0 -> no Error)
2282 *
2283 */
ais328dq_int2_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2284 int32_t ais328dq_int2_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2285 {
2286 ais328dq_int2_ths_t int2_ths;
2287 int32_t ret;
2288
2289 ret = ais328dq_read_reg(ctx, AIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
2290 *val = int2_ths.ths;
2291
2292 return ret;
2293 }
2294
2295 /**
2296 * @}
2297 *
2298 */
2299
2300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2301
