1 /**
2 ******************************************************************************
3 * @file ais2dw12_reg.c
4 * @author Sensors Software Solution Team
5 * @brief AIS2DW12 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ais2dw12_reg.h"
21
22 /**
23 * @defgroup AIS2DW12
24 * @brief This file provides a set of functions needed to drive the
25 * ais2dw12 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup AIS2DW12_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ais2dw12_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ais2dw12_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
ais2dw12_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak ais2dw12_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup Private_functions
92 * @brief Section collect all the utility functions needed by APIs.
93 * @{
94 *
95 */
96
bytecpy(uint8_t * target,uint8_t * source)97 static void bytecpy(uint8_t *target, uint8_t *source)
98 {
99 if ((target != NULL) && (source != NULL))
100 {
101 *target = *source;
102 }
103 }
104
105 /**
106 * @}
107 *
108 */
109
110 /**
111 * @defgroup AIS2DW12_Sensitivity
112 * @brief These functions convert raw-data into engineering units.
113 * @{
114 *
115 */
116
ais2dw12_from_fs2_to_mg(int16_t lsb)117 float_t ais2dw12_from_fs2_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.061f;
120 }
121
ais2dw12_from_fs4_to_mg(int16_t lsb)122 float_t ais2dw12_from_fs4_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.122f;
125 }
126
ais2dw12_from_fs2_12bit_to_mg(int16_t lsb)127 float_t ais2dw12_from_fs2_12bit_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
ais2dw12_from_fs4_12bit_to_mg(int16_t lsb)132 float_t ais2dw12_from_fs4_12bit_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
ais2dw12_from_lsb_to_celsius(int16_t lsb)137 float_t ais2dw12_from_lsb_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 256.0f) + 25.0f);
140 }
141
142 /**
143 * @}
144 *
145 */
146
147 /**
148 * @defgroup AIS2DW12_Data_Generation
149 * @brief This section groups all the functions concerning
150 * data generation
151 * @{
152 *
153 */
154
155 /**
156 * @brief Select accelerometer operating modes.[set]
157 *
158 * @param ctx read / write interface definitions
159 * @param val change the values of op_mode / pw_mode in reg CTRL1
160 * and low_noise in reg CTRL6
161 * @retval interface status (MANDATORY: return 0 -> no Error)
162 *
163 */
ais2dw12_power_mode_set(const stmdev_ctx_t * ctx,ais2dw12_mode_t val)164 int32_t ais2dw12_power_mode_set(const stmdev_ctx_t *ctx,
165 ais2dw12_mode_t val)
166 {
167 ais2dw12_ctrl1_t ctrl1;
168 int32_t ret;
169
170 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
171
172 if (ret == 0)
173 {
174 ctrl1.op_mode = ((uint8_t) val & 0x0CU) >> 2;
175 ctrl1.pw_mode = (uint8_t) val & 0x03U ;
176 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
177 }
178
179 return ret;
180 }
181
182 /**
183 * @brief Select accelerometer operating modes.[get]
184 *
185 * @param ctx read / write interface definitions
186 * @param val change the values of op_mode / pw_mode in reg CTRL1
187 * and low_noise in reg CTRL6
188 * @retval interface status (MANDATORY: return 0 -> no Error)
189 *
190 */
ais2dw12_power_mode_get(const stmdev_ctx_t * ctx,ais2dw12_mode_t * val)191 int32_t ais2dw12_power_mode_get(const stmdev_ctx_t *ctx,
192 ais2dw12_mode_t *val)
193 {
194 ais2dw12_ctrl1_t ctrl1;
195 int32_t ret;
196
197 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
198
199 switch ((ctrl1.op_mode << 2) + ctrl1.pw_mode)
200 {
201 case AIS2DW12_PWR_MD_4:
202 *val = AIS2DW12_PWR_MD_4;
203 break;
204
205 case AIS2DW12_PWR_MD_3:
206 *val = AIS2DW12_PWR_MD_3;
207 break;
208
209 case AIS2DW12_PWR_MD_2:
210 *val = AIS2DW12_PWR_MD_2;
211 break;
212
213 case AIS2DW12_PWR_MD_12bit:
214 *val = AIS2DW12_PWR_MD_12bit;
215 break;
216
217 case AIS2DW12_SINGLE_PWR_MD_4:
218 *val = AIS2DW12_SINGLE_PWR_MD_4;
219 break;
220
221 case AIS2DW12_SINGLE_PWR_MD_3:
222 *val = AIS2DW12_SINGLE_PWR_MD_3;
223 break;
224
225 case AIS2DW12_SINGLE_PWR_MD_2:
226 *val = AIS2DW12_SINGLE_PWR_MD_2;
227 break;
228
229 case AIS2DW12_SINGLE_PWR_MD_12bit:
230 *val = AIS2DW12_SINGLE_PWR_MD_12bit;
231 break;
232
233 default:
234 *val = AIS2DW12_PWR_MD_4;
235 break;
236 }
237
238 return ret;
239 }
240
241 /**
242 * @brief Accelerometer data rate selection.[set]
243 *
244 * @param ctx read / write interface definitions
245 * @param val change the values of odr in reg CTRL1
246 * @retval interface status (MANDATORY: return 0 -> no Error)
247 *
248 */
ais2dw12_data_rate_set(const stmdev_ctx_t * ctx,ais2dw12_odr_t val)249 int32_t ais2dw12_data_rate_set(const stmdev_ctx_t *ctx, ais2dw12_odr_t val)
250 {
251 ais2dw12_ctrl1_t ctrl1;
252 ais2dw12_ctrl3_t ctrl3;
253 int32_t ret;
254
255 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
256
257 if (ret == 0)
258 {
259 ctrl1.odr = (uint8_t) val;
260 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
261 }
262
263 if (ret == 0)
264 {
265 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
266 }
267
268 if (ret == 0)
269 {
270 ctrl3.slp_mode = ((uint8_t) val & 0x30U) >> 4;
271 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
272 }
273
274 return ret;
275 }
276
277 /**
278 * @brief Accelerometer data rate selection.[get]
279 *
280 * @param ctx read / write interface definitions
281 * @param val Get the values of odr in reg CTRL1
282 * @retval interface status (MANDATORY: return 0 -> no Error)
283 *
284 */
ais2dw12_data_rate_get(const stmdev_ctx_t * ctx,ais2dw12_odr_t * val)285 int32_t ais2dw12_data_rate_get(const stmdev_ctx_t *ctx, ais2dw12_odr_t *val)
286 {
287 ais2dw12_ctrl1_t ctrl1;
288 ais2dw12_ctrl3_t ctrl3;
289 int32_t ret;
290
291 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL1, (uint8_t *) &ctrl1, 1);
292
293 if (ret == 0)
294 {
295 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) &ctrl3, 1);
296
297 switch ((ctrl3.slp_mode << 4) + ctrl1.odr)
298 {
299 case AIS2DW12_XL_ODR_OFF:
300 *val = AIS2DW12_XL_ODR_OFF;
301 break;
302
303 case AIS2DW12_XL_ODR_12Hz5:
304 *val = AIS2DW12_XL_ODR_12Hz5;
305 break;
306
307 case AIS2DW12_XL_ODR_25Hz:
308 *val = AIS2DW12_XL_ODR_25Hz;
309 break;
310
311 case AIS2DW12_XL_ODR_50Hz:
312 *val = AIS2DW12_XL_ODR_50Hz;
313 break;
314
315 case AIS2DW12_XL_ODR_100Hz:
316 *val = AIS2DW12_XL_ODR_100Hz;
317 break;
318
319 case AIS2DW12_XL_SET_SW_TRIG:
320 *val = AIS2DW12_XL_SET_SW_TRIG;
321 break;
322
323 case AIS2DW12_XL_SET_PIN_TRIG:
324 *val = AIS2DW12_XL_SET_PIN_TRIG;
325 break;
326
327 default:
328 *val = AIS2DW12_XL_ODR_OFF;
329 break;
330 }
331 }
332
333 return ret;
334 }
335
336 /**
337 * @brief Block data update.[set]
338 *
339 * @param ctx read / write interface definitions
340 * @param val change the values of bdu in reg CTRL2
341 * @retval interface status (MANDATORY: return 0 -> no Error)
342 *
343 */
ais2dw12_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)344 int32_t ais2dw12_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
345 {
346 ais2dw12_ctrl2_t reg;
347 int32_t ret;
348
349 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
350
351 if (ret == 0)
352 {
353 reg.bdu = val;
354 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
355 }
356
357 return ret;
358 }
359
360 /**
361 * @brief Block data update.[get]
362 *
363 * @param ctx read / write interface definitions
364 * @param val change the values of bdu in reg CTRL2
365 * @retval interface status (MANDATORY: return 0 -> no Error)
366 *
367 */
ais2dw12_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)368 int32_t ais2dw12_block_data_update_get(const stmdev_ctx_t *ctx,
369 uint8_t *val)
370 {
371 ais2dw12_ctrl2_t reg;
372 int32_t ret;
373
374 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
375 *val = reg.bdu;
376
377 return ret;
378 }
379
380 /**
381 * @brief Accelerometer full-scale selection.[set]
382 *
383 * @param ctx read / write interface definitions
384 * @param val change the values of fs in reg CTRL6
385 * @retval interface status (MANDATORY: return 0 -> no Error)
386 *
387 */
ais2dw12_full_scale_set(const stmdev_ctx_t * ctx,ais2dw12_fs_t val)388 int32_t ais2dw12_full_scale_set(const stmdev_ctx_t *ctx, ais2dw12_fs_t val)
389 {
390 ais2dw12_ctrl6_t reg;
391 int32_t ret;
392
393 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
394
395 if (ret == 0)
396 {
397 reg.fs = (uint8_t) val;
398 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
399 }
400
401 return ret;
402 }
403
404 /**
405 * @brief Accelerometer full-scale selection.[get]
406 *
407 * @param ctx read / write interface definitions
408 * @param val Get the values of fs in reg CTRL6
409 * @retval interface status (MANDATORY: return 0 -> no Error)
410 *
411 */
ais2dw12_full_scale_get(const stmdev_ctx_t * ctx,ais2dw12_fs_t * val)412 int32_t ais2dw12_full_scale_get(const stmdev_ctx_t *ctx, ais2dw12_fs_t *val)
413 {
414 ais2dw12_ctrl6_t reg;
415 int32_t ret;
416
417 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
418
419 switch (reg.fs)
420 {
421 case AIS2DW12_2g:
422 *val = AIS2DW12_2g;
423 break;
424
425 case AIS2DW12_4g:
426 *val = AIS2DW12_4g;
427 break;
428
429 default:
430 *val = AIS2DW12_2g;
431 break;
432 }
433
434 return ret;
435 }
436
437 /**
438 * @brief The STATUS_REG register of the device.[get]
439 *
440 * @param ctx read / write interface definitions
441 * @param val union of registers from STATUS to
442 * @retval interface status (MANDATORY: return 0 -> no Error)
443 *
444 */
ais2dw12_status_reg_get(const stmdev_ctx_t * ctx,ais2dw12_status_t * val)445 int32_t ais2dw12_status_reg_get(const stmdev_ctx_t *ctx,
446 ais2dw12_status_t *val)
447 {
448 int32_t ret;
449
450 ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t *) val, 1);
451
452 return ret;
453 }
454
455 /**
456 * @brief Accelerometer new data available.[get]
457 *
458 * @param ctx read / write interface definitions
459 * @param val change the values of drdy in reg STATUS
460 * @retval interface status (MANDATORY: return 0 -> no Error)
461 *
462 */
ais2dw12_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)463 int32_t ais2dw12_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
464 {
465 ais2dw12_status_t reg;
466 int32_t ret;
467
468 ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS, (uint8_t *) ®, 1);
469 *val = reg.drdy;
470
471 return ret;
472 }
473 /**
474 * @brief Read all the interrupt/status flag of the device.[get]
475 *
476 * @param ctx read / write interface definitions
477 * @param val registers STATUS_DUP, WAKE_UP_SRC,
478 * TAP_SRC, SIXD_SRC, ALL_INT_SRC
479 * @retval interface status (MANDATORY: return 0 -> no Error)
480 *
481 */
ais2dw12_all_sources_get(const stmdev_ctx_t * ctx,ais2dw12_all_sources_t * val)482 int32_t ais2dw12_all_sources_get(const stmdev_ctx_t *ctx,
483 ais2dw12_all_sources_t *val)
484 {
485 uint8_t reg[5];
486 int32_t ret;
487
488 ret = ais2dw12_read_reg(ctx, AIS2DW12_STATUS_DUP, reg, 5);
489 bytecpy((uint8_t *)&val->status_dup, ®[0]);
490 bytecpy((uint8_t *)&val->wake_up_src, ®[1]);
491 bytecpy((uint8_t *)&val->sixd_src, ®[3]);
492 bytecpy((uint8_t *)&val->all_int_src, ®[4]);
493
494 return ret;
495 }
496
497 /**
498 * @brief Accelerometer X-axis user offset correction expressed in two’s
499 * complement, weight depends on bit USR_OFF_W. The value must be
500 * in the range [-127 127].[set]
501 *
502 * @param ctx read / write interface definitions
503 * @param buff buffer that contains data to write
504 * @retval interface status (MANDATORY: return 0 -> no Error)
505 *
506 */
ais2dw12_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)507 int32_t ais2dw12_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
508 {
509 int32_t ret;
510
511 ret = ais2dw12_write_reg(ctx, AIS2DW12_X_OFS_USR, buff, 1);
512
513 return ret;
514 }
515
516 /**
517 * @brief Accelerometer X-axis user offset correction expressed in two’s
518 * complement, weight depends on bit USR_OFF_W. The value must be
519 * in the range [-127 127].[get]
520 *
521 * @param ctx read / write interface definitions
522 * @param buff buffer that stores data read
523 * @retval interface status (MANDATORY: return 0 -> no Error)
524 *
525 */
ais2dw12_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)526 int32_t ais2dw12_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
527 {
528 int32_t ret;
529
530 ret = ais2dw12_read_reg(ctx, AIS2DW12_X_OFS_USR, buff, 1);
531
532 return ret;
533 }
534
535 /**
536 * @brief Accelerometer Y-axis user offset correction expressed in two’s
537 * complement, weight depends on bit USR_OFF_W. The value must be
538 * in the range [-127 127].[set]
539 *
540 * @param ctx read / write interface definitions
541 * @param buff buffer that contains data to write
542 * @retval interface status (MANDATORY: return 0 -> no Error)
543 *
544 */
ais2dw12_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)545 int32_t ais2dw12_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
546 {
547 int32_t ret;
548
549 ret = ais2dw12_write_reg(ctx, AIS2DW12_Y_OFS_USR, buff, 1);
550
551 return ret;
552 }
553
554 /**
555 * @brief Accelerometer Y-axis user offset correction expressed in two’s
556 * complement, weight depends on bit USR_OFF_W. The value must be
557 * in the range [-127 127].[get]
558 *
559 * @param ctx read / write interface definitions
560 * @param buff buffer that stores data read
561 * @retval interface status (MANDATORY: return 0 -> no Error)
562 *
563 */
ais2dw12_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)564 int32_t ais2dw12_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
565 {
566 int32_t ret;
567
568 ret = ais2dw12_read_reg(ctx, AIS2DW12_Y_OFS_USR, buff, 1);
569
570 return ret;
571 }
572
573 /**
574 * @brief Accelerometer Z-axis user offset correction expressed in two’s
575 * complement, weight depends on bit USR_OFF_W. The value must be
576 * in the range [-127 127].[set]
577 *
578 * @param ctx read / write interface definitions
579 * @param buff buffer that contains data to write
580 * @retval interface status (MANDATORY: return 0 -> no Error)
581 *
582 */
ais2dw12_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)583 int32_t ais2dw12_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
584 {
585 int32_t ret;
586
587 ret = ais2dw12_write_reg(ctx, AIS2DW12_Z_OFS_USR, buff, 1);
588
589 return ret;
590 }
591
592 /**
593 * @brief Accelerometer Z-axis user offset correction expressed in two’s
594 * complement, weight depends on bit USR_OFF_W. The value must be
595 * in the range [-127 127].[get]
596 *
597 * @param ctx read / write interface definitions
598 * @param buff buffer that stores data read
599 * @retval interface status (MANDATORY: return 0 -> no Error)
600 *
601 */
ais2dw12_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)602 int32_t ais2dw12_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
603 {
604 int32_t ret;
605
606 ret = ais2dw12_read_reg(ctx, AIS2DW12_Z_OFS_USR, buff, 1);
607
608 return ret;
609 }
610
611 /**
612 * @brief Weight of XL user offset bits of registers X_OFS_USR,
613 * Y_OFS_USR, Z_OFS_USR.[set]
614 *
615 * @param ctx read / write interface definitions
616 * @param val change the values of usr_off_w in
617 * reg CTRL_REG7
618 * @retval interface status (MANDATORY: return 0 -> no Error)
619 *
620 */
ais2dw12_offset_weight_set(const stmdev_ctx_t * ctx,ais2dw12_usr_off_w_t val)621 int32_t ais2dw12_offset_weight_set(const stmdev_ctx_t *ctx,
622 ais2dw12_usr_off_w_t val)
623 {
624 ais2dw12_ctrl7_t reg;
625 int32_t ret;
626
627 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
628
629 if (ret == 0)
630 {
631 reg.usr_off_w = (uint8_t) val;
632 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
633 }
634
635 return ret;
636 }
637
638 /**
639 * @brief Weight of XL user offset bits of registers X_OFS_USR,
640 * Y_OFS_USR, Z_OFS_USR.[get]
641 *
642 * @param ctx read / write interface definitions
643 * @param val Get the values of usr_off_w in reg CTRL_REG7
644 * @retval interface status (MANDATORY: return 0 -> no Error)
645 *
646 */
ais2dw12_offset_weight_get(const stmdev_ctx_t * ctx,ais2dw12_usr_off_w_t * val)647 int32_t ais2dw12_offset_weight_get(const stmdev_ctx_t *ctx,
648 ais2dw12_usr_off_w_t *val)
649 {
650 ais2dw12_ctrl7_t reg;
651 int32_t ret;
652
653 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
654
655 switch (reg.usr_off_w)
656 {
657 case AIS2DW12_LSb_977ug:
658 *val = AIS2DW12_LSb_977ug;
659 break;
660
661 case AIS2DW12_LSb_15mg6:
662 *val = AIS2DW12_LSb_15mg6;
663 break;
664
665 default:
666 *val = AIS2DW12_LSb_977ug;
667 break;
668 }
669
670 return ret;
671 }
672
673 /**
674 * @}
675 *
676 */
677
678 /**
679 * @defgroup AIS2DW12_Data_Output
680 * @brief This section groups all the data output functions.
681 * @{
682 *
683 */
684
685 /**
686 * @brief Temperature data output register (r). L and H registers
687 * together express a 16-bit word in two’s complement.[get]
688 *
689 * @param ctx read / write interface definitions
690 * @param buff buffer that stores data read
691 * @retval interface status (MANDATORY: return 0 -> no Error)
692 *
693 */
ais2dw12_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)694 int32_t ais2dw12_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
695 {
696 uint8_t buff[2];
697 int32_t ret;
698
699 ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_T_L, buff, 2);
700 *val = (int16_t)buff[1];
701 *val = (*val * 256) + (int16_t)buff[0];
702
703 return ret;
704 }
705
706 /**
707 * @brief Linear acceleration output register. The value is expressed as
708 * a 16-bit word in two’s complement.[get]
709 *
710 * @param ctx read / write interface definitions
711 * @param buff buffer that stores data read
712 * @retval interface status (MANDATORY: return 0 -> no Error)
713 *
714 */
ais2dw12_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)715 int32_t ais2dw12_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
716 {
717 uint8_t buff[6];
718 int32_t ret;
719
720 ret = ais2dw12_read_reg(ctx, AIS2DW12_OUT_X_L, buff, 6);
721 val[0] = (int16_t)buff[1];
722 val[0] = (val[0] * 256) + (int16_t)buff[0];
723 val[1] = (int16_t)buff[3];
724 val[1] = (val[1] * 256) + (int16_t)buff[2];
725 val[2] = (int16_t)buff[5];
726 val[2] = (val[2] * 256) + (int16_t)buff[4];
727
728 return ret;
729 }
730
731 /**
732 * @}
733 *
734 */
735
736 /**
737 * @defgroup AIS2DW12_Common
738 * @brief This section groups common useful functions.
739 * @{
740 *
741 */
742
743 /**
744 * @brief Device Who am I.[get]
745 *
746 * @param ctx read / write interface definitions
747 * @param buff buffer that stores data read
748 * @retval interface status (MANDATORY: return 0 -> no Error)
749 *
750 */
ais2dw12_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)751 int32_t ais2dw12_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
752 {
753 int32_t ret;
754
755 ret = ais2dw12_read_reg(ctx, AIS2DW12_WHO_AM_I, buff, 1);
756
757 return ret;
758 }
759
760 /**
761 * @brief Register address automatically incremented during multiple byte
762 * access with a serial interface.[set]
763 *
764 * @param ctx read / write interface definitions
765 * @param val change the values of if_add_inc in reg CTRL2
766 * @retval interface status (MANDATORY: return 0 -> no Error)
767 *
768 */
ais2dw12_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)769 int32_t ais2dw12_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
770 {
771 ais2dw12_ctrl2_t reg;
772 int32_t ret;
773
774 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
775
776 if (ret == 0)
777 {
778 reg.if_add_inc = val;
779 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
780 }
781
782 return ret;
783 }
784
785 /**
786 * @brief Register address automatically incremented during multiple
787 * byte access with a serial interface.[get]
788 *
789 * @param ctx read / write interface definitions
790 * @param val change the values of if_add_inc in reg CTRL2
791 * @retval interface status (MANDATORY: return 0 -> no Error)
792 *
793 */
ais2dw12_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)794 int32_t ais2dw12_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
795 {
796 ais2dw12_ctrl2_t reg;
797 int32_t ret;
798
799 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
800 *val = reg.if_add_inc;
801
802 return ret;
803 }
804
805 /**
806 * @brief Software reset. Restore the default values in user registers.[set]
807 *
808 * @param ctx read / write interface definitions
809 * @param val change the values of soft_reset in reg CTRL2
810 * @retval interface status (MANDATORY: return 0 -> no Error)
811 *
812 */
ais2dw12_reset_set(const stmdev_ctx_t * ctx,uint8_t val)813 int32_t ais2dw12_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
814 {
815 ais2dw12_ctrl2_t reg;
816 int32_t ret;
817
818 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
819
820 if (ret == 0)
821 {
822 reg.soft_reset = val;
823 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
824 }
825
826 return ret;
827 }
828
829 /**
830 * @brief Software reset. Restore the default values in user registers.[get]
831 *
832 * @param ctx read / write interface definitions
833 * @param val change the values of soft_reset in reg CTRL2
834 * @retval interface status (MANDATORY: return 0 -> no Error)
835 *
836 */
ais2dw12_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)837 int32_t ais2dw12_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
838 {
839 ais2dw12_ctrl2_t reg;
840 int32_t ret;
841
842 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
843 *val = reg.soft_reset;
844
845 return ret;
846 }
847
848 /**
849 * @brief Reboot memory content. Reload the calibration parameters.[set]
850 *
851 * @param ctx read / write interface definitions
852 * @param val change the values of boot in reg CTRL2
853 * @retval interface status (MANDATORY: return 0 -> no Error)
854 *
855 */
ais2dw12_boot_set(const stmdev_ctx_t * ctx,uint8_t val)856 int32_t ais2dw12_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
857 {
858 ais2dw12_ctrl2_t reg;
859 int32_t ret;
860
861 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
862
863 if (ret == 0)
864 {
865 reg.boot = val;
866 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
867 }
868
869 return ret;
870 }
871
872 /**
873 * @brief Reboot memory content. Reload the calibration parameters.[get]
874 *
875 * @param ctx read / write interface definitions
876 * @param val change the values of boot in reg CTRL2
877 * @retval interface status (MANDATORY: return 0 -> no Error)
878 *
879 */
ais2dw12_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)880 int32_t ais2dw12_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
881 {
882 ais2dw12_ctrl2_t reg;
883 int32_t ret;
884
885 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
886 *val = reg.boot;
887
888 return ret;
889 }
890
891 /**
892 * @brief Sensor self-test enable.[set]
893 *
894 * @param ctx read / write interface definitions
895 * @param val change the values of st in reg CTRL3
896 * @retval interface status (MANDATORY: return 0 -> no Error)
897 *
898 */
ais2dw12_self_test_set(const stmdev_ctx_t * ctx,ais2dw12_st_t val)899 int32_t ais2dw12_self_test_set(const stmdev_ctx_t *ctx, ais2dw12_st_t val)
900 {
901 ais2dw12_ctrl3_t reg;
902 int32_t ret;
903
904 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
905
906 if (ret == 0)
907 {
908 reg.st = (uint8_t) val;
909 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
910 }
911
912 return ret;
913 }
914
915 /**
916 * @brief Sensor self-test enable.[get]
917 *
918 * @param ctx read / write interface definitions
919 * @param val Get the values of st in reg CTRL3
920 * @retval interface status (MANDATORY: return 0 -> no Error)
921 *
922 */
ais2dw12_self_test_get(const stmdev_ctx_t * ctx,ais2dw12_st_t * val)923 int32_t ais2dw12_self_test_get(const stmdev_ctx_t *ctx, ais2dw12_st_t *val)
924 {
925 ais2dw12_ctrl3_t reg;
926 int32_t ret;
927
928 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
929
930 switch (reg.st)
931 {
932 case AIS2DW12_XL_ST_DISABLE:
933 *val = AIS2DW12_XL_ST_DISABLE;
934 break;
935
936 case AIS2DW12_XL_ST_POSITIVE:
937 *val = AIS2DW12_XL_ST_POSITIVE;
938 break;
939
940 case AIS2DW12_XL_ST_NEGATIVE:
941 *val = AIS2DW12_XL_ST_NEGATIVE;
942 break;
943
944 default:
945 *val = AIS2DW12_XL_ST_DISABLE;
946 break;
947 }
948
949 return ret;
950 }
951
952 /**
953 * @brief Data-ready pulsed / letched mode.[set]
954 *
955 * @param ctx read / write interface definitions
956 * @param val change the values of drdy_pulsed in reg CTRL_REG7
957 * @retval interface status (MANDATORY: return 0 -> no Error)
958 *
959 */
ais2dw12_data_ready_mode_set(const stmdev_ctx_t * ctx,ais2dw12_drdy_pulsed_t val)960 int32_t ais2dw12_data_ready_mode_set(const stmdev_ctx_t *ctx,
961 ais2dw12_drdy_pulsed_t val)
962 {
963 ais2dw12_ctrl7_t reg;
964 int32_t ret;
965
966 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
967
968 if (ret == 0)
969 {
970 reg.drdy_pulsed = (uint8_t) val;
971 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
972 }
973
974 return ret;
975 }
976
977 /**
978 * @brief Data-ready pulsed / letched mode.[get]
979 *
980 * @param ctx read / write interface definitions
981 * @param val Get the values of drdy_pulsed in reg CTRL_REG7
982 * @retval interface status (MANDATORY: return 0 -> no Error)
983 *
984 */
ais2dw12_data_ready_mode_get(const stmdev_ctx_t * ctx,ais2dw12_drdy_pulsed_t * val)985 int32_t ais2dw12_data_ready_mode_get(const stmdev_ctx_t *ctx,
986 ais2dw12_drdy_pulsed_t *val)
987 {
988 ais2dw12_ctrl7_t reg;
989 int32_t ret;
990
991 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
992
993 switch (reg.drdy_pulsed)
994 {
995 case AIS2DW12_DRDY_LATCHED:
996 *val = AIS2DW12_DRDY_LATCHED;
997 break;
998
999 case AIS2DW12_DRDY_PULSED:
1000 *val = AIS2DW12_DRDY_PULSED;
1001 break;
1002
1003 default:
1004 *val = AIS2DW12_DRDY_LATCHED;
1005 break;
1006 }
1007
1008 return ret;
1009 }
1010
1011 /**
1012 * @}
1013 *
1014 */
1015
1016 /**
1017 * @defgroup AIS2DW12_Filters
1018 * @brief This section group all the functions concerning the filters
1019 * configuration.
1020 * @{
1021 *
1022 */
1023
1024 /**
1025 * @brief Accelerometer filtering path for outputs.[set]
1026 *
1027 * @param ctx read / write interface definitions
1028 * @param val change the values of fds in reg CTRL6
1029 * @retval interface status (MANDATORY: return 0 -> no Error)
1030 *
1031 */
ais2dw12_filter_path_set(const stmdev_ctx_t * ctx,ais2dw12_fds_t val)1032 int32_t ais2dw12_filter_path_set(const stmdev_ctx_t *ctx,
1033 ais2dw12_fds_t val)
1034 {
1035 ais2dw12_ctrl6_t ctrl6;
1036 ais2dw12_ctrl7_t ctrl_reg7;
1037 int32_t ret;
1038
1039 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1040
1041 if (ret == 0)
1042 {
1043 ctrl6.fds = ((uint8_t) val & 0x10U) >> 4;
1044 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1045 }
1046
1047 if (ret == 0)
1048 {
1049 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1050 }
1051
1052 if (ret == 0)
1053 {
1054 ctrl_reg7.usr_off_on_out = (uint8_t) val & 0x01U;
1055 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @brief Accelerometer filtering path for outputs.[get]
1063 *
1064 * @param ctx read / write interface definitions
1065 * @param val Get the values of fds in reg CTRL6
1066 * @retval interface status (MANDATORY: return 0 -> no Error)
1067 *
1068 */
ais2dw12_filter_path_get(const stmdev_ctx_t * ctx,ais2dw12_fds_t * val)1069 int32_t ais2dw12_filter_path_get(const stmdev_ctx_t *ctx,
1070 ais2dw12_fds_t *val)
1071 {
1072 ais2dw12_ctrl6_t ctrl6;
1073 ais2dw12_ctrl7_t ctrl_reg7;
1074 int32_t ret;
1075
1076 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) &ctrl6, 1);
1077
1078 if (ret == 0)
1079 {
1080 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) &ctrl_reg7, 1);
1081
1082 switch ((ctrl6.fds << 4) + ctrl_reg7.usr_off_on_out)
1083 {
1084 case AIS2DW12_LPF_ON_OUT:
1085 *val = AIS2DW12_LPF_ON_OUT;
1086 break;
1087
1088 case AIS2DW12_USER_OFFSET_ON_OUT:
1089 *val = AIS2DW12_USER_OFFSET_ON_OUT;
1090 break;
1091
1092 case AIS2DW12_HIGH_PASS_ON_OUT:
1093 *val = AIS2DW12_HIGH_PASS_ON_OUT;
1094 break;
1095
1096 default:
1097 *val = AIS2DW12_LPF_ON_OUT;
1098 break;
1099 }
1100 }
1101
1102 return ret;
1103 }
1104
1105 /**
1106 * @brief Accelerometer cutoff filter frequency. Valid for low and high
1107 * pass filter.[set]
1108 *
1109 * @param ctx read / write interface definitions
1110 * @param val change the values of bw_filt in reg CTRL6
1111 * @retval interface status (MANDATORY: return 0 -> no Error)
1112 *
1113 */
ais2dw12_filter_bandwidth_set(const stmdev_ctx_t * ctx,ais2dw12_bw_filt_t val)1114 int32_t ais2dw12_filter_bandwidth_set(const stmdev_ctx_t *ctx,
1115 ais2dw12_bw_filt_t val)
1116 {
1117 ais2dw12_ctrl6_t reg;
1118 int32_t ret;
1119
1120 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
1121
1122 if (ret == 0)
1123 {
1124 reg.bw_filt = (uint8_t) val;
1125 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
1126 }
1127
1128 return ret;
1129 }
1130
1131 /**
1132 * @brief Accelerometer cutoff filter frequency. Valid for low and
1133 * high pass filter.[get]
1134 *
1135 * @param ctx read / write interface definitions
1136 * @param val Get the values of bw_filt in reg CTRL6
1137 * @retval interface status (MANDATORY: return 0 -> no Error)
1138 *
1139 */
ais2dw12_filter_bandwidth_get(const stmdev_ctx_t * ctx,ais2dw12_bw_filt_t * val)1140 int32_t ais2dw12_filter_bandwidth_get(const stmdev_ctx_t *ctx,
1141 ais2dw12_bw_filt_t *val)
1142 {
1143 ais2dw12_ctrl6_t reg;
1144 int32_t ret;
1145
1146 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL6, (uint8_t *) ®, 1);
1147
1148 switch (reg.bw_filt)
1149 {
1150 case AIS2DW12_ODR_DIV_2:
1151 *val = AIS2DW12_ODR_DIV_2;
1152 break;
1153
1154 case AIS2DW12_ODR_DIV_4:
1155 *val = AIS2DW12_ODR_DIV_4;
1156 break;
1157
1158 case AIS2DW12_ODR_DIV_10:
1159 *val = AIS2DW12_ODR_DIV_10;
1160 break;
1161
1162 case AIS2DW12_ODR_DIV_20:
1163 *val = AIS2DW12_ODR_DIV_20;
1164 break;
1165
1166 default:
1167 *val = AIS2DW12_ODR_DIV_2;
1168 break;
1169 }
1170
1171 return ret;
1172 }
1173
1174 /**
1175 * @brief Enable HP filter reference mode.[set]
1176 *
1177 * @param ctx read / write interface definitions
1178 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1179 * @retval interface status (MANDATORY: return 0 -> no Error)
1180 *
1181 */
ais2dw12_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)1182 int32_t ais2dw12_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
1183 {
1184 ais2dw12_ctrl7_t reg;
1185 int32_t ret;
1186
1187 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1188
1189 if (ret == 0)
1190 {
1191 reg.hp_ref_mode = val;
1192 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1193 }
1194
1195 return ret;
1196 }
1197
1198 /**
1199 * @brief Enable HP filter reference mode.[get]
1200 *
1201 * @param ctx read / write interface definitions
1202 * @param val change the values of hp_ref_mode in reg CTRL_REG7
1203 * @retval interface status (MANDATORY: return 0 -> no Error)
1204 *
1205 */
ais2dw12_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)1206 int32_t ais2dw12_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
1207 {
1208 ais2dw12_ctrl7_t reg;
1209 int32_t ret;
1210
1211 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1212 *val = reg.hp_ref_mode;
1213
1214 return ret;
1215 }
1216
1217 /**
1218 * @}
1219 *
1220 */
1221
1222 /**
1223 * @defgroup AIS2DW12_Serial_Interface
1224 * @brief This section groups all the functions concerning main serial
1225 * interface management (not auxiliary)
1226 * @{
1227 *
1228 */
1229
1230 /**
1231 * @brief SPI Serial Interface Mode selection.[set]
1232 *
1233 * @param ctx read / write interface definitions
1234 * @param val change the values of sim in reg CTRL2
1235 * @retval interface status (MANDATORY: return 0 -> no Error)
1236 *
1237 */
ais2dw12_spi_mode_set(const stmdev_ctx_t * ctx,ais2dw12_sim_t val)1238 int32_t ais2dw12_spi_mode_set(const stmdev_ctx_t *ctx, ais2dw12_sim_t val)
1239 {
1240 ais2dw12_ctrl2_t reg;
1241 int32_t ret;
1242
1243 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1244
1245 if (ret == 0)
1246 {
1247 reg.sim = (uint8_t) val;
1248 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1249 }
1250
1251 return ret;
1252 }
1253
1254 /**
1255 * @brief SPI Serial Interface Mode selection.[get]
1256 *
1257 * @param ctx read / write interface definitions
1258 * @param val Get the values of sim in reg CTRL2
1259 * @retval interface status (MANDATORY: return 0 -> no Error)
1260 *
1261 */
ais2dw12_spi_mode_get(const stmdev_ctx_t * ctx,ais2dw12_sim_t * val)1262 int32_t ais2dw12_spi_mode_get(const stmdev_ctx_t *ctx, ais2dw12_sim_t *val)
1263 {
1264 ais2dw12_ctrl2_t reg;
1265 int32_t ret;
1266
1267 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1268
1269 switch (reg.sim)
1270 {
1271 case AIS2DW12_SPI_4_WIRE:
1272 *val = AIS2DW12_SPI_4_WIRE;
1273 break;
1274
1275 case AIS2DW12_SPI_3_WIRE:
1276 *val = AIS2DW12_SPI_3_WIRE;
1277 break;
1278
1279 default:
1280 *val = AIS2DW12_SPI_4_WIRE;
1281 break;
1282 }
1283
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief Disable / Enable I2C interface.[set]
1289 *
1290 * @param ctx read / write interface definitions
1291 * @param val change the values of i2c_disable in
1292 * reg CTRL2
1293 * @retval interface status (MANDATORY: return 0 -> no Error)
1294 *
1295 */
ais2dw12_i2c_interface_set(const stmdev_ctx_t * ctx,ais2dw12_i2c_disable_t val)1296 int32_t ais2dw12_i2c_interface_set(const stmdev_ctx_t *ctx,
1297 ais2dw12_i2c_disable_t val)
1298 {
1299 ais2dw12_ctrl2_t reg;
1300 int32_t ret;
1301
1302 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1303
1304 if (ret == 0)
1305 {
1306 reg.i2c_disable = (uint8_t) val;
1307 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1308 }
1309
1310 return ret;
1311 }
1312
1313 /**
1314 * @brief Disable / Enable I2C interface.[get]
1315 *
1316 * @param ctx read / write interface definitions
1317 * @param val Get the values of i2c_disable in reg CTRL2
1318 * @retval interface status (MANDATORY: return 0 -> no Error)
1319 *
1320 */
ais2dw12_i2c_interface_get(const stmdev_ctx_t * ctx,ais2dw12_i2c_disable_t * val)1321 int32_t ais2dw12_i2c_interface_get(const stmdev_ctx_t *ctx,
1322 ais2dw12_i2c_disable_t *val)
1323 {
1324 ais2dw12_ctrl2_t reg;
1325 int32_t ret;
1326
1327 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1328
1329 switch (reg.i2c_disable)
1330 {
1331 case AIS2DW12_I2C_ENABLE:
1332 *val = AIS2DW12_I2C_ENABLE;
1333 break;
1334
1335 case AIS2DW12_I2C_DISABLE:
1336 *val = AIS2DW12_I2C_DISABLE;
1337 break;
1338
1339 default:
1340 *val = AIS2DW12_I2C_ENABLE;
1341 break;
1342 }
1343
1344 return ret;
1345 }
1346
1347 /**
1348 * @brief Disconnect CS pull-up.[set]
1349 *
1350 * @param ctx read / write interface definitions
1351 * @param val change the values of cs_pu_disc in reg CTRL2
1352 * @retval interface status (MANDATORY: return 0 -> no Error)
1353 *
1354 */
ais2dw12_cs_mode_set(const stmdev_ctx_t * ctx,ais2dw12_cs_pu_disc_t val)1355 int32_t ais2dw12_cs_mode_set(const stmdev_ctx_t *ctx,
1356 ais2dw12_cs_pu_disc_t val)
1357 {
1358 ais2dw12_ctrl2_t reg;
1359 int32_t ret;
1360
1361 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1362
1363 if (ret == 0)
1364 {
1365 reg.cs_pu_disc = (uint8_t) val;
1366 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1367 }
1368
1369 return ret;
1370 }
1371
1372 /**
1373 * @brief Disconnect CS pull-up.[get]
1374 *
1375 * @param ctx read / write interface definitions
1376 * @param val Get the values of cs_pu_disc in reg CTRL2
1377 * @retval interface status (MANDATORY: return 0 -> no Error)
1378 *
1379 */
ais2dw12_cs_mode_get(const stmdev_ctx_t * ctx,ais2dw12_cs_pu_disc_t * val)1380 int32_t ais2dw12_cs_mode_get(const stmdev_ctx_t *ctx,
1381 ais2dw12_cs_pu_disc_t *val)
1382 {
1383 ais2dw12_ctrl2_t reg;
1384 int32_t ret;
1385
1386 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL2, (uint8_t *) ®, 1);
1387
1388 switch (reg.cs_pu_disc)
1389 {
1390 case AIS2DW12_PULL_UP_CONNECT:
1391 *val = AIS2DW12_PULL_UP_CONNECT;
1392 break;
1393
1394 case AIS2DW12_PULL_UP_DISCONNECT:
1395 *val = AIS2DW12_PULL_UP_DISCONNECT;
1396 break;
1397
1398 default:
1399 *val = AIS2DW12_PULL_UP_CONNECT;
1400 break;
1401 }
1402
1403 return ret;
1404 }
1405
1406 /**
1407 * @}
1408 *
1409 */
1410
1411 /**
1412 * @defgroup AIS2DW12_Interrupt_Pins
1413 * @brief This section groups all the functions that manage interrupt pins
1414 * @{
1415 *
1416 */
1417
1418 /**
1419 * @brief Interrupt active-high/low.[set]
1420 *
1421 * @param ctx read / write interface definitions
1422 * @param val change the values of h_lactive in reg CTRL3
1423 * @retval interface status (MANDATORY: return 0 -> no Error)
1424 *
1425 */
ais2dw12_pin_polarity_set(const stmdev_ctx_t * ctx,ais2dw12_h_lactive_t val)1426 int32_t ais2dw12_pin_polarity_set(const stmdev_ctx_t *ctx,
1427 ais2dw12_h_lactive_t val)
1428 {
1429 ais2dw12_ctrl3_t reg;
1430 int32_t ret;
1431
1432 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1433
1434 if (ret == 0)
1435 {
1436 reg.h_lactive = (uint8_t) val;
1437 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1438 }
1439
1440 return ret;
1441 }
1442
1443 /**
1444 * @brief Interrupt active-high/low.[get]
1445 *
1446 * @param ctx read / write interface definitions
1447 * @param val Get the values of h_lactive in reg CTRL3
1448 * @retval interface status (MANDATORY: return 0 -> no Error)
1449 *
1450 */
ais2dw12_pin_polarity_get(const stmdev_ctx_t * ctx,ais2dw12_h_lactive_t * val)1451 int32_t ais2dw12_pin_polarity_get(const stmdev_ctx_t *ctx,
1452 ais2dw12_h_lactive_t *val)
1453 {
1454 ais2dw12_ctrl3_t reg;
1455 int32_t ret;
1456
1457 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1458
1459 switch (reg.h_lactive)
1460 {
1461 case AIS2DW12_ACTIVE_HIGH:
1462 *val = AIS2DW12_ACTIVE_HIGH;
1463 break;
1464
1465 case AIS2DW12_ACTIVE_LOW:
1466 *val = AIS2DW12_ACTIVE_LOW;
1467 break;
1468
1469 default:
1470 *val = AIS2DW12_ACTIVE_HIGH;
1471 break;
1472 }
1473
1474 return ret;
1475 }
1476
1477 /**
1478 * @brief Latched/pulsed interrupt.[set]
1479 *
1480 * @param ctx read / write interface definitions
1481 * @param val change the values of lir in reg CTRL3
1482 * @retval interface status (MANDATORY: return 0 -> no Error)
1483 *
1484 */
ais2dw12_int_notification_set(const stmdev_ctx_t * ctx,ais2dw12_lir_t val)1485 int32_t ais2dw12_int_notification_set(const stmdev_ctx_t *ctx,
1486 ais2dw12_lir_t val)
1487 {
1488 ais2dw12_ctrl3_t reg;
1489 int32_t ret;
1490
1491 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1492
1493 if (ret == 0)
1494 {
1495 reg.lir = (uint8_t) val;
1496 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1497 }
1498
1499 return ret;
1500 }
1501
1502 /**
1503 * @brief Latched/pulsed interrupt.[get]
1504 *
1505 * @param ctx read / write interface definitions
1506 * @param val Get the values of lir in reg CTRL3
1507 * @retval interface status (MANDATORY: return 0 -> no Error)
1508 *
1509 */
ais2dw12_int_notification_get(const stmdev_ctx_t * ctx,ais2dw12_lir_t * val)1510 int32_t ais2dw12_int_notification_get(const stmdev_ctx_t *ctx,
1511 ais2dw12_lir_t *val)
1512 {
1513 ais2dw12_ctrl3_t reg;
1514 int32_t ret;
1515
1516 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1517
1518 switch (reg.lir)
1519 {
1520 case AIS2DW12_INT_PULSED:
1521 *val = AIS2DW12_INT_PULSED;
1522 break;
1523
1524 case AIS2DW12_INT_LATCHED:
1525 *val = AIS2DW12_INT_LATCHED;
1526 break;
1527
1528 default:
1529 *val = AIS2DW12_INT_PULSED;
1530 break;
1531 }
1532
1533 return ret;
1534 }
1535
1536 /**
1537 * @brief Push-pull/open drain selection on interrupt pads.[set]
1538 *
1539 * @param ctx read / write interface definitions
1540 * @param val change the values of pp_od in reg CTRL3
1541 * @retval interface status (MANDATORY: return 0 -> no Error)
1542 *
1543 */
ais2dw12_pin_mode_set(const stmdev_ctx_t * ctx,ais2dw12_pp_od_t val)1544 int32_t ais2dw12_pin_mode_set(const stmdev_ctx_t *ctx, ais2dw12_pp_od_t val)
1545 {
1546 ais2dw12_ctrl3_t reg;
1547 int32_t ret;
1548
1549 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1550
1551 if (ret == 0)
1552 {
1553 reg.pp_od = (uint8_t) val;
1554 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1555 }
1556
1557 return ret;
1558 }
1559
1560 /**
1561 * @brief Push-pull/open drain selection on interrupt pads.[get]
1562 *
1563 * @param ctx read / write interface definitions
1564 * @param val Get the values of pp_od in reg CTRL3
1565 * @retval interface status (MANDATORY: return 0 -> no Error)
1566 *
1567 */
ais2dw12_pin_mode_get(const stmdev_ctx_t * ctx,ais2dw12_pp_od_t * val)1568 int32_t ais2dw12_pin_mode_get(const stmdev_ctx_t *ctx,
1569 ais2dw12_pp_od_t *val)
1570 {
1571 ais2dw12_ctrl3_t reg;
1572 int32_t ret;
1573
1574 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL3, (uint8_t *) ®, 1);
1575
1576 switch (reg.pp_od)
1577 {
1578 case AIS2DW12_PUSH_PULL:
1579 *val = AIS2DW12_PUSH_PULL;
1580 break;
1581
1582 case AIS2DW12_OPEN_DRAIN:
1583 *val = AIS2DW12_OPEN_DRAIN;
1584 break;
1585
1586 default:
1587 *val = AIS2DW12_PUSH_PULL;
1588 break;
1589 }
1590
1591 return ret;
1592 }
1593
1594 /**
1595 * @brief Select the signal that need to route on int1 pad.[set]
1596 *
1597 * @param ctx read / write interface definitions
1598 * @param val register CTRL4_INT1_PAD_CTRL.
1599 * @retval interface status (MANDATORY: return 0 -> no Error)
1600 *
1601 */
ais2dw12_pin_int1_route_set(const stmdev_ctx_t * ctx,ais2dw12_ctrl4_int1_t * val)1602 int32_t ais2dw12_pin_int1_route_set(const stmdev_ctx_t *ctx,
1603 ais2dw12_ctrl4_int1_t *val)
1604 {
1605 ais2dw12_ctrl5_int2_t ctrl5_int2_pad_ctrl;
1606 ais2dw12_ctrl7_t reg;
1607 int32_t ret;
1608
1609 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL5_INT2,
1610 (uint8_t *)&ctrl5_int2_pad_ctrl, 1);
1611
1612 if (ret == 0)
1613 {
1614 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1615 }
1616
1617 if (ret == 0)
1618 {
1619 if ((val->int1_ff |
1620 val->int1_wu |
1621 val->int1_6d |
1622 ctrl5_int2_pad_ctrl.int2_sleep_state |
1623 ctrl5_int2_pad_ctrl.int2_sleep_chg) != PROPERTY_DISABLE)
1624 {
1625 reg.interrupts_enable = PROPERTY_ENABLE;
1626 }
1627
1628 else
1629 {
1630 reg.interrupts_enable = PROPERTY_DISABLE;
1631 }
1632
1633 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL4_INT1,
1634 (uint8_t *) val, 1);
1635 }
1636
1637 if (ret == 0)
1638 {
1639 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1640 }
1641
1642 return ret;
1643 }
1644
1645 /**
1646 * @brief Select the signal that need to route on int1 pad.[get]
1647 *
1648 * @param ctx read / write interface definitions
1649 * @param val register CTRL4_INT1_PAD_CTRL.
1650 * @retval interface status (MANDATORY: return 0 -> no Error)
1651 *
1652 */
ais2dw12_pin_int1_route_get(const stmdev_ctx_t * ctx,ais2dw12_ctrl4_int1_t * val)1653 int32_t ais2dw12_pin_int1_route_get(const stmdev_ctx_t *ctx,
1654 ais2dw12_ctrl4_int1_t *val)
1655 {
1656 int32_t ret;
1657
1658 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL4_INT1,
1659 (uint8_t *) val, 1);
1660
1661 return ret;
1662 }
1663
1664 /**
1665 * @brief Select the signal that need to route on int2 pad.[set]
1666 *
1667 * @param ctx read / write interface definitions
1668 * @param val register CTRL5_INT2_PAD_CTRL.
1669 * @retval interface status (MANDATORY: return 0 -> no Error)
1670 *
1671 */
ais2dw12_pin_int2_route_set(const stmdev_ctx_t * ctx,ais2dw12_ctrl5_int2_t * val)1672 int32_t ais2dw12_pin_int2_route_set(const stmdev_ctx_t *ctx,
1673 ais2dw12_ctrl5_int2_t *val)
1674 {
1675 ais2dw12_ctrl4_int1_t ctrl4_int1_pad_ctrl;
1676 ais2dw12_ctrl7_t reg;
1677 int32_t ret;
1678
1679 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL4_INT1,
1680 (uint8_t *) &ctrl4_int1_pad_ctrl, 1);
1681
1682 if (ret == 0)
1683 {
1684 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1685 }
1686
1687 if (ret == 0)
1688 {
1689 if ((ctrl4_int1_pad_ctrl.int1_ff |
1690 ctrl4_int1_pad_ctrl.int1_wu |
1691 ctrl4_int1_pad_ctrl.int1_6d |
1692 val->int2_sleep_state | val->int2_sleep_chg) != PROPERTY_DISABLE)
1693 {
1694 reg.interrupts_enable = PROPERTY_ENABLE;
1695 }
1696
1697 else
1698 {
1699 reg.interrupts_enable = PROPERTY_DISABLE;
1700 }
1701
1702 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL5_INT2,
1703 (uint8_t *) val, 1);
1704 }
1705
1706 if (ret == 0)
1707 {
1708 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1709 }
1710
1711 return ret;
1712 }
1713
1714 /**
1715 * @brief Select the signal that need to route on int2 pad.[get]
1716 *
1717 * @param ctx read / write interface definitions
1718 * @param val register CTRL5_INT2_PAD_CTRL
1719 * @retval interface status (MANDATORY: return 0 -> no Error)
1720 *
1721 */
ais2dw12_pin_int2_route_get(const stmdev_ctx_t * ctx,ais2dw12_ctrl5_int2_t * val)1722 int32_t ais2dw12_pin_int2_route_get(const stmdev_ctx_t *ctx,
1723 ais2dw12_ctrl5_int2_t *val)
1724 {
1725 int32_t ret;
1726
1727 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL5_INT2,
1728 (uint8_t *) val, 1);
1729
1730 return ret;
1731 }
1732 /**
1733 * @brief All interrupt signals become available on INT1 pin.[set]
1734 *
1735 * @param ctx read / write interface definitions
1736 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1737 * @retval interface status (MANDATORY: return 0 -> no Error)
1738 *
1739 */
ais2dw12_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)1740 int32_t ais2dw12_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
1741 {
1742 ais2dw12_ctrl7_t reg;
1743 int32_t ret;
1744
1745 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1746
1747 if (ret == 0)
1748 {
1749 reg.int2_on_int1 = val;
1750 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1751 }
1752
1753 return ret;
1754 }
1755
1756 /**
1757 * @brief All interrupt signals become available on INT1 pin.[get]
1758 *
1759 * @param ctx read / write interface definitions
1760 * @param val change the values of int2_on_int1 in reg CTRL_REG7
1761 * @retval interface status (MANDATORY: return 0 -> no Error)
1762 *
1763 */
ais2dw12_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)1764 int32_t ais2dw12_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1765 {
1766 ais2dw12_ctrl7_t reg;
1767 int32_t ret;
1768
1769 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1770 *val = reg.int2_on_int1;
1771
1772 return ret;
1773 }
1774
1775 /**
1776 * @}
1777 *
1778 */
1779
1780 /**
1781 * @defgroup AIS2DW12_Wake_Up_Event
1782 * @brief This section groups all the functions that manage the Wake
1783 * Up event generation.
1784 * @{
1785 *
1786 */
1787
1788 /**
1789 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
1790 *
1791 * @param ctx read / write interface definitions
1792 * @param val change the values of wk_ths in reg WAKE_UP_THS
1793 * @retval interface status (MANDATORY: return 0 -> no Error)
1794 *
1795 */
ais2dw12_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1796 int32_t ais2dw12_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1797 {
1798 ais2dw12_wake_up_ths_t reg;
1799 int32_t ret;
1800
1801 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1802
1803 if (ret == 0)
1804 {
1805 reg.wk_ths = val;
1806 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1807 }
1808
1809 return ret;
1810 }
1811
1812 /**
1813 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
1814 *
1815 * @param ctx read / write interface definitions
1816 * @param val change the values of wk_ths in reg WAKE_UP_THS
1817 * @retval interface status (MANDATORY: return 0 -> no Error)
1818 *
1819 */
ais2dw12_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1820 int32_t ais2dw12_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1821 {
1822 ais2dw12_wake_up_ths_t reg;
1823 int32_t ret;
1824
1825 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS, (uint8_t *) ®, 1);
1826 *val = reg.wk_ths;
1827
1828 return ret;
1829 }
1830
1831 /**
1832 * @brief Wake up duration event.1LSb = 1 / ODR.[set]
1833 *
1834 * @param ctx read / write interface definitions
1835 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1836 * @retval interface status (MANDATORY: return 0 -> no Error)
1837 *
1838 */
ais2dw12_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1839 int32_t ais2dw12_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1840 {
1841 ais2dw12_wake_up_dur_t reg;
1842 int32_t ret;
1843
1844 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1845
1846 if (ret == 0)
1847 {
1848 reg.wake_dur = val;
1849 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1850 }
1851
1852 return ret;
1853 }
1854
1855 /**
1856 * @brief Wake up duration event.1LSb = 1 / ODR.[get]
1857 *
1858 * @param ctx read / write interface definitions
1859 * @param val change the values of wake_dur in reg WAKE_UP_DUR
1860 * @retval interface status (MANDATORY: return 0 -> no Error)
1861 *
1862 */
ais2dw12_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1863 int32_t ais2dw12_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1864 {
1865 ais2dw12_wake_up_dur_t reg;
1866 int32_t ret;
1867
1868 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
1869 *val = reg.wake_dur;
1870
1871 return ret;
1872 }
1873
1874 /**
1875 * @brief Data sent to wake-up interrupt function.[set]
1876 *
1877 * @param ctx read / write interface definitions
1878 * @param val change the values of usr_off_on_wu in reg CTRL_REG7
1879 * @retval interface status (MANDATORY: return 0 -> no Error)
1880 *
1881 */
ais2dw12_wkup_feed_data_set(const stmdev_ctx_t * ctx,ais2dw12_usr_off_on_wu_t val)1882 int32_t ais2dw12_wkup_feed_data_set(const stmdev_ctx_t *ctx,
1883 ais2dw12_usr_off_on_wu_t val)
1884 {
1885 ais2dw12_ctrl7_t reg;
1886 int32_t ret;
1887
1888 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1889
1890 if (ret == 0)
1891 {
1892 reg.usr_off_on_wu = (uint8_t) val;
1893 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1894 }
1895
1896 return ret;
1897 }
1898
1899 /**
1900 * @brief Data sent to wake-up interrupt function.[get]
1901 *
1902 * @param ctx read / write interface definitions
1903 * @param val Get the values of usr_off_on_wu in reg CTRL_REG7
1904 * @retval interface status (MANDATORY: return 0 -> no Error)
1905 *
1906 */
ais2dw12_wkup_feed_data_get(const stmdev_ctx_t * ctx,ais2dw12_usr_off_on_wu_t * val)1907 int32_t ais2dw12_wkup_feed_data_get(const stmdev_ctx_t *ctx,
1908 ais2dw12_usr_off_on_wu_t *val)
1909 {
1910 ais2dw12_ctrl7_t reg;
1911 int32_t ret;
1912
1913 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
1914
1915 switch (reg.usr_off_on_wu)
1916 {
1917 case AIS2DW12_HP_FEED:
1918 *val = AIS2DW12_HP_FEED;
1919 break;
1920
1921 case AIS2DW12_USER_OFFSET_FEED:
1922 *val = AIS2DW12_USER_OFFSET_FEED;
1923 break;
1924
1925 default:
1926 *val = AIS2DW12_HP_FEED;
1927 break;
1928 }
1929
1930 return ret;
1931 }
1932
1933 /**
1934 * @}
1935 *
1936 */
1937
1938 /**
1939 * @defgroup AIS2DW12_Activity/Inactivity_Detection
1940 * @brief This section groups all the functions concerning
1941 * activity/inactivity detection.
1942 * @{
1943 *
1944 */
1945
1946 /**
1947 * @brief Config activity / inactivity or
1948 * stationary / motion detection.[set]
1949 *
1950 * @param ctx read / write interface definitions
1951 * @param val change the values of sleep_on / stationary in
1952 * reg WAKE_UP_THS / WAKE_UP_DUR
1953 * @retval interface status (MANDATORY: return 0 -> no Error)
1954 *
1955 */
ais2dw12_act_mode_set(const stmdev_ctx_t * ctx,ais2dw12_sleep_on_t val)1956 int32_t ais2dw12_act_mode_set(const stmdev_ctx_t *ctx,
1957 ais2dw12_sleep_on_t val)
1958 {
1959 ais2dw12_wake_up_ths_t wake_up_ths;
1960 ais2dw12_wake_up_dur_t wake_up_dur;
1961 int32_t ret;
1962
1963 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,
1964 (uint8_t *) &wake_up_ths, 1);
1965
1966 if (ret == 0)
1967 {
1968 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
1969 (uint8_t *) &wake_up_dur, 1);
1970 }
1971
1972 if (ret == 0)
1973 {
1974 wake_up_ths.sleep_on = (uint8_t) val & 0x01U;
1975 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_THS,
1976 (uint8_t *) &wake_up_ths, 1);
1977 }
1978
1979 if (ret == 0)
1980 {
1981 wake_up_dur.stationary = ((uint8_t)val & 0x02U) >> 1;
1982 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,
1983 (uint8_t *) &wake_up_dur, 1);
1984 }
1985
1986 return ret;
1987 }
1988
1989 /**
1990 * @brief Config activity / inactivity or
1991 * stationary / motion detection. [get]
1992 *
1993 * @param ctx read / write interface definitions
1994 * @param val Get the values of sleep_on in reg WAKE_UP_THS
1995 * @retval interface status (MANDATORY: return 0 -> no Error)
1996 *
1997 */
ais2dw12_act_mode_get(const stmdev_ctx_t * ctx,ais2dw12_sleep_on_t * val)1998 int32_t ais2dw12_act_mode_get(const stmdev_ctx_t *ctx,
1999 ais2dw12_sleep_on_t *val)
2000 {
2001 ais2dw12_wake_up_ths_t wake_up_ths;
2002 ais2dw12_wake_up_dur_t wake_up_dur;;
2003 int32_t ret;
2004
2005 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_THS,
2006 (uint8_t *) &wake_up_ths, 1);
2007
2008 if (ret == 0)
2009 {
2010 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
2011 (uint8_t *) &wake_up_dur, 1);
2012
2013 switch ((wake_up_dur.stationary << 1) + wake_up_ths.sleep_on)
2014 {
2015 case AIS2DW12_NO_DETECTION:
2016 *val = AIS2DW12_NO_DETECTION;
2017 break;
2018
2019 case AIS2DW12_DETECT_ACT_INACT:
2020 *val = AIS2DW12_DETECT_ACT_INACT;
2021 break;
2022
2023 case AIS2DW12_DETECT_STAT_MOTION:
2024 *val = AIS2DW12_DETECT_STAT_MOTION;
2025 break;
2026
2027 default:
2028 *val = AIS2DW12_NO_DETECTION;
2029 break;
2030 }
2031 }
2032
2033 return ret;
2034 }
2035
2036 /**
2037 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
2038 *
2039 * @param ctx read / write interface definitions
2040 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2041 * @retval interface status (MANDATORY: return 0 -> no Error)
2042 *
2043 */
ais2dw12_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2044 int32_t ais2dw12_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2045 {
2046 ais2dw12_wake_up_dur_t reg;
2047 int32_t ret;
2048
2049 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2050
2051 if (ret == 0)
2052 {
2053 reg.sleep_dur = val;
2054 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2055 }
2056
2057 return ret;
2058 }
2059
2060 /**
2061 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[get]
2062 *
2063 * @param ctx read / write interface definitions
2064 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
2065 * @retval interface status (MANDATORY: return 0 -> no Error)
2066 *
2067 */
ais2dw12_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2068 int32_t ais2dw12_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2069 {
2070 ais2dw12_wake_up_dur_t reg;
2071 int32_t ret;
2072
2073 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR, (uint8_t *) ®, 1);
2074 *val = reg.sleep_dur;
2075
2076 return ret;
2077 }
2078
2079 /**
2080 * @}
2081 *
2082 */
2083
2084 /**
2085 * @defgroup AIS2DW12_Six_Position_Detection(6D/4D)
2086 * @brief This section groups all the functions concerning six
2087 * position detection (6D).
2088 * @{
2089 *
2090 */
2091
2092 /**
2093 * @brief Threshold for 4D/6D function.[set]
2094 *
2095 * @param ctx read / write interface definitions
2096 * @param val change the values of 6d_ths in reg SIXD_THS
2097 * @retval interface status (MANDATORY: return 0 -> no Error)
2098 *
2099 */
ais2dw12_6d_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2100 int32_t ais2dw12_6d_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
2101 {
2102 ais2dw12_sixd_ths_t reg;
2103 int32_t ret;
2104
2105 ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2106
2107 if (ret == 0)
2108 {
2109 reg._6d_ths = val;
2110 ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2111 }
2112
2113 return ret;
2114 }
2115
2116 /**
2117 * @brief Threshold for 4D/6D function.[get]
2118 *
2119 * @param ctx read / write interface definitions
2120 * @param val change the values of 6d_ths in reg SIXD_THS
2121 * @retval interface status (MANDATORY: return 0 -> no Error)
2122 *
2123 */
ais2dw12_6d_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2124 int32_t ais2dw12_6d_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
2125 {
2126 ais2dw12_sixd_ths_t reg;
2127 int32_t ret;
2128
2129 ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2130 *val = reg._6d_ths;
2131
2132 return ret;
2133 }
2134
2135 /**
2136 * @brief 4D orientation detection enable.[set]
2137 *
2138 * @param ctx read / write interface definitions
2139 * @param val change the values of 4d_en in reg SIXD_THS
2140 * @retval interface status (MANDATORY: return 0 -> no Error)
2141 *
2142 */
ais2dw12_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2143 int32_t ais2dw12_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2144 {
2145 ais2dw12_sixd_ths_t reg;
2146 int32_t ret;
2147
2148 ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2149
2150 if (ret == 0)
2151 {
2152 reg._4d_en = val;
2153 ret = ais2dw12_write_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2154 }
2155
2156 return ret;
2157 }
2158
2159 /**
2160 * @brief 4D orientation detection enable.[get]
2161 *
2162 * @param ctx read / write interface definitions
2163 * @param val change the values of 4d_en in reg SIXD_THS
2164 * @retval interface status (MANDATORY: return 0 -> no Error)
2165 *
2166 */
ais2dw12_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2167 int32_t ais2dw12_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2168 {
2169 ais2dw12_sixd_ths_t reg;
2170 int32_t ret;
2171
2172 ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_THS, (uint8_t *) ®, 1);
2173 *val = reg._4d_en;
2174
2175 return ret;
2176 }
2177
2178 /**
2179 * @brief Read the 6D tap source register.[get]
2180 *
2181 * @param ctx read / write interface definitions
2182 * @param val union of registers from SIXD_SRC
2183 * @retval interface status (MANDATORY: return 0 -> no Error)
2184 *
2185 */
ais2dw12_6d_src_get(const stmdev_ctx_t * ctx,ais2dw12_sixd_src_t * val)2186 int32_t ais2dw12_6d_src_get(const stmdev_ctx_t *ctx,
2187 ais2dw12_sixd_src_t *val)
2188 {
2189 int32_t ret;
2190
2191 ret = ais2dw12_read_reg(ctx, AIS2DW12_SIXD_SRC, (uint8_t *) val, 1);
2192
2193 return ret;
2194 }
2195 /**
2196 * @brief Data sent to 6D interrupt function.[set]
2197 *
2198 * @param ctx read / write interface definitions
2199 * @param val change the values of lpass_on6d in reg CTRL_REG7
2200 * @retval interface status (MANDATORY: return 0 -> no Error)
2201 *
2202 */
ais2dw12_6d_feed_data_set(const stmdev_ctx_t * ctx,ais2dw12_lpass_on6d_t val)2203 int32_t ais2dw12_6d_feed_data_set(const stmdev_ctx_t *ctx,
2204 ais2dw12_lpass_on6d_t val)
2205 {
2206 ais2dw12_ctrl7_t reg;
2207 int32_t ret;
2208
2209 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
2210
2211 if (ret == 0)
2212 {
2213 reg.lpass_on6d = (uint8_t) val;
2214 ret = ais2dw12_write_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
2215 }
2216
2217 return ret;
2218 }
2219
2220 /**
2221 * @brief Data sent to 6D interrupt function.[get]
2222 *
2223 * @param ctx read / write interface definitions
2224 * @param val Get the values of lpass_on6d in reg CTRL_REG7
2225 * @retval interface status (MANDATORY: return 0 -> no Error)
2226 *
2227 */
ais2dw12_6d_feed_data_get(const stmdev_ctx_t * ctx,ais2dw12_lpass_on6d_t * val)2228 int32_t ais2dw12_6d_feed_data_get(const stmdev_ctx_t *ctx,
2229 ais2dw12_lpass_on6d_t *val)
2230 {
2231 ais2dw12_ctrl7_t reg;
2232 int32_t ret;
2233
2234 ret = ais2dw12_read_reg(ctx, AIS2DW12_CTRL7, (uint8_t *) ®, 1);
2235
2236 switch (reg.lpass_on6d)
2237 {
2238 case AIS2DW12_ODR_DIV_2_FEED:
2239 *val = AIS2DW12_ODR_DIV_2_FEED;
2240 break;
2241
2242 case AIS2DW12_LPF2_FEED:
2243 *val = AIS2DW12_LPF2_FEED;
2244 break;
2245
2246 default:
2247 *val = AIS2DW12_ODR_DIV_2_FEED;
2248 break;
2249 }
2250
2251 return ret;
2252 }
2253
2254 /**
2255 * @}
2256 *
2257 */
2258
2259 /**
2260 * @defgroup AIS2DW12_Free_Fall
2261 * @brief This section group all the functions concerning
2262 * the free fall detection.
2263 * @{
2264 *
2265 */
2266
2267 /**
2268 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
2269 *
2270 * @param ctx read / write interface definitions
2271 * @param val change the values of ff_dur in reg
2272 * WAKE_UP_DUR /F REE_FALL
2273 * @retval interface status (MANDATORY: return 0 -> no Error)
2274 *
2275 */
ais2dw12_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)2276 int32_t ais2dw12_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
2277 {
2278 ais2dw12_wake_up_dur_t wake_up_dur;
2279 ais2dw12_free_fall_t free_fall;
2280 int32_t ret;
2281
2282 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
2283 (uint8_t *) &wake_up_dur, 1);
2284
2285 if (ret == 0)
2286 {
2287 ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,
2288 (uint8_t *) &free_fall, 1);
2289 }
2290
2291 if (ret == 0)
2292 {
2293 wake_up_dur.ff_dur = ((uint8_t) val & 0x20U) >> 5;
2294 free_fall.ff_dur = (uint8_t) val & 0x1FU;
2295 ret = ais2dw12_write_reg(ctx, AIS2DW12_WAKE_UP_DUR,
2296 (uint8_t *) &wake_up_dur, 1);
2297 }
2298
2299 if (ret == 0)
2300 {
2301 ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL,
2302 (uint8_t *) &free_fall, 1);
2303 }
2304
2305 return ret;
2306 }
2307
2308 /**
2309 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
2310 *
2311 * @param ctx read / write interface definitions
2312 * @param val change the values of ff_dur in
2313 * reg WAKE_UP_DUR /F REE_FALL
2314 * @retval interface status (MANDATORY: return 0 -> no Error)
2315 *
2316 */
ais2dw12_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)2317 int32_t ais2dw12_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
2318 {
2319 ais2dw12_wake_up_dur_t wake_up_dur;
2320 ais2dw12_free_fall_t free_fall;
2321 int32_t ret;
2322
2323 ret = ais2dw12_read_reg(ctx, AIS2DW12_WAKE_UP_DUR,
2324 (uint8_t *) &wake_up_dur, 1);
2325
2326 if (ret == 0)
2327 {
2328 ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL,
2329 (uint8_t *) &free_fall, 1);
2330 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
2331 }
2332
2333 return ret;
2334 }
2335
2336 /**
2337 * @brief Free fall threshold setting.[set]
2338 *
2339 * @param ctx read / write interface definitions
2340 * @param val change the values of ff_ths in reg FREE_FALL
2341 * @retval interface status (MANDATORY: return 0 -> no Error)
2342 *
2343 */
ais2dw12_ff_threshold_set(const stmdev_ctx_t * ctx,ais2dw12_ff_ths_t val)2344 int32_t ais2dw12_ff_threshold_set(const stmdev_ctx_t *ctx,
2345 ais2dw12_ff_ths_t val)
2346 {
2347 ais2dw12_free_fall_t reg;
2348 int32_t ret;
2349
2350 ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
2351
2352 if (ret == 0)
2353 {
2354 reg.ff_ths = (uint8_t) val;
2355 ret = ais2dw12_write_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
2356 }
2357
2358 return ret;
2359 }
2360
2361 /**
2362 * @brief Free fall threshold setting.[get]
2363 *
2364 * @param ctx read / write interface definitions
2365 * @param val Get the values of ff_ths in reg FREE_FALL
2366 * @retval interface status (MANDATORY: return 0 -> no Error)
2367 *
2368 */
ais2dw12_ff_threshold_get(const stmdev_ctx_t * ctx,ais2dw12_ff_ths_t * val)2369 int32_t ais2dw12_ff_threshold_get(const stmdev_ctx_t *ctx,
2370 ais2dw12_ff_ths_t *val)
2371 {
2372 ais2dw12_free_fall_t reg;
2373 int32_t ret;
2374
2375 ret = ais2dw12_read_reg(ctx, AIS2DW12_FREE_FALL, (uint8_t *) ®, 1);
2376
2377 switch (reg.ff_ths)
2378 {
2379 case AIS2DW12_FF_TSH_5LSb_FS2g:
2380 *val = AIS2DW12_FF_TSH_5LSb_FS2g;
2381 break;
2382
2383 case AIS2DW12_FF_TSH_7LSb_FS2g:
2384 *val = AIS2DW12_FF_TSH_7LSb_FS2g;
2385 break;
2386
2387 case AIS2DW12_FF_TSH_8LSb_FS2g:
2388 *val = AIS2DW12_FF_TSH_8LSb_FS2g;
2389 break;
2390
2391 case AIS2DW12_FF_TSH_10LSb_FS2g:
2392 *val = AIS2DW12_FF_TSH_10LSb_FS2g;
2393 break;
2394
2395 case AIS2DW12_FF_TSH_11LSb_FS2g:
2396 *val = AIS2DW12_FF_TSH_11LSb_FS2g;
2397 break;
2398
2399 case AIS2DW12_FF_TSH_13LSb_FS2g:
2400 *val = AIS2DW12_FF_TSH_13LSb_FS2g;
2401 break;
2402
2403 case AIS2DW12_FF_TSH_15LSb_FS2g:
2404 *val = AIS2DW12_FF_TSH_15LSb_FS2g;
2405 break;
2406
2407 case AIS2DW12_FF_TSH_16LSb_FS2g:
2408 *val = AIS2DW12_FF_TSH_16LSb_FS2g;
2409 break;
2410
2411 default:
2412 *val = AIS2DW12_FF_TSH_5LSb_FS2g;
2413 break;
2414 }
2415
2416 return ret;
2417 }
2418
2419 /**
2420 * @}
2421 *
2422 */
2423
2424 /**
2425 * @defgroup AIS2DW12_Fifo
2426 * @brief This section group all the functions concerning the fifo usage
2427 * @{
2428 *
2429 */
2430
2431 /**
2432 * @brief FIFO watermark level selection.[set]
2433 *
2434 * @param ctx read / write interface definitions
2435 * @param val change the values of fth in reg FIFO_CTRL
2436 * @retval interface status (MANDATORY: return 0 -> no Error)
2437 *
2438 */
ais2dw12_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)2439 int32_t ais2dw12_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
2440 {
2441 ais2dw12_fifo_ctrl_t reg;
2442 int32_t ret;
2443
2444 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2445
2446 if (ret == 0)
2447 {
2448 reg.fth = val;
2449 ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2450 }
2451
2452 return ret;
2453 }
2454
2455 /**
2456 * @brief FIFO watermark level selection.[get]
2457 *
2458 * @param ctx read / write interface definitions
2459 * @param val change the values of fth in reg FIFO_CTRL
2460 * @retval interface status (MANDATORY: return 0 -> no Error)
2461 *
2462 */
ais2dw12_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)2463 int32_t ais2dw12_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
2464 {
2465 ais2dw12_fifo_ctrl_t reg;
2466 int32_t ret;
2467
2468 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2469 *val = reg.fth;
2470
2471 return ret;
2472 }
2473
2474 /**
2475 * @brief FIFO mode selection.[set]
2476 *
2477 * @param ctx read / write interface definitions
2478 * @param val change the values of fmode in reg FIFO_CTRL
2479 * @retval interface status (MANDATORY: return 0 -> no Error)
2480 *
2481 */
ais2dw12_fifo_mode_set(const stmdev_ctx_t * ctx,ais2dw12_fmode_t val)2482 int32_t ais2dw12_fifo_mode_set(const stmdev_ctx_t *ctx,
2483 ais2dw12_fmode_t val)
2484 {
2485 ais2dw12_fifo_ctrl_t reg;
2486 int32_t ret;
2487
2488 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2489
2490 if (ret == 0)
2491 {
2492 reg.fmode = (uint8_t) val;
2493 ret = ais2dw12_write_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2494 }
2495
2496 return ret;
2497 }
2498
2499 /**
2500 * @brief FIFO mode selection.[get]
2501 *
2502 * @param ctx read / write interface definitions
2503 * @param val Get the values of fmode in reg FIFO_CTRL
2504 * @retval interface status (MANDATORY: return 0 -> no Error)
2505 *
2506 */
ais2dw12_fifo_mode_get(const stmdev_ctx_t * ctx,ais2dw12_fmode_t * val)2507 int32_t ais2dw12_fifo_mode_get(const stmdev_ctx_t *ctx,
2508 ais2dw12_fmode_t *val)
2509 {
2510 ais2dw12_fifo_ctrl_t reg;
2511 int32_t ret;
2512
2513 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_CTRL, (uint8_t *) ®, 1);
2514
2515 switch (reg.fmode)
2516 {
2517 case AIS2DW12_BYPASS_MODE:
2518 *val = AIS2DW12_BYPASS_MODE;
2519 break;
2520
2521 case AIS2DW12_FIFO_MODE:
2522 *val = AIS2DW12_FIFO_MODE;
2523 break;
2524
2525 case AIS2DW12_STREAM_TO_FIFO_MODE:
2526 *val = AIS2DW12_STREAM_TO_FIFO_MODE;
2527 break;
2528
2529 case AIS2DW12_BYPASS_TO_STREAM_MODE:
2530 *val = AIS2DW12_BYPASS_TO_STREAM_MODE;
2531 break;
2532
2533 case AIS2DW12_STREAM_MODE:
2534 *val = AIS2DW12_STREAM_MODE;
2535 break;
2536
2537 default:
2538 *val = AIS2DW12_BYPASS_MODE;
2539 break;
2540 }
2541
2542 return ret;
2543 }
2544
2545 /**
2546 * @brief Number of unread samples stored in FIFO.[get]
2547 *
2548 * @param ctx read / write interface definitions
2549 * @param val change the values of diff in reg FIFO_SAMPLES
2550 * @retval interface status (MANDATORY: return 0 -> no Error)
2551 *
2552 */
ais2dw12_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)2553 int32_t ais2dw12_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
2554 {
2555 ais2dw12_fifo_samples_t reg;
2556 int32_t ret;
2557
2558 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
2559 *val = reg.diff;
2560
2561 return ret;
2562 }
2563 /**
2564 * @brief FIFO overrun status.[get]
2565 *
2566 * @param ctx read / write interface definitions
2567 * @param val change the values of fifo_ovr in reg FIFO_SAMPLES
2568 * @retval interface status (MANDATORY: return 0 -> no Error)
2569 *
2570 */
ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2571 int32_t ais2dw12_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2572 {
2573 ais2dw12_fifo_samples_t reg;
2574 int32_t ret;
2575
2576 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
2577 *val = reg.fifo_ovr;
2578
2579 return ret;
2580 }
2581 /**
2582 * @brief FIFO threshold status flag.[get]
2583 *
2584 * @param ctx read / write interface definitions
2585 * @param val change the values of fifo_fth in reg FIFO_SAMPLES
2586 * @retval interface status (MANDATORY: return 0 -> no Error)
2587 *
2588 */
ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)2589 int32_t ais2dw12_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
2590 {
2591 ais2dw12_fifo_samples_t reg;
2592 int32_t ret;
2593
2594 ret = ais2dw12_read_reg(ctx, AIS2DW12_FIFO_SAMPLES, (uint8_t *) ®, 1);
2595 *val = reg.fifo_fth;
2596
2597 return ret;
2598 }
2599
2600 /**
2601 * @}
2602 *
2603 */
2604
2605 /**
2606 * @}
2607 *
2608 */
2609
2610 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2611
