1 /* 2 * Copyright (c) 2016 Linaro Limited. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file SoC configuration macros for the ARM LTD Beetle SoC. 9 * 10 */ 11 12 #ifndef _ARM_BEETLE_SOC_REGS_H_ 13 #define _ARM_BEETLE_SOC_REGS_H_ 14 15 /* System Control Register (SYSCON) */ 16 struct syscon { 17 /* Offset: 0x000 (r/w) remap control register */ 18 volatile uint32_t remap; 19 /* Offset: 0x004 (r/w) pmu control register */ 20 volatile uint32_t pmuctrl; 21 /* Offset: 0x008 (r/w) reset option register */ 22 volatile uint32_t resetop; 23 /* Offset: 0x00c (r/w) emi control register */ 24 volatile uint32_t emictrl; 25 /* Offset: 0x010 (r/w) reset information register */ 26 volatile uint32_t rstinfo; 27 volatile uint32_t reserved0[3]; 28 /* Offset: 0x020 (r/w)AHB peripheral access control set */ 29 volatile uint32_t ahbper0set; 30 /* Offset: 0x024 (r/w)AHB peripheral access control clear */ 31 volatile uint32_t ahbper0clr; 32 volatile uint32_t reserved1[2]; 33 /* Offset: 0x030 (r/w)APB peripheral access control set */ 34 volatile uint32_t apbper0set; 35 /* Offset: 0x034 (r/w)APB peripheral access control clear */ 36 volatile uint32_t apbper0clr; 37 volatile uint32_t reserved2[2]; 38 /* Offset: 0x040 (r/w) main clock control register */ 39 volatile uint32_t mainclk; 40 /* Offset: 0x044 (r/w) auxiliary / rtc control register */ 41 volatile uint32_t auxclk; 42 /* Offset: 0x048 (r/w) pll control register */ 43 volatile uint32_t pllctrl; 44 /* Offset: 0x04c (r/w) pll status register */ 45 volatile uint32_t pllstatus; 46 /* Offset: 0x050 (r/w) sleep control register */ 47 volatile uint32_t sleepcfg; 48 /* Offset: 0x054 (r/w) flash auxiliary settings control register */ 49 volatile uint32_t flashauxcfg; 50 volatile uint32_t reserved3[10]; 51 /* Offset: 0x080 (r/w) AHB peripheral clock set in active state */ 52 volatile uint32_t ahbclkcfg0set; 53 /* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */ 54 volatile uint32_t ahbclkcfg0clr; 55 /* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */ 56 volatile uint32_t ahbclkcfg1set; 57 /* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */ 58 volatile uint32_t ahbclkcfg1clr; 59 /* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */ 60 volatile uint32_t ahbclkcfg2set; 61 /* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */ 62 volatile uint32_t ahbclkcfg2clr; 63 volatile uint32_t reserved4[2]; 64 /* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */ 65 volatile uint32_t apbclkcfg0set; 66 /* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */ 67 volatile uint32_t apbclkcfg0clr; 68 /* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */ 69 volatile uint32_t apbclkcfg1set; 70 /* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */ 71 volatile uint32_t apbclkcfg1clr; 72 /* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */ 73 volatile uint32_t apbclkcfg2set; 74 /* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */ 75 volatile uint32_t apbclkcfg2clr; 76 volatile uint32_t reserved5[2]; 77 /* Offset: 0x0c0 (r/w) AHB peripheral reset select set */ 78 volatile uint32_t ahbprst0set; 79 /* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */ 80 volatile uint32_t ahbprst0clr; 81 /* Offset: 0x0c8 (r/w) APB peripheral reset select set */ 82 volatile uint32_t apbprst0set; 83 /* Offset: 0x0cc (r/w) APB peripheral reset select clear */ 84 volatile uint32_t apbprst0clr; 85 /* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */ 86 volatile uint32_t pwrdncfg0set; 87 /* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */ 88 volatile uint32_t pwrdncfg0clr; 89 /* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */ 90 volatile uint32_t pwrdncfg1set; 91 /* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */ 92 volatile uint32_t pwrdncfg1clr; 93 /* Offset: 0x0e0 ( /w) rtc reset */ 94 volatile uint32_t rtcreset; 95 /* Offset: 0x0e4 (r/w) event interface control register */ 96 volatile uint32_t eventcfg; 97 volatile uint32_t reserved6[2]; 98 /* Offset: 0x0f0 (r/w) sram power control override */ 99 volatile uint32_t pwrovride0; 100 /* Offset: 0x0f4 (r/w) embedded flash power control override */ 101 volatile uint32_t pwrovride1; 102 /* Offset: 0x0f8 (r/ ) memory status register */ 103 volatile uint32_t memorystatus; 104 volatile uint32_t reserved7[1]; 105 /* Offset: 0x100 (r/w) io pad settings */ 106 volatile uint32_t gpiopadcfg0; 107 /* Offset: 0x104 (r/w) io pad settings */ 108 volatile uint32_t gpiopadcfg1; 109 /* Offset: 0x108 (r/w) testmode boot bypass */ 110 volatile uint32_t testmodecfg; 111 }; 112 113 #endif /* _ARM_BEETLE_SOC_REGS_H_ */ 114
