1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * This file has been automatically generated 9 * Tool Version: 1.0.0 10 * Generation Date: 2023-10-11 11 */ 12 13 #ifndef _SEDI_IPC_REGS_H_ 14 #define _SEDI_IPC_REGS_H_ 15 16 #include <sedi_reg_defs.h> 17 18 19 /* ********* IPC PISR_AGENT2ISH *********** 20 * 21 * Register of SEDI IPC 22 * PISR_AGENT2ISH: Peripheral Interrupt Status - IRQ to ISH 23 * AddressOffset : 0x0 24 * AccessType : RW 25 * WritableBitMask: 0x8000001 26 * ResetValue : (uint32_t)0x0 27 */ 28 SEDI_REG_DEFINE(IPC, PISR_AGENT2ISH, 0x0, RW, (uint32_t)0x8000001, (uint32_t)0x0); 29 30 /* 31 * Bit Field of Register PISR_AGENT2ISH 32 * AGENT2ISH_DB: Inbound Ipc Request From AGENT2ISH 33 * BitOffset : 0 34 * BitWidth : 1 35 * AccessType: RO_V 36 * ResetValue: (uint32_t)0x0 37 */ 38 SEDI_RBF_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_DB, 0, 1, RO_V, (uint32_t)0x0); 39 SEDI_RBFV_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_DB, 0, 0); 40 SEDI_RBFV_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_DB, 1, 1); 41 42 /* 43 * Bit Field of Register PISR_AGENT2ISH 44 * RESERVED1: Reserved Field 45 * BitOffset : 1 46 * BitWidth : 26 47 * AccessType: RO 48 * ResetValue: (uint32_t)0x0 49 */ 50 SEDI_RBF_DEFINE(IPC, PISR_AGENT2ISH, RESERVED1, 1, 26, RO, (uint32_t)0x0); 51 52 /* 53 * Bit Field of Register PISR_AGENT2ISH 54 * AGENT2ISH_BCISC: AGENT2ISH Busy Clear Interrupt 55 * BitOffset : 27 56 * BitWidth : 1 57 * AccessType: RW_1C_V 58 * ResetValue: (uint32_t)0x0 59 */ 60 SEDI_RBF_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_BCISC, 27, 1, RW_1C_V, (uint32_t)0x0); 61 SEDI_RBFV_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_BCISC, 0, 0); 62 SEDI_RBFV_DEFINE(IPC, PISR_AGENT2ISH, AGENT2ISH_BCISC, 1, 1); 63 64 /* 65 * Bit Field of Register PISR_AGENT2ISH 66 * RESERVED0: Reserved Field 67 * BitOffset : 28 68 * BitWidth : 4 69 * AccessType: RO 70 * ResetValue: (uint32_t)0x0 71 */ 72 SEDI_RBF_DEFINE(IPC, PISR_AGENT2ISH, RESERVED0, 28, 4, RO, (uint32_t)0x0); 73 74 /* ********* IPC PIMR_AGENT2ISH *********** 75 * 76 * Register of SEDI IPC 77 * PIMR_AGENT2ISH: Peripheral Interrupt Mask - IRQ to ISH 78 * AddressOffset : 0x4 79 * AccessType : RW 80 * WritableBitMask: 0x8000801 81 * ResetValue : (uint32_t)0x0 82 */ 83 SEDI_REG_DEFINE(IPC, PIMR_AGENT2ISH, 0x4, RW, (uint32_t)0x8000801, (uint32_t)0x0); 84 85 /* 86 * Bit Field of Register PIMR_AGENT2ISH 87 * AGENT2ISH_DB: Reserved Field 88 * BitOffset : 0 89 * BitWidth : 1 90 * AccessType: RW 91 * ResetValue: (uint32_t)0x0 92 */ 93 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_DB, 0, 1, RW, (uint32_t)0x0); 94 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_DB, 0, 0); 95 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_DB, 1, 1); 96 97 /* 98 * Bit Field of Register PIMR_AGENT2ISH 99 * RESERVED2: Reserved Field 100 * BitOffset : 1 101 * BitWidth : 10 102 * AccessType: RO 103 * ResetValue: (uint32_t)0x0 104 */ 105 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, RESERVED2, 1, 10, RO, (uint32_t)0x0); 106 107 /* 108 * Bit Field of Register PIMR_AGENT2ISH 109 * ISH2AGENT_BC: Mask Bit For ISH2AGENT Busy Clear 110 * BitOffset : 11 111 * BitWidth : 1 112 * AccessType: RW 113 * ResetValue: (uint32_t)0x0 114 */ 115 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, ISH2AGENT_BC, 11, 1, RW, (uint32_t)0x0); 116 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, ISH2AGENT_BC, 0, 0); 117 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, ISH2AGENT_BC, 1, 1); 118 119 /* 120 * Bit Field of Register PIMR_AGENT2ISH 121 * RESERVED1: Reserved Field 122 * BitOffset : 12 123 * BitWidth : 15 124 * AccessType: RO 125 * ResetValue: (uint32_t)0x0 126 */ 127 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, RESERVED1, 12, 15, RO, (uint32_t)0x0); 128 129 /* 130 * Bit Field of Register PIMR_AGENT2ISH 131 * AGENT2ISH_BCISC: Mask Bit For AGENT2IBCISC 132 * BitOffset : 27 133 * BitWidth : 1 134 * AccessType: RW 135 * ResetValue: (uint32_t)0x0 136 */ 137 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_BCISC, 27, 1, RW, (uint32_t)0x0); 138 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_BCISC, 0, 0); 139 SEDI_RBFV_DEFINE(IPC, PIMR_AGENT2ISH, AGENT2ISH_BCISC, 1, 1); 140 141 /* 142 * Bit Field of Register PIMR_AGENT2ISH 143 * RESERVED0: Reserved Field 144 * BitOffset : 28 145 * BitWidth : 4 146 * AccessType: RO 147 * ResetValue: (uint32_t)0x0 148 */ 149 SEDI_RBF_DEFINE(IPC, PIMR_AGENT2ISH, RESERVED0, 28, 4, RO, (uint32_t)0x0); 150 151 /* ********* IPC PIMR_ISH2AGENT *********** 152 * 153 * Register of SEDI IPC 154 * PIMR_ISH2AGENT: Peripheral Interrupt Mask - IRQ to AGENT 155 * AddressOffset : 0x8 156 * AccessType : RW 157 * WritableBitMask: 0x101 158 * ResetValue : (uint32_t)0x0 159 */ 160 SEDI_REG_DEFINE(IPC, PIMR_ISH2AGENT, 0x8, RW, (uint32_t)0x101, (uint32_t)0x0); 161 162 /* 163 * Bit Field of Register PIMR_ISH2AGENT 164 * ISH2AGENT_DB: Outbound Ipc Request From ISH2AGENT Mask 165 * BitOffset : 0 166 * BitWidth : 1 167 * AccessType: RW 168 * ResetValue: (uint32_t)0x0 169 */ 170 SEDI_RBF_DEFINE(IPC, PIMR_ISH2AGENT, ISH2AGENT_DB, 0, 1, RW, (uint32_t)0x0); 171 SEDI_RBFV_DEFINE(IPC, PIMR_ISH2AGENT, ISH2AGENT_DB, 0, 0); 172 SEDI_RBFV_DEFINE(IPC, PIMR_ISH2AGENT, ISH2AGENT_DB, 1, 1); 173 174 /* 175 * Bit Field of Register PIMR_ISH2AGENT 176 * RESERVED1: Reserved Field 177 * BitOffset : 1 178 * BitWidth : 7 179 * AccessType: RO 180 * ResetValue: (uint32_t)0x0 181 */ 182 SEDI_RBF_DEFINE(IPC, PIMR_ISH2AGENT, RESERVED1, 1, 7, RO, (uint32_t)0x0); 183 184 /* 185 * Bit Field of Register PIMR_ISH2AGENT 186 * AGENT2ISH_BC: AGENT2ISH Busy Clear Interrupt Mask 187 * BitOffset : 8 188 * BitWidth : 1 189 * AccessType: RW 190 * ResetValue: (uint32_t)0x0 191 */ 192 SEDI_RBF_DEFINE(IPC, PIMR_ISH2AGENT, AGENT2ISH_BC, 8, 1, RW, (uint32_t)0x0); 193 SEDI_RBFV_DEFINE(IPC, PIMR_ISH2AGENT, AGENT2ISH_BC, 0, 0); 194 SEDI_RBFV_DEFINE(IPC, PIMR_ISH2AGENT, AGENT2ISH_BC, 1, 1); 195 196 /* 197 * Bit Field of Register PIMR_ISH2AGENT 198 * RESERVED0: Reserved Field 199 * BitOffset : 9 200 * BitWidth : 23 201 * AccessType: RO 202 * ResetValue: (uint32_t)0x0 203 */ 204 SEDI_RBF_DEFINE(IPC, PIMR_ISH2AGENT, RESERVED0, 9, 23, RO, (uint32_t)0x0); 205 206 /* ********* IPC PISR_ISH2AGENT *********** 207 * 208 * Register of SEDI IPC 209 * PISR_ISH2AGENT: Peripheral Interrupt Status - IRQ to AGENT 210 * AddressOffset : 0x0c 211 * AccessType : RW 212 * WritableBitMask: 0x101 213 * ResetValue : (uint32_t)0x0 214 */ 215 SEDI_REG_DEFINE(IPC, PISR_ISH2AGENT, 0x0c, RW, (uint32_t)0x101, (uint32_t)0x0); 216 217 /* 218 * Bit Field of Register PISR_ISH2AGENT 219 * ISH2AGENT_DB: Outbound Ipc Request From ISH2AGENT Status 220 * BitOffset : 0 221 * BitWidth : 1 222 * AccessType: RO_V 223 * ResetValue: (uint32_t)0x0 224 */ 225 SEDI_RBF_DEFINE(IPC, PISR_ISH2AGENT, ISH2AGENT_DB, 0, 1, RO_V, (uint32_t)0x0); 226 SEDI_RBFV_DEFINE(IPC, PISR_ISH2AGENT, ISH2AGENT_DB, 0, 0); 227 SEDI_RBFV_DEFINE(IPC, PISR_ISH2AGENT, ISH2AGENT_DB, 1, 1); 228 229 /* 230 * Bit Field of Register PISR_ISH2AGENT 231 * RESERVED1: Reserved Field 232 * BitOffset : 1 233 * BitWidth : 7 234 * AccessType: RO 235 * ResetValue: (uint32_t)0x0 236 */ 237 SEDI_RBF_DEFINE(IPC, PISR_ISH2AGENT, RESERVED1, 1, 7, RO, (uint32_t)0x0); 238 239 /* 240 * Bit Field of Register PISR_ISH2AGENT 241 * AGENT2ISH_BC: AGENT2ISH Busy Clear Interrupt Status 242 * BitOffset : 8 243 * BitWidth : 1 244 * AccessType: RW_1C_V 245 * ResetValue: (uint32_t)0x0 246 */ 247 SEDI_RBF_DEFINE(IPC, PISR_ISH2AGENT, AGENT2ISH_BC, 8, 1, RW_1C_V, (uint32_t)0x0); 248 SEDI_RBFV_DEFINE(IPC, PISR_ISH2AGENT, AGENT2ISH_BC, 0, 0); 249 SEDI_RBFV_DEFINE(IPC, PISR_ISH2AGENT, AGENT2ISH_BC, 1, 1); 250 251 /* 252 * Bit Field of Register PISR_ISH2AGENT 253 * RESERVED0: Reserved Field 254 * BitOffset : 9 255 * BitWidth : 23 256 * AccessType: RO 257 * ResetValue: (uint32_t)0x0 258 */ 259 SEDI_RBF_DEFINE(IPC, PISR_ISH2AGENT, RESERVED0, 9, 23, RO, (uint32_t)0x0); 260 261 /* ********* IPC CIM_AGENT *********** 262 * 263 * Register of SEDI IPC 264 * CIM_AGENT: AGENT Channel Interrupt Mask 265 * AddressOffset : 0x10 266 * AccessType : RW 267 * WritableBitMask: 0x1 268 * ResetValue : (uint32_t)0x0 269 */ 270 SEDI_REG_DEFINE(IPC, CIM_AGENT, 0x10, RW, (uint32_t)0x1, (uint32_t)0x0); 271 272 /* 273 * Bit Field of Register CIM_AGENT 274 * CH_INTR_MASK: Channel Intrupt Mask 275 * BitOffset : 0 276 * BitWidth : 1 277 * AccessType: RW 278 * ResetValue: (uint32_t)0x0 279 */ 280 SEDI_RBF_DEFINE(IPC, CIM_AGENT, CH_INTR_MASK, 0, 1, RW, (uint32_t)0x0); 281 SEDI_RBFV_DEFINE(IPC, CIM_AGENT, CH_INTR_MASK, 0, 0); 282 SEDI_RBFV_DEFINE(IPC, CIM_AGENT, CH_INTR_MASK, 1, 1); 283 284 /* 285 * Bit Field of Register CIM_AGENT 286 * RESERVED0: Reserved Field 287 * BitOffset : 1 288 * BitWidth : 31 289 * AccessType: RO 290 * ResetValue: (uint32_t)0x0 291 */ 292 SEDI_RBF_DEFINE(IPC, CIM_AGENT, RESERVED0, 1, 31, RO, (uint32_t)0x0); 293 294 /* ********* IPC CIS_AGENT *********** 295 * 296 * Register of SEDI IPC 297 * CIS_AGENT: AGENT Channel Interrupt Status 298 * AddressOffset : 0x14 299 * AccessType : RO 300 * WritableBitMask: 0x1 301 * ResetValue : (uint32_t)0x0 302 */ 303 SEDI_REG_DEFINE(IPC, CIS_AGENT, 0x14, RO, (uint32_t)0x1, (uint32_t)0x0); 304 305 /* 306 * Bit Field of Register CIS_AGENT 307 * CH_INTR_STATUS: Channel Interrupt Status 308 * BitOffset : 0 309 * BitWidth : 1 310 * AccessType: RO_V 311 * ResetValue: (uint32_t)0x0 312 */ 313 SEDI_RBF_DEFINE(IPC, CIS_AGENT, CH_INTR_STATUS, 0, 1, RO_V, (uint32_t)0x0); 314 SEDI_RBFV_DEFINE(IPC, CIS_AGENT, CH_INTR_STATUS, 0, 0); 315 SEDI_RBFV_DEFINE(IPC, CIS_AGENT, CH_INTR_STATUS, 1, 1); 316 317 /* 318 * Bit Field of Register CIS_AGENT 319 * RESERVED0: Reserved Field 320 * BitOffset : 1 321 * BitWidth : 31 322 * AccessType: RO 323 * ResetValue: (uint32_t)0x0 324 */ 325 SEDI_RBF_DEFINE(IPC, CIS_AGENT, RESERVED0, 1, 31, RO, (uint32_t)0x0); 326 327 /* ********* IPC ISH_AGENT_FWSTS_AGENT *********** 328 * 329 * Register of SEDI IPC 330 * ISH_AGENT_FWSTS_AGENT: AGENT Firmware Status 331 * AddressOffset : 0x34 332 * AccessType : RW 333 * WritableBitMask: 0xffffffff 334 * ResetValue : (uint32_t)0x0 335 */ 336 SEDI_REG_DEFINE(IPC, ISH_AGENT_FWSTS_AGENT, 0x34, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 337 338 /* 339 * Bit Field of Register ISH_AGENT_FWSTS_AGENT 340 * ISH_AGENT_FWSTS: AGENT Firmware Status Register 341 * BitOffset : 0 342 * BitWidth : 32 343 * AccessType: RW 344 * ResetValue: (uint32_t)0x0 345 */ 346 SEDI_RBF_DEFINE(IPC, ISH_AGENT_FWSTS_AGENT, ISH_AGENT_FWSTS, 0, 32, RW, (uint32_t)0x0); 347 348 /* ********* IPC ISH_AGENT_COMM_AGENT *********** 349 * 350 * Register of SEDI IPC 351 * ISH_AGENT_COMM_AGENT: AGENT Communication 352 * AddressOffset : 0x38 353 * AccessType : RW 354 * WritableBitMask: 0xffffffff 355 * ResetValue : (uint32_t)0x0 356 */ 357 SEDI_REG_DEFINE(IPC, ISH_AGENT_COMM_AGENT, 0x38, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 358 359 /* 360 * Bit Field of Register ISH_AGENT_COMM_AGENT 361 * AGENT_COMM: AGENT Communication Register 362 * BitOffset : 0 363 * BitWidth : 32 364 * AccessType: RW 365 * ResetValue: (uint32_t)0x0 366 */ 367 SEDI_RBF_DEFINE(IPC, ISH_AGENT_COMM_AGENT, AGENT_COMM, 0, 32, RW, (uint32_t)0x0); 368 369 /* ********* IPC AGENT2ISH_DOORBELL_AGENT *********** 370 * 371 * Register of SEDI IPC 372 * AGENT2ISH_DOORBELL_AGENT: Inbound Doorbell AGENT To ISH 373 * AddressOffset : 0x48 374 * AccessType : RW 375 * WritableBitMask: 0xffffffff 376 * ResetValue : (uint32_t)0x0 377 */ 378 SEDI_REG_DEFINE(IPC, AGENT2ISH_DOORBELL_AGENT, 0x48, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 379 380 /* 381 * Bit Field of Register AGENT2ISH_DOORBELL_AGENT 382 * PAYLOAD_31BIT: AGENT2ISH Doorbell Payload 383 * BitOffset : 0 384 * BitWidth : 31 385 * AccessType: RW 386 * ResetValue: (uint32_t)0x0 387 */ 388 SEDI_RBF_DEFINE(IPC, AGENT2ISH_DOORBELL_AGENT, PAYLOAD_31BIT, 0, 31, RW, (uint32_t)0x0); 389 390 /* 391 * Bit Field of Register AGENT2ISH_DOORBELL_AGENT 392 * BUSY: AGENT2ISH Doorbell Busy Bit 393 * BitOffset : 31 394 * BitWidth : 1 395 * AccessType: RW 396 * ResetValue: (uint32_t)0x0 397 */ 398 SEDI_RBF_DEFINE(IPC, AGENT2ISH_DOORBELL_AGENT, BUSY, 31, 1, RW, (uint32_t)0x0); 399 SEDI_RBFV_DEFINE(IPC, AGENT2ISH_DOORBELL_AGENT, BUSY, 0, 0); 400 SEDI_RBFV_DEFINE(IPC, AGENT2ISH_DOORBELL_AGENT, BUSY, 1, 1); 401 402 /* ********* IPC ISH2AGENT_DOORBELL_AGENT *********** 403 * 404 * Register of SEDI IPC 405 * ISH2AGENT_DOORBELL_AGENT: Outbound DoorbellISH To AGENT 406 * AddressOffset : 0x54 407 * AccessType : RW 408 * WritableBitMask: 0xffffffff 409 * ResetValue : (uint32_t)0x0 410 */ 411 SEDI_REG_DEFINE(IPC, ISH2AGENT_DOORBELL_AGENT, 0x54, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 412 413 /* 414 * Bit Field of Register ISH2AGENT_DOORBELL_AGENT 415 * PAYLOAD_31BIT: ISH2AGENT Doorbell Payload 416 * BitOffset : 0 417 * BitWidth : 31 418 * AccessType: RW 419 * ResetValue: (uint32_t)0x0 420 */ 421 SEDI_RBF_DEFINE(IPC, ISH2AGENT_DOORBELL_AGENT, PAYLOAD_31BIT, 0, 31, RW, (uint32_t)0x0); 422 423 /* 424 * Bit Field of Register ISH2AGENT_DOORBELL_AGENT 425 * BUSY: ISH2AGENT Doorbell Busy 426 * BitOffset : 31 427 * BitWidth : 1 428 * AccessType: RW 429 * ResetValue: (uint32_t)0x0 430 */ 431 SEDI_RBF_DEFINE(IPC, ISH2AGENT_DOORBELL_AGENT, BUSY, 31, 1, RW, (uint32_t)0x0); 432 SEDI_RBFV_DEFINE(IPC, ISH2AGENT_DOORBELL_AGENT, BUSY, 0, 0); 433 SEDI_RBFV_DEFINE(IPC, ISH2AGENT_DOORBELL_AGENT, BUSY, 1, 1); 434 435 /* ********* IPC ISH2AGENT_MSG_AGENT *********** 436 * 437 * Register of SEDI IPC 438 * ISH2AGENT_MSG_AGENT: Outbound Inter Processor Message 1 From ISH To AGENT 439 * AddressOffset : 0x60 440 * AccessType : RW 441 * WritableBitMask: 0xffffffff 442 * ResetValue : (uint32_t)0x0 443 */ 444 SEDI_REG_DEFINE(IPC, ISH2AGENT_MSG_AGENT, 0x60, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 445 446 /* 447 * Bit Field of Register ISH2AGENT_MSG_AGENT 448 * MSG: Outbound message register from ISH to AGENT 449 * BitOffset : 0 450 * BitWidth : 32 451 * AccessType: RW 452 * ResetValue: (uint32_t)0x0 453 */ 454 SEDI_RBF_DEFINE(IPC, ISH2AGENT_MSG_AGENT, MSG, 0, 32, RW, (uint32_t)0x0); 455 456 /* ********* IPC AGENT2ISH_MSG_AGENT *********** 457 * 458 * Register of SEDI IPC 459 * AGENT2ISH_MSG_AGENT: Inbound Inter Processor Message 1 From AGENT To ISH 460 * AddressOffset : 0xe0 461 * AccessType : RW 462 * WritableBitMask: 0xffffffff 463 * ResetValue : (uint32_t)0x0 464 */ 465 SEDI_REG_DEFINE(IPC, AGENT2ISH_MSG_AGENT, 0xe0, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 466 467 /* 468 * Bit Field of Register AGENT2ISH_MSG_AGENT 469 * MSG: Inbound message register from AGENT to ISH 470 * BitOffset : 0 471 * BitWidth : 32 472 * AccessType: RW 473 * ResetValue: (uint32_t)0x0 474 */ 475 SEDI_RBF_DEFINE(IPC, AGENT2ISH_MSG_AGENT, MSG, 0, 32, RW, (uint32_t)0x0); 476 477 /* ********* IPC REMAP_AGENT *********** 478 * 479 * Register of SEDI IPC 480 * REMAP_AGENT: Remap0 For AGENT 481 * AddressOffset : 0x360 482 * AccessType : RW 483 * WritableBitMask: 0xffffffff 484 * ResetValue : (uint32_t)0x0 485 */ 486 SEDI_REG_DEFINE(IPC, REMAP_AGENT, 0x360, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 487 488 /* 489 * Bit Field of Register REMAP_AGENT 490 * REMAP: Remap Address Register 491 * BitOffset : 0 492 * BitWidth : 32 493 * AccessType: RW 494 * ResetValue: (uint32_t)0x0 495 */ 496 SEDI_RBF_DEFINE(IPC, REMAP_AGENT, REMAP, 0, 32, RW, (uint32_t)0x0); 497 498 /* ********* IPC ISH_IPC_BUSY_CLEAR_AGENT *********** 499 * 500 * Register of SEDI IPC 501 * ISH_IPC_BUSY_CLEAR_AGENT: ISH IPC Busy Clear For AGENT 502 * AddressOffset : 0x378 503 * AccessType : RW 504 * WritableBitMask: 0x1 505 * ResetValue : (uint32_t)0x0 506 */ 507 SEDI_REG_DEFINE(IPC, ISH_IPC_BUSY_CLEAR_AGENT, 0x378, RW, (uint32_t)0x1, (uint32_t)0x0); 508 509 /* 510 * Bit Field of Register ISH_IPC_BUSY_CLEAR_AGENT 511 * ISH2AGENT_BUSY_CLEAR: Busy Clear Interrupt From ISH2AGENT 512 * BitOffset : 0 513 * BitWidth : 1 514 * AccessType: RW_1C_V 515 * ResetValue: (uint32_t)0x0 516 */ 517 SEDI_RBF_DEFINE(IPC, ISH_IPC_BUSY_CLEAR_AGENT, ISH2AGENT_BUSY_CLEAR, 0, 1, RW_1C_V, (uint32_t)0x0); 518 SEDI_RBFV_DEFINE(IPC, ISH_IPC_BUSY_CLEAR_AGENT, ISH2AGENT_BUSY_CLEAR, 0, 0); 519 SEDI_RBFV_DEFINE(IPC, ISH_IPC_BUSY_CLEAR_AGENT, ISH2AGENT_BUSY_CLEAR, 1, 1); 520 521 /* 522 * Bit Field of Register ISH_IPC_BUSY_CLEAR_AGENT 523 * RESERVED0: Reserved Field 524 * BitOffset : 1 525 * BitWidth : 31 526 * AccessType: RO 527 * ResetValue: (uint32_t)0x0 528 */ 529 SEDI_RBF_DEFINE(IPC, ISH_IPC_BUSY_CLEAR_AGENT, RESERVED0, 1, 31, RO, (uint32_t)0x0); 530 531 /* ********* IPC IPC_D0I3C_AGENT *********** 532 * 533 * Register of SEDI IPC 534 * IPC_D0I3C_AGENT: D0i3 Control For AGENT 535 * AddressOffset : 0x6d0 536 * AccessType : RW 537 * WritableBitMask: 0x1f 538 * ResetValue : (uint32_t)0x8 539 */ 540 SEDI_REG_DEFINE(IPC, IPC_D0I3C_AGENT, 0x6d0, RW, (uint32_t)0x1f, (uint32_t)0x8); 541 542 /* 543 * Bit Field of Register IPC_D0I3C_AGENT 544 * CIP: Command In Progress 545 * BitOffset : 0 546 * BitWidth : 1 547 * AccessType: RW_1C_V 548 * ResetValue: (uint32_t)0x0 549 */ 550 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, CIP, 0, 1, RW_1C_V, (uint32_t)0x0); 551 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, CIP, 0, 0); 552 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, CIP, 1, 1); 553 554 /* 555 * Bit Field of Register IPC_D0I3C_AGENT 556 * IR: Interrupt Required 557 * BitOffset : 1 558 * BitWidth : 1 559 * AccessType: RW 560 * ResetValue: (uint32_t)0x0 561 */ 562 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, IR, 1, 1, RW, (uint32_t)0x0); 563 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, IR, 0, 0); 564 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, IR, 1, 1); 565 566 /* 567 * Bit Field of Register IPC_D0I3C_AGENT 568 * D0i3: D0i3 State 569 * BitOffset : 2 570 * BitWidth : 1 571 * AccessType: RW 572 * ResetValue: (uint32_t)0x0 573 */ 574 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, D0i3, 2, 1, RW, (uint32_t)0x0); 575 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, D0i3, 0, 0); 576 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, D0i3, 1, 1); 577 578 /* 579 * Bit Field of Register IPC_D0I3C_AGENT 580 * RR: Restore Required 581 * BitOffset : 3 582 * BitWidth : 1 583 * AccessType: RW_1C 584 * ResetValue: (uint32_t)0x1 585 */ 586 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, RR, 3, 1, RW_1C, (uint32_t)0x1); 587 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, RR, 0, 0); 588 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, RR, 1, 1); 589 590 /* 591 * Bit Field of Register IPC_D0I3C_AGENT 592 * IRC: Interrupt Request Capable 593 * BitOffset : 4 594 * BitWidth : 1 595 * AccessType: RO_V 596 * ResetValue: (uint32_t)0x0 597 */ 598 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, IRC, 4, 1, RO_V, (uint32_t)0x0); 599 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, IRC, 0, 0); 600 SEDI_RBFV_DEFINE(IPC, IPC_D0I3C_AGENT, IRC, 1, 1); 601 602 /* 603 * Bit Field of Register IPC_D0I3C_AGENT 604 * RESERVED0: Reserved 605 * BitOffset : 5 606 * BitWidth : 27 607 * AccessType: RO 608 * ResetValue: (uint32_t)0x0 609 */ 610 SEDI_RBF_DEFINE(IPC, IPC_D0I3C_AGENT, RESERVED0, 5, 27, RO, (uint32_t)0x0); 611 612 /* ********* IPC AGENT2ISH_CSR_AGENT *********** 613 * 614 * Register of SEDI IPC 615 * AGENT2ISH_CSR_AGENT: AGENT To ISH Control Status 616 * AddressOffset : 0x6d4 617 * AccessType : RW 618 * WritableBitMask: 0xffffffff 619 * ResetValue : (uint32_t)0x0 620 */ 621 SEDI_REG_DEFINE(IPC, AGENT2ISH_CSR_AGENT, 0x6d4, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 622 623 /* 624 * Bit Field of Register AGENT2ISH_CSR_AGENT 625 * CSR: Control Status 626 * BitOffset : 0 627 * BitWidth : 32 628 * AccessType: RW_1S_V 629 * ResetValue: (uint32_t)0x0 630 */ 631 SEDI_RBF_DEFINE(IPC, AGENT2ISH_CSR_AGENT, CSR, 0, 32, RW_1S_V, (uint32_t)0x0); 632 633 /* ********* IPC AGENT2ISH_CSR_CLR_AGENT *********** 634 * 635 * Register of SEDI IPC 636 * AGENT2ISH_CSR_CLR_AGENT: AGENT To ISH Status Clear 637 * AddressOffset : 0x6d8 638 * AccessType : RW 639 * WritableBitMask: 0xffffffff 640 * ResetValue : (uint32_t)0x0 641 */ 642 SEDI_REG_DEFINE(IPC, AGENT2ISH_CSR_CLR_AGENT, 0x6d8, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 643 644 /* 645 * Bit Field of Register AGENT2ISH_CSR_CLR_AGENT 646 * CSR: Status Clear 647 * BitOffset : 0 648 * BitWidth : 32 649 * AccessType: RW_1C_V 650 * ResetValue: (uint32_t)0x0 651 */ 652 SEDI_RBF_DEFINE(IPC, AGENT2ISH_CSR_CLR_AGENT, CSR, 0, 32, RW_1C_V, (uint32_t)0x0); 653 654 /* ********* IPC SPARE *********** 655 * 656 * Register of SEDI IPC 657 * SPARE: Spare Register 658 * AddressOffset : 0x700 659 * AccessType : RW 660 * WritableBitMask: 0xffffffff 661 * ResetValue : (uint32_t)0x0 662 */ 663 SEDI_REG_DEFINE(IPC, SPARE, 0x700, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 664 665 /* 666 * Bit Field of Register SPARE 667 * SPARE: Spare 668 * BitOffset : 0 669 * BitWidth : 32 670 * AccessType: RW 671 * ResetValue: (uint32_t)0x0 672 */ 673 SEDI_RBF_DEFINE(IPC, SPARE, SPARE, 0, 32, RW, (uint32_t)0x0); 674 675 /* 676 * Registers' Address Map Structure 677 */ 678 679 typedef struct { 680 /* Peripheral Interrupt Status - IRQ to ISH */ 681 __IO_RW uint32_t pisr_agent2ish; 682 683 /* Peripheral Interrupt Mask - IRQ to ISH */ 684 __IO_RW uint32_t pimr_agent2ish; 685 686 /* Peripheral Interrupt Mask - IRQ to AGENT */ 687 __IO_RW uint32_t pimr_ish2agent; 688 689 /* Peripheral Interrupt Status - IRQ to AGENT */ 690 __IO_RW uint32_t pisr_ish2agent; 691 692 /* AGENT Channel Interrupt Mask */ 693 __IO_RW uint32_t cim_agent; 694 695 /* AGENT Channel Interrupt Status */ 696 __IO_R uint32_t cis_agent; 697 698 /* Reserved */ 699 __IO_RW uint32_t reserved0[7]; 700 701 /* AGENT Firmware Status */ 702 __IO_RW uint32_t ish_agent_fwsts_agent; 703 704 /* AGENT Communication */ 705 __IO_RW uint32_t ish_agent_comm_agent; 706 707 /* Reserved */ 708 __IO_RW uint32_t reserved1[3]; 709 710 /* Inbound Doorbell AGENT To ISH */ 711 __IO_RW uint32_t agent2ish_doorbell_agent; 712 713 /* Reserved */ 714 __IO_RW uint32_t reserved2[2]; 715 716 /* Outbound DoorbellISH To AGENT */ 717 __IO_RW uint32_t ish2agent_doorbell_agent; 718 719 /* Reserved */ 720 __IO_RW uint32_t reserved3[2]; 721 722 /* Outbound Inter Processor Message 1 From ISH To AGENT */ 723 __IO_RW uint32_t ish2agent_msg_agent[32]; 724 725 /* Inbound Inter Processor Message 1 From AGENT To ISH */ 726 __IO_RW uint32_t agent2ish_msg_agent[32]; 727 728 /* Reserved */ 729 __IO_RW uint32_t reserved4[128]; 730 731 /* Remap0 For AGENT */ 732 __IO_RW uint32_t remap_agent[6]; 733 734 /* ISH IPC Busy Clear For AGENT */ 735 __IO_RW uint32_t ish_ipc_busy_clear_agent; 736 737 /* Reserved */ 738 __IO_RW uint32_t reserved5[213]; 739 740 /* D0i3 Control For AGENT */ 741 __IO_RW uint32_t ipc_d0i3c_agent; 742 743 /* AGENT To ISH Control Status */ 744 __IO_RW uint32_t agent2ish_csr_agent; 745 746 /* AGENT To ISH Status Clear */ 747 __IO_RW uint32_t agent2ish_csr_clr_agent; 748 749 /* Reserved */ 750 __IO_RW uint32_t reserved6[9]; 751 752 /* Spare Register */ 753 __IO_RW uint32_t spare; 754 755 } sedi_ipc_regs_t; 756 757 758 #endif /* _SEDI_IPC_REGS_H_ */ 759
