1 /*
2 * Copyright (c) 2023 Analog Devices Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/drivers/sensor.h>
8 #include <zephyr/kernel.h>
9 #include <zephyr/device.h>
10 #include <string.h>
11 #include <zephyr/init.h>
12 #include <zephyr/sys/printk.h>
13 #include <zephyr/sys/__assert.h>
14 #include <stdlib.h>
15 #include <zephyr/logging/log.h>
16
17 #include "adxl367.h"
18
19 #define DT_DRV_COMPAT adi_adxl367
20
21 LOG_MODULE_REGISTER(ADXL367, CONFIG_SENSOR_LOG_LEVEL);
22
23 static const uint8_t adxl367_scale_mul[3] = {1, 2, 4};
24 static uint8_t samples_per_set;
25
26 /**
27 * @brief Configures activity detection.
28 *
29 * @param dev - The device structure.
30 * @param th - Structure holding the activity threshold information:
31 * Enable/Disable Activity detection
32 * Enable/Disable Referenced Activity detection
33 * Set Threshold value
34 * @return 0 in case of success, negative error code otherwise.
35 */
adxl367_setup_activity_detection(const struct device * dev,const struct adxl367_activity_threshold * th)36 static int adxl367_setup_activity_detection(const struct device *dev,
37 const struct adxl367_activity_threshold *th)
38 {
39 struct adxl367_data *data = dev->data;
40 int ret;
41
42
43 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,
44 ADXL367_ACT_INACT_CTL_ACT_EN_MSK |
45 ADXL367_ACT_INACT_CTL_ACT_REF_MSK,
46 FIELD_PREP(ADXL367_ACT_INACT_CTL_ACT_EN_MSK, th->enable) |
47 FIELD_PREP(ADXL367_ACT_INACT_CTL_ACT_REF_MSK,
48 th->referenced));
49 if (ret != 0) {
50 return ret;
51 }
52
53 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_H, ADXL367_THRESH_H_MSK,
54 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6));
55 if (ret != 0) {
56 return ret;
57 }
58
59 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_ACT_L, ADXL367_THRESH_L_MSK,
60 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F));
61 }
62
63 /**
64 * @brief Configures activity detection.
65 *
66 * @param dev - The device structure.
67 * @param th - Structure holding the inactivity threshold information:
68 * Enable/Disable inactivity detection
69 * Enable/Disable Referenced inactivity detection
70 * Set Threshold value
71 *
72 * @return 0 in case of success, negative error code otherwise.
73 */
adxl367_setup_inactivity_detection(const struct device * dev,const struct adxl367_activity_threshold * th)74 static int adxl367_setup_inactivity_detection(const struct device *dev,
75 const struct adxl367_activity_threshold *th)
76 {
77 struct adxl367_data *data = dev->data;
78 int ret;
79
80 ret = data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,
81 ADXL367_ACT_INACT_CTL_INACT_EN_MSK |
82 ADXL367_ACT_INACT_CTL_INACT_REF_MSK,
83 FIELD_PREP(ADXL367_ACT_INACT_CTL_INACT_EN_MSK,
84 th->enable) |
85 FIELD_PREP(ADXL367_ACT_INACT_CTL_INACT_REF_MSK,
86 th->referenced));
87 if (ret != 0) {
88 return ret;
89 }
90
91 ret = data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_H, ADXL367_THRESH_H_MSK,
92 FIELD_PREP(ADXL367_THRESH_H_MSK, th->value >> 6));
93 if (ret != 0) {
94 return ret;
95 }
96
97 return data->hw_tf->write_reg_mask(dev, ADXL367_THRESH_INACT_L, ADXL367_THRESH_L_MSK,
98 FIELD_PREP(ADXL367_THRESH_L_MSK, th->value & 0x3F));
99 }
100
101 /**
102 * @brief Set the mode of operation.
103 *
104 * @param dev - The device structure.
105 * @param op_mode - Mode of operation.
106 * Accepted values: ADXL367_STANDBY
107 * ADXL367_MEASURE
108 *
109 * @return 0 in case of success, negative error code otherwise.
110 */
111 #ifdef CONFIG_ADXL367_STREAM
adxl367_set_op_mode(const struct device * dev,enum adxl367_op_mode op_mode)112 int adxl367_set_op_mode(const struct device *dev,
113 enum adxl367_op_mode op_mode)
114 #else
115 static int adxl367_set_op_mode(const struct device *dev,
116 enum adxl367_op_mode op_mode)
117 #endif /* CONFIG_ADXL367_STREAM */
118 {
119 struct adxl367_data *data = dev->data;
120 int ret;
121
122 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,
123 ADXL367_POWER_CTL_MEASURE_MSK,
124 FIELD_PREP(ADXL367_POWER_CTL_MEASURE_MSK, op_mode));
125 if (ret != 0) {
126 return ret;
127 }
128
129 if (op_mode == ADXL367_MEASURE) {
130 /* Wait 100 ms to allow the acceleration outputs to settle */
131 k_sleep(K_MSEC(100));
132 }
133
134 #ifdef CONFIG_ADXL367_STREAM
135 data->pwr_reg &= ~ADXL367_POWER_CTL_MEASURE_MSK;
136 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_MEASURE_MSK, op_mode);
137 #endif /* CONFIG_ADXL372_STREAM */
138
139 return 0;
140 }
141
142 /**
143 * @brief Autosleep. When set to 1, autosleep is enabled, and the device enters
144 * wake-up mode automatically upon detection of inactivity.
145 *
146 * @param dev - The device structure.
147 * @param enable - Accepted values: true
148 * false
149 *
150 * @return 0 in case of success, negative error code otherwise.
151 */
adxl367_set_autosleep(const struct device * dev,bool enable)152 static int adxl367_set_autosleep(const struct device *dev, bool enable)
153 {
154 int ret;
155 struct adxl367_data *data = dev->data;
156
157 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,
158 ADXL367_POWER_CTL_AUTOSLEEP_MSK,
159 FIELD_PREP(ADXL367_POWER_CTL_AUTOSLEEP_MSK, enable));
160
161 #ifdef CONFIG_ADXL367_STREAM
162 if (ret == 0) {
163 data->pwr_reg &= ~ADXL367_POWER_CTL_AUTOSLEEP_MSK;
164 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_AUTOSLEEP_MSK, enable);
165 }
166 #endif /* CONFIG_ADXL372_STREAM */
167
168 return ret;
169 }
170
171 /**
172 * @brief Noise Mode. When set to 1, low noise mode is enabled
173 *
174 * @param dev - The device structure.
175 * @param enable - Accepted values: true
176 * false
177 *
178 * @return 0 in case of success, negative error code otherwise.
179 */
adxl367_set_low_noise(const struct device * dev,bool enable)180 static int adxl367_set_low_noise(const struct device *dev, bool enable)
181 {
182 int ret;
183 struct adxl367_data *data = dev->data;
184
185 ret = data->hw_tf->write_reg_mask(dev, ADXL367_POWER_CTL,
186 ADXL367_POWER_CTL_NOISE_MSK,
187 FIELD_PREP(ADXL367_POWER_CTL_NOISE_MSK, enable));
188
189 #ifdef CONFIG_ADXL367_STREAM
190 if (ret == 0) {
191 data->pwr_reg &= ~ADXL367_POWER_CTL_NOISE_MSK;
192 data->pwr_reg |= FIELD_PREP(ADXL367_POWER_CTL_NOISE_MSK, enable);
193 }
194 #endif /* CONFIG_ADXL372_STREAM */
195
196 return ret;
197 }
198
199 /**
200 * @brief Link/Loop Activity Processing.
201 *
202 * @param dev - The device structure.
203 * @param mode - Mode of operation.
204 * Accepted values: ADXL367_DEFAULT
205 * ADXL367_LINKED
206 * ADXL367_LOOPED
207 *
208 * @return 0 in case of success, negative error code otherwise.
209 */
adxl367_set_act_proc_mode(const struct device * dev,enum adxl367_act_proc_mode mode)210 static int adxl367_set_act_proc_mode(const struct device *dev,
211 enum adxl367_act_proc_mode mode)
212 {
213 struct adxl367_data *data = dev->data;
214
215 return data->hw_tf->write_reg_mask(dev, ADXL367_ACT_INACT_CTL,
216 ADXL367_ACT_INACT_CTL_LINKLOOP_MSK,
217 FIELD_PREP(ADXL367_ACT_INACT_CTL_LINKLOOP_MSK, mode));
218 }
219
220
221 /**
222 * @brief Selects the Output Data Rate of the device.
223 * @param dev - The device structure.
224 * @param odr - Output Data Rate option.
225 * Accepted values: ADXL367_ODR_12P5HZ,
226 * ADXL367_ODR_25HZ,
227 * ADXL367_ODR_50HZ,
228 * ADXL367_ODR_100HZ,
229 * ADXL367_ODR_200HZ,
230 * ADXL367_ODR_400HZ
231 * @return 0 in case of success, negative error code otherwise.
232 */
adxl367_set_output_rate(const struct device * dev,enum adxl367_odr odr)233 int adxl367_set_output_rate(const struct device *dev, enum adxl367_odr odr)
234 {
235 struct adxl367_data *data = dev->data;
236 int ret;
237
238 ret = data->hw_tf->write_reg_mask(dev,
239 ADXL367_FILTER_CTL,
240 ADXL367_FILTER_CTL_ODR_MSK,
241 FIELD_PREP(ADXL367_FILTER_CTL_ODR_MSK, odr));
242
243 #ifdef CONFIG_ADXL367_STREAM
244 if (ret == 0) {
245 data->odr = odr;
246 }
247 #endif /* CONFIG_ADXL367_STREAM */
248
249 return ret;
250 }
251
252 /**
253 * @brief Selects the measurement range.
254 *
255 * @param dev - The device structure.
256 * @param range - Range option.
257 * Accepted values: ADXL367_2G_RANGE, +/- 2g
258 * ADXL367_4G_RANGE, +/- 4g
259 * ADXL367_8G_RANGE +/- 8g
260 *
261 * @return 0 in case of success, negative error code otherwise.
262 */
adxl367_set_range(const struct device * dev,enum adxl367_range range)263 int adxl367_set_range(const struct device *dev, enum adxl367_range range)
264 {
265 struct adxl367_data *data = dev->data;
266 int ret;
267
268 ret = data->hw_tf->write_reg_mask(dev,
269 ADXL367_FILTER_CTL,
270 ADXL367_FILTER_CTL_RANGE_MSK,
271 FIELD_PREP(ADXL367_FILTER_CTL_RANGE_MSK, range));
272
273 #ifdef CONFIG_ADXL367_STREAM
274 if (ret == 0) {
275 data->range = range;
276 }
277 #endif /* CONFIG_ADXL367_STREAM */
278
279 return ret;
280 }
281
282 /**
283 * @brief Set the activity timer
284 *
285 * @param dev - The device structure.
286 * @param time - The value set in this register.
287 *
288 * @return 0 in case of success, negative error code otherwise.
289 */
adxl367_set_activity_time(const struct device * dev,uint8_t time)290 static int adxl367_set_activity_time(const struct device *dev, uint8_t time)
291 {
292 struct adxl367_data *data = dev->data;
293
294 return data->hw_tf->write_reg(dev, ADXL367_TIME_ACT, time);
295 }
296
297 /**
298 * Set the inactivity timer
299 * @param dev - The device structure.
300 * @param time - is the 16-bit value set by the TIME_INACT_L register
301 * (eight LSBs) and the TIME_INACT_H register (eight MSBs).
302 * @return 0 in case of success, negative error code otherwise.
303 */
adxl367_set_inactivity_time(const struct device * dev,uint16_t time)304 static int adxl367_set_inactivity_time(const struct device *dev,
305 uint16_t time)
306 {
307 int ret;
308 struct adxl367_data *data = dev->data;
309
310 ret = data->hw_tf->write_reg(dev, ADXL367_TIME_INACT_H, time >> 8);
311 if (ret != 0) {
312 return ret;
313 }
314
315 return data->hw_tf->write_reg(dev, ADXL367_TIME_INACT_L, time & 0xFF);
316 }
317
318 /**
319 * @brief Performs self test.
320 *
321 * @param dev - The device structure.
322 *
323 * @return 0 in case of success, negative error code otherwise.
324 */
adxl367_self_test(const struct device * dev)325 int adxl367_self_test(const struct device *dev)
326 {
327 int ret;
328 struct adxl367_data *data = dev->data;
329 const struct adxl367_dev_config *cfg = dev->config;
330 int16_t x_axis_1, x_axis_2, dif, min, max;
331 uint8_t read_val[2];
332
333 uint32_t st_delay_ms;
334
335 /* 4 / ODR value in ms */
336 switch (cfg->odr) {
337 case ADXL367_ODR_12P5HZ:
338 st_delay_ms = 320;
339 break;
340 case ADXL367_ODR_25HZ:
341 st_delay_ms = 160;
342 break;
343 case ADXL367_ODR_50HZ:
344 st_delay_ms = 80;
345 break;
346 case ADXL367_ODR_100HZ:
347 st_delay_ms = 40;
348 break;
349 case ADXL367_ODR_200HZ:
350 st_delay_ms = 20;
351 break;
352 case ADXL367_ODR_400HZ:
353 st_delay_ms = 10;
354 break;
355 default:
356 return -EINVAL;
357 }
358
359 ret = adxl367_set_op_mode(dev, ADXL367_MEASURE);
360 if (ret != 0) {
361 return ret;
362 }
363
364 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_MSK,
365 FIELD_PREP(ADXL367_SELF_TEST_ST_MSK, 1));
366 if (ret != 0) {
367 return ret;
368 }
369
370 /* 4 / ODR */
371 k_sleep(K_MSEC(st_delay_ms));
372
373 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, read_val, 2);
374 if (ret != 0) {
375 return ret;
376 }
377
378 x_axis_1 = ((int16_t)read_val[0] << 6) + (read_val[1] >> 2);
379
380 /* extend sign to 16 bits */
381 if ((x_axis_1 & BIT(13)) != 0) {
382 x_axis_1 |= GENMASK(15, 14);
383 }
384
385 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST,
386 ADXL367_SELF_TEST_ST_FORCE_MSK,
387 FIELD_PREP(ADXL367_SELF_TEST_ST_FORCE_MSK, 1));
388 if (ret != 0) {
389 return ret;
390 }
391
392 /* 4 / ODR */
393 k_sleep(K_MSEC(st_delay_ms));
394
395 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, read_val, 2);
396 if (ret != 0) {
397 return ret;
398 }
399
400 x_axis_2 = ((int16_t)read_val[0] << 6) + (read_val[1] >> 2);
401
402 /* extend sign to 16 bits */
403 if ((x_axis_2 & BIT(13)) != 0) {
404 x_axis_2 |= GENMASK(15, 14);
405 }
406
407 ret = adxl367_set_op_mode(dev, ADXL367_STANDBY);
408 if (ret != 0) {
409 return ret;
410 }
411
412 ret = data->hw_tf->write_reg_mask(dev, ADXL367_SELF_TEST, ADXL367_SELF_TEST_ST_FORCE_MSK |
413 ADXL367_SELF_TEST_ST_MSK,
414 FIELD_PREP(ADXL367_SELF_TEST_ST_FORCE_MSK, 0) |
415 FIELD_PREP(ADXL367_SELF_TEST_ST_MSK, 0));
416 if (ret != 0) {
417 return ret;
418 }
419
420 dif = x_axis_2 - x_axis_1;
421 min = ADXL367_SELF_TEST_MIN * adxl367_scale_mul[data->range];
422 max = ADXL367_SELF_TEST_MAX * adxl367_scale_mul[data->range];
423
424 if ((dif >= min) && (dif <= max)) {
425 LOG_INF("ADXL367 passed self-test\n");
426 ret = 0;
427 } else {
428 LOG_ERR("ADXL367 failed self-test\n");
429 ret = -EINVAL;
430 }
431
432 return ret;
433 }
434
435 /**
436 * @brief Enables temperature reading.
437 *
438 * @param dev - The device structure.
439 * @param enable - 1 - ENABLE
440 * 2 - DISABLE
441 *
442 * @return 0 in case of success, negative error code otherwise.
443 */
adxl367_temp_read_en(const struct device * dev,bool enable)444 int adxl367_temp_read_en(const struct device *dev, bool enable)
445 {
446 struct adxl367_data *data = dev->data;
447
448 return data->hw_tf->write_reg_mask(dev,
449 ADXL367_TEMP_CTL,
450 ADXL367_TEMP_EN_MSK,
451 FIELD_PREP(ADXL367_TEMP_EN_MSK, enable));
452 }
453
454 /**
455 * @brief Sets the number of FIFO sample sets.
456 *
457 * @param dev - The device structure.
458 * @param sets_nb - Sample sets number. For example, if ADXL367_FIFO_FORMAT_XYZ
459 * is selected, a value of 2 will represent 6 entries.
460 *
461 * @return 0 in case of success, negative error code otherwise.
462 */
adxl367_set_fifo_sample_sets_nb(const struct device * dev,uint16_t sets_nb)463 int adxl367_set_fifo_sample_sets_nb(const struct device *dev,
464 uint16_t sets_nb)
465 {
466 struct adxl367_data *data = dev->data;
467 int ret;
468 uint8_t fifo_samples_msb = sets_nb & BIT(9) ? 1U : 0U;
469
470 /* bit 9 goes to FIFO_SAMPLES from ADXL367_FIFO_CONTROL */
471 ret = data->hw_tf->write_reg_mask(dev, ADXL367_FIFO_CONTROL,
472 ADXL367_FIFO_CONTROL_FIFO_SAMPLES_MSK,
473 FIELD_PREP(ADXL367_FIFO_CONTROL_FIFO_SAMPLES_MSK,
474 fifo_samples_msb));
475 if (ret != 0) {
476 return ret;
477 }
478
479 /* write last 8 bits to ADXL367_FIFO_SAMPLES */
480 return data->hw_tf->write_reg(dev, ADXL367_FIFO_SAMPLES, sets_nb & 0xFF);
481 }
482
483 /**
484 * @brief Sets FIFO mode.
485 *
486 * @param dev - The device structure.
487 * @param mode - FIFO mode.
488 * Accepted values: ADXL367_FIFO_DISABLED,
489 * ADXL367_OLDEST_SAVED,
490 * ADXL367_STREAM_MODE,
491 * ADXL367_TRIGGERED_MODE
492 *
493 * @return 0 in case of success, negative error code otherwise.
494 */
adxl367_set_fifo_mode(const struct device * dev,enum adxl367_fifo_mode mode)495 int adxl367_set_fifo_mode(const struct device *dev,
496 enum adxl367_fifo_mode mode)
497 {
498 struct adxl367_data *data = dev->data;
499
500 return data->hw_tf->write_reg_mask(dev,
501 ADXL367_FIFO_CONTROL,
502 ADXL367_FIFO_CONTROL_FIFO_MODE_MSK,
503 FIELD_PREP(ADXL367_FIFO_CONTROL_FIFO_MODE_MSK, mode));
504 }
505
506 /**
507 * @brief Sets FIFO read mode.
508 *
509 * @param dev - The device structure.
510 * @param read_mode - FIFO read mode.
511 * Accepted values: ADXL367_12B_CHID,
512 * ADXL367_8B,
513 * ADXL367_12B,
514 * ADXL367_14B_CHID
515 *
516 * @return 0 in case of success, negative error code otherwise.
517 */
adxl367_set_fifo_read_mode(const struct device * dev,enum adxl367_fifo_read_mode read_mode)518 int adxl367_set_fifo_read_mode(const struct device *dev,
519 enum adxl367_fifo_read_mode read_mode)
520 {
521 struct adxl367_data *data = dev->data;
522
523 return data->hw_tf->write_reg_mask(dev, ADXL367_ADC_CTL,
524 ADXL367_FIFO_8_12BIT_MSK,
525 FIELD_PREP(ADXL367_FIFO_8_12BIT_MSK, read_mode));
526 }
527
528 /**
529 * @brief Sets FIFO format.
530 *
531 * @param dev - The device structure.
532 * @param format - FIFO format.
533 * Accepted values: ADXL367_FIFO_FORMAT_XYZ,
534 * ADXL367_FIFO_FORMAT_X,
535 * ADXL367_FIFO_FORMAT_Y,
536 * ADXL367_FIFO_FORMAT_Z,
537 * ADXL367_FIFO_FORMAT_XYZT,
538 * ADXL367_FIFO_FORMAT_XT,
539 * ADXL367_FIFO_FORMAT_YT,
540 * ADXL367_FIFO_FORMAT_ZT,
541 * ADXL367_FIFO_FORMAT_XYZA,
542 * ADXL367_FIFO_FORMAT_XA,
543 * ADXL367_FIFO_FORMAT_YA,
544 * ADXL367_FIFO_FORMAT_ZA
545 *
546 * @return 0 in case of success, negative error code otherwise.
547 */
adxl367_set_fifo_format(const struct device * dev,enum adxl367_fifo_format format)548 int adxl367_set_fifo_format(const struct device *dev,
549 enum adxl367_fifo_format format)
550 {
551 int ret;
552 struct adxl367_data *data = dev->data;
553
554 ret = data->hw_tf->write_reg_mask(dev,
555 ADXL367_FIFO_CONTROL,
556 ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK,
557 FIELD_PREP(ADXL367_FIFO_CONTROL_FIFO_CHANNEL_MSK, format));
558 if (ret != 0) {
559 return ret;
560 }
561
562 switch (format) {
563 case ADXL367_FIFO_FORMAT_XYZ:
564 samples_per_set = 3;
565 break;
566 case ADXL367_FIFO_FORMAT_X:
567 case ADXL367_FIFO_FORMAT_Y:
568 case ADXL367_FIFO_FORMAT_Z:
569 samples_per_set = 1;
570 break;
571 case ADXL367_FIFO_FORMAT_XYZT:
572 case ADXL367_FIFO_FORMAT_XYZA:
573 samples_per_set = 4;
574 break;
575 case ADXL367_FIFO_FORMAT_XT:
576 case ADXL367_FIFO_FORMAT_YT:
577 case ADXL367_FIFO_FORMAT_ZT:
578 case ADXL367_FIFO_FORMAT_XA:
579 case ADXL367_FIFO_FORMAT_YA:
580 case ADXL367_FIFO_FORMAT_ZA:
581 samples_per_set = 2;
582 break;
583 default:
584 return -EINVAL;
585 }
586
587 return 0;
588 }
589
590 /**
591 * @brief Configures the FIFO feature. Uses ADXL367_14B_CHID read mode as
592 * default.
593 *
594 * @param dev - The device structure.
595 * @param mode - FIFO mode selection.
596 * Example: ADXL367_FIFO_DISABLED,
597 * ADXL367_OLDEST_SAVED,
598 * ADXL367_STREAM_MODE,
599 * ADXL367_TRIGGERED_MODE
600 * @param format - FIFO format selection.
601 * Example: ADXL367_FIFO_FORMAT_XYZ,
602 * ADXL367_FIFO_FORMAT_X,
603 * ADXL367_FIFO_FORMAT_Y,
604 * ADXL367_FIFO_FORMAT_Z,
605 * ADXL367_FIFO_FORMAT_XYZT,
606 * ADXL367_FIFO_FORMAT_XT,
607 * ADXL367_FIFO_FORMAT_YT,
608 * ADXL367_FIFO_FORMAT_ZT,
609 * ADXL367_FIFO_FORMAT_XYZA,
610 * ADXL367_FIFO_FORMAT_XA,
611 * ADXL367_FIFO_FORMAT_YA,
612 * ADXL367_FIFO_FORMAT_ZA
613 * @param read_mode - FIFO read mode.
614 * Accepted values: ADXL367_12B_CHID,
615 * ADXL367_8B,
616 * ADXL367_12B,
617 * ADXL367_14B_CHID
618 * @param sets_nb - Specifies the number of samples sets to store in the FIFO.
619 *
620 * @return 0 in case of success, negative error code otherwise.
621 */
adxl367_fifo_setup(const struct device * dev,enum adxl367_fifo_mode mode,enum adxl367_fifo_format format,enum adxl367_fifo_read_mode read_mode,uint8_t sets_nb)622 int adxl367_fifo_setup(const struct device *dev,
623 enum adxl367_fifo_mode mode,
624 enum adxl367_fifo_format format,
625 enum adxl367_fifo_read_mode read_mode,
626 uint8_t sets_nb)
627 {
628 int ret;
629
630 ret = adxl367_set_fifo_mode(dev, mode);
631 if (ret != 0) {
632 return ret;
633 }
634
635 ret = adxl367_set_fifo_format(dev, format);
636 if (ret != 0) {
637 return ret;
638 }
639
640 ret = adxl367_set_fifo_sample_sets_nb(dev, sets_nb);
641 if (ret != 0) {
642 return ret;
643 }
644
645 ret = adxl367_set_fifo_read_mode(dev, read_mode);
646 if (ret != 0) {
647 return ret;
648 }
649
650 #ifdef CONFIG_ADXL367_STREAM
651 struct adxl367_data *data = (struct adxl367_data *)dev->data;
652
653 data->fifo_config.fifo_mode = mode;
654 data->fifo_config.fifo_format = format;
655 data->fifo_config.fifo_samples = sets_nb;
656 data->fifo_config.fifo_read_mode = read_mode;
657 #endif /* CONFIG_ADXL367_STREAM */
658
659 return ret;
660 }
661
662 /**
663 * @brief Software reset.
664 *
665 * @param dev - The device structure.
666 *
667 * @return 0 in case of success, negative error code otherwise.
668 */
adxl367_reset(const struct device * dev)669 static int adxl367_reset(const struct device *dev)
670 {
671 int ret;
672 struct adxl367_data *data = dev->data;
673
674 ret = adxl367_set_op_mode(dev, ADXL367_STANDBY);
675 if (ret != 0) {
676 return ret;
677 }
678
679 /* Writing code 0x52 resets the device */
680 ret = data->hw_tf->write_reg(dev, ADXL367_SOFT_RESET, ADXL367_RESET_CODE);
681 if (ret != 0) {
682 return ret;
683 }
684
685 /* Delay required after performing software reset */
686 k_sleep(K_MSEC(8));
687
688 return ret;
689 }
690
691
692 /**
693 * @brief Reads the 3-axis raw data from the accelerometer.
694 *
695 * @param dev - The device structure.
696 * @param accel_data - store the XYZ axis accelerometer data.
697 *
698 * @return 0 in case of success, negative error code otherwise.
699 */
adxl367_get_accel_data(const struct device * dev,struct adxl367_xyz_accel_data * accel_data)700 int adxl367_get_accel_data(const struct device *dev,
701 struct adxl367_xyz_accel_data *accel_data)
702 {
703 int ret;
704 uint8_t xyz_values[6] = { 0 };
705 uint8_t reg_data, nready = 1U;
706 struct adxl367_data *data = dev->data;
707
708 while (nready != 0) {
709 ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data);
710 if (ret != 0) {
711 return ret;
712 }
713
714 if ((reg_data & ADXL367_STATUS_DATA_RDY) != 0) {
715 nready = 0U;
716 }
717 }
718
719 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_X_DATA_H, xyz_values, 6);
720 if (ret != 0) {
721 return ret;
722 }
723
724 /* result is 14 bits long, ignore last 2 bits from low byte */
725 accel_data->x = ((int16_t)xyz_values[0] << 6) + (xyz_values[1] >> 2);
726 accel_data->y = ((int16_t)xyz_values[2] << 6) + (xyz_values[3] >> 2);
727 accel_data->z = ((int16_t)xyz_values[4] << 6) + (xyz_values[5] >> 2);
728
729 /* extend sign to 16 bits */
730 if ((accel_data->x & BIT(13)) != 0) {
731 accel_data->x |= GENMASK(15, 14);
732 }
733
734 if ((accel_data->y & BIT(13)) != 0) {
735 accel_data->y |= GENMASK(15, 14);
736 }
737
738 if ((accel_data->z & BIT(13)) != 0) {
739 accel_data->z |= GENMASK(15, 14);
740 }
741
742 return 0;
743 }
744
745 /**
746 * @brief Reads the raw temperature of the device. If ADXL367_TEMP_EN is not
747 * set, use adxl367_temp_read_en() first to enable temperature reading.
748 *
749 * @param dev - The device structure.
750 * @param raw_temp - Raw value of temperature.
751 *
752 * @return 0 in case of success, negative error code otherwise.
753 */
adxl367_get_temp_data(const struct device * dev,int16_t * raw_temp)754 int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp)
755 {
756 int ret;
757 uint8_t temp[2] = { 0 };
758 uint8_t reg_data, nready = 1U;
759 struct adxl367_data *data = dev->data;
760
761 while (nready != 0) {
762 ret = data->hw_tf->read_reg(dev, ADXL367_STATUS, ®_data);
763 if (ret != 0) {
764 return ret;
765 }
766
767 if ((reg_data & ADXL367_STATUS_DATA_RDY) != 0) {
768 nready = 0U;
769 }
770 }
771
772 ret = data->hw_tf->read_reg_multiple(dev, ADXL367_TEMP_H, temp, 2);
773 if (ret != 0) {
774 return ret;
775 }
776
777 *raw_temp = ((int16_t)temp[0] << 6) + (temp[1] >> 2);
778 /* extend sign to 16 bits */
779 if ((*raw_temp & BIT(13)) != 0) {
780 *raw_temp |= GENMASK(15, 14);
781 }
782
783 return 0;
784 }
785
adxl367_attr_set_thresh(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)786 static int adxl367_attr_set_thresh(const struct device *dev,
787 enum sensor_channel chan,
788 enum sensor_attribute attr,
789 const struct sensor_value *val)
790 {
791 const struct adxl367_dev_config *cfg = dev->config;
792 struct adxl367_activity_threshold threshold;
793 int64_t llvalue;
794 int32_t value;
795 int64_t micro_ms2 = val->val1 * 1000000LL + val->val2;
796
797 llvalue = llabs((micro_ms2 * 10) / SENSOR_G);
798
799 value = (int32_t) llvalue;
800
801 threshold.value = value;
802 threshold.enable = cfg->activity_th.enable;
803 threshold.referenced = cfg->activity_th.referenced;
804
805 switch (chan) {
806 case SENSOR_CHAN_ACCEL_X:
807 case SENSOR_CHAN_ACCEL_Y:
808 case SENSOR_CHAN_ACCEL_Z:
809 case SENSOR_CHAN_ACCEL_XYZ:
810 if (attr == SENSOR_ATTR_UPPER_THRESH) {
811 return adxl367_setup_activity_detection(dev, &threshold);
812 } else {
813 return adxl367_setup_inactivity_detection(dev, &threshold);
814 }
815
816 default:
817 LOG_ERR("attr_set() not supported on this channel");
818 return -ENOTSUP;
819 }
820 }
821
adxl367_attr_set_odr(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)822 static int adxl367_attr_set_odr(const struct device *dev,
823 enum sensor_channel chan,
824 enum sensor_attribute attr,
825 const struct sensor_value *val)
826 {
827 enum adxl367_odr odr;
828
829 switch (val->val1) {
830 case 12:
831 case 13:
832 odr = ADXL367_ODR_12P5HZ;
833 break;
834 case 25:
835 odr = ADXL367_ODR_25HZ;
836 break;
837 case 50:
838 odr = ADXL367_ODR_50HZ;
839 break;
840 case 100:
841 odr = ADXL367_ODR_100HZ;
842 break;
843 case 200:
844 odr = ADXL367_ODR_200HZ;
845 break;
846 case 400:
847 odr = ADXL367_ODR_400HZ;
848 break;
849 default:
850 return -EINVAL;
851 }
852
853 return adxl367_set_output_rate(dev, odr);
854 }
855
adxl367_attr_set(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)856 static int adxl367_attr_set(const struct device *dev,
857 enum sensor_channel chan,
858 enum sensor_attribute attr,
859 const struct sensor_value *val)
860 {
861 switch (attr) {
862 case SENSOR_ATTR_SAMPLING_FREQUENCY:
863 return adxl367_attr_set_odr(dev, chan, attr, val);
864 case SENSOR_ATTR_UPPER_THRESH:
865 case SENSOR_ATTR_LOWER_THRESH:
866 return adxl367_attr_set_thresh(dev, chan, attr, val);
867 default:
868 return -ENOTSUP;
869 }
870 }
871
adxl367_sample_fetch(const struct device * dev,enum sensor_channel chan)872 static int adxl367_sample_fetch(const struct device *dev,
873 enum sensor_channel chan)
874 {
875 struct adxl367_data *data = dev->data;
876 int ret;
877
878 ret = adxl367_get_accel_data(dev, &data->sample);
879 if (ret != 0) {
880 return ret;
881 }
882
883 return adxl367_get_temp_data(dev, &data->temp_val);
884 }
885 #ifdef CONFIG_SENSOR_ASYNC_API
adxl367_accel_convert(struct sensor_value * val,int16_t value,enum adxl367_range range)886 void adxl367_accel_convert(struct sensor_value *val, int16_t value,
887 enum adxl367_range range)
888 #else
889 static void adxl367_accel_convert(struct sensor_value *val, int16_t value,
890 enum adxl367_range range)
891 #endif /*CONFIG_SENSOR_ASYNC_API*/
892 {
893 int64_t micro_ms2 = value * (SENSOR_G * 250 / 1000 *
894 adxl367_scale_mul[range] / 1000);
895
896 val->val1 = micro_ms2 / 1000000;
897 val->val2 = micro_ms2 % 1000000;
898 }
899
900 #ifdef CONFIG_SENSOR_ASYNC_API
adxl367_temp_convert(struct sensor_value * val,int16_t value)901 void adxl367_temp_convert(struct sensor_value *val, int16_t value)
902 #else
903 static void adxl367_temp_convert(struct sensor_value *val, int16_t value)
904 #endif /*CONFIG_SENSOR_ASYNC_API*/
905 {
906 int64_t temp_data = (value - ADXL367_TEMP_25C);
907
908 val->val1 = temp_data / 54 /*temp sensitivity LSB/C*/ + 25/*bias test conditions*/;
909 val->val2 = temp_data % 54 * 10000;
910 }
911
adxl367_channel_get(const struct device * dev,enum sensor_channel chan,struct sensor_value * val)912 static int adxl367_channel_get(const struct device *dev,
913 enum sensor_channel chan,
914 struct sensor_value *val)
915 {
916 struct adxl367_data *data = dev->data;
917
918 switch (chan) {
919 case SENSOR_CHAN_ACCEL_X:
920 adxl367_accel_convert(val, data->sample.x, data->range);
921 break;
922 case SENSOR_CHAN_ACCEL_Y:
923 adxl367_accel_convert(val, data->sample.y, data->range);
924 break;
925 case SENSOR_CHAN_ACCEL_Z:
926 adxl367_accel_convert(val, data->sample.z, data->range);
927 break;
928 case SENSOR_CHAN_ACCEL_XYZ:
929 adxl367_accel_convert(val++, data->sample.x, data->range);
930 adxl367_accel_convert(val++, data->sample.y, data->range);
931 adxl367_accel_convert(val, data->sample.z, data->range);
932 break;
933 case SENSOR_CHAN_DIE_TEMP:
934 adxl367_temp_convert(val, data->temp_val);
935 break;
936 default:
937 return -ENOTSUP;
938 }
939
940 return 0;
941 }
942
943 static DEVICE_API(sensor, adxl367_api_funcs) = {
944 .attr_set = adxl367_attr_set,
945 .sample_fetch = adxl367_sample_fetch,
946 .channel_get = adxl367_channel_get,
947 #ifdef CONFIG_ADXL367_TRIGGER
948 .trigger_set = adxl367_trigger_set,
949 #endif
950 #ifdef CONFIG_SENSOR_ASYNC_API
951 .submit = adxl367_submit,
952 .get_decoder = adxl367_get_decoder,
953 #endif /* CONFIG_SENSOR_ASYNC_API */
954 };
955
adxl367_probe(const struct device * dev)956 static int adxl367_probe(const struct device *dev)
957 {
958 const struct adxl367_dev_config *cfg = dev->config;
959 struct adxl367_data *data = dev->data;
960 uint8_t dev_id, part_id;
961 int ret;
962
963 ret = adxl367_reset(dev);
964 if (ret != 0) {
965 return ret;
966 }
967
968 ret = data->hw_tf->read_reg(dev, ADXL367_DEVID, &dev_id);
969 if (ret != 0) {
970 return ret;
971 }
972 ret = data->hw_tf->read_reg(dev, ADXL367_PART_ID, &part_id);
973 if (ret != 0) {
974 return ret;
975 }
976
977 if (dev_id != ADXL367_DEVID_VAL || part_id != ADXL367_PARTID_VAL) {
978 LOG_ERR("failed to read id (0x%X:0x%X)\n", dev_id, part_id);
979 return -ENODEV;
980 }
981
982 data->range = cfg->range;
983
984 #ifdef CONFIG_ADXL367_TRIGGER
985 data->act_proc_mode = ADXL367_LINKED;
986 #else
987 data->act_proc_mode = ADXL367_LOOPED;
988 #endif
989
990 ret = adxl367_self_test(dev);
991 if (ret != 0) {
992 return ret;
993 }
994
995 ret = adxl367_temp_read_en(dev, cfg->temp_en);
996 if (ret != 0) {
997 return ret;
998 }
999
1000 ret = adxl367_set_autosleep(dev, cfg->autosleep);
1001 if (ret != 0) {
1002 return ret;
1003 }
1004
1005 ret = adxl367_set_low_noise(dev, cfg->low_noise);
1006 if (ret != 0) {
1007 return ret;
1008 }
1009
1010 ret = adxl367_setup_activity_detection(dev, &cfg->activity_th);
1011 if (ret != 0) {
1012 return ret;
1013 }
1014
1015 ret = adxl367_setup_inactivity_detection(dev, &cfg->inactivity_th);
1016 if (ret != 0) {
1017 return ret;
1018 }
1019
1020 ret = adxl367_set_activity_time(dev, cfg->activity_time);
1021 if (ret != 0) {
1022 return ret;
1023 }
1024
1025 ret = adxl367_set_inactivity_time(dev, cfg->inactivity_time);
1026 if (ret != 0) {
1027 return ret;
1028 }
1029
1030 ret = adxl367_set_output_rate(dev, cfg->odr);
1031 if (ret != 0) {
1032 return ret;
1033 }
1034
1035 ret = adxl367_fifo_setup(dev, cfg->fifo_config.fifo_mode,
1036 cfg->fifo_config.fifo_format,
1037 cfg->fifo_config.fifo_read_mode,
1038 cfg->fifo_config.fifo_samples);
1039 if (ret != 0) {
1040 return ret;
1041 }
1042
1043 if (IS_ENABLED(CONFIG_ADXL367_TRIGGER)) {
1044 ret = adxl367_init_interrupt(dev);
1045 if (ret != 0) {
1046 LOG_ERR("Failed to initialize interrupt!");
1047 return -EIO;
1048 }
1049 }
1050
1051 ret = adxl367_set_op_mode(dev, cfg->op_mode);
1052 if (ret != 0) {
1053 return ret;
1054 }
1055
1056 ret = adxl367_set_range(dev, data->range);
1057 if (ret != 0) {
1058 return ret;
1059 }
1060
1061 return adxl367_set_act_proc_mode(dev, data->act_proc_mode);
1062 }
1063
adxl367_init(const struct device * dev)1064 static int adxl367_init(const struct device *dev)
1065 {
1066 int ret;
1067 const struct adxl367_dev_config *cfg = dev->config;
1068
1069 ret = cfg->bus_init(dev);
1070 if (ret != 0) {
1071 LOG_ERR("Failed to initialize sensor bus\n");
1072 return ret;
1073 }
1074
1075 return adxl367_probe(dev);
1076 }
1077
1078 /*
1079 * Device creation macro, shared by ADXL367_DEFINE_SPI() and
1080 * ADXL367_DEFINE_I2C().
1081 */
1082
1083 #define ADXL367_DEVICE_INIT(inst, chipid) \
1084 SENSOR_DEVICE_DT_INST_DEFINE(inst, \
1085 adxl367_init, \
1086 NULL, \
1087 &adxl367_data_##inst##chipid, \
1088 &adxl367_config_##inst##chipid, \
1089 POST_KERNEL, \
1090 CONFIG_SENSOR_INIT_PRIORITY, \
1091 &adxl367_api_funcs);
1092
1093 #ifdef CONFIG_ADXL367_TRIGGER
1094 #define ADXL367_CFG_IRQ(inst) \
1095 .interrupt = GPIO_DT_SPEC_INST_GET(inst, int1_gpios),
1096 #else
1097 #define ADXL367_CFG_IRQ(inst)
1098 #endif /* CONFIG_ADXL367_TRIGGER */
1099
1100 #define ADXL367_CONFIG(inst, chipid) \
1101 .odr = DT_INST_PROP(inst, odr), \
1102 .autosleep = false, \
1103 .low_noise = false, \
1104 .temp_en = true, \
1105 .range = ADXL367_2G_RANGE, \
1106 .activity_th.value = CONFIG_ADXL367_ACTIVITY_THRESHOLD, \
1107 .activity_th.referenced = \
1108 IS_ENABLED(CONFIG_ADXL367_REFERENCED_ACTIVITY_DETECTION_MODE), \
1109 .activity_th.enable = \
1110 IS_ENABLED(CONFIG_ADXL367_ACTIVITY_DETECTION_MODE), \
1111 .activity_time = CONFIG_ADXL367_ACTIVITY_TIME, \
1112 .inactivity_th.value = CONFIG_ADXL367_INACTIVITY_THRESHOLD, \
1113 .inactivity_th.referenced = \
1114 IS_ENABLED(CONFIG_ADXL367_REFERENCED_INACTIVITY_DETECTION_MODE),\
1115 .inactivity_th.enable = \
1116 IS_ENABLED(CONFIG_ADXL367_INACTIVITY_DETECTION_MODE), \
1117 .inactivity_time = CONFIG_ADXL367_INACTIVITY_TIME, \
1118 .fifo_config.fifo_mode = ADXL367_FIFO_DISABLED, \
1119 .fifo_config.fifo_format = ADXL367_FIFO_FORMAT_XYZ, \
1120 .fifo_config.fifo_samples = 128, \
1121 .fifo_config.fifo_read_mode = ADXL367_14B_CHID, \
1122 .op_mode = ADXL367_MEASURE, \
1123 .chip_id = chipid,
1124
1125 /*
1126 * Instantiation macros used when a device is on a SPI bus.
1127 */
1128 #define ADXL367_SPI_CFG SPI_WORD_SET(8) | SPI_TRANSFER_MSB
1129
1130 #define ADXL367_RTIO_DEFINE(inst, chipid) \
1131 SPI_DT_IODEV_DEFINE(adxl367_iodev_##inst##chipid, DT_DRV_INST(inst), \
1132 ADXL367_SPI_CFG, 0U); \
1133 RTIO_DEFINE(adxl367_rtio_ctx_##inst##chipid, 8, 8);
1134
1135 #define ADXL367_CONFIG_SPI(inst, chipid) \
1136 { \
1137 .bus_init = adxl367_spi_init, \
1138 .spi = SPI_DT_SPEC_INST_GET(inst, ADXL367_SPI_CFG, 0), \
1139 ADXL367_CONFIG(inst, chipid) \
1140 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int1_gpios), \
1141 (ADXL367_CFG_IRQ(inst)), ()) \
1142 }
1143
1144 #define ADXL367_DEFINE_SPI(inst, chipid) \
1145 IF_ENABLED(CONFIG_ADXL367_STREAM, (ADXL367_RTIO_DEFINE(inst, chipid))); \
1146 static struct adxl367_data adxl367_data_##inst##chipid = { \
1147 IF_ENABLED(CONFIG_ADXL367_STREAM, (.rtio_ctx = &adxl367_rtio_ctx_##inst##chipid, \
1148 .iodev = &adxl367_iodev_##inst##chipid,)) \
1149 }; \
1150 static const struct adxl367_dev_config adxl367_config_##inst##chipid = \
1151 ADXL367_CONFIG_SPI(inst, chipid); \
1152 ADXL367_DEVICE_INIT(inst, chipid)
1153
1154 /*
1155 * Instantiation macros used when a device is on an I2C bus.
1156 */
1157
1158 #define ADXL367_CONFIG_I2C(inst, chipid) \
1159 { \
1160 .bus_init = adxl367_i2c_init, \
1161 .i2c = I2C_DT_SPEC_INST_GET(inst), \
1162 ADXL367_CONFIG(inst, chipid) \
1163 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int1_gpios), \
1164 (ADXL367_CFG_IRQ(inst)), ()) \
1165 }
1166
1167 #define ADXL367_DEFINE_I2C(inst, chipid) \
1168 static struct adxl367_data adxl367_data_##inst##chipid; \
1169 static const struct adxl367_dev_config adxl367_config_##inst##chipid = \
1170 ADXL367_CONFIG_I2C(inst, chipid); \
1171 ADXL367_DEVICE_INIT(inst, chipid)
1172 /*
1173 * Main instantiation macro. Use of COND_CODE_1() selects the right
1174 * bus-specific macro at preprocessor time.
1175 */
1176
1177 #define ADXL367_DEFINE(inst, chipid) \
1178 COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
1179 (ADXL367_DEFINE_SPI(inst, chipid)), \
1180 (ADXL367_DEFINE_I2C(inst, chipid)))
1181
1182 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADXL367_DEFINE, ADXL367_CHIP_ID)
1183
1184 #undef DT_DRV_COMPAT
1185 #define DT_DRV_COMPAT adi_adxl366
1186 DT_INST_FOREACH_STATUS_OKAY_VARGS(ADXL367_DEFINE, ADXL366_CHIP_ID)
1187 #undef DT_DRV_COMPAT
1188
