1 /*
2 * Copyright (c) 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_adxl345
8
9 #include <zephyr/drivers/sensor.h>
10 #include <zephyr/init.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/i2c.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/sys/__assert.h>
15
16 #include "adxl345.h"
17
18 LOG_MODULE_REGISTER(ADXL345, CONFIG_SENSOR_LOG_LEVEL);
19
20 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
adxl345_bus_is_ready_i2c(const union adxl345_bus * bus)21 static bool adxl345_bus_is_ready_i2c(const union adxl345_bus *bus)
22 {
23 return device_is_ready(bus->i2c.bus);
24 }
25
adxl345_reg_access_i2c(const struct device * dev,uint8_t cmd,uint8_t reg_addr,uint8_t * data,size_t length)26 static int adxl345_reg_access_i2c(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
27 uint8_t *data, size_t length)
28 {
29 const struct adxl345_dev_config *cfg = dev->config;
30
31 if (cmd == ADXL345_READ_CMD) {
32 return i2c_burst_read_dt(&cfg->bus.i2c, reg_addr, data, length);
33 } else {
34 return i2c_burst_write_dt(&cfg->bus.i2c, reg_addr, data, length);
35 }
36 }
37 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
38
39 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
adxl345_bus_is_ready_spi(const union adxl345_bus * bus)40 static bool adxl345_bus_is_ready_spi(const union adxl345_bus *bus)
41 {
42 return spi_is_ready_dt(&bus->spi);
43 }
44
adxl345_reg_access_spi(const struct device * dev,uint8_t cmd,uint8_t reg_addr,uint8_t * data,size_t length)45 int adxl345_reg_access_spi(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
46 uint8_t *data, size_t length)
47 {
48 const struct adxl345_dev_config *cfg = dev->config;
49 uint8_t access = reg_addr | cmd | (length == 1 ? 0 : ADXL345_MULTIBYTE_FLAG);
50 const struct spi_buf buf[2] = {{.buf = &access, .len = 1}, {.buf = data, .len = length}};
51 const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
52 struct spi_buf_set tx = {
53 .buffers = buf,
54 .count = 2,
55 };
56 int ret;
57
58 if (cmd == ADXL345_READ_CMD) {
59 tx.count = 1;
60 ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx);
61 return ret;
62 } else {
63 ret = spi_write_dt(&cfg->bus.spi, &tx);
64 return ret;
65 }
66 }
67 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
68
adxl345_reg_access(const struct device * dev,uint8_t cmd,uint8_t addr,uint8_t * data,size_t len)69 int adxl345_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr,
70 uint8_t *data, size_t len)
71 {
72 const struct adxl345_dev_config *cfg = dev->config;
73
74 return cfg->reg_access(dev, cmd, addr, data, len);
75 }
76
adxl345_reg_write(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)77 int adxl345_reg_write(const struct device *dev, uint8_t addr, uint8_t *data,
78 uint8_t len)
79 {
80
81 return adxl345_reg_access(dev, ADXL345_WRITE_CMD, addr, data, len);
82 }
83
adxl345_reg_read(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)84 int adxl345_reg_read(const struct device *dev, uint8_t addr, uint8_t *data,
85 uint8_t len)
86 {
87
88 return adxl345_reg_access(dev, ADXL345_READ_CMD, addr, data, len);
89 }
90
adxl345_reg_write_byte(const struct device * dev,uint8_t addr,uint8_t val)91 int adxl345_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val)
92 {
93 return adxl345_reg_write(dev, addr, &val, 1);
94 }
95
adxl345_reg_read_byte(const struct device * dev,uint8_t addr,uint8_t * buf)96 int adxl345_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf)
97
98 {
99 return adxl345_reg_read(dev, addr, buf, 1);
100 }
101
adxl345_reg_write_mask(const struct device * dev,uint8_t reg_addr,uint8_t mask,uint8_t data)102 int adxl345_reg_write_mask(const struct device *dev,
103 uint8_t reg_addr,
104 uint8_t mask,
105 uint8_t data)
106 {
107 int ret;
108 uint8_t tmp;
109
110 ret = adxl345_reg_read_byte(dev, reg_addr, &tmp);
111 if (ret) {
112 return ret;
113 }
114
115 tmp &= ~mask;
116 tmp |= data;
117
118 return adxl345_reg_write_byte(dev, reg_addr, tmp);
119 }
120
adxl345_bus_is_ready(const struct device * dev)121 static inline bool adxl345_bus_is_ready(const struct device *dev)
122 {
123 const struct adxl345_dev_config *cfg = dev->config;
124
125 return cfg->bus_is_ready(&cfg->bus);
126 }
127
adxl345_get_status(const struct device * dev,uint8_t * status1,uint16_t * fifo_entries)128 int adxl345_get_status(const struct device *dev,
129 uint8_t *status1,
130 uint16_t *fifo_entries)
131 {
132 uint8_t buf[2], length = 1U;
133 int ret;
134
135 ret = adxl345_reg_read(dev, ADXL345_INT_SOURCE, buf, length);
136
137 *status1 = buf[0];
138 ret = adxl345_reg_read(dev, ADXL345_FIFO_STATUS_REG, buf+1, length);
139 if (fifo_entries) {
140 *fifo_entries = buf[1] & 0x3F;
141 }
142
143 return ret;
144 }
145
146 /**
147 * Configure the operating parameters for the FIFO.
148 * @param dev - The device structure.
149 * @param mode - FIFO Mode. Specifies FIFO operating mode.
150 * Accepted values: ADXL345_FIFO_BYPASSED
151 * ADXL345_FIFO_STREAMED
152 * ADXL345_FIFO_TRIGGERED
153 * ADXL345_FIFO_OLD_SAVED
154 * @param trigger - FIFO trigger. Links trigger event to appropriate INT.
155 * Accepted values: ADXL345_INT1
156 * ADXL345_INT2
157 * @param fifo_samples - FIFO Samples. Watermark number of FIFO samples that
158 * triggers a FIFO_FULL condition when reached.
159 * Values range from 0 to 32.
160
161 * @return 0 in case of success, negative error code otherwise.
162 */
adxl345_configure_fifo(const struct device * dev,enum adxl345_fifo_mode mode,enum adxl345_fifo_trigger trigger,uint16_t fifo_samples)163 int adxl345_configure_fifo(const struct device *dev,
164 enum adxl345_fifo_mode mode,
165 enum adxl345_fifo_trigger trigger,
166 uint16_t fifo_samples)
167 {
168 struct adxl345_dev_data *data = dev->data;
169 uint8_t fifo_config;
170 int ret;
171
172 if (fifo_samples > 32) {
173 return -EINVAL;
174 }
175
176 fifo_config = (ADXL345_FIFO_CTL_TRIGGER_MODE(trigger) |
177 ADXL345_FIFO_CTL_MODE_MODE(mode) |
178 ADXL345_FIFO_CTL_SAMPLES_MODE(fifo_samples));
179
180 ret = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, fifo_config);
181 if (ret) {
182 return ret;
183 }
184
185 data->fifo_config.fifo_trigger = trigger;
186 data->fifo_config.fifo_mode = mode;
187 data->fifo_config.fifo_samples = fifo_samples;
188
189 return 0;
190 }
191
192 /**
193 * Set the mode of operation.
194 * @param dev - The device structure.
195 * @param op_mode - Mode of operation.
196 * Accepted values: ADXL345_STANDBY
197 * ADXL345_MEASURE
198 * @return 0 in case of success, negative error code otherwise.
199 */
adxl345_set_op_mode(const struct device * dev,enum adxl345_op_mode op_mode)200 int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode)
201 {
202 return adxl345_reg_write_mask(dev, ADXL345_POWER_CTL_REG,
203 ADXL345_POWER_CTL_MEASURE_MSK,
204 ADXL345_POWER_CTL_MEASURE_MODE(op_mode));
205 }
206
207 /**
208 * Set Output data rate.
209 * @param dev - The device structure.
210 * @param odr - Output data rate.
211 * Accepted values: ADXL345_ODR_12HZ
212 * ADXL345_ODR_25HZ
213 * ADXL345_ODR_50HZ
214 * ADXL345_ODR_100HZ
215 * ADXL345_ODR_200HZ
216 * ADXL345_ODR_400HZ
217 * @return 0 in case of success, negative error code otherwise.
218 */
adxl345_set_odr(const struct device * dev,enum adxl345_odr odr)219 static int adxl345_set_odr(const struct device *dev, enum adxl345_odr odr)
220 {
221 return adxl345_reg_write_mask(dev, ADXL345_RATE_REG,
222 ADXL345_ODR_MSK,
223 ADXL345_ODR_MODE(odr));
224 }
225
adxl345_attr_set_odr(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)226 static int adxl345_attr_set_odr(const struct device *dev,
227 enum sensor_channel chan,
228 enum sensor_attribute attr,
229 const struct sensor_value *val)
230 {
231 enum adxl345_odr odr;
232 struct adxl345_dev_data *data = dev->data;
233
234 switch (val->val1) {
235 case 12:
236 odr = ADXL345_ODR_12HZ;
237 break;
238 case 25:
239 odr = ADXL345_ODR_25HZ;
240 break;
241 case 50:
242 odr = ADXL345_ODR_50HZ;
243 break;
244 case 100:
245 odr = ADXL345_ODR_100HZ;
246 break;
247 case 200:
248 odr = ADXL345_ODR_200HZ;
249 break;
250 case 400:
251 odr = ADXL345_ODR_400HZ;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 int ret = adxl345_set_odr(dev, odr);
258
259 if (ret == 0) {
260 data->odr = odr;
261 }
262
263 return ret;
264 }
265
adxl345_attr_set(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)266 static int adxl345_attr_set(const struct device *dev,
267 enum sensor_channel chan,
268 enum sensor_attribute attr,
269 const struct sensor_value *val)
270 {
271 switch (attr) {
272 case SENSOR_ATTR_SAMPLING_FREQUENCY:
273 return adxl345_attr_set_odr(dev, chan, attr, val);
274 default:
275 return -ENOTSUP;
276 }
277 }
278
adxl345_read_sample(const struct device * dev,struct adxl345_sample * sample)279 int adxl345_read_sample(const struct device *dev,
280 struct adxl345_sample *sample)
281 {
282 int16_t raw_x, raw_y, raw_z;
283 uint8_t axis_data[6], status1;
284 struct adxl345_dev_data *data = dev->data;
285
286 if (!IS_ENABLED(CONFIG_ADXL345_TRIGGER)) {
287 do {
288 adxl345_get_status(dev, &status1, NULL);
289 } while (!(ADXL345_STATUS_DATA_RDY(status1)));
290 }
291
292 int rc = adxl345_reg_read(dev, ADXL345_X_AXIS_DATA_0_REG, axis_data, 6);
293
294 if (rc < 0) {
295 LOG_ERR("Samples read failed with rc=%d\n", rc);
296 return rc;
297 }
298
299 raw_x = axis_data[0] | (axis_data[1] << 8);
300 raw_y = axis_data[2] | (axis_data[3] << 8);
301 raw_z = axis_data[4] | (axis_data[5] << 8);
302
303 sample->x = raw_x;
304 sample->y = raw_y;
305 sample->z = raw_z;
306
307 sample->selected_range = data->selected_range;
308 sample->is_full_res = data->is_full_res;
309
310 return 0;
311 }
312
adxl345_accel_convert(struct sensor_value * val,int16_t sample)313 void adxl345_accel_convert(struct sensor_value *val, int16_t sample)
314 {
315 if (sample & BIT(9)) {
316 sample |= ADXL345_COMPLEMENT;
317 }
318
319 val->val1 = ((sample * SENSOR_G) / 32) / 1000000;
320 val->val2 = ((sample * SENSOR_G) / 32) % 1000000;
321 }
322
adxl345_sample_fetch(const struct device * dev,enum sensor_channel chan)323 static int adxl345_sample_fetch(const struct device *dev,
324 enum sensor_channel chan)
325 {
326 struct adxl345_dev_data *data = dev->data;
327 struct adxl345_sample sample;
328 uint8_t samples_count;
329 int rc;
330
331 data->sample_number = 0;
332 rc = adxl345_reg_read_byte(dev, ADXL345_FIFO_STATUS_REG, &samples_count);
333 if (rc < 0) {
334 LOG_ERR("Failed to read FIFO status rc = %d\n", rc);
335 return rc;
336 }
337
338 __ASSERT_NO_MSG(samples_count <= ARRAY_SIZE(data->bufx));
339
340 for (uint8_t s = 0; s < samples_count; s++) {
341 rc = adxl345_read_sample(dev, &sample);
342 if (rc < 0) {
343 LOG_ERR("Failed to fetch sample rc=%d\n", rc);
344 return rc;
345 }
346 data->bufx[s] = sample.x;
347 data->bufy[s] = sample.y;
348 data->bufz[s] = sample.z;
349 }
350
351 return 0;
352 }
353
adxl345_channel_get(const struct device * dev,enum sensor_channel chan,struct sensor_value * val)354 static int adxl345_channel_get(const struct device *dev,
355 enum sensor_channel chan,
356 struct sensor_value *val)
357 {
358 struct adxl345_dev_data *data = dev->data;
359
360 if (data->sample_number >= ARRAY_SIZE(data->bufx)) {
361 data->sample_number = 0;
362 }
363
364 switch (chan) {
365 case SENSOR_CHAN_ACCEL_X:
366 adxl345_accel_convert(val, data->bufx[data->sample_number]);
367 data->sample_number++;
368 break;
369 case SENSOR_CHAN_ACCEL_Y:
370 adxl345_accel_convert(val, data->bufy[data->sample_number]);
371 data->sample_number++;
372 break;
373 case SENSOR_CHAN_ACCEL_Z:
374 adxl345_accel_convert(val, data->bufz[data->sample_number]);
375 data->sample_number++;
376 break;
377 case SENSOR_CHAN_ACCEL_XYZ:
378 adxl345_accel_convert(val++, data->bufx[data->sample_number]);
379 adxl345_accel_convert(val++, data->bufy[data->sample_number]);
380 adxl345_accel_convert(val, data->bufz[data->sample_number]);
381 data->sample_number++;
382 break;
383 default:
384 return -ENOTSUP;
385 }
386
387 return 0;
388 }
389
390 static DEVICE_API(sensor, adxl345_api_funcs) = {
391 .attr_set = adxl345_attr_set,
392 .sample_fetch = adxl345_sample_fetch,
393 .channel_get = adxl345_channel_get,
394 #ifdef CONFIG_ADXL345_TRIGGER
395 .trigger_set = adxl345_trigger_set,
396 #endif
397 #ifdef CONFIG_SENSOR_ASYNC_API
398 .submit = adxl345_submit,
399 .get_decoder = adxl345_get_decoder,
400 #endif
401 };
402
403 #ifdef CONFIG_ADXL345_TRIGGER
404 /**
405 * Configure the INT1 and INT2 interrupt pins.
406 * @param dev - The device structure.
407 * @param int1 - INT1 interrupt pins.
408 * @return 0 in case of success, negative error code otherwise.
409 */
adxl345_interrupt_config(const struct device * dev,uint8_t int1)410 static int adxl345_interrupt_config(const struct device *dev,
411 uint8_t int1)
412 {
413 int ret;
414 const struct adxl345_dev_config *cfg = dev->config;
415
416 ret = adxl345_reg_write_byte(dev, ADXL345_INT_MAP, int1);
417 if (ret) {
418 return ret;
419 }
420
421 ret = adxl345_reg_write_byte(dev, ADXL345_INT_ENABLE, int1);
422 if (ret) {
423 return ret;
424 }
425
426 uint8_t samples;
427
428 ret = adxl345_reg_read_byte(dev, ADXL345_INT_MAP, &samples);
429 ret = adxl345_reg_read_byte(dev, ADXL345_INT_ENABLE, &samples);
430 #ifdef CONFIG_ADXL345_TRIGGER
431 gpio_pin_interrupt_configure_dt(&cfg->interrupt,
432 GPIO_INT_EDGE_TO_ACTIVE);
433 #endif
434 return 0;
435 }
436 #endif
437
adxl345_init(const struct device * dev)438 static int adxl345_init(const struct device *dev)
439 {
440 int rc;
441 struct adxl345_dev_data *data = dev->data;
442 #ifdef CONFIG_ADXL345_TRIGGER
443 const struct adxl345_dev_config *cfg = dev->config;
444 #endif
445 uint8_t dev_id, full_res;
446
447 data->sample_number = 0;
448
449 if (!adxl345_bus_is_ready(dev)) {
450 LOG_ERR("bus not ready");
451 return -ENODEV;
452 }
453
454 rc = adxl345_reg_read_byte(dev, ADXL345_DEVICE_ID_REG, &dev_id);
455 if (rc < 0 || dev_id != ADXL345_PART_ID) {
456 LOG_ERR("Read PART ID failed: 0x%x\n", rc);
457 return -ENODEV;
458 }
459
460 #if CONFIG_ADXL345_STREAM
461 rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE);
462 if (rc < 0) {
463 LOG_ERR("FIFO enable failed\n");
464 return -EIO;
465 }
466 #endif
467
468 rc = adxl345_reg_write_byte(dev, ADXL345_DATA_FORMAT_REG, ADXL345_RANGE_8G);
469 if (rc < 0) {
470 LOG_ERR("Data format set failed\n");
471 return -EIO;
472 }
473
474 data->selected_range = ADXL345_RANGE_8G;
475
476 rc = adxl345_reg_write_byte(dev, ADXL345_RATE_REG, ADXL345_RATE_25HZ);
477 if (rc < 0) {
478 LOG_ERR("Rate setting failed\n");
479 return -EIO;
480 }
481
482 #ifdef CONFIG_ADXL345_TRIGGER
483 rc = adxl345_configure_fifo(dev, ADXL345_FIFO_STREAMED,
484 ADXL345_INT2,
485 SAMPLE_NUM);
486 if (rc) {
487 return rc;
488 }
489 #endif
490
491 rc = adxl345_reg_write_byte(dev, ADXL345_POWER_CTL_REG, ADXL345_ENABLE_MEASURE_BIT);
492 if (rc < 0) {
493 LOG_ERR("Enable measure bit failed\n");
494 return -EIO;
495 }
496
497 #ifdef CONFIG_ADXL345_TRIGGER
498 rc = adxl345_init_interrupt(dev);
499 if (rc < 0) {
500 LOG_ERR("Failed to initialize interrupt!");
501 return -EIO;
502 }
503
504 rc = adxl345_set_odr(dev, cfg->odr);
505 if (rc) {
506 return rc;
507 }
508 rc = adxl345_interrupt_config(dev, ADXL345_INT_MAP_WATERMARK_MSK);
509 if (rc) {
510 return rc;
511 }
512 #endif
513
514 rc = adxl345_reg_read_byte(dev, ADXL345_DATA_FORMAT_REG, &full_res);
515 uint8_t is_full_res_set = (full_res & ADXL345_DATA_FORMAT_FULL_RES) != 0;
516
517 data->is_full_res = is_full_res_set;
518 return 0;
519 }
520
521 #ifdef CONFIG_ADXL345_TRIGGER
522 #define ADXL345_CFG_IRQ(inst) \
523 .interrupt = GPIO_DT_SPEC_INST_GET(inst, int2_gpios),
524 #else
525 #define ADXL345_CFG_IRQ(inst)
526 #endif /* CONFIG_ADXL345_TRIGGER */
527
528 #define ADXL345_RTIO_SPI_DEFINE(inst) \
529 COND_CODE_1(CONFIG_SPI_RTIO, \
530 (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
531 SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
532 SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
533 ())
534
535 #define ADXL345_RTIO_I2C_DEFINE(inst) \
536 COND_CODE_1(CONFIG_I2C_RTIO, \
537 (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
538 ())
539
540 /* Conditionally set the RTIO size based on the presence of SPI/I2C
541 * lines 541 - 542.
542 * The sizes of sqe and cqe pools are increased due to the amount of
543 * multibyte reads needed for watermark using 31 samples
544 * (adx345_stram - line 203), using smaller amounts of samples
545 * to trigger an interrupt can decrease the pool sizes.
546 */
547 #define ADXL345_RTIO_DEFINE(inst) \
548 /* Conditionally include SPI and/or I2C parts based on their presence */ \
549 COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
550 (ADXL345_RTIO_SPI_DEFINE(inst)), \
551 ()) \
552 COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
553 (ADXL345_RTIO_I2C_DEFINE(inst)), \
554 ()) \
555 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, spi_dt_spec) && \
556 DT_INST_NODE_HAS_PROP(inst, i2c_dt_spec), \
557 (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 128, 128);), \
558 (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);)) \
559
560 #define ADXL345_CONFIG(inst) \
561 .odr = DT_INST_PROP(inst, odr), \
562 .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
563 .fifo_config.fifo_trigger = ADXL345_INT2, \
564 .fifo_config.fifo_samples = SAMPLE_NUM, \
565 .odr = ADXL345_RATE_25HZ, \
566
567 #define ADXL345_CONFIG_SPI(inst) \
568 { \
569 .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \
570 SPI_WORD_SET(8) | \
571 SPI_TRANSFER_MSB | \
572 SPI_MODE_CPOL | \
573 SPI_MODE_CPHA, \
574 0)}, \
575 .bus_is_ready = adxl345_bus_is_ready_spi, \
576 .reg_access = adxl345_reg_access_spi, \
577 .bus_type = ADXL345_BUS_SPI, \
578 ADXL345_CONFIG(inst) \
579 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
580 (ADXL345_CFG_IRQ(inst)), ()) \
581 }
582
583 #define ADXL345_CONFIG_I2C(inst) \
584 { \
585 .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
586 .bus_is_ready = adxl345_bus_is_ready_i2c, \
587 .reg_access = adxl345_reg_access_i2c, \
588 .bus_type = ADXL345_BUS_I2C, \
589 ADXL345_CONFIG(inst) \
590 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
591 (ADXL345_CFG_IRQ(inst)), ()) \
592 }
593
594 #define ADXL345_DEFINE(inst) \
595 IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
596 static struct adxl345_dev_data adxl345_data_##inst = { \
597 COND_CODE_1(adxl345_iodev_##inst, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
598 .iodev = &adxl345_iodev_##inst,), ()) \
599 }; \
600 static const struct adxl345_dev_config adxl345_config_##inst = \
601 COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
602 (ADXL345_CONFIG_I2C(inst))); \
603 \
604 SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \
605 &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL,\
606 CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); \
607
608 DT_INST_FOREACH_STATUS_OKAY(ADXL345_DEFINE)
609
