1 /*
2 * Copyright (c) 2020 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_adxl345
8
9 #include <zephyr/drivers/sensor.h>
10 #include <zephyr/init.h>
11 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/i2c.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/sys/__assert.h>
15
16 #include "adxl345.h"
17
18 LOG_MODULE_REGISTER(ADXL345, CONFIG_SENSOR_LOG_LEVEL);
19
20 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
adxl345_bus_is_ready_i2c(const union adxl345_bus * bus)21 static bool adxl345_bus_is_ready_i2c(const union adxl345_bus *bus)
22 {
23 return device_is_ready(bus->i2c.bus);
24 }
25
adxl345_reg_access_i2c(const struct device * dev,uint8_t cmd,uint8_t reg_addr,uint8_t * data,size_t length)26 static int adxl345_reg_access_i2c(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
27 uint8_t *data, size_t length)
28 {
29 const struct adxl345_dev_config *cfg = dev->config;
30
31 if (cmd == ADXL345_READ_CMD) {
32 return i2c_burst_read_dt(&cfg->bus.i2c, reg_addr, data, length);
33 } else {
34 return i2c_burst_write_dt(&cfg->bus.i2c, reg_addr, data, length);
35 }
36 }
37 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
38
39 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
adxl345_bus_is_ready_spi(const union adxl345_bus * bus)40 static bool adxl345_bus_is_ready_spi(const union adxl345_bus *bus)
41 {
42 return spi_is_ready_dt(&bus->spi);
43 }
44
adxl345_reg_access_spi(const struct device * dev,uint8_t cmd,uint8_t reg_addr,uint8_t * data,size_t length)45 int adxl345_reg_access_spi(const struct device *dev, uint8_t cmd, uint8_t reg_addr,
46 uint8_t *data, size_t length)
47 {
48 const struct adxl345_dev_config *cfg = dev->config;
49 uint8_t access = reg_addr | cmd | (length == 1 ? 0 : ADXL345_MULTIBYTE_FLAG);
50 const struct spi_buf buf[2] = {{.buf = &access, .len = 1}, {.buf = data, .len = length}};
51 const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
52 struct spi_buf_set tx = {
53 .buffers = buf,
54 .count = 2,
55 };
56 int ret;
57
58 if (cmd == ADXL345_READ_CMD) {
59 tx.count = 1;
60 ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx);
61 return ret;
62 } else {
63 ret = spi_write_dt(&cfg->bus.spi, &tx);
64 return ret;
65 }
66 }
67 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
68
adxl345_reg_access(const struct device * dev,uint8_t cmd,uint8_t addr,uint8_t * data,size_t len)69 int adxl345_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr,
70 uint8_t *data, size_t len)
71 {
72 const struct adxl345_dev_config *cfg = dev->config;
73
74 return cfg->reg_access(dev, cmd, addr, data, len);
75 }
76
adxl345_reg_write(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)77 int adxl345_reg_write(const struct device *dev, uint8_t addr, uint8_t *data,
78 uint8_t len)
79 {
80
81 return adxl345_reg_access(dev, ADXL345_WRITE_CMD, addr, data, len);
82 }
83
adxl345_reg_read(const struct device * dev,uint8_t addr,uint8_t * data,uint8_t len)84 int adxl345_reg_read(const struct device *dev, uint8_t addr, uint8_t *data,
85 uint8_t len)
86 {
87
88 return adxl345_reg_access(dev, ADXL345_READ_CMD, addr, data, len);
89 }
90
adxl345_reg_write_byte(const struct device * dev,uint8_t addr,uint8_t val)91 int adxl345_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val)
92 {
93 return adxl345_reg_write(dev, addr, &val, 1);
94 }
95
adxl345_reg_read_byte(const struct device * dev,uint8_t addr,uint8_t * buf)96 int adxl345_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf)
97
98 {
99 return adxl345_reg_read(dev, addr, buf, 1);
100 }
101
adxl345_reg_write_mask(const struct device * dev,uint8_t reg_addr,uint8_t mask,uint8_t data)102 int adxl345_reg_write_mask(const struct device *dev,
103 uint8_t reg_addr,
104 uint8_t mask,
105 uint8_t data)
106 {
107 int ret;
108 uint8_t tmp;
109
110 ret = adxl345_reg_read_byte(dev, reg_addr, &tmp);
111 if (ret) {
112 return ret;
113 }
114
115 tmp &= ~mask;
116 tmp |= data;
117
118 return adxl345_reg_write_byte(dev, reg_addr, tmp);
119 }
120
adxl345_bus_is_ready(const struct device * dev)121 static inline bool adxl345_bus_is_ready(const struct device *dev)
122 {
123 const struct adxl345_dev_config *cfg = dev->config;
124
125 return cfg->bus_is_ready(&cfg->bus);
126 }
127
adxl345_get_status(const struct device * dev,uint8_t * status1,uint16_t * fifo_entries)128 int adxl345_get_status(const struct device *dev,
129 uint8_t *status1,
130 uint16_t *fifo_entries)
131 {
132 uint8_t buf[2], length = 1U;
133 int ret;
134
135 ret = adxl345_reg_read(dev, ADXL345_INT_SOURCE, buf, length);
136
137 *status1 = buf[0];
138 ret = adxl345_reg_read(dev, ADXL345_FIFO_STATUS_REG, buf+1, length);
139 if (fifo_entries) {
140 *fifo_entries = buf[1] & 0x3F;
141 }
142
143 return ret;
144 }
145
146 /**
147 * Configure the operating parameters for the FIFO.
148 * @param dev - The device structure.
149 * @param mode - FIFO Mode. Specifies FIFO operating mode.
150 * Accepted values: ADXL345_FIFO_BYPASSED
151 * ADXL345_FIFO_STREAMED
152 * ADXL345_FIFO_TRIGGERED
153 * ADXL345_FIFO_OLD_SAVED
154 * @param trigger - FIFO trigger. Links trigger event to appropriate INT.
155 * Accepted values: ADXL345_INT1
156 * ADXL345_INT2
157 * @param fifo_samples - FIFO Samples. Watermark number of FIFO samples that
158 * triggers a FIFO_FULL condition when reached.
159 * Values range from 0 to 32.
160
161 * @return 0 in case of success, negative error code otherwise.
162 */
adxl345_configure_fifo(const struct device * dev,enum adxl345_fifo_mode mode,enum adxl345_fifo_trigger trigger,uint16_t fifo_samples)163 int adxl345_configure_fifo(const struct device *dev,
164 enum adxl345_fifo_mode mode,
165 enum adxl345_fifo_trigger trigger,
166 uint16_t fifo_samples)
167 {
168 struct adxl345_dev_data *data = dev->data;
169 uint8_t fifo_config;
170 int ret;
171
172 if (fifo_samples > 32) {
173 return -EINVAL;
174 }
175
176 fifo_config = (ADXL345_FIFO_CTL_TRIGGER_MODE(trigger) |
177 ADXL345_FIFO_CTL_MODE_MODE(mode) |
178 ADXL345_FIFO_CTL_SAMPLES_MODE(fifo_samples));
179
180 ret = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, fifo_config);
181 if (ret) {
182 return ret;
183 }
184
185 data->fifo_config.fifo_trigger = trigger;
186 data->fifo_config.fifo_mode = mode;
187 data->fifo_config.fifo_samples = fifo_samples;
188
189 return 0;
190 }
191
192 /**
193 * Set the mode of operation.
194 * @param dev - The device structure.
195 * @param op_mode - Mode of operation.
196 * Accepted values: ADXL345_STANDBY
197 * ADXL345_MEASURE
198 * @return 0 in case of success, negative error code otherwise.
199 */
adxl345_set_op_mode(const struct device * dev,enum adxl345_op_mode op_mode)200 int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode)
201 {
202 return adxl345_reg_write_mask(dev, ADXL345_POWER_CTL_REG,
203 ADXL345_POWER_CTL_MEASURE_MSK,
204 ADXL345_POWER_CTL_MEASURE_MODE(op_mode));
205 }
206
207 /**
208 * Set Output data rate.
209 * @param dev - The device structure.
210 * @param odr - Output data rate.
211 * Accepted values: ADXL345_ODR_12HZ
212 * ADXL345_ODR_25HZ
213 * ADXL345_ODR_50HZ
214 * ADXL345_ODR_100HZ
215 * ADXL345_ODR_200HZ
216 * ADXL345_ODR_400HZ
217 * @return 0 in case of success, negative error code otherwise.
218 */
adxl345_set_odr(const struct device * dev,enum adxl345_odr odr)219 static int adxl345_set_odr(const struct device *dev, enum adxl345_odr odr)
220 {
221 return adxl345_reg_write_mask(dev, ADXL345_RATE_REG,
222 ADXL345_ODR_MSK,
223 ADXL345_ODR_MODE(odr));
224 }
225
adxl345_attr_set_odr(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)226 static int adxl345_attr_set_odr(const struct device *dev,
227 enum sensor_channel chan,
228 enum sensor_attribute attr,
229 const struct sensor_value *val)
230 {
231 enum adxl345_odr odr;
232 struct adxl345_dev_config *cfg = (struct adxl345_dev_config *)dev->config;
233
234 switch (val->val1) {
235 case 12:
236 odr = ADXL345_ODR_12HZ;
237 break;
238 case 25:
239 odr = ADXL345_ODR_25HZ;
240 break;
241 case 50:
242 odr = ADXL345_ODR_50HZ;
243 break;
244 case 100:
245 odr = ADXL345_ODR_100HZ;
246 break;
247 case 200:
248 odr = ADXL345_ODR_200HZ;
249 break;
250 case 400:
251 odr = ADXL345_ODR_400HZ;
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 int ret = adxl345_set_odr(dev, odr);
258
259 if (ret == 0) {
260 cfg->odr = odr;
261 }
262
263 return ret;
264 }
265
adxl345_attr_set(const struct device * dev,enum sensor_channel chan,enum sensor_attribute attr,const struct sensor_value * val)266 static int adxl345_attr_set(const struct device *dev,
267 enum sensor_channel chan,
268 enum sensor_attribute attr,
269 const struct sensor_value *val)
270 {
271 switch (attr) {
272 case SENSOR_ATTR_SAMPLING_FREQUENCY:
273 return adxl345_attr_set_odr(dev, chan, attr, val);
274 default:
275 return -ENOTSUP;
276 }
277 }
278
adxl345_read_sample(const struct device * dev,struct adxl345_sample * sample)279 int adxl345_read_sample(const struct device *dev,
280 struct adxl345_sample *sample)
281 {
282 int16_t raw_x, raw_y, raw_z;
283 uint8_t axis_data[6], status1;
284
285 if (!IS_ENABLED(CONFIG_ADXL345_TRIGGER)) {
286 do {
287 adxl345_get_status(dev, &status1, NULL);
288 } while (!(ADXL345_STATUS_DATA_RDY(status1)));
289 }
290
291 int rc = adxl345_reg_read(dev, ADXL345_X_AXIS_DATA_0_REG, axis_data, 6);
292
293 if (rc < 0) {
294 LOG_ERR("Samples read failed with rc=%d\n", rc);
295 return rc;
296 }
297
298 raw_x = axis_data[0] | (axis_data[1] << 8);
299 raw_y = axis_data[2] | (axis_data[3] << 8);
300 raw_z = axis_data[4] | (axis_data[5] << 8);
301
302 sample->x = raw_x;
303 sample->y = raw_y;
304 sample->z = raw_z;
305
306 return 0;
307 }
308
adxl345_accel_convert(struct sensor_value * val,int16_t sample)309 void adxl345_accel_convert(struct sensor_value *val, int16_t sample)
310 {
311 if (sample & BIT(9)) {
312 sample |= ADXL345_COMPLEMENT;
313 }
314
315 val->val1 = ((sample * SENSOR_G) / 32) / 1000000;
316 val->val2 = ((sample * SENSOR_G) / 32) % 1000000;
317 }
318
adxl345_sample_fetch(const struct device * dev,enum sensor_channel chan)319 static int adxl345_sample_fetch(const struct device *dev,
320 enum sensor_channel chan)
321 {
322 struct adxl345_dev_data *data = dev->data;
323 struct adxl345_sample sample;
324 uint8_t samples_count;
325 int rc;
326
327 data->sample_number = 0;
328 rc = adxl345_reg_read_byte(dev, ADXL345_FIFO_STATUS_REG, &samples_count);
329 if (rc < 0) {
330 LOG_ERR("Failed to read FIFO status rc = %d\n", rc);
331 return rc;
332 }
333
334 __ASSERT_NO_MSG(samples_count <= ARRAY_SIZE(data->bufx));
335
336 for (uint8_t s = 0; s < samples_count; s++) {
337 rc = adxl345_read_sample(dev, &sample);
338 if (rc < 0) {
339 LOG_ERR("Failed to fetch sample rc=%d\n", rc);
340 return rc;
341 }
342 data->bufx[s] = sample.x;
343 data->bufy[s] = sample.y;
344 data->bufz[s] = sample.z;
345 }
346
347 return 0;
348 }
349
adxl345_channel_get(const struct device * dev,enum sensor_channel chan,struct sensor_value * val)350 static int adxl345_channel_get(const struct device *dev,
351 enum sensor_channel chan,
352 struct sensor_value *val)
353 {
354 struct adxl345_dev_data *data = dev->data;
355
356 if (data->sample_number >= ARRAY_SIZE(data->bufx)) {
357 data->sample_number = 0;
358 }
359
360 switch (chan) {
361 case SENSOR_CHAN_ACCEL_X:
362 adxl345_accel_convert(val, data->bufx[data->sample_number]);
363 data->sample_number++;
364 break;
365 case SENSOR_CHAN_ACCEL_Y:
366 adxl345_accel_convert(val, data->bufy[data->sample_number]);
367 data->sample_number++;
368 break;
369 case SENSOR_CHAN_ACCEL_Z:
370 adxl345_accel_convert(val, data->bufz[data->sample_number]);
371 data->sample_number++;
372 break;
373 case SENSOR_CHAN_ACCEL_XYZ:
374 adxl345_accel_convert(val++, data->bufx[data->sample_number]);
375 adxl345_accel_convert(val++, data->bufy[data->sample_number]);
376 adxl345_accel_convert(val, data->bufz[data->sample_number]);
377 data->sample_number++;
378 break;
379 default:
380 return -ENOTSUP;
381 }
382
383 return 0;
384 }
385
386 static DEVICE_API(sensor, adxl345_api_funcs) = {
387 .attr_set = adxl345_attr_set,
388 .sample_fetch = adxl345_sample_fetch,
389 .channel_get = adxl345_channel_get,
390 #ifdef CONFIG_ADXL345_TRIGGER
391 .trigger_set = adxl345_trigger_set,
392 #endif
393 #ifdef CONFIG_SENSOR_ASYNC_API
394 .submit = adxl345_submit,
395 .get_decoder = adxl345_get_decoder,
396 #endif
397 };
398
399 #ifdef CONFIG_ADXL345_TRIGGER
400 /**
401 * Configure the INT1 and INT2 interrupt pins.
402 * @param dev - The device structure.
403 * @param int1 - INT1 interrupt pins.
404 * @return 0 in case of success, negative error code otherwise.
405 */
adxl345_interrupt_config(const struct device * dev,uint8_t int1)406 static int adxl345_interrupt_config(const struct device *dev,
407 uint8_t int1)
408 {
409 int ret;
410 const struct adxl345_dev_config *cfg = dev->config;
411
412 ret = adxl345_reg_write_byte(dev, ADXL345_INT_MAP, int1);
413 if (ret) {
414 return ret;
415 }
416
417 ret = adxl345_reg_write_byte(dev, ADXL345_INT_ENABLE, int1);
418 if (ret) {
419 return ret;
420 }
421
422 uint8_t samples;
423
424 ret = adxl345_reg_read_byte(dev, ADXL345_INT_MAP, &samples);
425 ret = adxl345_reg_read_byte(dev, ADXL345_INT_ENABLE, &samples);
426 #ifdef CONFIG_ADXL345_TRIGGER
427 gpio_pin_interrupt_configure_dt(&cfg->interrupt,
428 GPIO_INT_EDGE_TO_ACTIVE);
429 #endif
430 return 0;
431 }
432 #endif
433
adxl345_init(const struct device * dev)434 static int adxl345_init(const struct device *dev)
435 {
436 int rc;
437 struct adxl345_dev_data *data = dev->data;
438 #ifdef CONFIG_ADXL345_TRIGGER
439 const struct adxl345_dev_config *cfg = dev->config;
440 #endif
441 uint8_t dev_id, full_res;
442
443 data->sample_number = 0;
444
445 if (!adxl345_bus_is_ready(dev)) {
446 LOG_ERR("bus not ready");
447 return -ENODEV;
448 }
449
450 rc = adxl345_reg_read_byte(dev, ADXL345_DEVICE_ID_REG, &dev_id);
451 if (rc < 0 || dev_id != ADXL345_PART_ID) {
452 LOG_ERR("Read PART ID failed: 0x%x\n", rc);
453 return -ENODEV;
454 }
455
456 rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE);
457 if (rc < 0) {
458 LOG_ERR("FIFO enable failed\n");
459 return -EIO;
460 }
461
462 rc = adxl345_reg_write_byte(dev, ADXL345_DATA_FORMAT_REG, ADXL345_RANGE_8G);
463 if (rc < 0) {
464 LOG_ERR("Data format set failed\n");
465 return -EIO;
466 }
467
468 data->selected_range = ADXL345_RANGE_8G;
469
470 rc = adxl345_reg_write_byte(dev, ADXL345_RATE_REG, ADXL345_RATE_25HZ);
471 if (rc < 0) {
472 LOG_ERR("Rate setting failed\n");
473 return -EIO;
474 }
475
476 #ifdef CONFIG_ADXL345_TRIGGER
477 rc = adxl345_configure_fifo(dev, ADXL345_FIFO_STREAMED,
478 ADXL345_INT2,
479 SAMPLE_NUM);
480 if (rc) {
481 return rc;
482 }
483 #endif
484
485 rc = adxl345_reg_write_byte(dev, ADXL345_POWER_CTL_REG, ADXL345_ENABLE_MEASURE_BIT);
486 if (rc < 0) {
487 LOG_ERR("Enable measure bit failed\n");
488 return -EIO;
489 }
490
491 #ifdef CONFIG_ADXL345_TRIGGER
492 rc = adxl345_init_interrupt(dev);
493 if (rc < 0) {
494 LOG_ERR("Failed to initialize interrupt!");
495 return -EIO;
496 }
497
498 rc = adxl345_set_odr(dev, cfg->odr);
499 if (rc) {
500 return rc;
501 }
502 rc = adxl345_interrupt_config(dev, ADXL345_INT_MAP_WATERMARK_MSK);
503 if (rc) {
504 return rc;
505 }
506 #endif
507
508 rc = adxl345_reg_read_byte(dev, ADXL345_DATA_FORMAT_REG, &full_res);
509 uint8_t is_full_res_set = (full_res & ADXL345_DATA_FORMAT_FULL_RES) != 0;
510
511 data->is_full_res = is_full_res_set;
512 return 0;
513 }
514
515 #ifdef CONFIG_ADXL345_TRIGGER
516 #define ADXL345_CFG_IRQ(inst) \
517 .interrupt = GPIO_DT_SPEC_INST_GET(inst, int2_gpios),
518 #else
519 #define ADXL345_CFG_IRQ(inst)
520 #endif /* CONFIG_ADXL345_TRIGGER */
521
522 #define ADXL345_RTIO_SPI_DEFINE(inst) \
523 COND_CODE_1(CONFIG_SPI_RTIO, \
524 (SPI_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst), \
525 SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \
526 SPI_MODE_CPOL | SPI_MODE_CPHA, 0U);), \
527 ())
528
529 #define ADXL345_RTIO_I2C_DEFINE(inst) \
530 COND_CODE_1(CONFIG_I2C_RTIO, \
531 (I2C_DT_IODEV_DEFINE(adxl345_iodev_##inst, DT_DRV_INST(inst));), \
532 ())
533
534 /* Conditionally set the RTIO size based on the presence of SPI/I2C
535 * lines 541 - 542.
536 * The sizes of sqe and cqe pools are increased due to the amount of
537 * multibyte reads needed for watermark using 31 samples
538 * (adx345_stram - line 203), using smaller amounts of samples
539 * to trigger an interrupt can decrease the pool sizes.
540 */
541 #define ADXL345_RTIO_DEFINE(inst) \
542 /* Conditionally include SPI and/or I2C parts based on their presence */ \
543 COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
544 (ADXL345_RTIO_SPI_DEFINE(inst)), \
545 ()) \
546 COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
547 (ADXL345_RTIO_I2C_DEFINE(inst)), \
548 ()) \
549 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, spi_dt_spec) && \
550 DT_INST_NODE_HAS_PROP(inst, i2c_dt_spec), \
551 (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 128, 128);), \
552 (RTIO_DEFINE(adxl345_rtio_ctx_##inst, 64, 64);)) \
553
554 #define ADXL345_CONFIG(inst) \
555 .odr = DT_INST_PROP(inst, odr), \
556 .fifo_config.fifo_mode = ADXL345_FIFO_STREAMED, \
557 .fifo_config.fifo_trigger = ADXL345_INT2, \
558 .fifo_config.fifo_samples = SAMPLE_NUM, \
559 .odr = ADXL345_RATE_25HZ, \
560
561 #define ADXL345_CONFIG_SPI(inst) \
562 { \
563 .bus = {.spi = SPI_DT_SPEC_INST_GET(inst, \
564 SPI_WORD_SET(8) | \
565 SPI_TRANSFER_MSB | \
566 SPI_MODE_CPOL | \
567 SPI_MODE_CPHA, \
568 0)}, \
569 .bus_is_ready = adxl345_bus_is_ready_spi, \
570 .reg_access = adxl345_reg_access_spi, \
571 .bus_type = ADXL345_BUS_SPI, \
572 ADXL345_CONFIG(inst) \
573 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
574 (ADXL345_CFG_IRQ(inst)), ()) \
575 }
576
577 #define ADXL345_CONFIG_I2C(inst) \
578 { \
579 .bus = {.i2c = I2C_DT_SPEC_INST_GET(inst)}, \
580 .bus_is_ready = adxl345_bus_is_ready_i2c, \
581 .reg_access = adxl345_reg_access_i2c, \
582 .bus_type = ADXL345_BUS_I2C, \
583 ADXL345_CONFIG(inst) \
584 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, int2_gpios), \
585 (ADXL345_CFG_IRQ(inst)), ()) \
586 }
587
588 #define ADXL345_DEFINE(inst) \
589 IF_ENABLED(CONFIG_ADXL345_STREAM, (ADXL345_RTIO_DEFINE(inst))); \
590 static struct adxl345_dev_data adxl345_data_##inst = { \
591 COND_CODE_1(adxl345_iodev_##inst, (.rtio_ctx = &adxl345_rtio_ctx_##inst, \
592 .iodev = &adxl345_iodev_##inst,), ()) \
593 }; \
594 static const struct adxl345_dev_config adxl345_config_##inst = \
595 COND_CODE_1(DT_INST_ON_BUS(inst, spi), (ADXL345_CONFIG_SPI(inst)), \
596 (ADXL345_CONFIG_I2C(inst))); \
597 \
598 SENSOR_DEVICE_DT_INST_DEFINE(inst, adxl345_init, NULL, \
599 &adxl345_data_##inst, &adxl345_config_##inst, POST_KERNEL,\
600 CONFIG_SENSOR_INIT_PRIORITY, &adxl345_api_funcs); \
601
602 DT_INST_FOREACH_STATUS_OKAY(ADXL345_DEFINE)
603
