1 /* 2 * Copyright (c) 2016 Nordic Semiconductor ASA 3 * Copyright (c) 2016 Vinayak Kariappa Chettimada 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /* 9 * PDU fields sizes 10 */ 11 12 #define PDU_PREAMBLE_SIZE(phy) (phy&0x3) 13 #define PDU_ACCESS_ADDR_SIZE 4 14 #define PDU_HEADER_SIZE 2 15 #define PDU_MIC_SIZE 4 16 #define PDU_CRC_SIZE 3 17 #define PDU_OVERHEAD_SIZE(phy) (PDU_PREAMBLE_SIZE(phy) + \ 18 PDU_ACCESS_ADDR_SIZE + \ 19 PDU_HEADER_SIZE + \ 20 PDU_CRC_SIZE) 21 22 #define BDADDR_SIZE 6 23 #define ADVA_SIZE BDADDR_SIZE 24 #define SCANA_SIZE BDADDR_SIZE 25 #define INITA_SIZE BDADDR_SIZE 26 #define TARGETA_SIZE BDADDR_SIZE 27 #define LLDATA_SIZE 22 28 29 /* Constant offsets in extended header (TargetA is present in PDUs with AdvA) */ 30 #define ADVA_OFFSET 0 31 #define TGTA_OFFSET (ADVA_OFFSET + BDADDR_SIZE) 32 33 #define BYTES2US(bytes, phy) (((bytes)<<3)/BIT((phy&0x3)>>1)) 34 35 /* Advertisement channel minimum payload size */ 36 #define PDU_AC_PAYLOAD_SIZE_MIN 1 37 /* Advertisement channel maximum legacy payload size */ 38 #define PDU_AC_LEG_PAYLOAD_SIZE_MAX 37 39 /* Advertisement channel maximum extended payload size */ 40 #define PDU_AC_EXT_PAYLOAD_SIZE_MAX 255 41 42 /* Advertisement channel maximum payload size */ 43 #if defined(CONFIG_BT_CTLR_ADV_EXT) 44 #define PDU_AC_EXT_HEADER_SIZE_MIN offsetof(struct pdu_adv_com_ext_adv, \ 45 ext_hdr_adv_data) 46 #define PDU_AC_EXT_HEADER_SIZE_MAX 63 47 /* TODO: PDU_AC_EXT_PAYLOAD_OVERHEAD can be reduced based on supported 48 * features, like omitting support for periodic advertising will reduce 49 * 18 octets in the Common Extended Advertising Payload Format. 50 */ 51 #define PDU_AC_EXT_PAYLOAD_OVERHEAD (PDU_AC_EXT_HEADER_SIZE_MIN + \ 52 PDU_AC_EXT_HEADER_SIZE_MAX) 53 #define PDU_AC_PAYLOAD_SIZE_MAX MAX(MIN((PDU_AC_EXT_PAYLOAD_OVERHEAD + \ 54 CONFIG_BT_CTLR_ADV_DATA_LEN_MAX), \ 55 PDU_AC_EXT_PAYLOAD_SIZE_MAX), \ 56 PDU_AC_LEG_PAYLOAD_SIZE_MAX) 57 #else 58 #define PDU_AC_PAYLOAD_SIZE_MAX PDU_AC_LEG_PAYLOAD_SIZE_MAX 59 #endif 60 61 /* Link Layer header size of Adv PDU. Assumes pdu_adv is packed */ 62 #define PDU_AC_LL_HEADER_SIZE (offsetof(struct pdu_adv, payload)) 63 64 /* Link Layer Advertisement channel maximum PDU buffer size */ 65 #define PDU_AC_LL_SIZE_MAX (PDU_AC_LL_HEADER_SIZE + PDU_AC_PAYLOAD_SIZE_MAX) 66 67 /* Advertisement channel maximum legacy advertising/scan data size */ 68 #define PDU_AC_DATA_SIZE_MAX 31 69 70 /* Advertisement channel Access Address */ 71 #define PDU_AC_ACCESS_ADDR 0x8e89bed6 72 73 /* Data channel minimum payload size and time */ 74 #define PDU_DC_PAYLOAD_SIZE_MIN 27 75 #define PDU_DC_PAYLOAD_TIME_MIN 328 76 77 /* Link Layer header size of Data PDU. Assumes pdu_data is packed */ 78 #define PDU_DC_LL_HEADER_SIZE (offsetof(struct pdu_data, lldata)) 79 80 /* Link Layer Max size of an empty PDU. TODO: Remove; only used in Nordic LLL */ 81 #define PDU_EM_LL_SIZE_MAX (PDU_DC_LL_HEADER_SIZE) 82 83 /* Link Layer header size of BIS PDU. Assumes pdu_bis is packed */ 84 #define PDU_BIS_LL_HEADER_SIZE (offsetof(struct pdu_bis, payload)) 85 86 /* Event Active Clock Jitter */ 87 #define EVENT_CLOCK_JITTER_US 2 88 /* Event interframe timings */ 89 #define EVENT_IFS_US 150 90 /* Standard allows 2 us timing uncertainty inside the event */ 91 #define EVENT_IFS_MAX_US (EVENT_IFS_US + EVENT_CLOCK_JITTER_US) 92 /* Controller will layout extended adv with minimum separation */ 93 #define EVENT_MAFS_US 300 94 /* Standard allows 2 us timing uncertainty inside the event */ 95 #define EVENT_MAFS_MAX_US (EVENT_MAFS_US + EVENT_CLOCK_JITTER_US) 96 /* Minimum Subevent Space timings */ 97 #define EVENT_MSS_US 150 98 /* Standard allows 2 us timing uncertainty inside the event */ 99 #define EVENT_MSS_MAX_US (EVENT_MSS_US + EVENT_CLOCK_JITTER_US) 100 101 /* Instant maximum value and maximum latency (or delta) past the instant */ 102 #define EVENT_INSTANT_MAX 0xffff 103 #define EVENT_INSTANT_LATENCY_MAX 0x7fff 104 105 /* Offset Units field encoding */ 106 #define OFFS_UNIT_30_US 30 107 #define OFFS_UNIT_300_US 300 108 #define OFFS_UNIT_VALUE_30_US 0 109 #define OFFS_UNIT_VALUE_300_US 1 110 /* Value specified in BT Spec. Vol 6, Part B, section 2.3.4.6 */ 111 #define OFFS_ADJUST_US 245760 112 113 /* Advertiser's Sleep Clock Accuracy Value */ 114 #define SCA_500_PPM 500 /* 51 ppm to 500 ppm */ 115 #define SCA_50_PPM 50 /* 0 ppm to 50 ppm */ 116 #define SCA_VALUE_500_PPM 0 /* 51 ppm to 500 ppm */ 117 #define SCA_VALUE_50_PPM 1 /* 0 ppm to 50 ppm */ 118 119 /* Sleep Clock Accuracy, calculate drift in microseconds */ 120 #define SCA_DRIFT_50_PPM_US(t) (((t) * 50UL) / 1000000UL) 121 #define SCA_DRIFT_500_PPM_US(t) (((t) * 500UL) / 1000000UL) 122 123 /* transmitWindowDelay times (us) */ 124 #define WIN_DELAY_LEGACY 1250 125 #define WIN_DELAY_UNCODED 2500 126 #define WIN_DELAY_CODED 3750 127 128 /* Channel Map Size */ 129 #define PDU_CHANNEL_MAP_SIZE 5 130 131 /* 132 * Macros to return correct Data Channel PDU time 133 * Note: formula is valid for 1M, 2M and Coded S8 134 * see BT spec Version 5.1 Vol 6. Part B, chapters 2.1 and 2.2 135 * for packet formats and thus lengths 136 */ 137 138 #define PHY_LEGACY 0 139 #define PHY_1M BIT(0) 140 #define PHY_2M BIT(1) 141 #define PHY_CODED BIT(2) 142 #define PHY_FLAGS_S2 0 143 #define PHY_FLAGS_S8 BIT(0) 144 145 #if defined(CONFIG_BT_CTLR_PHY_CODED) 146 #define CODED_PHY_PREAMBLE_TIME_US 80 147 #define CODED_PHY_ACCESS_ADDRESS_TIME_US 256 148 #define CODED_PHY_CI_TIME_US 16 149 #define CODED_PHY_TERM1_TIME_US 24 150 #define CODED_PHY_CRC_SIZE 24 151 #define CODED_PHY_TERM2_SIZE 3 152 153 #define FEC_BLOCK1_US ((CODED_PHY_ACCESS_ADDRESS_TIME_US) + \ 154 (CODED_PHY_CI_TIME_US) + \ 155 (CODED_PHY_TERM1_TIME_US)) 156 157 /* cs = 0, S2 coding scheme, use PHY_FLAGS_S2 158 * cs = 1, S8 coding scheme, use PHY_FLAGS_S8 159 * 160 * Not using the term CI, Coding Indicator, where in the Spec its defined value 161 * of 0 is S8 encoding, 1 is S2 encoding. 162 */ 163 #define FEC_BLOCK2_US(octets, mic, cs) (((((PDU_HEADER_SIZE) + \ 164 (octets) + \ 165 (mic)) << 3) + \ 166 (CODED_PHY_CRC_SIZE) + \ 167 (CODED_PHY_TERM2_SIZE)) << \ 168 (1 + (((cs) & 0x01) << 1))) 169 170 #define PDU_US(octets, mic, phy, cs) (((phy) & PHY_CODED) ? \ 171 ((CODED_PHY_PREAMBLE_TIME_US) + \ 172 (FEC_BLOCK1_US) + \ 173 FEC_BLOCK2_US((octets), (mic), \ 174 (cs))) : \ 175 (((PDU_PREAMBLE_SIZE(phy) + \ 176 (PDU_ACCESS_ADDR_SIZE) + \ 177 (PDU_HEADER_SIZE) + \ 178 (octets) + \ 179 (mic) + \ 180 (PDU_CRC_SIZE)) << 3) / \ 181 BIT(((phy) & 0x03) >> 1))) 182 183 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), \ 184 PHY_FLAGS_S8) 185 186 #else /* !CONFIG_BT_CTLR_PHY_CODED */ 187 #define PDU_US(octets, mic, phy, cs) (((PDU_PREAMBLE_SIZE(phy) + \ 188 (PDU_ACCESS_ADDR_SIZE) + \ 189 (PDU_HEADER_SIZE) + \ 190 (octets) + \ 191 (mic) + \ 192 (PDU_CRC_SIZE)) << 3) / \ 193 BIT(((phy) & 0x03) >> 1)) 194 195 #define PDU_MAX_US(octets, mic, phy) PDU_US((octets), (mic), (phy), 0) 196 #endif /* !CONFIG_BT_CTLR_PHY_CODED */ 197 198 #define PDU_DC_MAX_US(octets, phy) PDU_MAX_US((octets), (PDU_MIC_SIZE), (phy)) 199 200 #define PDU_DC_US(octets, mic, phy, cs) PDU_US((octets), (mic), (phy), (cs)) 201 202 #define PDU_AC_MAX_US(octets, phy) PDU_MAX_US((octets), 0, (phy)) 203 204 #define PDU_AC_US(octets, phy, cs) PDU_US((octets), 0, (phy), (cs)) 205 206 #define PKT_BIS_US(octets, mic, phy) PDU_MAX_US((octets), (mic), (phy)) 207 208 struct pdu_adv_adv_ind { 209 uint8_t addr[BDADDR_SIZE]; 210 uint8_t data[PDU_AC_DATA_SIZE_MAX]; 211 } __packed; 212 213 struct pdu_adv_direct_ind { 214 uint8_t adv_addr[BDADDR_SIZE]; 215 uint8_t tgt_addr[BDADDR_SIZE]; 216 } __packed; 217 218 struct pdu_adv_scan_rsp { 219 uint8_t addr[BDADDR_SIZE]; 220 uint8_t data[PDU_AC_DATA_SIZE_MAX]; 221 } __packed; 222 223 struct pdu_adv_scan_req { 224 uint8_t scan_addr[BDADDR_SIZE]; 225 uint8_t adv_addr[BDADDR_SIZE]; 226 } __packed; 227 228 struct pdu_adv_connect_ind { 229 uint8_t init_addr[BDADDR_SIZE]; 230 uint8_t adv_addr[BDADDR_SIZE]; 231 struct { 232 uint8_t access_addr[4]; 233 uint8_t crc_init[3]; 234 uint8_t win_size; 235 uint16_t win_offset; 236 uint16_t interval; 237 uint16_t latency; 238 uint16_t timeout; 239 uint8_t chan_map[PDU_CHANNEL_MAP_SIZE]; 240 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 241 uint8_t hop:5; 242 uint8_t sca:3; 243 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 244 uint8_t sca:3; 245 uint8_t hop:5; 246 #else 247 #error "Unsupported endianness" 248 #endif 249 250 } __packed; 251 } __packed; 252 253 struct pdu_adv_ext_hdr { 254 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 255 uint8_t adv_addr:1; 256 uint8_t tgt_addr:1; 257 uint8_t cte_info:1; 258 uint8_t adi:1; 259 uint8_t aux_ptr:1; 260 uint8_t sync_info:1; 261 uint8_t tx_pwr:1; 262 uint8_t rfu:1; 263 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 264 uint8_t rfu:1; 265 uint8_t tx_pwr:1; 266 uint8_t sync_info:1; 267 uint8_t aux_ptr:1; 268 uint8_t adi:1; 269 uint8_t cte_info:1; 270 uint8_t tgt_addr:1; 271 uint8_t adv_addr:1; 272 #else 273 #error "Unsupported endianness" 274 #endif 275 uint8_t data[0]; 276 } __packed; 277 278 struct pdu_adv_com_ext_adv { 279 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 280 uint8_t ext_hdr_len:6; 281 uint8_t adv_mode:2; 282 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 283 uint8_t adv_mode:2; 284 uint8_t ext_hdr_len:6; 285 #else 286 #error "Unsupported endianness" 287 #endif 288 union { 289 struct pdu_adv_ext_hdr ext_hdr; 290 uint8_t ext_hdr_adv_data[0]; 291 }; 292 } __packed; 293 294 enum pdu_adv_mode { 295 EXT_ADV_MODE_NON_CONN_NON_SCAN = 0x00, 296 EXT_ADV_MODE_CONN_NON_SCAN = 0x01, 297 EXT_ADV_MODE_NON_CONN_SCAN = 0x02, 298 }; 299 300 #define PDU_ADV_SID_COUNT 16 301 302 struct pdu_adv_adi { 303 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 304 uint16_t did:12; 305 uint16_t sid:4; 306 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 307 uint16_t sid:4; 308 uint16_t did:12; 309 #else 310 #error "Unsupported endianness" 311 #endif 312 } __packed; 313 314 struct pdu_adv_aux_ptr { 315 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 316 uint8_t chan_idx:6; 317 uint8_t ca:1; 318 uint8_t offs_units:1; 319 uint16_t offs:13; 320 uint16_t phy:3; 321 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 322 uint8_t offs_units:1; 323 uint8_t ca:1; 324 uint8_t chan_idx:6; 325 uint16_t phy:3; 326 uint16_t offs:13; 327 #else 328 #error "Unsupported endianness" 329 #endif 330 } __packed; 331 332 enum pdu_adv_aux_ptr_ca { 333 EXT_ADV_AUX_PTR_CA_500_PPM = 0x00, 334 EXT_ADV_AUX_PTR_CA_50_PPM = 0x01, 335 }; 336 337 enum pdu_adv_offs_units { 338 EXT_ADV_AUX_PTR_OFFS_UNITS_30 = 0x00, 339 EXT_ADV_AUX_PTR_OFFS_UNITS_300 = 0x01, 340 }; 341 342 enum pdu_adv_aux_phy { 343 EXT_ADV_AUX_PHY_LE_1M = 0x00, 344 EXT_ADV_AUX_PHY_LE_2M = 0x01, 345 EXT_ADV_AUX_PHY_LE_CODED = 0x02, 346 }; 347 348 struct pdu_cte_info { 349 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 350 uint8_t time:5; 351 uint8_t rfu:1; 352 uint8_t type:2; 353 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 354 uint8_t type:2; 355 uint8_t rfu:1; 356 uint8_t time:5; 357 #else 358 #error "Unsupported endianness" 359 #endif 360 }; 361 362 struct pdu_adv_sync_info { 363 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 364 uint16_t offs:13; 365 uint16_t offs_units:1; 366 uint16_t offs_adjust:1; 367 uint16_t rfu:1; 368 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 369 uint16_t rfu:1; 370 uint16_t offs_adjust:1; 371 uint16_t offs_units:1; 372 uint16_t offs:13; 373 #else 374 #error "Unsupported endianness" 375 #endif 376 uint16_t interval; 377 uint8_t sca_chm[PDU_CHANNEL_MAP_SIZE]; 378 uint32_t aa; 379 uint8_t crc_init[3]; 380 uint16_t evt_cntr; 381 } __packed; 382 383 #define PDU_SYNC_INFO_SCA_CHM_SCA_BYTE_OFFSET 4 384 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS 5 385 #define PDU_SYNC_INFO_SCA_CHM_SCA_BIT_MASK \ 386 (0x07 << (PDU_SYNC_INFO_SCA_CHM_SCA_BIT_POS)) 387 388 struct pdu_adv_sync_chm_upd_ind { 389 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 390 uint16_t instant; 391 } __packed; 392 393 enum pdu_adv_type { 394 PDU_ADV_TYPE_ADV_IND = 0x00, 395 PDU_ADV_TYPE_DIRECT_IND = 0x01, 396 PDU_ADV_TYPE_NONCONN_IND = 0x02, 397 PDU_ADV_TYPE_SCAN_REQ = 0x03, 398 PDU_ADV_TYPE_AUX_SCAN_REQ = PDU_ADV_TYPE_SCAN_REQ, 399 PDU_ADV_TYPE_SCAN_RSP = 0x04, 400 PDU_ADV_TYPE_ADV_IND_SCAN_RSP = 0x05, 401 PDU_ADV_TYPE_CONNECT_IND = 0x05, 402 PDU_ADV_TYPE_AUX_CONNECT_REQ = PDU_ADV_TYPE_CONNECT_IND, 403 PDU_ADV_TYPE_SCAN_IND = 0x06, 404 PDU_ADV_TYPE_EXT_IND = 0x07, 405 PDU_ADV_TYPE_AUX_ADV_IND = PDU_ADV_TYPE_EXT_IND, 406 PDU_ADV_TYPE_AUX_SCAN_RSP = PDU_ADV_TYPE_EXT_IND, 407 PDU_ADV_TYPE_AUX_SYNC_IND = PDU_ADV_TYPE_EXT_IND, 408 PDU_ADV_TYPE_AUX_CHAIN_IND = PDU_ADV_TYPE_EXT_IND, 409 PDU_ADV_TYPE_AUX_CONNECT_RSP = 0x08, 410 } __packed; 411 412 struct pdu_adv { 413 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 414 uint8_t type:4; 415 uint8_t rfu:1; 416 uint8_t chan_sel:1; 417 uint8_t tx_addr:1; 418 uint8_t rx_addr:1; 419 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 420 uint8_t rx_addr:1; 421 uint8_t tx_addr:1; 422 uint8_t chan_sel:1; 423 uint8_t rfu:1; 424 uint8_t type:4; 425 #else 426 #error "Unsupported endianness" 427 #endif 428 429 uint8_t len; 430 431 union { 432 uint8_t payload[0]; 433 struct pdu_adv_adv_ind adv_ind; 434 struct pdu_adv_direct_ind direct_ind; 435 struct pdu_adv_scan_req scan_req; 436 struct pdu_adv_scan_rsp scan_rsp; 437 struct pdu_adv_connect_ind connect_ind; 438 439 #if defined(CONFIG_BT_CTLR_ADV_EXT) 440 struct pdu_adv_com_ext_adv adv_ext_ind; 441 #endif /* CONFIG_BT_CTLR_ADV_EXT */ 442 } __packed; 443 } __packed; 444 445 enum pdu_data_llid { 446 PDU_DATA_LLID_RESV = 0x00, 447 PDU_DATA_LLID_DATA_CONTINUE = 0x01, 448 PDU_DATA_LLID_DATA_START = 0x02, 449 PDU_DATA_LLID_CTRL = 0x03, 450 }; 451 452 enum pdu_data_llctrl_type { 453 PDU_DATA_LLCTRL_TYPE_CONN_UPDATE_IND = 0x00, 454 PDU_DATA_LLCTRL_TYPE_CHAN_MAP_IND = 0x01, 455 PDU_DATA_LLCTRL_TYPE_TERMINATE_IND = 0x02, 456 PDU_DATA_LLCTRL_TYPE_ENC_REQ = 0x03, 457 PDU_DATA_LLCTRL_TYPE_ENC_RSP = 0x04, 458 PDU_DATA_LLCTRL_TYPE_START_ENC_REQ = 0x05, 459 PDU_DATA_LLCTRL_TYPE_START_ENC_RSP = 0x06, 460 PDU_DATA_LLCTRL_TYPE_UNKNOWN_RSP = 0x07, 461 PDU_DATA_LLCTRL_TYPE_FEATURE_REQ = 0x08, 462 PDU_DATA_LLCTRL_TYPE_FEATURE_RSP = 0x09, 463 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_REQ = 0x0A, 464 PDU_DATA_LLCTRL_TYPE_PAUSE_ENC_RSP = 0x0B, 465 PDU_DATA_LLCTRL_TYPE_VERSION_IND = 0x0C, 466 PDU_DATA_LLCTRL_TYPE_REJECT_IND = 0x0D, 467 PDU_DATA_LLCTRL_TYPE_PER_INIT_FEAT_XCHG = 0x0E, 468 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_REQ = 0x0F, 469 PDU_DATA_LLCTRL_TYPE_CONN_PARAM_RSP = 0x10, 470 PDU_DATA_LLCTRL_TYPE_REJECT_EXT_IND = 0x11, 471 PDU_DATA_LLCTRL_TYPE_PING_REQ = 0x12, 472 PDU_DATA_LLCTRL_TYPE_PING_RSP = 0x13, 473 PDU_DATA_LLCTRL_TYPE_LENGTH_REQ = 0x14, 474 PDU_DATA_LLCTRL_TYPE_LENGTH_RSP = 0x15, 475 PDU_DATA_LLCTRL_TYPE_PHY_REQ = 0x16, 476 PDU_DATA_LLCTRL_TYPE_PHY_RSP = 0x17, 477 PDU_DATA_LLCTRL_TYPE_PHY_UPD_IND = 0x18, 478 PDU_DATA_LLCTRL_TYPE_MIN_USED_CHAN_IND = 0x19, 479 PDU_DATA_LLCTRL_TYPE_CIS_REQ = 0x1F, 480 PDU_DATA_LLCTRL_TYPE_CIS_RSP = 0x20, 481 PDU_DATA_LLCTRL_TYPE_CIS_IND = 0x21, 482 PDU_DATA_LLCTRL_TYPE_CIS_TERMINATE_IND = 0x22, 483 }; 484 485 struct pdu_data_llctrl_conn_update_ind { 486 uint8_t win_size; 487 uint16_t win_offset; 488 uint16_t interval; 489 uint16_t latency; 490 uint16_t timeout; 491 uint16_t instant; 492 } __packed; 493 494 struct pdu_data_llctrl_chan_map_ind { 495 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 496 uint16_t instant; 497 } __packed; 498 499 struct pdu_data_llctrl_terminate_ind { 500 uint8_t error_code; 501 } __packed; 502 503 struct pdu_data_llctrl_enc_req { 504 uint8_t rand[8]; 505 uint8_t ediv[2]; 506 uint8_t skdm[8]; 507 uint8_t ivm[4]; 508 } __packed; 509 510 struct pdu_data_llctrl_enc_rsp { 511 uint8_t skds[8]; 512 uint8_t ivs[4]; 513 } __packed; 514 515 struct pdu_data_llctrl_start_enc_req { 516 /* no members */ 517 } __packed; 518 519 struct pdu_data_llctrl_start_enc_rsp { 520 /* no members */ 521 } __packed; 522 523 struct pdu_data_llctrl_unknown_rsp { 524 uint8_t type; 525 } __packed; 526 527 struct pdu_data_llctrl_feature_req { 528 uint8_t features[8]; 529 } __packed; 530 531 struct pdu_data_llctrl_feature_rsp { 532 uint8_t features[8]; 533 } __packed; 534 535 struct pdu_data_llctrl_pause_enc_req { 536 /* no members */ 537 } __packed; 538 539 struct pdu_data_llctrl_pause_enc_rsp { 540 /* no members */ 541 } __packed; 542 543 struct pdu_data_llctrl_version_ind { 544 uint8_t version_number; 545 uint16_t company_id; 546 uint16_t sub_version_number; 547 } __packed; 548 549 struct pdu_data_llctrl_reject_ind { 550 uint8_t error_code; 551 } __packed; 552 553 struct pdu_data_llctrl_per_init_feat_xchg { 554 uint8_t features[8]; 555 } __packed; 556 557 struct pdu_data_llctrl_conn_param_req { 558 uint16_t interval_min; 559 uint16_t interval_max; 560 uint16_t latency; 561 uint16_t timeout; 562 uint8_t preferred_periodicity; 563 uint16_t reference_conn_event_count; 564 uint16_t offset0; 565 uint16_t offset1; 566 uint16_t offset2; 567 uint16_t offset3; 568 uint16_t offset4; 569 uint16_t offset5; 570 } __packed; 571 572 struct pdu_data_llctrl_conn_param_rsp { 573 uint16_t interval_min; 574 uint16_t interval_max; 575 uint16_t latency; 576 uint16_t timeout; 577 uint8_t preferred_periodicity; 578 uint16_t reference_conn_event_count; 579 uint16_t offset0; 580 uint16_t offset1; 581 uint16_t offset2; 582 uint16_t offset3; 583 uint16_t offset4; 584 uint16_t offset5; 585 } __packed; 586 587 struct pdu_data_llctrl_reject_ext_ind { 588 uint8_t reject_opcode; 589 uint8_t error_code; 590 } __packed; 591 592 struct pdu_data_llctrl_ping_req { 593 /* no members */ 594 } __packed; 595 596 struct pdu_data_llctrl_ping_rsp { 597 /* no members */ 598 } __packed; 599 600 struct pdu_data_llctrl_length_req { 601 uint16_t max_rx_octets; 602 uint16_t max_rx_time; 603 uint16_t max_tx_octets; 604 uint16_t max_tx_time; 605 } __packed; 606 607 struct pdu_data_llctrl_length_rsp { 608 uint16_t max_rx_octets; 609 uint16_t max_rx_time; 610 uint16_t max_tx_octets; 611 uint16_t max_tx_time; 612 } __packed; 613 614 struct pdu_data_llctrl_phy_req { 615 uint8_t tx_phys; 616 uint8_t rx_phys; 617 } __packed; 618 619 struct pdu_data_llctrl_phy_rsp { 620 uint8_t tx_phys; 621 uint8_t rx_phys; 622 } __packed; 623 624 struct pdu_data_llctrl_phy_upd_ind { 625 uint8_t c_to_p_phy; 626 uint8_t p_to_c_phy; 627 uint16_t instant; 628 } __packed; 629 630 struct pdu_data_llctrl_min_used_chans_ind { 631 uint8_t phys; 632 uint8_t min_used_chans; 633 } __packed; 634 635 struct pdu_data_llctrl_cis_req { 636 uint8_t cig_id; 637 uint8_t cis_id; 638 uint8_t c_phy; 639 uint8_t p_phy; 640 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 641 uint16_t c_max_sdu:12; 642 uint16_t rfu0:3; 643 uint16_t framed:1; 644 uint16_t p_max_sdu:12; 645 uint16_t rfu1:4; 646 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 647 uint16_t framed:1; 648 uint16_t rfu0:3; 649 uint16_t c_max_sdu:12; 650 uint16_t rfu1:4; 651 uint16_t p_max_sdu:12; 652 #else 653 #error "Unsupported endianness" 654 #endif 655 uint8_t c_sdu_interval[3]; 656 uint8_t p_sdu_interval[3]; 657 uint16_t c_max_pdu; 658 uint16_t p_max_pdu; 659 uint8_t nse; 660 uint8_t sub_interval[3]; 661 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 662 uint8_t c_bn:4; 663 uint8_t p_bn:4; 664 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 665 uint8_t p_bn:4; 666 uint8_t c_bn:4; 667 #else 668 #error "Unsupported endianness" 669 #endif 670 uint8_t c_ft; 671 uint8_t p_ft; 672 uint16_t iso_interval; 673 uint8_t cis_offset_min[3]; 674 uint8_t cis_offset_max[3]; 675 uint16_t conn_event_count; 676 } __packed; 677 678 struct pdu_data_llctrl_cis_rsp { 679 uint8_t cis_offset_min[3]; 680 uint8_t cis_offset_max[3]; 681 uint16_t conn_event_count; 682 } __packed; 683 684 struct pdu_data_llctrl_cis_ind { 685 uint8_t aa[4]; 686 uint8_t cis_offset[3]; 687 uint8_t cig_sync_delay[3]; 688 uint8_t cis_sync_delay[3]; 689 uint16_t conn_event_count; 690 } __packed; 691 692 struct pdu_data_llctrl_cis_terminate_ind { 693 uint8_t cig_id; 694 uint8_t cis_id; 695 uint8_t error_code; 696 } __packed; 697 698 struct pdu_data_llctrl { 699 uint8_t opcode; 700 union { 701 struct pdu_data_llctrl_conn_update_ind conn_update_ind; 702 struct pdu_data_llctrl_chan_map_ind chan_map_ind; 703 struct pdu_data_llctrl_terminate_ind terminate_ind; 704 struct pdu_data_llctrl_enc_req enc_req; 705 struct pdu_data_llctrl_enc_rsp enc_rsp; 706 struct pdu_data_llctrl_start_enc_req start_enc_req; 707 struct pdu_data_llctrl_start_enc_rsp start_enc_rsp; 708 struct pdu_data_llctrl_unknown_rsp unknown_rsp; 709 struct pdu_data_llctrl_feature_req feature_req; 710 struct pdu_data_llctrl_feature_rsp feature_rsp; 711 struct pdu_data_llctrl_pause_enc_req pause_enc_req; 712 struct pdu_data_llctrl_pause_enc_rsp pause_enc_rsp; 713 struct pdu_data_llctrl_version_ind version_ind; 714 struct pdu_data_llctrl_reject_ind reject_ind; 715 struct pdu_data_llctrl_per_init_feat_xchg per_init_feat_xchg; 716 struct pdu_data_llctrl_conn_param_req conn_param_req; 717 struct pdu_data_llctrl_conn_param_rsp conn_param_rsp; 718 struct pdu_data_llctrl_reject_ext_ind reject_ext_ind; 719 struct pdu_data_llctrl_ping_req ping_req; 720 struct pdu_data_llctrl_ping_rsp ping_rsp; 721 struct pdu_data_llctrl_length_req length_req; 722 struct pdu_data_llctrl_length_rsp length_rsp; 723 struct pdu_data_llctrl_phy_req phy_req; 724 struct pdu_data_llctrl_phy_rsp phy_rsp; 725 struct pdu_data_llctrl_phy_upd_ind phy_upd_ind; 726 struct pdu_data_llctrl_min_used_chans_ind min_used_chans_ind; 727 struct pdu_data_llctrl_cis_req cis_req; 728 struct pdu_data_llctrl_cis_rsp cis_rsp; 729 struct pdu_data_llctrl_cis_ind cis_ind; 730 struct pdu_data_llctrl_cis_terminate_ind cis_terminate_ind; 731 } __packed; 732 } __packed; 733 734 #define PDU_DATA_LLCTRL_LEN(type) (offsetof(struct pdu_data_llctrl, type) + \ 735 sizeof(struct pdu_data_llctrl_ ## type)) 736 737 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 738 struct profile { 739 uint8_t lcur; 740 uint8_t lmin; 741 uint8_t lmax; 742 uint8_t cur; 743 uint8_t min; 744 uint8_t max; 745 uint8_t radio; 746 uint8_t lll; 747 uint8_t ull_high; 748 uint8_t ull_low; 749 } __packed; 750 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 751 752 struct pdu_data { 753 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 754 uint8_t ll_id:2; 755 uint8_t nesn:1; 756 uint8_t sn:1; 757 uint8_t md:1; 758 uint8_t rfu:3; 759 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 760 uint8_t rfu:3; 761 uint8_t md:1; 762 uint8_t sn:1; 763 uint8_t nesn:1; 764 uint8_t ll_id:2; 765 #else 766 #error "Unsupported endianness" 767 #endif 768 769 uint8_t len; 770 771 #if !defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32) 772 #if !defined(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR) 773 uint8_t resv:8; /* TODO: remove nRF specific code */ 774 #endif /* !CONFIG_BT_CTLR_DATA_LENGTH_CLEAR */ 775 #endif /* !CONFIG_SOC_OPENISA_RV32M1_RISCV32 */ 776 777 union { 778 struct pdu_data_llctrl llctrl; 779 uint8_t lldata[0]; 780 781 #if defined(CONFIG_BT_CTLR_CONN_RSSI) 782 uint8_t rssi; 783 #endif /* CONFIG_BT_CTLR_CONN_RSSI */ 784 785 #if defined(CONFIG_BT_CTLR_PROFILE_ISR) 786 struct profile profile; 787 #endif /* CONFIG_BT_CTLR_PROFILE_ISR */ 788 } __packed; 789 } __packed; 790 791 struct pdu_cis { 792 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 793 uint8_t ll_id:2; 794 uint8_t nesn:1; 795 uint8_t sn:1; 796 uint8_t cie:1; 797 uint8_t rfu0:1; 798 uint8_t npi:1; 799 uint8_t rfu1:1; 800 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 801 uint8_t rfu1:1; 802 uint8_t npi:1; 803 uint8_t rfu0:1; 804 uint8_t cie:1; 805 uint8_t sn:1; 806 uint8_t nesn:1; 807 uint8_t ll_id:2; 808 #else 809 #error "Unsupported endianness" 810 #endif /* __BYTE_ORDER__ */ 811 uint8_t length; 812 uint8_t payload[0]; 813 } __packed; 814 815 enum pdu_big_ctrl_type { 816 PDU_BIG_CTRL_TYPE_CHAN_MAP_IND = 0x00, 817 PDU_BIG_CTRL_TYPE_TERM_IND = 0x01, 818 }; 819 820 struct pdu_big_ctrl_chan_map_ind { 821 uint8_t chm[PDU_CHANNEL_MAP_SIZE]; 822 uint16_t instant; 823 } __packed; 824 825 struct pdu_big_ctrl_term_ind { 826 uint8_t reason; 827 uint16_t instant; 828 } __packed; 829 830 831 struct pdu_big_ctrl { 832 uint8_t opcode; 833 union { 834 uint8_t ctrl_data[0]; 835 struct pdu_big_ctrl_chan_map_ind chan_map_ind; 836 struct pdu_big_ctrl_term_ind term_ind; 837 } __packed; 838 } __packed; 839 840 enum pdu_bis_llid { 841 /** Unframed complete or end fragment */ 842 PDU_BIS_LLID_COMPLETE_END = 0x00, 843 /** Unframed start or continuation fragment */ 844 PDU_BIS_LLID_START_CONTINUE = 0x01, 845 /** Framed; one or more segments of a SDU */ 846 PDU_BIS_LLID_FRAMED = 0x02, 847 /** BIG Control PDU */ 848 PDU_BIS_LLID_CTRL = 0x03, 849 }; 850 851 struct pdu_bis { 852 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 853 uint8_t ll_id:2; 854 uint8_t cssn:3; 855 uint8_t cstf:1; 856 uint8_t rfu:2; 857 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 858 uint8_t rfu:2; 859 uint8_t cstf:1; 860 uint8_t cssn:3; 861 uint8_t ll_id:2; 862 #else 863 #error "Unsupported endianness" 864 #endif /* __BYTE_ORDER__ */ 865 uint8_t len; 866 union { 867 uint8_t payload[0]; 868 struct pdu_big_ctrl ctrl; 869 } __packed; 870 } __packed; 871 872 struct pdu_big_info { 873 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 874 uint32_t offs:14; 875 uint32_t offs_units:1; 876 uint32_t iso_interval:12; 877 uint32_t num_bis:5; 878 879 uint32_t nse:5; 880 uint32_t bn:3; 881 uint32_t sub_interval:20; 882 uint32_t pto:4; 883 884 uint32_t spacing:20; 885 uint32_t irc:4; 886 uint32_t max_pdu:8; 887 888 uint8_t rfu; 889 890 uint32_t seed_access_addr; 891 892 uint32_t sdu_interval:20; 893 uint32_t max_sdu:12; 894 #elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ 895 uint32_t num_bis:5; 896 uint32_t iso_interval:12; 897 uint32_t offs_units:1; 898 uint32_t offs:14; 899 900 uint32_t pto:4; 901 uint32_t sub_interval:20; 902 uint32_t bn:3; 903 uint32_t nse:5; 904 905 uint32_t max_pdu:8; 906 uint32_t irc:4; 907 uint32_t spacing:20; 908 909 uint8_t rfu; 910 911 uint32_t seed_access_addr; 912 913 uint32_t max_sdu:12; 914 uint32_t sdu_interval:20; 915 #else 916 #error "Unsupported endianness" 917 #endif /* __BYTE_ORDER__ */ 918 919 uint16_t base_crc_init; 920 921 uint8_t chm_phy[PDU_CHANNEL_MAP_SIZE]; /* 37 bit chm; 3 bit phy */ 922 uint8_t payload_count_framing[5]; /* 39 bit count; 1 bit framing */ 923 924 uint8_t giv; /* encryption required */ 925 uint16_t gskd; /* encryption required */ 926 } __packed; 927
